Silicon SPDT Switch, Nonreflective,
100 MHz to 44 GHz
Enhanced Product
ADRF5026-EP
Rev. 0 Document Feedback
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FEATURES
Ultrawideband frequency range: 100 MHz to 44 GHz
Nonreflective design
Low insertion loss: 1.2 dB to 18 GHz, 1.7 dB to 26 GHz, 2.4 dB
to 40 GHz, 3.8 dB to 44 GHz
High isolation: 55 dB to 18 GHz, 53 dB to 26 GHz, 50 dB to
40 GHz, 45 dB to 44 GHz
High input linearity: 27 dBm typical P1dB, 53 dBm typical IP3
High power handling: 24 dBm insertion loss path,
24 dBm isolation path
All off state control
No low frequency spurious signals
0.1 dB RF settling time: 40 ns typical
20-terminal, 3 mm × 3 mm LGA package
Pin compatible with ADRF5027, low frequency cutoff version
ENHANCED PRODUCT FEATURES
Supports defense and aerospace applications (AQEC standard)
Military temperature range (−55°C to +105°C)
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Product change notification
Qualification data available on request
APPLICATIONS
Industrial scanners
Test and instrumentation
Cellular infrastructure: 5G mmWave
Military radios, radars, electronic counter measures (ECMs)
Microwave radios and very small aperture terminals (VSATs)
FUNCTIONAL BLOCK DIAGRAM
GND
RF2
GND
GND
GND
GND
GND
RF1
GND
GND
DRIVER
RFC
GND
GND
VSS
EN
GND
CTRL
VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
16
17
18
19
20
15
14
GND
GND
50Ω
50Ω
23688-001
Figure 1.
GENERAL DESCRIPTION
The ADRF5026-EP is a nonreflective, single-pole, double-throw
(SPDT) RF switch manufactured in a silicon process.
The ADRF5026-EP operates from 100 MHz to 44 GHz with
better than 3.8 dB of insertion loss and 45 dB of isolation. The
ADRF5026-EP features an all off control, where both RF ports
are in an isolation state. The ADRF5026-EP has a nonreflective
design and both of the RF ports are internally terminated to 50 Ω.
The ADRF5026-EP requires a dual-supply voltage of +3.3 V
and −3.3 V. The device employs CMOS and low voltage
transistor transistor logic (LVTTL)-compatible controls.
The ADRF5026-EP is pin compatible with the ADRF5027 low
frequency cutoff version, which operates from 9 kHz to 44 GHz.
The ADRF5026-EP RF ports are designed to match a characteris-
tic impedance of 50 Ω. For ultrawideband products, impedance
matching on the RF transmission lines can further optimize
high frequency insertion loss and return loss characteristics.
Refer to the ADRF5026 data sheet for an example of a matched
circuit that achieves a flat insertion loss response of 2.4 dB from
28 GHz to 43 GHz.
The ADRF5026-EP comes in a 20-terminal, 3 mm × 3 mm,
RoHS compliant, land grid array (LGA) package and can
operate from −55°C to +105°C.
Additional application and technical information can be found
in the ADRF5026 data sheet.
ADRF5026-EP Enhanced Product
Rev. 0 | Page 2 of 8
TABLE OF CONTENTS
Features .............................................................................................. 1
Enhanced Product Features ............................................................ 1
Applications ...................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications .................................................................................... 3
Electrical Specifications ............................................................... 3
Absolute Maximum Ratings ........................................................... 5
Thermal Resistance .......................................................................5
Power Derating Curves ................................................................5
ESD Caution ..................................................................................5
Pin Configuration and Function Descriptions .............................6
Interface Schematics .....................................................................6
Typical Performance Characteristics .............................................7
Outline Dimensions ..........................................................................8
Ordering Guide .............................................................................8
REVISION HISTORY
10/2020—Revision 0: Initial Version
Enhanced Product ADRF5026-EP
Rev. 0 | Page 3 of 8
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
VDD = 3.3 V, VSS = −3.3 V, CTRL pin voltage (VCTRL) = EN pin voltage (VEN) = 0 V or VDD, and TCASE = 25°C in a 50 Ω system, unless
otherwise noted.
Table 1.
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
FREQUENCY RANGE 100 44,000 MHz
INSERTION LOSS IL
Between RFC and RF1/RF2 100 MHz to 18 GHz 1.2 dB
18 GHz to 26 GHz 1.7 dB
26 GHz to 35 GHz 2.2 dB
35 GHz to 40 GHz 2.4 dB
40 GHz to 44 GHz1 3.8 dB
RETURN LOSS RL
RFC and RF1/RF2 (On) 100 MHz to 18 GHz 22 dB
18 GHz to 26 GHz 12 dB
26 GHz to 35 GHz 9 dB
35 GHz to 40 GHz 10 dB
40 GHz to 44 GHz
1
dB
RF1/RF2 (Off) 100 MHz to 18 GHz 23 dB
18 GHz to 26 GHz 23 dB
26 GHz to 35 GHz 21 dB
35 GHz to 40 GHz 13 dB
40 GHz to 44 GHz1 12 dB
ISOLATION
Between RFC and RF1/RF2 100 MHz to 18 GHz 55 dB
18 GHz to 26 GHz 53 dB
26 GHz to 35 GHz 53 dB
35 GHz to 40 GHz 50 dB
40 GHz to 44 GHz 45 dB
Between RF1 and RF2 100 MHz to 18 GHz 63 dB
18 GHz to 26 GHz 60 dB
26 GHz to 35 GHz
dB
35 GHz to 40 GHz 63 dB
40 GHz to 44 GHz 55 dB
SWITCHING CHARACTERISTICS
Rise and Fall Time tRISE, tFALL 10% to 90% of RF output 3 ns
On and Off Time tON, tOFF 50% of triggered VCTRL to 90% of RF output 14 ns
RF Settling Time
0.1 dB 50% of triggered VCTRL to 0.1 dB of final RF output 40 ns
0.05 dB 50% of triggered VCTRL to 0.05 dB of final RF output 45 ns
INPUT LINEARITY 100 MHz to 40 GHz
1 dB Compression P1dB 27 dBm
Third-Order Intercept
IP3
Two-tone input power = 12 dBm each tone, Δf = 1 MHz
dBm
SUPPLY CURRENT VDD and VSS pins
Positive IDD 2 µA
Negative ISS 100 µA
ADRF5026-EP Enhanced Product
Rev. 0 | Page 4 of 8
Parameter Symbol Test Conditions/Comments Min Typ Max Unit
DIGITAL CONTROL INPUTS CTRL and EN pins
Voltage
Low VINL 0 0.8 V
High VINH 1.2 3.3 V
Current
Low and High Current IINL, IINH <1 µA
RECOMMENDED OPERATING
CONDITONS
Supply Voltage
Positive VDD 3.15 3.45 V
Negative VSS −3.45 −3.15 V
Digital Control Voltage VCTRL, VEN 0 VDD V
RF Input Power2 PIN f = 100 MHz to 40 GHz, TCASE = 85°C3
Insertion Loss Path RF signal is applied to RFC or through connected
RF1/RF2
24 dBm
Isolation Path RF signal is applied to terminated RF1/RF2 24 dBm
Hot Switching RF signal is present at RFC while switching between RF1
and RF2
24 dBm
Case Temperature TCASE −55 +105 °C
1 Impedance matching on RF transmission lines improves high frequency performance. Refer to the ADRF5026 data sheet for more information.
2 For power derating vs. frequency, see Figure 2 and Figure 3. This power derating is applicable for insertion loss path, isolation path, and hot switching power
specifications.
3 For 105°C operation, the power handling degrades from the TCASE = 85°C specification by 3 dB.
Enhanced Product ADRF5026-EP
Rev. 0 | Page 5 of 8
ABSOLUTE MAXIMUM RATINGS
For recommended operating conditions, see Table 1.
Table 2.
Parameter Rating
Positive Supply Voltage −0.3 V to +3.6 V
Negative Supply Voltage −3.6 V to +0.3 V
Digital Control Inputs
Voltage −0.3 V to VDD + 0.3 V
Current 3 mA
RF Input Power1 (100 MHz to 40 GHz at
TCASE = 85°C2)
Insertion Loss Path 26 dBm
Isolation Path 25 dBm
Hot Switching 25 dBm
Temperature
Junction, TJ 135°C
Storage Range −65°C to +150°C
Reflow 260°C
Electrostatic Discharge (ESD) Sensitivity
Human Body Model (HBM)
RFC, RF1, RF2 Pins 500 V
Digital Pins 2000 V
Charged Device Model (CDM) 1250 V
1 For power derating vs. frequency, see Figure 2 and Figure 3. This power
derating is applicable for insertion loss path, isolation path, and hot
switching power specifications.
2 For 105°C operation, the power handling degrades from the TCASE = 85°C
specification by 3 dB.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
Only one absolute maximum rating can be applied at any one
time.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
θJC is the junction to case bottom (channel to package bottom)
thermal resistance.
Table 3. Thermal Resistance
Package Type θJC Unit
CC-20-4
Through Path 423 °C/W
Terminated Path 241 °C/W
POWER DERATING CURVES
2
–14
–12
–10
–8
–6
–4
–2
0
10k 100k 1M 10M 100M 1G 10G 100G
POWER DE RATI NG (dB)
FRE Q UE NCY ( Hz )
23688-002
Figure 2. Power Derating vs. Frequency, Low Frequency Detail, TCASE = 85°C
2
–12
–10
–8
–6
–4
–2
0
30 32 34 36 38 40 42 44 46 48 50
POWER DE RATI NG (dB)
FRE Q UE NCY ( GHz)
23688-003
Figure 3. Power Derating vs. Frequency, High Frequency Detail, TCASE = 85°C
0.500
0.450
0.400
0.350
0.300
0.250
0.200
0.150
0.100
0.050
0
–55 –45 –35 –25 –15 –5 515 35 35 55 75 9545 65 85 105
MAXIMUM POWER DISSIPATIO N (Watts)
CASE TEMPERATURE (°C)
23688-008
Figure 4. Maximum Power Dissipation vs. Case Temperature
ESD CAUTION
ADRF5026-EP Enhanced Product
Rev. 0 | Page 6 of 8
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND
RF2
GND
GND
GND
GND
GND
RF1
GND
GND
RFC
GND
GND
VSS
EN
GND
CTRL
VDD
1
2
3
4
5
678 9 10
11
12
13
1617181920
15
14
GND
GND
TOP VIEW
(No t t o Scal e)
ADRF5026-EP
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED
TO THE RF AND DC G ROUND O F T HE P CB.
23688-004
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1, 2, 4, 5, 6, 7, 9, 10,
13, 16, 17, 19, 20
GND Ground. These pins must be connected to the RF and dc ground of the PCB.
3 RFC RF Common Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is
necessary when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
8 RF1 RF1 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
11 VDD Positive Supply Voltage.
12 CTRL Control Input Voltage. See Figure 7 for the interface schematic.
14 EN Enable Input Voltage. See Figure 7 for the interface schematic.
15 VSS Negative Supply Voltage.
18 RF2 RF2 Port. This pin is dc-coupled to 0 V and ac matched to 50 Ω. No dc blocking capacitor is necessary
when the RF line potential is equal to 0 V dc. See Figure 6 for the interface schematic.
EPAD Exposed Pad. The exposed pad must be connected to the RF and dc ground of the PCB.
INTERFACE SCHEMATICS
RFC,
RF1,
RF2
23688-005
Figure 6. RFC, RF1, RF2 Interface Schematic
VDD
VDD
CTRL, EN
23688-006
Figure 7. CTRL, EN Interface Schematic
Enhanced Product ADRF5026-EP
Rev. 0 | Page 7 of 8
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 3.3 V, VSS = −3.3 V, VCTRL/VEN = 0 V or VDD, and TCASE = 25°C in a 50 Ω system, unless otherwise noted.
Insertion loss is measured on the probe matrix board using ground-signal-ground (GSG) probes close to the RFx pins. Signal coupling
between the probes limits the isolation performance of the ADRF5026-EP. Isolation is measured on the ADRF5026-EVALZ evaluation board.
See the ADRF5026 data sheet for details on the ADRF5026-EVALZ evaluation board and probe matrix board.
See the ADRF5026 data sheet for a full set of Typical Performance Characteristics plots.
0
–8
–7
–6
–5
–4
–3
–2
–1
0510 15 20 25 30 35 40 45 50
INSERTION LOSS (dB)
FRE Q UE NCY ( GHz)
T
CASE
= –55° C
T
CASE
= +25°C
T
CASE
= –40° C
T
CASE
= +85°C
T
CASE
= +105°C
23688-007
Figure 8. Insertion Loss vs. Frequency over Temperature
ADRF5026-EP Enhanced Product
Rev. 0 | Page 8 of 8
OUTLINE DIMENSIONS
06-21-2018-D
PKG-005264
3.10
3.00
2.90
TOP VIEW
SIDE VIEW
BOTTOM VIEW
1
5
6
10
11
15
16 20
1.60
1.50 SQ
1.40
0.40
BSC
0.13
REF
0.75
REF
1.60 REF
SQ
0.25
0.20
0.15
0.30
0.25
0.20
FOR PROPER CONNECTION OF
THE EXPOSED PADS, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
EXPOSED
PAD
0.530 REF
CHAMFERED
PIN 1 (0.3 × 45°)
PIN 1
CORNER AREA
0.236
0.196
0.156
0.776
0.726
0.676
Figure 9. 20-Terminal Land Grid Array [LGA]
3 mm × 3 mm Body and 0.726 mm Package Height
(CC-20-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option Marking Code
ADRF5026SCCZ-EP −55°C to +105°C 20-Terminal Land Grid Array [LGA] CC-20-4 6EP
ADRF5026SCCZ-EPR7 −55°C to +105°C 20-Terminal Land Grid Array [LGA] CC-20-4 6EP
1 Z = RoHS Compliant Part.
©2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D23688-10/20(0)