Page 1 of 4
Document No. 70-0202-01 www. pse mi.com ©2006 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
The PE42660 is a HaRP™-enhanced SP6T
RF Switch developed on the UltraCMOS™
process technology. It addresses the specific
design needs of the Quad-Band GSM Handset
Antenna Switch Modu le Market. On-ch i p
CMOS de code logic facilit ates three-pin low
voltage CMOS control, while high ESD
toleranc e of 1500 V at all ports, no bloc king
cap aci tor req ui r em e nts, an d on- chi p SAW fil t er
over-voltage protection devices make this the
u l tim ate in integration and ruggedness.
Peregrine’s HaRP™ technology
enhancements deliver high linearity and
exceptional harmonics performance. It is an
innovative feature of the UltraCMOS™
proc es s , pr ov i ding perf or m a nc e su per i or to
GaAs with th e ec o nom y and in te gr ation of
conventional CMOS.
Pro duct Specificat ion
SP6T UltraCMOS™ 2.75 V Switch
100 – 3000 MH z
Product Description
Figure 1. Functional Diagram
PE42660 DIE
Features
• Three pin CMOS logic control with
integral decoder/driver
• Exceptional harmonics performance:
2fo = -85 dBc and 3fo = -83 dBc
• Low TX insertion loss: 0.55 dB at
900 MH z, 0.65 dB at 190 0 MHz
• TX – RX Isolation of 48 dB at 900 MHz,
40 dB at 1900 MHz
• 1500 V HBM ESD tol er ance all por ts
• 41 dBm P1 dB
• No blocking capacitors required
Figure 2. Die Top View
RX1
RX2
RX3
RX4
TX1
TX2
CMOS
Control/Driver
and ESD
V1 V2 V3
ANT TX1
TX2
GND
GND
RX1
GND
RX2
GND
RX3
GND
RX4
GND
GND VDD V3 GND V2 V1 GND
GND
Product Specification
PE42660
Page 2 of 4
©2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0202-01 UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
Table 2. Opera ti ng Ranges Table 3. Absolute Max imum Rati ngs
Part perf or m anc e is not guar anteed under t hes e
conditi ons . Expos ur e to absolut e maximum c onditions
for extended per iods of time may adversely aff ec t
reliability . Stress es in exces s of absolute maxim um
rati ngs m ay c aus e per m anent damage.
Note : 3. Ass um es RF in p ut perio d of 4620 µs and duty cycle of 50%.
4. VDD within operating range specified in Table 2.
Table 1. Electrical Specifications @ +25 °C, VDD = 2.75 V (ZS = ZL = 50 )
Parameter Conditions Typical Units
Operational Frequency 100-3000 MHz
Inser t io n Los s
ANT - TX - 850 / 900 MHz
ANT - TX - 1800 / 1900 MHz
ANT - RX - 850 / 900 MHz
ANT - RX - 1800 / 1900 MHz
0.55
0.65
0.90
1.00
dB
dB
dB
dB
Isolation
TX - RX - 850 / 900 MHz
TX - RX - 1800 / 1900 MHz
TX - TX - 850 / 900 MHz
TX - TX - 1800 / 1900 MHz
48
40
29
25
dB
dB
dB
dB
Return Loss 850 / 90 0 MHz
1800 / 19 00 MH z 22
23 dB
2nd Harmonic1 35 dBm TX Input - 850 / 900 MHz
33 dBm TX Input - 1800 / 1900 MHz -85
-84 dBc
3rd Harmonic1 35 dBm TX Input - 850 / 900 MHz
33 dBm TX In put - 1800 / 1900 MHz -83
-82 dBc
Switching Time (10-90%) (90-10%) RF 2 µs
Notes: 1. Pu lsed RF input duty cycle of 50% and 4620 µs, measured per 3GPP TS 45.005
Note : 2. Ass um es RF in p ut perio d of 4620 µs and duty cycle of 50%.
Parameter Symbol Min Typ Max Units
Temperature range TOP -40 +85 °C
VDD Supply Voltage VDD 2.65 2.75 2.85 V
IDD Power Su pply Current
(VDD = 2.75 V) IDD 13 50 µA
TX input power2 (VSWR 3:1)
824-915 MHz PIN
+35
TX input power2 (VSWR 3:1)
1710-1910 MHz +33
RX input power2
(VSWR 1:1) PIN +20 dBm
Control Voltage High VIH 0.7 x
VDD V
Control Voltage Low VIL 0.3 x
VDD V
dBm
Symbol Parameter/Conditions Min Max Units
VDD Power supply voltage -0.3 4.0 V
VI Voltage on any input -0.3 VDD+ 0.3 V
TST Storage temperature range -65 +150 °C
PIN(50 )
TX input power (50 ) 3,4
824-915 MHz +38
dBm
TX input power (50 ) 3,4
1710-1910 MHz +36
RX input power (50 ) 3,4 +23
PIN (:1 )
TX input pow er (VSWR = (:1)3,4
824-915 MHz +35
dBm
TX input pow er (VSWR = (:1)3,4
1710-1910 MHz +33
VESD ESD Voltage (HBM, MIL_STD
883 Method 30 15 . 7) 1500 V
Product Specification
PE42660
Page 3 of 4
Document No. 70-0202-01 www. pse mi.com ©2006 Peregrine Semiconductor Corp. All rights reserved.
Contact sales@psemi.com for full version of datasheet
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS™ device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latc h-Up Avoidance
Unlike conv ent ional CMOS d evices, UltraCMO S™
devices are immune to latch-up.
Table 5. Truth Table
Table 6. Ordering Information
Table 4 . Pin Descriptions Figure 3. Pin Configuration (Top View)
Notes: 5. Bond wires should be physically short and connected to
gro un d pl ane for bes t per f or m anc e.
6. Blocking capacitors needed only when non-zero DC
voltage p resent.
Pin No. Pin Name Description
1 ANT6 RF Common – Antenna
2 TX16 RF I/O - TX1
3 GND5 Grou nd (R e qu ir es tw o bo nd wir es )
4 TX26 RF I/O – TX2
5 GND5 Ground
6 GND5 Ground
7 VDD Supply
8 V3 Sw itch con trol input, CMOS logic level
9 GND5 Ground
10 V2 Switch control input, CMOS logic level
11 V1 Switch control input, CMOS logic level
12 GND5 Ground
13 GND5 Ground
14 RX46 RF I/O – RX4
15 GND5 Ground
16 RX36 RF I/O – RX3
17 GND5 Ground
18 RX26 RF I/O – RX2
19 GND5 Ground
20 RX16 RF I/O – RX1
TX1
PE42660
Die
ANT
TX2
RX1
RX2
V
DD
V3
V2
V1
GND
GND
GND
GND
GND
RX3
GND
GND
GND
GND
RX4
GND
1
2
3
4
5
67 89101112
13
14
15
16
17
18
19
20
Path V3 V2 V1
ANT – RX1 0 0 0
ANT – RX2 0 0 1
ANT – RX3 0 1 0
ANT – RX4 0 1 1
ANT - TX1 1 0 x
ANT - TX2 1 1 x
Order Code Die ID Description Package Shippin g Method
42660-90 C9807_01 PE42660-DIE-D Fil m Fra me Wafer (Gross Die / Wafer Quantity)
42660-99 C9807_01 PE42660-DIE-400G Waffle Pack 400 Dice / Waffle Pack
42660-00 C9807_01 PE42660-DIE-1H Evaluation Kit 1/ box
Product Specification
PE42660
Page 4 of 4
©2006 Peregrine Semiconductor Corp. All rights reserved. Document No. 70-0202-01 UltraCMOS™ RFIC Solutions
Contact sales@psemi.com for full version of datasheet
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For a list of representat ives in your area, please r efer to our W eb site at: www.psemi.com
Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data
sheet contains design target specificat ions f or product
development. Spec ifications and features may change in
any manner without notice.
Preliminary Specification
The data sheet contains pr eliminary data. Addit ional data
may be added at a later date. Peregrine reserves the right
to change specifications at any tim e without notice in order
to supply t he best possible product.
Product Specification
The data sheet contains final data . In the event Peregrine
dec ide s to cha nge the spe c ific a tions, Pereg rine will not ify
cust omers of the intended changes by issu ing a DCN
(Document Change Notice).
The information in this data sheet is believed t o be reliable.
Howeve r, Peregrine assum es no liability f or th e use of this
information. Use shall be entir ely at the user’s own risk.
No patent rights or licenses to any circuits described in this
data sheet are implied or granted t o any third party.
Peregrine’s pr oducts are not designed or intended for use in
devices or systems intended for surgical implant, or in other
applications intended to support or sustain life, or in any
application in which the failure of the Per egrine product could
create a situation in which personal injury or death m ight occur.
Peregr ine assumes no liability for damages, including
consequential or incident al dam ages, arising out of the use of
its products in such applications .
The Peregr ine nam e, logo, and UTSi are registered t r ademarks
and UltraCMOS and HaRP are trademarks of Peregrine
Semiconductor Corp.
South As ia Pa cific
Peregrine Semiconductor, China
Shanghai, 200040, P.R. China
Tel: +86-21-5836-8276
Fax: +86-21-5836-7652
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