Wireless Components ASK Single Conversion Receiver 390MHz TDA 5204 E1 Version 1.0 Specification December 2000 preliminary Revision History Current Version: 1.0 as of 12.01.01 Previous Version: none Page (in previous Version) Page (in current Version) Subjects (major changes since last revision) ABM(R), AOP(R), ARCOFI(R), ARCOFI(R)-BA, ARCOFI(R)-SP, DigiTape(R), EPIC(R)-1, EPIC(R)-S, ELIC(R), FALC(R)54, FALC(R)56, FALC(R)-E1, FALC(R)-LH, IDEC(R), IOM(R), IOM(R)-1, IOM(R)-2, IPAT(R)-2, ISAC(R)-P, ISAC(R)-S, ISAC(R)-S TE, ISAC(R)-P TE, ITAC(R), IWE(R), MUSAC(R)-A, OCTAT(R)-P, QUAT(R)-S, SICAT(R), SICOFI(R), SICOFI(R)2, SICOFI(R)-4, SICOFI(R)-4C, SLICOFI(R) are registered trademarks of Infineon Technologies AG. ACETM, ASMTM, ASPTM, POTSWIRETM, QuadFALCTM, SCOUTTM are trademarks of Infineon Technologies AG. Edition 12.00 Published by Infineon Technologies AG, Balanstrae 73, 81541 Munchen (c) Infineon Technologies AG December 2000. All Rights Reserved. Attention please! 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Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of the Infineon Technologies AG, may only be used in life-support devices or systems2 with the express written approval of the Infineon Technologies AG. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered. TDA 5204 E1 preliminary Product Info Product Info General Description Features The IC is a very low power consump- Package tion single chip ASK Single Conversion Receiver for receive frequencies between 385 and 406MHz. The Receiver offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life. Low supply current (Is = 4.8mA typ.) Supply voltage range 5V 10% Temperature range -40C...+85C Power down mode with very low 390MHz band Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with supply current (50nA typ) Fully integrated VCO and PLL external capacitors Data slicer with self-adjusting Synthesiser threshold RF input sensitivity < -110dBm Application Keyless Entry Systems Remote Control Systems Fire Alarm Systems Low Bitrate Communication Systems Ordering Information Type Ordering Code Package TDA 5204 Q67037-A1169 P-TSSOP-28-1 available on tape and reel Wireless Components Product Info Specification, December 2000 1 Table of Contents 1 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-i 2 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.4 Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 2.5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3.3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.1 Low Noise Amplifier (LNA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 3.4.2 Mixer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.3 PLL Synthesizer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.4 Crystal Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 3.4.5 Limiter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.6 Data Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.7 Data Slicer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.8 Peak Detector. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 3.4.9 Bandgap Reference Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 4 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4-1 4.1 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.2 Data Filter Design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 4.4 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.5 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-1 5.1 Electrical Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 5.1.2 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-3 5.1.3 AC/DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-4 5.2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 5.3 Test Board Layouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 5.4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 2 Product Description Contents of this Chapter 2.1 2.2 2.3 2.4 2.5 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 Possible Receive Ranges. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 TDA 5204 E1 preliminary Product Description 2.1 Overview The IC is a very low power consumption single chip ASK Superheterodyne Receiver (SHR) for the frequency band 390MHz. The SHR offers a high level of integration and needs only a few external components. The device contains a low noise amplifier (LNA), a double balanced mixer, a fully integrated VCO, a PLL synthesiser, a crystal oscillator, a limiter with RSSI generator, a data filter, a data comparator (slicer) and a peak detector. Additionally there is a power down feature to save battery life. 2.2 Application Keyless Entry Systems Remote Control Systems Fire Alarm Systems Low Bitrate Communication Systems 2.3 Features Wireless Components Low supply current (Is = 4.8mA typ.) Supply voltage range 5V 10% Power down mode with very low supply current (50nA typ.) Fully integrated VCO and PLL Synthesiser RF input sensitivity < -110dBm frequency band 390MHz Selectable reference frequency Limiter with RSSI generation, operating at 10.7MHz 2nd order low pass data filter with external capacitors Data slicer with self-adjusting threshold Temperature range -40C...+85C 2-2 Specification, December 2000 TDA 5204 E1 preliminary Product Description 2.4 Possible Receive Ranges 385...406MHz (high-side injected) 406...428MHz (low-side injected) 781...823MHz (high-side injected) 803...844MHz (low-side injected) 2.5 Package Outlines P_TSSOP_28.EPS Figure 2-1 Wireless Components P-TSSOP-28-1 package outlines 2-3 Specification, December 2000 3 Functional Description Contents of this Chapter 3.1 3.2 3.3 3.4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Pin Definition and Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Functional Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 TDA 5204 E1 preliminary Functional Description 3.1 Pin Configuration CRST1 1 28 CRST2 VCC 2 27 PWDN LNI 3 26 PDO TAGC 4 25 DATA AGND 5 24 3VOUT LNO 6 23 THRES VCC 7 22 FFB MI 8 21 OPP MIX 9 20 SLN AGND 10 19 SLP FSEL 11 18 LIMX IFO 12 17 LIM DGND 13 16 CSEL VDD 14 15 LF TDA5204 Pin_Configuration.wmf Figure 3-1 Wireless Components IC Pin Configuration 3-2 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 3.2 Pin Definition and Function Table 3-1 Pin Definition and Function Pin No. Symbol 1 CRST1 Equivalent I/O-Schematic Function External Crystal Connector 1 4.15V 1 2 VCC 5V Supply 3 LNI LNA Input 3 1k 4 TAGC AGC Time Constant Control 4.3V 4uA 1k 4 1.5uA 1.7V 5 AGND Analogue Ground Return 6 LNO LNA Output 1k 6 7 VCC Wireless Components 5V Supply 3-3 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 8 MI Mixer Input 1.7V 2k 2k 8 9 9 MIX 10 AGND Analogue Ground Return 11 FSEL 390MHz: not applicable - has to be left open Complementary Mixer Input 1.2V 40k 11 12 IFO 10.7 MHz IF Mixer Output 300uA 2.2V 60 12 4.5k 13 DGND Digital Ground Return 14 VDD 5V Supply (PLL Counter Circuitry) 15 LF PLL Filter Access Point (Loop Filter) 4.8V 200 15 30uA 100 30uA 2.4V Wireless Components 3-4 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 16 CSEL 6.xx or 12.xx MHz Quartz Selector 1.2V 80k 16 17 LIM Limiter Input 15k 2.4V 330 17 18 LIMX 19 SLP 15k 18 Complementary Limiter Input Data Filter Output Data Slicer Positive Input Peak Detector Input 10k 100 19 10k 40u 20 SLN Data Slicer Negative Input 10k 20 21 OPP OpAmp Noninverting Input 200 21 Wireless Components 3-5 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 22 FFB Data Filter Feedback Pin 100k 22 23 THRES AGC Threshold Input 10k 23 24 3VOUT 3V Reference Output 24 3V 25 DATA Data Output 200 25 80k Wireless Components 3-6 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 26 PDO Peak Detector Output 200 26 27 PDWN Power Down Input Vs --> Power ON GND---> Power Down 27 220k 220k 28 CRST2 External Crystal Connector 2 4.15V 28 Wireless Components 3-7 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 3.3 Functional Block Diagram VCC IF Filter 3 RF LNO MI 6 8 MIX IFO 9 12 LIM LIMX FFB OPP SLP SLN 17 18 22 21 19 20 LNA RSSI 25 DATA 26 PDO 23 THRES SLICER TAGC 4 TDA 5204 AGC Reference VDD 14 24 3VOUT UREF : 1/2 VCO : 128/64 DGND 13 DET Crystal OSC Bandgap Reference Loop Filter 2/7 VCC 5/10 AGND 11 FSEL 15 LF 16 1 CSEL 28 27 PDWN Crystal Function_5204.wmf Figure 3-2 Main Block Diagram 3.4 Functional Blocks 3.4.1 Low Noise Amplifier (LNA) The LNA is an on-chip cascode amplifier with a voltage gain of 15 to 20dB. The gain figure is determined by the external matching networks situated ahead of LNA and between the LNA output LNO (Pin 6) and the Mixer Inputs MI and MIX (Pins 8 and 9). The noise figure of the LNA is approximately 2dB, the current consumption is 500A. The gain can be reduced by approximately 18dB. The switching point of this AGC action can be determined externally by applying a threshold voltage at the THRES pin (Pin 23). This voltage is compared internally with the received signal (RSSI) level generated by the limiter circuitry. In case that the RSSI level is higher than the threshold voltage the LNA gain is reduced and vice versa. The threshold voltage can be generated by attaching a voltage divider between the 3VOUT pin (Pin 24) which provides a temperature stable 3V output generated from the internal bandgap voltage and the THRES pin as described in Section 4.1. The time constant of the AGC action can be determined by connecting a capacitor to the TAGC pin (Pin 4) and should be chosen along with the appropriate threshold voltage according to the intended operat- Wireless Components 3-8 Specification, December 2000 TDA 5204 E1 preliminary Functional Description ing case and interference scenario to be expected during operation. The optimum choice of AGC time constant and the threshold voltage is described in Section 4.1. 3.4.2 Mixer The Double Balanced Mixer downconverts the input frequency (RF) 390MHz to the intermediate frequency (IF) at 10.7MHz with a voltage gain of approximately 21dB. A low pass filter with a corner frequency of 20MHz is built on chip in order to suppress RF signals to appear at the IF output ( IFO pin). The IF output is internally consisting of an emitter follower that has a source impedance of approximately 330= to facilitate interfacing the pin directly to a standard 10.7MHz ceramic filter without additional matching circuitry. 3.4.3 PLL Synthesizer The Phase Locked Loop synthesiser consists of a VCO, an asynchronous divider chain, a phase detector with charge pump and a loop filter and is fully implemented on-chip. The VCO is including spiral inductors and varactor diodes. It's nominal centre frequency is 800MHz. The FSEL pin (Pin 11) has to be left open. No additional components are necessary. The oscillator signal is fed both to the synthesiser divider chain and to the downconverting mixer. The VCO signal is divided by two before it is fed to the mixer. The loop filter is also realised fully on-chip. 3.4.4 Crystal Oscillator The on-chip crystal oscillator circuitry allows for utilisation of quartzes both in the 6 and 12MHz range as the overall division ratio of the PLL can be switched between 64 and 128 via the CSEL (Pin 16 ) pin according to the following table. Table 3-2 CSEL Pin Operating States CSEL Crystal Frequency Open 6.xx MHz Shorted to ground 12.xx MHz The calculation of the value of the necessary quartz load capacitance is shown in Section 4.3, the quartz frequency calculation is expained in Section 4.4. Wireless Components 3-9 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 3.4.5 Limiter The Limiter is an AC coupled multistage amplifier with a cumulative gain of approximately 80dB that has a bandpass-characteristic centred around 10.7MHz. It has an input impedance of 330 =to allow for easy interfacing to a 10.7MHz ceramic IF filter. The limiter circuit acts as a Receive Signal Strength Indicator (RSSI) generator which produces a DC voltage that is directly proportional to the input signal level as can be seen in Figure 4.1. This signal is used to demodulate the ASK receive signal in the subsequent baseband circuitry and to turn down the LNA gain by approximately 18dB in case the input signal strength is too strong as described in Section 3.4.1 and Section 4.1. 3.4.6 Data Filter The data filter comprises an OP-Amp with a bandwidth of 100kHz used as a voltage follower and two 100k= on-chip resistors. Along with two external capacitors a 2nd order Sallen-Key low pass filter is formed. The selection of the capacitor values is described in Section 4.2. 3.4.7 Data Slicer The data slicer is a fast comparator with a bandwidth of 100 kHz. This allows for a maximum receive data rate of approximately 120kBaud. The maximum achievable data rate also depends on the IF Filter bandwidth and the local oscillator tolerance values. Both inputs are accessible. The output delivers a digital data signal (CMOS-like levels) for the detector. The self-adjusting threshold on pin SLN (pin 20) its generated by RC-term or peak detector depending on the baseband coding scheme. The data slicer threshold generation alternatives are described in more detail in Section 4.5. 3.4.8 Peak Detector The peak detector generates a DC voltage which is proportional to the peak value of the receive data signal. An external RC network is necessary. The output can be used as an indicator for the signal strength and also as a reference for the data slicer. The maximum output current is approx. 900A. Wireless Components 3 - 10 Specification, December 2000 TDA 5204 E1 preliminary Functional Description 3.4.9 Bandgap Reference Circuitry A Bandgap Reference Circuit provides a temperature stable reference voltage for the device. A power down mode is available to switch off all subcircuits which is controlled by the PWDN pin (Pin 27) as shown in the following table. The supply current drawn in this case is typically 50nA. Table 3-3 PDWN Pin Operating States PDWN Operating State Open or tied to ground Powerdown Mode Receiver On Tied to Vs Wireless Components 3 - 11 Specification, December 2000 4 Applications Contents of this Chapter 4.1 4.2 4.3 4.4 4.5 LNA and Automatic Gain Control (AGC) . . . . . . . . . . . . . . . . . . . . . . 4-2 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Quartz Load Capacitance Calculation . . . . . . . . . . . . . . . . . . . . . . . . 4-5 Quartz Frequency Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Data Slicer Threshold Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 TDA 5204 E1 preliminary Applications 4.1 LNA and Automatic Gain Control (AGC) The AGC extends the dynamic range of the receiver. The automatic gain control in the TDA5204 is a narrow-band control loop which compares the receive signal strength signal (RSSI, 0.8V to 2.8V) from the limiter with a fixed threshold voltage applied to pin 23 (THRES). In the following figure the internal circuitry of the LNA automatic gain control is shown. R4 R5 Uthreshold Pins: 24 23 RSSI (0.8 - 2.8V) +3V OTA VCC Iload Gain control voltage RSSI > Uthreshold: Iload=4.2A RSSI < Uthreshold: Iload= -1.5A 4 UC C LNA Uc:< 2.6V : Gain high Uc:> 2.6V : Gain low Ucmax= VCC - 0.7V Ucmin = 1.67V LNA_autom.wmf Figure 4-1 LNA Automatic Gain Control Circuitry The fixed voltage on pin 23 is generated on the external voltage divider. The comparator is a transimpedance amplifier (OTA), which creates a positive current (+4.2uA) in the case the RSSI level is larger than the threshold voltage. Otherwise the current is -1.5uA. This leads to an asymmetric fast-attack and slow-release behaviour and thus to fast reaction to the low gain mode and slow reaction to the high gain mode. This current is converted into a control voltage over an external capacitor C attached to pin 4 (TAGC) which defines the gain of the LNA. The limits of the control voltages for the LNA on pin4 are 1.67V for high gain mode and Vcc-0.7V for low gain mode. Wireless Components 4-2 Specification, January 2001 TDA 5204 E1 preliminary Applications LNA always in high gain mode 3 2 RSSI Level Range UTHRES Voltage Range 2.5 RSSI Level 1.5 1 LNA always in low gain mode 0.5 0 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 Input Level at LNA Input [dBm] RSSI-AGC.wmf Figure 4-2 RSSI Level an Permissive AGC Threhold Level The value of the capacitor defines the response time of the AGC. For a stable control loop the capacitor value should be at least 47nF. The AGC can be disabled by tying the THRES-pin either to GND or to VCC as show here: LNA high gain: - pin 23 (THRES) shorted to VCC LNA low gain: - pin 23 (THRES) shorted to GND In these cases capacitor and voltage divider are not necessary. Wireless Components 4-3 Specification, January 2001 TDA 5204 E1 preliminary Applications 4.2 Data Filter Design Utilising the on-board voltage follower and the two 100k on-chip resistors a 2nd order Sallen-Key low pass data filter can be constructed by adding 2 external capacitors between pins 19 (SLP) and 22 (FFB) and to pin 21 (OPP) as depicted in the following figure and described in the following formulas1. C1 Pins: C2 22 21 R R 100k 100k 19 Filter_Design.wmf Figure 4-3 Data Filter Design (1) (2) 2 Q bC 1 = -----------------------R 2f 3dB b C2 = --------------------------------4Q R f 3dB with Q = ------ba (3) the quality factor of the poles where in case of a Bessel filter a = 1.3617, b = 0.618 and thus Q = 0.577 and in case of a Butterworth filter a = 1.41, b = 1 and thus Q = 0.71 Example: Butterworth filter with f3dB = 5kHz and R = 100k: C1 = 450pF, C2 = 225pF 1. taken from Tietze/Schenk: Halbleiterschaltungstechnik, Springer Berlin, 1999 Wireless Components 4-4 Specification, January 2001 TDA 5204 E1 preliminary Applications 4.3 Quartz Load Capacitance Calculation The value of the capacitor necessary to achieve that the quartz oscillator is operating at the intended frequency is determined by the reactive part of the negative resistance of the oscillator circuit as shown in Section 5.1.3 and by the quartz specifications given by the quartz manufacturer. CS Pin 28 Crystal Input impedance Z1-28 TDA5204 Pin 1 Quartz_load.wmf Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator The quartz oscillator input impedance consists of a negative resistance and an inductance L. Crystal specified with load capacitance CS = 1 1 + (2 f CL )2 L with CL the load capacitance (refer to the quartz crystal specification). Examples with typ. values: 6.26 MHz: CL = 12 pF L=21uH CS = 8.6 pF 12.52 MHz: CL = 12 pF L=19uH CS = 5 pF These values may be obtained by putting two capacitors in series to the quartz. Wireless Components 4-5 Specification, January 2001 TDA 5204 E1 preliminary Applications 4.4 Quartz Frequency Calculation The quartz frequency is calculated by using the following formula: QU = (RF 10.7MHz) / r with (1), RF .... receive frequency +/- ... high-side / low-side injected LO .... local oscillator (PLL) frequency (RF 10.7) QU .... quartz oscillator frequency r .... ratio of local oscillator (PLL) frequency and quartz frequency as shown in the subsequent table. Table 4-1 frequency range fRF 385...406MHz high-side injected X 406...428MHz 781...823MHz low-side injected open X X 803...844MHz open GND X Table 4-2 FSEL Pin11 GND Table 4-3 quartz crystal range CSEL Pin16 FSEL CSEL Ratio r (fLO/fQU) 6.xx MHz open open open 64 12.xx MHz GND open GND 32 GND open 128 GND GND 64 Example: fRF=390MHz fQU=(390MHz+10.7MHz) / 64 = 6.2609375MHz fQU=(390MHz+10.7MHz) / 32 = 12.521875MHz Wireless Components 4-6 Specification, January 2001 TDA 5204 E1 preliminary Applications 4.5 Data Slicer Threshold Generation The threshold of the data slicer can be generated in two ways, depending on the signal coding scheme used. In case of a signal coding scheme without DC content such as Manchester coding the threshold can be generated using an external R-C integrator as shown in the following . The cut-off frequency of the R-C integrator has to be lower than the lowest frequency appearing in the data signal. In order to keep distortion low, the minimum value for R is 20k. R C Pins: 19 data out 25 20 Uthreshold data filter data slicer Data_slice1.wmf Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator Another possibility for threshold generation is to use the peak detector in connection with two resistors and one capacitor as shown in the following figure. The component values are depending on the coding scheme and the protocol used. R C R Pins: peak detector 26 19 data out 25 20 Uthreshold data slicer data filter Data_slice2.wmf Figure 4-6 Wireless Components Data Slicer Threshold Generation Utilising the Peak Detector 4-7 Specification, January 2001 5 Reference Contents of this Chapter 5.1 5.2 5.3 5.4 Electrical Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-2 Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Test Board Layouts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 TDA 5204 E1 preliminary Reference 5.1 Electrical Data 5.1.1 Absolute Maximum Ratings WARNING The maximum ratings may not be exceeded under any circumstances, not even momentarily and individually, as permanent damage to the IC will result. Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C # Parameter Symbol Limit Values min max Unit 1 Supply Voltage Vs -0.3 5.5 V 2 Junction Temperature Tj -40 +125 C 3 Storage Temperature Ts -60 +150 C 4 Thermal Resistance RthJA 114 K/W 5 ESD integrity, all pins VESD +1 kV Wireless Components 5-2 -1 Remarks HBM according to MIL STD 883D, method 3015.7 Specification, January 2001 TDA 5204 E1 preliminary Reference 5.1.2 Operating Range Within the operating range the IC operates as explained in the circuit description. The AC/DC characteristic limits are not guaranteed. Supply voltage: VCC = 4.5V .. 5.5V Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 85C # Parameter Symbol Limit Values min 1 Supply Current 2 Unit Test Conditions fRF = 390MHz L Item max IS 6.4 mA Power Down Current IPWDN 250 nA 3 Receiver Input Level RFin -110 -13 dBm 4 Receive Frequency fRF 385 406 MHz @ source impedance 50, BER 2E-3, average power level, Manchester encoded datarate 4kBit, 280kHz IF Bandwidth, with AGC This value is guaranteed by design. Wireless Components 5-3 Specification, January 2001 TDA 5204 E1 preliminary Reference 5.1.3 AC/DC Characteristics AC/DC characteristics involve the spread of values guaranteed within the specified voltage and ambient temp. range. Typical characteristics are the median of the production. The device performance parameters marked with were measured on an Infineon evaluation board as desdribed in Section 5.2. Currents flowing into the device are denoted as positive currents and vice versa. Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V # Parameter Symbol Limit Values min typ max Unit Test Conditions Pin 27 (PDWN) open or tied to 0 V L Item Supply Supply Current 1 Supply current, standby mode IS PDWN 50 150 nA 2 Supply current IS 4.8 5.5 mA LNA Signal Input LNI (PIN 3), high gain mode 1 Average Power Level at BER = 2E-3 (Sensitivity) RFin -112 2 dBm Input impedance, fRF = 390 MHz S11 LNA 0.879 / -31 deg 3 Input level @ 1dB C.P. fRF=390 MHz P1dBLNA -14 dBm 4 Input 3rd order intercept point fRF = 390 MHz IIP3LNA -10 dBm 5 LO signal feedthrough at antenna port LOLNI -119 dBm Manchester encoded datarate 4kBit, 280kHz IF Bandwidth fin = 390MHz Signal Output LNO (PIN 6), high gain mode 1 Gain fRF = 390 MHz S21 LNA 1.578 / 141.8deg 2 Output impedance, fRF = 390 MHz S22 LNA 0.8822 / -12.13deg 3 Voltage Gain Antenna to MI fRF = 390 MHz GAntMI 21 dB 4 Noise Figure NFLNA 2 dB excluding matching network loss - see Appendix Signal Input LNI, low gain mode 1 Input impedance, fRF = 390 MHz S11 LNA 0.903 / -31.8deg 2 Input level @ 1dB C. P. fRF = 390 MHz P1dBLNA -7 Wireless Components 5-4 dBm matched input Specification, January 2001 TDA 5204 E1 preliminary Reference Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol Limit Values min typ Unit Test Conditions L dBm fin = 390MHz Item max Signal Input LNI, VTHRES = GND, low gain mode 3 Input 3rd order intercept point fRF = 390 MHz -13 IIP3LNA Signal Output LNO, VTHRES = GND, low gain mode 1 Gain fRF = 390 MHz S21 LNA 0.1834 / 144deg 2 Output impedance, fRF = 390 MHz S22 LNA 0.897 / -12.4deg 3 Voltage Gain Antenna to MI fRF = 390 MHz GAntMI 2 dB Signal 3VOUT (PIN 24) 1 Output voltage V3VOUT 2 Load current out I3VOUT 2.9 3 3.1 V -50 A Signal THRES (PIN 23) 1 Input Voltage range VTHRES 0 VS V 2 LNA low gain mode VTHRES 0 0.5 V 3 LNA high gain mode VTHRES 3.3 VS V 4 Current in ITHRES_in -5 see chapter 4.1 nA Signal TAGC (PIN 4) 1 Current out, LNA low gain state ITAGC_out -2.5 -4.2 -5.5 A RSSI > VTHRES 2 Current in, LNA high gain state ITAGC_in 0.5 1.5 4 A RSSI < VTHRES MIXER Signal Input MI/MIX (PINS 8/9) 1 Input impedance, fRF = 390 MHz S11 MIX 0.9413 / -13.1deg 2 Input 3rd order intercept point IIP3MIX -25 dBm Signal Output IFO (PIN 12) 1 Output impedance ZIFO 330 2 Conversion Voltage Gain fRF=390 MHz GMIX +21 dB 3 Noise Figure, SSB (~DSB NF+3dB) NFMIX 13 dB 4 RF to IF isolation ARF-IF 46 dB Wireless Components 5-5 Specification, January 2001 TDA 5204 E1 preliminary Reference Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol Limit Values Unit Test Conditions L min typ max ZLIM 264 330 396 60 70 80 dB dB Item LIMITER Signal Input LIM/X (PINS 17/18) 1 Input Impedance 2 RSSI dynamic range DRRSSI 3 RSSI linearity LINRSSI 4 Operating frequency (3dB points) fLIM 5 10.7 23 MHz 5 RSSI Level at Data Filter Output SLP RSSIlow 0.4 0.8 1.2 V Limiter_in: 10uV 6 RSSI Level at Data Filter Output SLP RSSIhigh 2.3 2.8 3.2 V Limiter_in: 100mV 1 DATA FILTER 1 Max. useable bandwidth BWBB 100 kHz 100 kHz FILT SLICER Signal Output DATA (PIN 25) 1 Max. useable bandwith BWBB SLIC 2 LOW output voltage VSLIC_L 0 100 mV 3 HIGH output voltage VSLIC_H Vs-1.2 VS-1 Vs-0.7 V 4 Output current ISLIC_out -400 -800 -1100 A high level drive 5 Output impedance Rout 60 80 100 k low level drive Iload -500 -950 -1200 A Ileakage 0 700 2000 nA PEAK DETECTOR Signal Output PDO (PIN 26) 1 Load current 2 Leakage current Wireless Components 5-6 Specification, January 2001 TDA 5204 E1 preliminary Reference Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V (continued) Parameter Symbol Limit Values min typ Unit Test Conditions MHz fundamental mode, series resonance L Item max CRYSTAL OSCILLATOR Signals CRSTL1, CRISTL 2, (PINS 1/28) 1 Operating frequency fCRSTL 2 Negative Resistance @ ~6MHz Re{Z1-28} -750 3 Negatve Resitance @ ~12MHz Re{Z1-28} -450 4 Input Indutance @ ~6MHz Im{Z1-28}/ 2 f 21 uH 5 Input Inductance @ ~12MHz Im{Z1-28}/ 2 f 19 uH 1 14 PLL Signal LF (PIN 15) 1 Tuning voltage relative to Vs VTUNE 0.5 1.05 2 V POWER DOWN Pin Signal PDWN (PIN 27) 1 Powerdown Mode On PWDNON 0 0.8 V 2 Powerdown Mode Off PWDNOff 2.8 VS V 3 Input bias current IPWD 4 Start-up Time until valid IF signal is detected TSU 19 uA 1 ms Power On Mode PLL DIVIDER Signal CSEL (PIN 16) 1 fCRSTL range 6.xxMHz VCSEL 1.4 4 V 2 fCRSTL range 12.xxMHz VCSEL 0 0.2 V 3 Bias current CSEL ICSEL -5 A or open CSEL tied to GND Measured only in lab. Wireless Components 5-7 Specification, January 2001 TDA 5204 E1 preliminary Reference 5.2 Test Circuit DATE: Jul.19, 1999 n Board FILE: -10 V 2.0 TITLE: TDA5200 /-01 /-02 Evaluatio Infineon Technologies Design Center Graz The device performance parameters marked with in Section 5.1.3 were measured on an Infineon evaluation board. This evaluation board can be obtained together with evaluation boards of the accompanying transmitter device TDA51xx in an evaluation kit that may be ordered on the INFINEON RKE Webpage www.infineon.com/rke Test_circuit.wmf Figure 5-1 Wireless Components Schematic of the Evaluation Board 5-8 Specification, January 2001 TDA 5204 E1 preliminary Reference 5.3 Test Board Layouts Wireless Components Figure 5-2 Top Side of the Evaluation Board (TDA5210 Testboard is the same) Figure 5-3 Bottom Side of the Evaluation Board 5-9 Specification, January 2001 TDA 5204 E1 preliminary Reference Figure 5-4 Wireless Components Component Placement on the Evaluation Board 5 - 10 Specification, January 2001 TDA 5204 E1 preliminary Reference 5.4 Bill of Materials The following components are necessary for evaluation of the TDA5204 at 390MHz without use of a Microchip HCS515 decoder. Table 5-4 Bill of Materials Ref Value Specification R1 100k 0805, 5% R2 100k 0805, 5% R3 820k 0805, 5% R4 120k 0805, 5% R5 180k 0805, 5% R6 10k 0805, 5% L1 15nH Toko, PTL2012-F15N0G L2 10pF C1 1.8pF 0805, COG, 0.1pF C2 6.8pF 0805, COG, 0.1pF C3 6.8pF 0805, COG, 0.1pF C4 100pF 0805, COG, 5% C5 47nF 1206, X7R, 10% 0805,COG, 2% a C6 12nH C7 100pF 0805, COG, 5% C8 33pF 0805, COG, 5% C9 100pF 0805, COG, 5% C10 10nF 0805, X7R, 10% C11 10nF 0805, X7R, 10% C12 220pF 0805, COG, 5% C13 47nF 0805, X7R, 10% C14 470pF 0805, COG, 5% C15 47nF 0805, X7R, 10% C16 12pF 0805, COG, 0.1pF C17 12pF 0805, COG, 2% Q2 (390MHz + 10.7MHz)/32 HC49/U, fundamental mode, CL = 12pF, 12.521875 MHz: Jauch Q12.521875-S11-1252-12-10/20 F1 SFE10.7MA5-A Murata X2, X3 142-0701-801 Johnson Toko, PTL2012-F15N0G b X1, X4, S1, S5 2-pole pin connector S4 3-pole pin connector, or not equipped IC1 TDA 5204 Infineon a. / b. The coil is at the place of the capacity and vice versa. Wireless Components 5 - 11 Specification, January 2001 TDA 5204 E1 preliminary Reference The following components are necessary in addition to the above mentioned ones for evaluation of the TDA5204 in conjunction with a Microchip HCS515 decoder. Table 5-5 Bill of Materials Addendum Ref Value Specification R21 22k 0805, 5% R22 100k 0805, 5% R23 22k 0805, 5% R24 820k 0805, 5% R25 560k 0805, 5% C21 100nF 1206, X7R, 10% C22 100nF 1206, X7R, 10% IC2 HCS515 Microchip T1 BC 847B Infineon D1 LS T670-JL Infineon Wireless Components 5 - 12 Specification, January 2001 TDA 5204 E1 preliminary List of Figures List of Figures Figure 2-1 P-TSSOP-28-1 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 Figure 3-1 IC Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Figure 3-2 Main Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 Figure 4-1 LNA Automatic Gain Control Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 Figure 4-2 RSSI Level an Permissive AGC Threhold Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Figure 4-3 Data Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 Figure 4-4 Determination of Series Capacitance Value for the Quartz Oscillator . . . . . . . . . . . . . . 4-5 Figure 4-5 Data Slicer Threshold Generation with External R-C Integrator . . . . . . . . . . . . . . . . . . 4-7 Figure 4-6 Data Slicer Threshold Generation Utilising the Peak Detector . . . . . . . . . . . . . . . . . . . 4-7 Figure 5-1 Schematic of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-8 Figure 5-2 Top Side of the Evaluation Board (TDA5210 Testboard is the same) . . . . . . . . . . . . . . 5-9 Figure 5-3 Bottom Side of the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-9 Figure 5-4 Component Placement on the Evaluation Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-10 Wireless Components List of Figures - 1 Specification, December 2000 TDA 5204 E1 preliminary List of Tables List of Tables Table 3-1 Pin Definition and Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Table 3-3 PDWN Pin Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 Table 5-1 Absolute Maximum Ratings, Ambient temperature TAMB=-40C ... + 85C . . . . . . . . . 5-2 Table 5-2 Operating Range, Ambient temperature TAMB= -40C ... + 85C . . . . . . . . . . . . . . . . . 5-3 Table 5-3 AC/DC Characteristics with TA 25 C, VVCC = 4.5 ... 5.5 V . . . . . . . . . . . . . . . . . . . . . 5-4 Table 5-4 Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-11 Table 5-5 Bill of Materials Addendum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-12 Wireless Components List of Tables - 1 Specification, December 2000