74ALVCH16373TX_NL - Fairchild Semiconductor

October 2001

Revised February 2002

74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold

74ALVCH16373

Low Voltage 16-Bi t Transparent Latch with Bushold

General Description

The ALVCH16373 contains sixteen non-inverting latches

with 3-STATE outputs and is intended for bus oriented

applications. The device is byte controlled. The flip-flops

appear to be transparent to the data when the Latch

Enable (LE) is HIGH. When LE is LOW, the data that meets

the setup time is latched. Data appears on the bus when

the Output Enable (OE) is LOW. When OE is HIGH, the

outputs are in a high impedance state.

The ALVCH16373 data inputs include active bushold cir-

cuitry, eliminating the need for external pull-up resistors to

hold unused or floating data inputs at a valid logic level.

The 74ALVCH1 6373 is designe d for low voltage (1.65V to

3.6V) VCC applications with output compatibility up to 3.6V.

The 74ALVCH16373 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Features

■1.65V to 3.6V VCC supply operation

■3.6V tolerant control inputs and outputs

■Bushold on data inputs eliminates the need for external

pull-up/pull-down resistors

■tPD (In to On)

3.6 ns max for 3.0V to 3.6V VCC

4.5 ns max for 2.3V to 2.7V VCC

6.8 ns max for 1.65V to 1.95V VCC

■Uses patente d noise /E MI reducti o n circuitr y

■Latch-up conforms to JEDEC JED78

■ESD performa nce :

Human body model > 2000V

Machine model > 200V

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending suffix let te r “X” to the ord ering code.

Logic Symbol

Order Number Package

Number Package Description

74ALVCH16373T MTD48 48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

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74ALVCH16373

Connection Diagram Pin Descriptio ns

Truth Tables

H = HIGH Voltage Level

L = LO W Voltage Level

X = Immaterial (HIGH or LOW, control inputs may not float)

Z = High Impedance

O0 = Previous O0 bef ore HIGH-t o-LOW of Lat c h Enable

Pin Names Description

OEnOutput Enable Input (Active LOW)

LEnLatch Enable Input

I0–I15 Bushold Inputs

O0–O15 Outputs

NC No Connect

Inputs Outputs

LE1OE1I0–I7O0–O7

XHXZ

HLLL

HLHH

LLXO

Inputs Outputs

LE2OE2I8–I15 O8–O15

XHXZ

HLLL

HLHH

LLXO

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74ALVCH16373

Functional Description

The 74ALVCH163 73 contains sixteen edge D-type latches

with 3-STATE outputs. The device is byte controlled with

each byte functioning identically, but independent of the

other. Control pins can be shorted together to obtain full

16-bit operation. The following description applies to each

byte. When the Latch Enable (LEn) input is HIGH, data on

the In enters the latches. In this condition the latches are

transparent, i.e., a lat ch output will change state e ach time

its I input changes. When LEn is LOW, the latches store

information that was present on the I inputs a setup time

preceding the HIGH-to-LOW transition on LEn. The

3-STATE outputs are controlled by the Output Enable

(OEn) input. When OEn is LOW the standard outputs are in

the 2-state mode. When OEn is HIGH, the standard outputs

are in th e h igh i mp eda nce m ode bu t th i s d oes no t interfere

with entering new data into the latches.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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74ALVCH16373

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions (Note 3)

Note 1: The Absolute Maximum Ratings are those values beyond which

the saf ety of the device cannot be gu aranteed. Th e device shoul d not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the Absolute Maximum Rat-

ings. The “Recommended Operating Conditions” table will define the condi-

tio ns f or actual de v ice oper ation.

Note 2: IO Absolute Maximum Rating must be observed.

Note 3: Floating or unused inputs must be held HIGH or LOW.

DC Electrical Characteristics

Supply Voltage (VCC)−0.5V to +4.6V

DC In put Voltage (VI)−0.5V to 4.6V

Output Voltage (VO) (Note 2) −0.5V to VCC +0.5V

DC Input Diode Current (IIK)

VI < 0V −50 mA

DC Output Diode Current (IOK)

VO < 0V −50 mA

DC Output Source/Sink Current

(IOH/IOL)±50 mA

DC VCC or GND Current per

Supply Pin (ICC or GND) ±100 mA

Storage Temperature Range (TSTG)−65°C to +150°C

Power Supply

Operating 1.65V to 3.6V

Input Voltage (VI) 0V to VCC

Output Voltage (VO) 0V to VCC

Free Air Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆t/∆V)

VIN = 0.8V to 2.0V, VCC = 3.0V 10 ns/V

Symbol Parameter Conditions VCC Min Max Units

(V)

VIH HIGH Level Input Voltage 1.65 -1.95 0.65 x VCC V2.3 - 2.7 1.7

2.7 - 3.6 2.0

VIL LOW Level Input Voltage 1.65 -1.95 0.35 x VCC V2.3 - 2.7 0.7

2.7 - 3.6 0.8

VOH HIGH Level Output Voltage IOH = −100 µA 1.65 - 3.6 VCC - 0.2

IOH = −4 mA 1.65 1.2

IOH = −6 mA 2.3 2

IOH = −12 mA 2.3 1.7

2.7 2.2

3.0 2.4

IOH = −24 mA 3.0 2

VOL LOW Level Output Voltage IOL = 100 µA 1.65 - 3.6 0.2

IOL = 4 mA 1.65 0.45

IOL = 6 mA 2.3 0.4

IOL = 12mA 2.3 0.7

2.7 0.4

IOL = 24 mA 3 0.55

IIInput Leakage Current 0 ≤ VI ≤ 3.6V 3.6 ±5.0 µA

II(HOLD) Bushold Input Minimum VIN = 0.58V 1.65 25

µA

Drive Hold Current VIN = 1.07V 1.65 −25

VIN = 0.7V 2.3 45

VIN = 1.7V 2.3 −45

VIN = 0.8V 3.0 75

VIN = 2.0V 3.0 −75

0 < VO ≤ 3.6V 3.6 ±500

IOZ 3-STATE Output Leakage 0 ≤ VO ≤ 3.6V 3.6 ±10 µA

ICC Quiescent Supply Current VI = VCC or GND, IO = 0 3.6 40 µA

∆ICC Increase in ICC per Input VIH = VCC − 0.6V 3 -3.6 750 µA

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74ALVCH16373

AC Electrical Characteristics

Capacitance

Symbol Parameter

T A = −40°C to +85°C, RL = 500Ω

Units

CL = 50 pF CL = 30 pF

V CC = 3.3V ± 0.3V V CC = 2.7V V CC = 2.5V ± 0.2V V CC = 1.8V ± 0.15V

Min Max Min Max Min Max Min Max

tWPulse W idth 3.3 3.3 3.3 4.0 ns

tSSetup Time 1.1 1 1 2.5 ns

tHHold Time 1.4 1.7 1.5 1.0 ns

tPHL, tPLH Propagation Delay In to On1.1 3.6 4.3 1 4.5 1.5 6.8 ns

tPHL, tPLH Propagation Delay LE to On13.9 4.614.91.57.8ns

tPZL, tPZH Output Enable Time 1.0 4.7 5.7 1.0 6.0 1.5 9.2 ns

tPLZ, tPHZ Output Disable Time 1.4 4.1 4.5 1.2 5.1 1.5 6.8 ns

Symbol Parameter Conditions TA = +25°C Units

VCC Typical

CIN Input Capacitance Control VI = 0V or VCC 3.3 3 pF

Data VI = 0V or VCC 3.3 6

COUT Output Capacitance VI = 0V or VCC 3.3 7 pF

CPD Power Dissipation Capacitance Outputs Enabled f = 10 MHz, CL = 50 pF 3.3 22

2.5 19

Outputs Disabled f = 10 MHz, CL = 50 pF 3.3 5

2.5 4

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74ALVCH16373

AC Loading and Waveforms

FIGURE 1. AC Test Circuit

TABLE 1. Values for Figure 1

TABLE 2. Var ia ble Matrix

(Input Characteristics: f = 1MHz; tr = tf = 2ns; Z0 = 50Ω)

FIGURE 2. Waveform for Inverting and

Non-In verting Functions FIGURE 3. 3-STATE Output HIGH Enable and

Disable Times for Low Voltage Logic

FIGURE 4. 3-STATE Output LOW Enable and Disable Times for Low Voltage Logic

FIGURE 5. Propagation Delay, Pulse Width and

tREC Waveforms

FIGURE 6. Setup Time, Hold Time and

Recovery Time for Low Voltage Logic

TEST SWITCH

tPLH, tPHL Open

tPZL, tPLZ VL

tPZH, tPHZ GND

Symbol VCC

3.3V ± 0.3 V 2.7V 2.5V ± 0.2V 1.8V ± 0.15V

Vmi 1.5V 1.5V VCC/2 VCC/2

Vmo 1.5V 1.5V VCC/2 VCC/2

VXVOL + 0.3V VOL + 0.3V VOL + 0.15V VOL + 0.15V

VYVOH − 0.3V VOH − 0.3V VOH − 0.15V VOH − 0.15V

VL6V 6V VCC*2 VCC*2

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74ALVCH16373 Low Voltage 16-Bit Transparent Latch with Bushold

Physical Dimensions inches (millimeters) unless otherwise noted

48-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 6.1mm Wide

Package Number MTD48

Fairchild does not assume an y responsibility for u se of any circuitry described, no circuit patent license s are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

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to perform when properly used in accordance with

instruct ions fo r use pr ovi de d in the l abe ling, can be rea-

sonably expected to result in a significant injury to the

user.

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