LTC2315-12 12-Bit, 5Msps Serial Sampling ADC in TSOT FEATURES n n n n n n n n n n n n DESCRIPTION 5Msps Throughput Rate Guaranteed 12-Bit No Missing Codes Internal Reference: 2.048V/4.096V Span Low Noise: 73dB SNR Low Power: 6.4mA at 5Msps and 5V Dual Supply Range: 3V/5V operation Sleep Mode with < 1A Typical Supply Current Nap Mode with Quick Wake-up < 1 conversion Separate 1.8V to 5V Digital I/O Supply High Speed SPI-Compatible Serial I/O Guaranteed Operation from -40C to 125C 8-Lead TSOT-23 Package The LTC(R)2315-12 is a 12-bit, 5Msps, serial sampling A/D converter that draws only 6.4mA from a wide range analog supply adjustable from 2.7V to 5.25V. The LTC2315-12 contains an integrated bandgap and reference buffer which provide a low cost, high performance (20ppm/C max) and space saving applications solution. The LTC2315-12 achieves outstanding AC performance of 72.6dB SINAD and -84dB THD while sampling a 500kHz input frequency. The extremely high sample rate-to-power ratio makes the LTC2315-12 ideal for compact, low power, high speed systems. The LTC2315-12 also provides both nap and sleep modes for further optimization of the device power within a system. APPLICATIONS n n n n n n n The LTC2315-12 has a high-speed SPI-compatible serial interface that supports 1.8V, 2.5V, 3V and 5V logic. The fast 5Msps throughput makes the LTC2315-12 ideally suited for a wide variety of high speed applications. Communication Systems High Speed Data Acquisition Handheld Terminal Interface Medical Imaging Uninterrupted Power Supplies Battery Operated Systems Automotive Complete 14-/12-Bit Pin-Compatible SAR ADC Family 500ksps L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners. 2.5Msps 4.5Msps 5Msps 14-Bit LTC2312-14 LTC2313-14 LTC2314-14 12-Bit LTC2312-12 LTC2313-12 LTC2315-12 Power 3V/5V 9mW/15mW 14mW/25mW 18mW/31mW 19mW/32mW TYPICAL APPLICATION 5V Supply, Internal Reference, 5Msps, 12-bit Sampling ADC 0 VDD -20 CS 2.2F ANALOG INPUT 0V TO 4.096V VDD = 5V SNR = 73.1dBFS SINAD = 72.6dBFS THD = -84dB SFDR = 87dBc LTC2315-12 REF SCK GND SDO AIN SERIAL DATA LINK TO ASIC, PLD, MPU, DSP OR SHIFT REGISTERS OVDD 2.2F DIGITAL OUTPUT SUPPLY 1.8V TO 5V AMPLITUDE (dBFS) 5V 2.2F 16k Point FFT, fS = 5Msps, fIN = 500kHz -40 -60 -80 -100 -120 231512 TA01 -140 0 500 1000 2000 1500 FREQUENCY (kHz) 2500 231512 TA01a 231512fa For more information www.linear.com/LTC2315-12 1 LTC2315-12 ABSOLUTE MAXIMUM RATINGS (Notes 1, 2) PIN CONFIGURATION Supply Voltage (VDD, OVDD)........................................6V Reference (REF) and Analog Input (AIN) Voltage (Note 3).......................................(-0.3V) to (VDD + 0.3V) Digital Input Voltage (Note 3)... (-0.3V) to (OVDD + 0.3V) Digital Output Voltage.............. (-0.3V) to (OVDD + 0.3V) Power Dissipation................................................100mW Operating Temperature Range LTC2315C................................................. 0C to 70C LTC2315I...............................................-40C to 85C LTC2315H........................................... -40C to 125C Storage Temperature Range................... -65C to 150C Lead Temperature Range (Soldering, 10 sec)......... 300C TOP VIEW VDD REF GND AIN 1 2 3 4 8 7 6 5 CS SCK SDO OVDD TS8 PACKAGE 8-LEAD PLASTIC TSOT-23 TJMAX = 150C, JA = 195C/W ORDER INFORMATION Lead Free Finish TAPE AND REEL (MINI) TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE LTC2315CTS8-12#TRMPBF LTC2315CTS8-12#TRPBF LTFZG 8-Lead Plastic TSOT-23 0C to 70C LTC2315ITS8-12#TRMPBF LTC2315ITS8-12#TRPBF LTFZG 8-Lead Plastic TSOT-23 LTC2315HTS8-12#TRMPBF LTC2315HTS8-12#TRPBF LTFZG 8-Lead Plastic TSOT-23 TRM = 500 pieces. *Temperature grades are identified by a label on the shipping container. Consult LTC Marketing for parts specified with wider operating temperature ranges. Consult LTC Marketing for information on lead based finish parts. For more information on lead free part marking, go to: http://www.linear.com/leadfree/ For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ -40C to 85C -40C to 125C 231512fa 2 For more information www.linear.com/LTC2315-12 LTC2315-12 ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER VAIN Absolute Input Range VIN Input Voltage Range IIN Analog Input DC Leakage Current CIN Analog Input Capacitance CONDITIONS MIN l (Note 11) TYP UNITS -0.05 VDD + 0.05 V 0 VREF V 1 A -1 l MAX Sample Mode Hold Mode 13 3 pF pF CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS Resolution No Missing Codes MIN l 12 l 12 TYP MAX UNITS Bits Bits Transition Noise (Note 6) 0.33 LSBRMS INL Integral Linearity Error VDD = 5V (Note 5) VDD = 3V (Note 5) l l -1.25 -1.5 0.25 0.3 1.25 1.5 LSB LSB DNL Differential Linearity Error VDD = 5V VDD = 3V l l -0.99 -0.99 0.15 0.2 0.99 0.99 LSB LSB Offset Error VDD = 5V VDD = 3V l l -4 -6 0.5 1 4 6 LSB LSB Full-Scale Error VDD = 5V VDD = 3V l l -7 -9 1.5 2 7 9 LSB LSB Total Unadjusted Error VDD = 5V VDD = 3V l l -8 -10 2 2.5 8 10 LSB LSB DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C and AIN = -1dBFS. (Note 4) SYMBOL PARAMETER CONDITIONS MIN TYP fIN = 500kHz, VDD = 5V fIN = 500kHz, VDD = 3V l l SINAD Signal-to-(Noise + Distortion) Ratio SNR MAX UNITS 69.5 67.5 72.6 69.5 dB dB Signal-to-Noise Ratio fIN = 500kHz, VDD = 5V fIN = 500kHz, VDD = 3V l l 70 68 73 70 dB dB THD Total Harmonic Distortion First 5 Harmonics fIN = 500kHz, VDD = 5V fIN = 500kHz, VDD = 3V l l -84 -84 -76 -75 dB dB SFDR Spurious Free Dynamic Range fIN = 500kHz, VDD = 5V fIN = 500kHz, VDD = 3V l l 87 87 78 77 dB dB IMD Intermodulation Distortion 2nd Order Terms 3rd Order Terms fIN1 = 461kHz, fIN2 = 541kHz AIN1, AIN2 = -7dBFS -77 -89 dBc dBc Full Power Bandwidth At 3dB At 0.1dB 130 20 MHz MHz -3dB Input Linear Bandwidth SINAD 68dB 5 MHz tAP Aperture Delay 1 ns tJITTER Aperture Jitter 10 psRMS 231512fa For more information www.linear.com/LTC2315-12 3 LTC2315-12 REFERENCE INPUT/OUTPUT The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER VREF CONDITIONS VREF Output Voltage 2.7V VDD 3.6V 4.75 VDD 5.25V VREF Temperature Coefficient l l MIN TYP MAX UNITS 2.040 4.080 2.048 4.096 2.056 4.112 V V 7 20 l ppm/C VREF Output Resistance Normal Operation Overdrive Condition (VREFIN VREFOUT + 50mV) 2 52 k VREF Line Regulation 2.7V VDD 3.6V 4.75 VDD 5.25V 2 0.8 mV/V mV/V 4.15 V VREF 2.048V/4.096V Supply Threshold VREF 2.048V/4.096V Supply Threshold Hysteresis VREF Input Voltage Range (External Reference Input) 150 2.7V VDD 3.6V 4.75 VDD 5.25V l l VREF + 50mV VREF + 50mV mV V V VDD 4.3 DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS MIN VIH High Level Input Voltage l VIL Low Level Input Voltage l IIN Digital Input Current l -10 OVDD-0.2 CIN Digital Input Capacitance High Level Output Voltage IO = -500A (Source) l MAX UNITS 0.8 * OVDD VIN = 0V to OVDD VOH TYP V 0.2 * OVDD V 10 A 5 VOL Low Level Output Voltage IO = 500A (Sink) l IOZ High-Z Output Leakage Current VOUT = 0V to OVDD, CS = High l COZ High-Z Output Capacitance CS = High ISOURCE Output Source Current ISINK Output Sink Current pF V -10 0.2 V 10 A 4 pF VOUT = 0V, OVDD = 1.8V -20 mA VOUT = OVDD = 1.8V 20 mA POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER VDD Supply Voltage 3V Operational Range 5V Operational Range OVDD CONDITIONS Digital Output Supply Voltage MIN TYP MAX UNITS l l 2.7 4.75 3 5 3.6 5.25 V V l 1.71 Supply Current, Static Mode ITOTAL = IVDD + IOVDD Operational Mode Nap Mode Sleep Mode CS = 0V, SCK = 0V l l PD CS = 0V, SCK = 0V l l Power Dissipation, Static Mode Operational Mode Nap Mode Sleep Mode l l 5.25 V 3.5 6.4 1.8 0.8 4 7.5 mA mA mA A 17.5 32 9 4 20 37.5 5 25 mW mW mW W 231512fa 4 For more information www.linear.com/LTC2315-12 LTC2315-12 ADC TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. (Note 4) SYMBOL PARAMETER CONDITIONS fSAMPLE(MAX) Maximum Sampling Frequency fSCK Shift Clock Frequency tSCK Shift Clock Period MIN TYP MAX UNITS (Notes 7, 8) l 5 MHz (Notes 7, 8) l 87.5 MHz l tTHROUGHPUT Minimum Throughput Time, tACQ + tCONV 11.4 ns 200 l ns tCONV Conversion Time l 160 ns l 40 ns (Note 7) l 5 ns 5 Acquisition Time Minimum CS Pulse Width t2 SCK Setup Time After CS (Note 7) l t3 SDO Enable Time After CS (Notes 7, 8) l 10 ns t4 SDO Data Valid Access Time after SCK (Notes 7, 8, 9) l 9.1 ns tACQ t1 ns t5 SCLK Low Time l 4.5 ns t6 SCLK High Time l 4.5 ns t7 SDO Data Valid Hold Time After SCK (Notes 7, 8, 9) l 1 ns t8 SDO into Hi-Z State Time After 16th SCK (Notes 7, 8, 10) l 3 10 ns t9 SDO into Hi-Z State Time After CS (Notes 7, 8, 10) l 3 10 ns t10 CS Setup Time After 14th SCK (Note 7) l 5 Latency l ns 1 Cycle Latency tWAKE_NAP Power-Up Time from Nap Mode See Nap Mode Section 50 ns tWAKE_SLEEP Power-Up Time from Sleep Mode See Sleep Mode Section 1.1 ms Note 1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2. All voltage values are with respect to ground. Note 3. When these pin voltages are taken below ground or above VDD (AIN, REF) or OVDD (SCK, CS, SDO) they will be clamped by internal diodes. This product can handle input currents up to 100mA below ground or above VDD or OVDD without latch-up. Note 4. VDD = 5V, OVDD = 2.5V, fSMPL = 5MHz, fSCK = 87.5MHz, AIN = -1dBFS and internal reference unless otherwise noted. Note 5. Integral nonlinearity is defined as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve. The deviation is measured from the center of the quantization band. Note 6. Typical RMS noise at code transitions. Note 7. Parameter tested and guaranteed at OVDD = 2.5V. All input signals are specified with tr = tf = 1nS (10% to 90% of OVDD) and timed from a voltage level of OVDD/2. Note 8. All timing specifications given are with a 10pF capacitance load. Load capacitances greater than this will require a digital buffer. Note 9. The time required for the output to cross the VIH or VIL voltage. Note 10. Guaranteed by design, not subject to test. Note 11. Recommended operating conditions. 231512fa For more information www.linear.com/LTC2315-12 5 LTC2315-12 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps, unless otherwise noted. Differential Nonlinearity vs Output Code 1.0 0.8 0.8 0.6 0.6 0.4 0.4 0.2 0.2 0.0 -0.2 -0.6 -0.6 -0.8 -0.8 2048 3072 OUTPUT CODE -1.0 4096 40000 20000 10000 0 1024 2048 3072 OUTPUT CODE 231512 G01 16k Point FFT, fS = 5Msps fIN = 500kHz -40 -60 -80 -100 74 0 500 1000 2000 1500 INPUT FREQUENCY (kHz) SINAD 71 -80 VDD = 5V SNR VDD = 3V 69 2500 SINAD 0 2500 THD 3RD -90 -95 1500 2000 500 1000 INPUT FREQUENCY (kHz) 2500 231512 G06a 231512 G03 2ND 3RD 0 1500 2000 500 1000 INPUT FREQUENCY (kHz) 73 -75 72 SINAD 71 70 SNR 68 -55 -35 -15 THD, Harmonics vs Temperature, fIN = 500kHz VDD = 3V -80 VDD = 5V SNR VDD = 3V SINAD 2500 231512 G06 SNR, SINAD vs Temperature, fIN = 500kHz -85 -90 THD 2ND 3RD -95 69 0 2051 -90 -100 74 -85 THD -85 231512 G05 75 2ND 2050 -95 1500 2000 500 1000 INPUT FREQUENCY (kHz) 231512 G04 SNR, SINAD (dBFS) RIN/CIN = 50/47pF fS = 5Msps VDD = 5V 2049 CODE 2048 RIN/CIN = 50/47pF fS = 5Msps VDD = 3V -80 70 -75 THD, HARMONICS (dB) SNR 72 THD, Harmonics vs Input Frequency (100kHz to 2.2MHz) -100 -75 73 -120 -140 2047 THD, Harmonics vs Input Frequency (100kHz to 2.2MHz) THD, HARMONICS (dB) AMPLITUDE (dBFS) SNR, SINAD vs Input Frequency (100kHz to 2.2MHz) VDD = 5V SNR = 73.1dBFS SINAD = 72.6dBFS THD = -84dB SFDR = 87dBc -20 0 4096 231512 G02 SNR, SINAD (dBFS) 0 30000 THD, HARMONICS (dB) 1024 = 0.33 50000 -0.2 -0.4 0 60000 0.0 -0.4 -1.0 DC Histogram Near Mid-Scale (Code 2048) COUNTS 1.0 DNL (LSB) INL (LSB) Integral Nonlinearity vs Output Code 5 25 45 65 85 105 125 TEMPERATURE (C) 231512 G07 -100 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 231512 G08 231512fa 6 For more information www.linear.com/LTC2315-12 LTC2315-12 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps, unless otherwise noted. 74 VDD = 5V Reference Current vs Reference Voltage 600 fS = 5Msps SNR -80 73 SNR, SINAD (dBFS) THD, HARMONICS (dB) SNR, SINAD vs Reference Voltage fIN = 500kHz THD -85 3RD -90 2ND VDD = 3.6V -100 -55 -35 -15 70 5 25 45 65 85 105 125 TEMPERATURE (C) SINAD SINAD OPERATION NOT ALLOWED 71 -95 VDD = 5V SNR 72 500 REFERENCE CURRENT (A) -75 THD, Harmonics vs Temperature, fIN = 500kHz 2 2.5 3 3.5 4 REFERENCE VOLTAGE (V) VDD = 3.6V 300 Full-Scale Error vs Temperature OPERATION NOT ALLOWED 100 0 2 2.5 3 3.5 4 REFERENCE VOLTAGE (V) Offset Error vs Temperature Supply Current vs Temperature 6.5 3 6.25 0 -1 -2 0.5 SUPPLY CURRENT (mA) OFFSET ERROR (LSB) 1 4.5 231512 G11 1 2 fS = 3Msps fS = 3Msps 231512 G10 4 VDD = 5V 200 4.5 231512 G08a 0 -0.5 VDD = 5V 6 5.75 5.5 VDD = 3V 5.25 -3 -4 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) -1 -55 -35 -15 SUPPLY CURRENT (mA) 6 0.75 0.5 VDD = 3V VDD = 3V OVDD = 1.8V 5 ITOT 4 IVDD 3 2 1 VDD = 5V 0 -55 -35 -15 231512 G14 Supply Current vs SCK Frequency 7 IVDD + IOVDD 0.25 5 25 45 65 85 105 125 TEMPERATURE (C) 231512 G13 Shutdown Current vs Temperature 1 5 -55 -35 -15 5 25 45 65 85 105 125 TEMPERATURE (C) 231512 G12 SHUTDOWN CURRENT (A) FULL-SCALE ERROR (LSB) fS = 5Msps 400 0 5 25 45 65 85 105 125 TEMPERATURE (C) 10 IOVDD 20 231512 G15 30 40 50 60 70 SCK FREQUENCY (MHz) 80 90 231512 G16 231512fa For more information www.linear.com/LTC2315-12 7 LTC2315-12 TYPICAL PERFORMANCE CHARACTERISTICS unless otherwise noted. 6.00 5Msps 5.75 fSCK = 87.5MHz 5.50 5.25 Output Supply Current (IOVDD) vs Output Supply Voltage (OVDD) 5Msps 6.25 SUPPLY CURRENT (mA) 2.5 OPERATION NOT ALLOWED 3Msps 5.00 3Msps fSCK = 52.5MHz 4.75 4.50 2.6 2.9 3.2 3.5 3.8 4.1 4.4 4.7 5.0 5.3 SUPPLY VOLTAGE (V) OUTPUT SUPPLY CURRENT (mA) 6.50 Supply Current (IVDD) vs Supply Voltage (VDD) TA = 25C, VDD = 5V, OVDD = 2.5V, fSMPL = 5Msps, 2.0 5Msps fSCK = 87.5MHz 1.5 1.0 3Msps fSCK = 52.5MHz 0.5 0 1.7 2.3 2.9 3.5 4.1 4.7 OUTPUT SUPPLY VOLTAGE (V) 5.3 231512 G18 231512 G17 PIN FUNCTIONS VDD (Pin 1): Power Supply. The ranges of VDD are 2.7V to 3.6V and 4.75V to 5.25V. Bypass VDD to GND with a 2.2F ceramic chip capacitor. REF (Pin 2): Reference Input/Output. The REF pin voltage defines the input span of the ADC, 0V to VREF. By default, REF is an output pin and produces a reference voltage VREF of either 2.048V or 4.096V depending on VDD (see Table 2). Bypass to GND with a 2.2F, low ESR, high quality ceramic chip capacitor. The REF pin may be overdriven with a voltage at least 50mV higher than the internal reference voltage output. GND (Pin 3): Ground. The GND pin must be tied directly to a solid ground plane. AIN (Pin 4): Analog Input. AIN is a single-ended input with respect to GND with a range from 0V to VREF. SDO (Pin 6): Serial Data Output. The A/D conversion result is shifted out on SDO as a serial data stream with the MSB first through the LSB last. There is 1 cycle of conversion latency. Logic levels are determined by OVDD. SCK (Pin 7): Serial Data Clock Input. The SCK serial clock falling edge advances the conversion process and outputs a bit of the serialized conversion result, MSB first to LSB last. SDO data transitions on the falling edge of SCK. A continuous or burst clock may be used. Logic levels are determined by OVDD. CS (Pin 8): Chip Select Input. This active low signal starts a conversion on the falling edge and frames the serial data transfer. Bringing CS high places the sample-and-hold into sample mode and also forces the SDO pin into high impedance. Logic levels are determined by OVDD. OVDD (Pin 5): I/O Interface Digital Power. The OVDD range is 1.71V to 5.25V. This supply is nominally set to the same supply as the host interface (1.8V, 2.5V, 3.3V or 5V). Bypass to GND with a 2.2F ceramic chip capacitor. 231512fa 8 For more information www.linear.com/LTC2315-12 LTC2315-12 BLOCK DIAGRAM 2.2F 2.2F ANALOG SUPPLY RANGE 2.7V TO 5.25V DIGITAL SUPPLY RANGE 1.71V TO 5.25V 1 5 VDD OVDD 2.5V LDO ANALOG INPUT RANGE 0V TO VREF AIN + 4 THREE-STATE SERIAL OUTPUT PORT 12-BIT SAR ADC S/H - SDO 6 REF SCK 2 2.2F GND 2x/4x 3 7 TIMING LOGIC 1.024V BANDGAP CS 8 TS8 PACKAGE 231512 BD ALL CAPACITORS UNLESS NOTED ARE HIGH QUALITY, CERAMIC CHIP TYPE TIMING DIAGRAMS SCK 16TH EDGE t8 t9 CS OVDD/2 Hi-Z SDO OVDD/2 Hi-Z SDO Figure 1. SDO Into Hi-Z after 16TH SCK Figure 2. SDO Into Hi-Z after CS 231512 TD01 231512 TD02 t7 SCK t4 SCK OVDD/2 V SDO OH VOL OVDD/2 VOH SDO Figure 3. SDO Data Valid Hold after SCK VOL Figure 4. SDO Data Valid Access after SCK 231512 TD03 t10 CS tCONV = 13.5 * tSCK + t2 + t10 t2 1 2 3 t5 t3 0 (MSB) B10 tACQ-MIN 4 t4 B11* tACQ-MIN = 40ns tCONV t6 SCK SDO 231512 TD04 B9 12 13 14 t9 t7 B0 0 HI-Z STATE tTHROUGHPUT *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION Figure 5: LTC2315-12 Serial Interface Timing Diagram (SCK Low During tACQ) For more information www.linear.com/LTC2315-12 231512 TD05 231512fa 9 LTC2315-12 TIMING DIAGRAMS t10 CS tCONV(MIN) = 13 * tSCK + t2 + t10 t2 SCK t6 1 2 SDO 0 3 0 tACQ-MIN 4 5 t5 t3 tACQ-MIN = 40ns tCONV t4 B11* B10 13 14 t9 t7 B9 B1 (MSB) B0 0 HI-Z STATE tTHROUGHPUT *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231512 TD06 Figure 6: LTC2315-12 Serial Interface Timing Diagram (SCK High During tACQ) CS tCONV = 14 * tSCK t2 SCK t6 18 1 2 SDO 3 4 t5 t3 0 0 B11* B10 B9 tACQ t10 5 t4 (MSB) tACQ = 4 * tSCK tCONV 13 14 15 16 17 18 t9 t7 B1 B0 0 HI-Z STATE tTHROUGHPUT = 18 * tSCK *NOTE: SDO REPRESENTS THE ANALOG INPUT FROM THE PREVIOUS CONVERSION 231512 TD07 Figure 7: LTC2315-12 Serial Interface Timing Diagram (SCK Continuous) 231512fa 10 For more information www.linear.com/LTC2315-12 LTC2315-12 APPLICATIONS INFORMATION Overview The LTC(R)2315-12 is a low noise, high speed, 12-bit successive approximation register (SAR) ADC. The LTC2315-12 operates over a wide supply range (2.7V to 5.25V) and provides a low drift (20ppm/C maximum), internal reference and reference buffer. The internal reference buffer is automatically configured to a 2.048V span in low supply range (2.7V to 3.6V) and to a 4.096V span in the high supply range (4.75V to 5.25V). The LTC2315-12 samples at a 5Msps rate and supports an 87.5MHz data clock. The LTC2315-12 achieves excellent dynamic performance (73dB SNR, 84dB THD) while dissipating only 32mW from a 5V supply at the 5Msps conversion rate. The LTC2315-12 outputs the conversion data with one cycle of conversion latency on the SDO pin. The SDO pin output logic levels are supplied by the dedicated OVDD supply pin which has a wide supply range (1.71V to 5.25V) allowing the LTC2315-12 to communicate with 1.8V, 2.5V, 3V or 5V systems. The LTC2315-12 provides both nap and sleep power-down modes through serial interface control to reduce power dissipation during inactive periods. Serial Interface The LT2315-12 communicates with microcontrollers, DSPs and other external circuitry via a 3-wire interface. A falling CS edge starts a conversion and frames the serial data transfer. SCK provides the conversion clock for the current sample and controls the data readout on the SDO pin of the previous sample. CS transitioning low clocks out the first leading zero and subsequent SCK falling edges clock out the remaining data as shown in Figures 5, 6 and 7 for three different timing schemes. Data is serially output MSB first through LSB last, followed by trailing zeros if further SCK falling edges are applied. Figure 5 illustrates that during the case where SCK is held low during the acquisition phase, only one leading zero is output. Figures 6 and 7 illustrate that for the SCK held high during acquisition or continuous clocking mode two leading zeros are output. Leading zeros allow the 12-bit data result to be framed with both leading and trailing zeros for timing and data verification. Since the rising edge of SCK will be coincident with the falling edge of CS, delay t2 is the delay to the first falling edge of SCK, which is simply 0.5 * tSCK. Delays t2 (CS falling edge to SCK leading edge) and t10 (14th falling SCK edge to CS rising edge) must be observed for Figures 5, 6 and 7 and any timing implementation in order for the conversion process and data readout to occur correctly. The user can bring CS high after the 14th falling SCK edge provided that timing delay t10 is observed. Prematurely terminating the conversion by bringing CS high before the 14th falling SCK edge plus delay t10 will cause a loss of conversion data for that sample. The sample-and-hold is placed in sample mode when CS is brought high. As shown in Figure 6, a sample rate of 5Msps can be achieved on the LTC2315-12 by using an 87.5MHz SCK data clock and a minimum acquisition time of 40ns which results in the minimum throughput time (tTHROUGHPUT) of 200ns. Note that the maximum throughput of 5Msps can only be achieved with the timing implementation of SCK held high during acquisition as shown in Figure 6. The LTC2315-12 also supports a continuous data clock as shown in Figure 7. With a continuous data clock the acquisition time period and conversion time period must be designed as an exact integer number of data clock periods. Because the minimum acquisition time is not an exact multiple of the minimum SCK period, the maximum sample rate for the continuous SCK timing is less than 5Msps. For example, a 4.86Msps throughput is achieved using exactly 18 data clock periods with the maximum data clock frequency of 87.5MHz. For this particular case, the acquisition time period and conversion clock period are designed as 4 data clock periods (TACQ = 45.7ns) and 14 data clock periods (TCONV = 160ns) respectively, yielding a throughput time of 205.7ns. 231512fa For more information www.linear.com/LTC2315-12 11 LTC2315-12 APPLICATIONS INFORMATION The following table illustrates the maximum throughput achievable for each of the three timing patterns. Note that in order to achieve the maximum throughput rate of 5Msps, the timing pattern where SCK is held high during the acquisition time must be used. Table 1: Maximum Throughput vs Timing Pattern TIMING PATTERN MAXIMUM THROUGHPUT SCK high during TACQ 5Msps SCK low during TACQ 4.86Msps SCK continuous (tTHROUGHPUT = 18 periods) 4.86Msps Serial Data Output (SDO) The SDO output is always forced into the high impedance state while CS is high. The falling edge of CS starts the conversion and enables SDO. The A/D conversion result is shifted out on the SDO pin as a serial data stream with the MSB first. The data stream consists of either one leading zero (SCK held low during acquisition, Fig. 5) or two leading zeros (SCK held high during acquisition, Fig. 6) followed by 12 bits of conversion data. There is 1 cycle of conversion latency. Subsequent falling SCK edges after the LSB is output will output zeros on the SDO pin. The SDO output returns to the high impedance state after the 16th falling edge of SCK. digital logic operating between 1.8V and 5V, including 2.5V and 3.3V systems. Entering Nap/Sleep Mode Pulsing CS two times and holding SCK static places the LTC2315-12 into nap mode. Pulsing CS four times and holding SCK static places the LTC2315-12 into sleep mode. In sleep mode, all bias circuitry is shut down, including the internal bandgap and reference buffer, and only leakage currents remain (0.8A typical). Because the reference buffer is externally bypassed with a large capacitor (2.2F), the LTC2315-12 requires a significant wait time (1.1ms) to recharge this capacitance before an accurate conversion can be made. In contrast, nap mode does not power down the internal bandgap or reference buffer allowing for a fast wake-up and accurate conversion within one conversion clock cycle. Supply current during nap mode is nominally 1.8mA. Exiting Nap/Sleep Mode The output swing on the SDO pin is controlled by the OVDD pin voltage and supports a wide operating range from 1.71V to 5.25V independent of the VDD pin voltage. Waking up the LTC2315-12 from either nap or sleep mode, as shown in Figures 8 and 9, requires SCK to be pulsed one time. A conversion may be started immediately following nap mode as shown in Figure 8. A period of time allowing the reference voltage to recover must follow waking up from sleep mode as shown in Figure 9. The wait period required before initiating a conversion for the recommended value of CREF of 2.2F is 1.1ms. Power Considerations Power Supply Sequencing The LTC2315-12 provides two sets of power supply pins: the analog 5V power supply (VDD) and the digital input/ output interface power supply (OVDD). The flexible OVDD supply allows the LTC2315-12 to communicate with any The LTC2315-12 does not have any specific power supply sequencing requirements. Care should be taken to observe the maximum voltage relationships described in the Absolute Maximum Ratings section. 231512fa 12 For more information www.linear.com/LTC2315-12 LTC2315-12 APPLICATIONS INFORMATION 1 CS 2 NAP MODE SCK START tACQ HOLD STATIC HIGH or LOW Z SDO 0 Z HOLD STATIC HIGH or LOW HI-Z STATE 0 231512 F08 Figure 8: LTC2315-12 Entering/Exiting Nap Mode 1 CS 2 3 4 VREF RECOVERY NAP MODE SCK SDO SLEEP MODE tWAIT START tACQ HOLD STATIC HIGH or LOW Z 0 Z 0 HI-Z STATE 231512 F09 Figure 9: LTC2315-12 Entering/Exiting Sleep Mode Single-Ended Analog Input Drive Choosing an Input Amplifier The analog input of the LTC2315-12 is easy to drive. The input draws only one small current spike while charging the sample-and-hold capacitor at the end of conversion. During the conversion, the analog input draws only a small leakage current. If the source impedance of the driving circuit is low, then the input of the LTC2315-12 can be driven directly. As the source impedance increases, so will the acquisition time. For minimum acquisition time with high source impedance, a buffer amplifier should be used. The main requirement is that the amplifier driving the analog input must settle after the small current spike before the next conversion starts. Settling time must be less than tACQ-MIN (40ns) for full performance at the maximum throughput rate. While choosing an input amplifier, also keep in mind the amount of noise and harmonic distortion the amplifier contributes. Choosing an input amplifier is easy if a few requirements are taken into consideration. First, to limit the magnitude of the voltage spike seen by the amplifier from charging the sampling capacitor, choose an amplifier that has a low output impedance (<50) at the closed-loop bandwidth frequency. For example, if an amplifier is used in a gain of 1 and has a unity-gain bandwidth of 100MHz, then the output impedance at 100MHz must be less than 50. The second requirement is that the closed-loop bandwidth must be greater than 100MHz to ensure adequate small signal settling for full throughput rate. If slower op amps are used, more time for settling can be provided by increasing the time between conversions. The best choice for an op amp to drive the LTC2315-12 will depend on the application. Generally, applications fall into two categories: AC applications where dynamic specifications are most 231512fa For more information www.linear.com/LTC2315-12 13 LTC2315-12 APPLICATIONS INFORMATION critical and time domain applications where DC accuracy and settling time are most critical. The following list is a summary of the op amps that are suitable for driving the LTC2315-12. (More detailed information is available on the Linear Technology website at www.linear.com.) LT6230: 215MHz GBWP, -80dBc Distortion at 1MHz, Unity-Gain Stable, Rail-to-Rail Input and Output, 3.5mA/ Amplifier, 1.1nV/Hz. LT6200: 165MHz GBWP, -85dBc Distortion at 1MHz, UnityGain Stable, R-R In and Out, 15mA/Amplifier, 0.95nV/Hz. LT1818/LT1819: 400MHz GBWP, -85dBc Distortion at 5MHz, Unity-Gain Stable, 9mA/Amplifier, Single/Dual Voltage Mode Operational Amplifier. Input Drive Circuits The analog input of the LTC2315-12 is designed to be driven single-ended with respect to GND. A low impedance source can directly drive the high impedance analog input of the LTC2315-12 without gain error. A high impedance source should be buffered to minimize settling time during acquisition and to optimize the distortion performance of the ADC. For best performance, a buffer amplifier should be used to drive the analog input of the LTC2315-12. The amplifier provides low output impedance to allow for fast settling of the analog signal during the acquisition phase. It also provides isolation between the signal source and the ADC inputs which draw a small current spike during acquisition. Input Filtering The noise and distortion of the buffer amplifier and other circuitry must be considered since they add to the ADC noise and distortion. Noisy input circuitry should be filtered prior to the analog inputs to minimize noise. A simple 1-pole RC filter is sufficient for many applications. A simple 1-pole RC filter is sufficient for many applications. For example, Figure 10 shows a recommended single-ended buffered drive circuit using the LT1818 in unity gain mode. The 47pF capacitor from AIN to ground and 50 source resistor limits the input bandwidth to 68MHz. The 47pF capacitor also acts as a charge reservoir for the input sample-and-hold and isolates the LT1818 from sampling glitch kick-back. The 50 source resistor is used to help stabilize the settling response of the drive amplifier. When choosing values of source resistance and shunt capacitance, the drive amplifier data sheet should be consulted and followed for optimum settling response. If lower input bandwidths are desired, care should be taken to optimize the settling response of the driver amplifier with higher values of shunt capacitance or series resistance. High quality capacitors and resistors should be used in the RC filter since these components can add distortion. NP0/C0G and silver mica type dielectric capacitors have excellent linearity. Carbon surface mount resistors can generate distortion from self heating and from damage that may occur during soldering. Metal film surface mount resistors are much less susceptible to both problems. When high amplitude unwanted signals are close in frequency to the desired signal frequency, a multiple pole filter is required. High external source resistance, combined with external shunt capacitance at Pin 4 and 13pF of input capacitance on the LTC2315-12 in sample mode, will significantly reduce the internal 130MHz input bandwidth and may increase the required acquisition time beyond the minimum acquisition time (tACQ-MIN) of 40ns. ANALOG IN Large filter RC time constants slow down the settling at the analog inputs. It is important that the overall RC time constants be short enough to allow the analog inputs to completely settle to >12-bit resolution within the minimum acquisition time (tACQ-MIN) of 40ns. + - LT1818 LTC2315-12 50 AIN 47pF GND 2315112 F10 Figure 10. RC Input Filter 231512fa 14 For more information www.linear.com/LTC2315-12 LTC2315-12 APPLICATIONS INFORMATION ADC Reference A low noise, low temperature drift reference is critical to achieving the full data sheet performance of the ADC. The LTC2315-12 provides an excellent internal reference with a guaranteed 20ppm/C maximum temperature coefficient. For added flexibility, an external reference may also be used. The high speed, low noise internal reference buffer is used only in the internal reference configuration. The reference buffer must be overdriven in the external reference configuration with a voltage 50mV higher than the nominal reference output voltage in the internal configuration. Using the Internal Reference The internal bandgap and reference buffer are active by default when the LTC2315-12 is not in sleep mode. The reference voltage at the REF pin scales automatically with the supply voltage at the VDD pin. The scaling of the reference voltage with supply is shown in the following table. the internal reference voltage (see Table 2) and must be less than or equal to the supply voltage (or 4.3V for the 5V supply range). For example, a 3.3V external reference may be used with a 3.3V VDD supply voltage to provide a 3.3V analog input voltage span (i.e. 3.3V > 2.048V + 50mV). Or alternatively, a 2.5V reference may be used with a 3V supply voltage to provide a 2.5V input voltage range (i.e. 2.5V > 2.048V + 50mV). The LTC6655-3.3, LTC6655-2.5, available from Linear Technology, may be suitable for many applications requiring a high performance external reference for either 3.3V or 2.5V input spans respectively. Transfer Function Figure 11 depicts the transfer function of the LTC2315-12. The code transitions occur midway between successive integer LSB values (i.e. 0.5LSB, 1.5LSB, 2.5LSB... FS0.5LSB). The output code is straight binary with 1LSB = VREF/4,096. Table 2: Reference Voltage vs Supply Range REF VOLTAGE (VREF) 111...111 2.7V -> 3.6V 2.048V 111...110 4.75V -> 5.25V 4.096V The reference voltage also determines the full-scale analog input range of the LTC2315-12. For example, a 2.048V reference voltage will accommodate an analog input range from 0V to 2.048V. An analog input voltage that goes below 0V will be coded as all zeros and an analog input voltage that exceeds 2.048V will be coded as all ones. It is recommended that the REF pin be bypassed to ground with a low ESR, 2.2F ceramic chip capacitor for optimum performance. OUTPUT CODE SUPPLY VOLTAGE (VDD) 000...001 000...000 0 1LSB FS - 1LSB INPUT VOLTAGE (V) 231512 F11 Figure 11. LTC2315-12 Transfer Function External Reference DC Performance An external reference can be used with the LTC2315-12 if better performance is required or to accommodate a larger input voltage span. The only constraints are that the external reference voltage must be 50mV higher than The noise of an ADC can be evaluated in two ways: signal-tonoise ratio (SNR) in the frequency domain and histogram in the time domain. The LTC2315-12 excels in both. The noise in the time domain histogram is the transition noise associated 231512fa For more information www.linear.com/LTC2315-12 15 LTC2315-12 APPLICATIONS INFORMATION with a 12-bit resolution ADC which can be measured with a fixed DC signal applied to the input of the ADC. The resulting output codes are collected over a large number of conversions. The shape of the distribution of codes will give an indication of the magnitude of the transition noise. In Figure 12, the distribution of output codes is shown for a DC input that has been digitized 16,384 times. The distribution is Gaussian and the RMS code transition noise is 0.33LSB. This corresponds to a noise level of 73dB relative to a full scale voltage of 4.096V. 60000 = 0.33 ENOB = (SINAD - 1.76)/6.02 At the maximum sampling rate of 5MHz, the LTC2315-12 maintains an ENOB above 11.7 bits up to the Nyquist input frequency of 2.5MHz. (Figure 14) The signal-to-noise ratio (SNR) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components except the first five harmonics and DC. Figure 13 shows that the LTC2315-12 achieves a typical SNR of 73dB at a 5MHz sampling rate with a 500kHz input frequency. 40000 COUNTS The effective number of bits (ENOB) is a measurement of the resolution of an ADC and is directly related to SINAD by the equation where ENOB is the effective number of bits of resolution and SINAD is expressed in dB: Signal-to-Noise Ratio (SNR) 50000 30000 20000 10000 0 Effective Number of Bits (ENOB) 2047 2048 2049 CODE 2050 2051 231512 F12 Figure 12. Histogram for 16384 Conversions Dynamic Performance The LTC2315-12 has excellent high speed sampling capability. Fast Fourier Transform (FFT) techniques are used to test the ADC's frequency response, distortion and noise at the rated throughput. By applying a low distortion sine wave and analyzing the digital output using an FFT algorithm, the ADC's spectral content can be examined for frequencies outside the applied fundamental. The LTC2315-12 provides guaranteed tested limits for both AC distortion and noise measurements. Signal-to-Noise and Distortion Ratio (SINAD) The signal-to-noise and distortion ratio (SINAD) is the ratio between the RMS amplitude of the fundamental input frequency and the RMS amplitude of all other frequency components at the A/D output. The output is band-limited to frequencies from above DC and below half the sampling frequency. Figure 14 shows the LTC2315-12 maintains a SINAD above 71dB up to the Nyquist input frequency of 2.5MHz. Total Harmonic Distortion (THD) Total Harmonic Distortion (THD) is the ratio of the RMS sum of all harmonics of the input signal to the fundamental itself. The out-of-band harmonics alias into the frequency band between DC and half the sampling frequency (fSMPL/2). THD is expressed as: THD=20log V22 + V32 + V42 + VN2 V1 where V1 is the RMS amplitude of the fundamental frequency and V2 through VN are the amplitudes of the second through Nth harmonics. THD versus Input Frequency is shown in the Typical Performance Characteristics section. The LTC2315-12 has excellent distortion performance up to the Nyquist frequency. Intermodulation Distortion (IMD) If the ADC input signal consists of more than one spectral component, the ADC transfer function nonlinearity can produce intermodulation distortion (IMD) in addition to THD. IMD is the change in one sinusoidal input caused by the presence of another sinusoidal input at a different frequency. 231512fa 16 For more information www.linear.com/LTC2315-12 LTC2315-12 APPLICATIONS INFORMATION 0 -20 AMPLITUDE (dBFS) If two pure sine waves of frequencies fa and fb are applied to the ADC input, nonlinearities in the ADC transfer function can create distortion products at the sum and difference frequencies m * fa n * fb , where m and n = 0, 1, 2, 3, etc. For example, the 2nd order IMD terms include (fa fb). If the two input sine waves are equal in magnitude, the value (in decibels) of the 2nd order IMD products can be expressed by the following formula: VDD = 5V SNR = 73.1dBFS SINAD = 72.6dBFS THD = -84dB SFDR = 87dBc -40 -60 -80 -100 -120 -140 IMD(fa fb) = 20 * log[VA (fa fb)/VA (fa)] 0 500 1000 2000 1500 FREQUENCY (kHz) The LTC2315-12 has excellent IMD as shown in Figure 15. 2500 231512 F13 Figure 13. 16k Point FFT of the LTC2315-12 at fIN = 500 kHz 11.8 The spurious free dynamic range is the largest spectral component excluding DC, the input signal and the harmonics included in the THD. This value is expressed in decibels relative to the RMS value of a full-scale input signal. 72 11.7 Full-Power and Full-Linear Bandwidth 71 11.5 12.0 74 73 ENOB SINAD (dBFS) VDD = 5V VDD = 3V 11.3 70 69 0 1500 2000 500 1000 INPUT FREQUENCY (kHz) 11.2 2500 231512 F14 Figure 14. LTC2315-12 ENOB/SINAD vs fIN 0 VDD = 5V fS = 5Msps fa = 461.421kHz fb = 541.421kHz IMD2 (fb + fa) = -77.4dBc IMD3 (2fb -fa) = -89.4dBc -20 -40 MAGNITUDE (dB) Spurious Free Dynamic Range (SFDR) -60 -80 -100 -120 -140 -160 0 1500 2000 500 1000 INPUT FREQUENCY (kHz) 2500 231512 F15 Figure 15. LTC2315-12 IMD Plot The full-power bandwidth is the input frequency at which the amplitude of the reconstructed fundamental is reduced by 3dB for a full-scale input signal. The full-linear bandwidth is the input frequency at which the SINAD has dropped to 68dB (11 effective bits). The LTC2315-12 has been designed to optimize the input bandwidth, allowing the ADC to under-sample input signals with frequencies above the converter's Nyquist frequency. The noise floor stays very low at high frequencies and SINAD becomes dominated by distortion at frequencies beyond Nyquist. Recommended Layout To obtain the best performance from the LTC2315-12 a printed circuit board is required. Layout for the printed circuit board (PCB) should ensure the digital and analog signal lines are separated as much as possible. In particular, care should be taken not to run any digital clocks or signals alongside analog signals or underneath the ADC. The following is an example of a recommended PCB layout. A single solid ground plane is used. Bypass capacitors to the supplies are placed as close as possible to the supply pins. Low impedance common returns for these bypass capacitors are essential to the low noise operation of the 231512fa For more information www.linear.com/LTC2315-12 17 LTC2315-12 APPLICATIONS INFORMATION ADC. The analog input traces are screened by ground. For more details and information refer to DC1563, the evaluation kit for the LTC2315-12. parator. The problem can be eliminated by forcing the microprocessor into a "Wait" state during conversion or by using three-state buffers to isolate the ADC data bus. Bypassing Considerations High quality tantalum and ceramic bypass capacitors should be used at the VDD, OVDD and REF pins. For optimum performance, a 2.2F ceramic chip capacitor should be used for the VDD and OVDD pins. The recommended bypassing for the REF pin is also a low ESR, 2.2F ceramic capacitor. The traces connecting the pins and the bypass capacitors must be kept as short as possible and should be made as wide as possible avoiding the use of vias. The following is an example of a recommended PCB layout. All analog circuitry grounds should be terminated at the LTC2315-12. The ground return from the LTC2315-12 to the power supply should be low impedance for noise free operation. Digital circuitry grounds must be connected to the digital supply common. In applications where the ADC data outputs and control signals are connected to a continuously active microprocessor bus, it is possible to get errors in the conversion results. These errors are due to feed-through from the microprocessor to the successive approximation com- Figure 17. Layer 1 Top Layer Figure 18. Layer 2 GND Plane Figure 16. Top Silkscreen 231512fa 18 For more information www.linear.com/LTC2315-12 LTC2315-12 APPLICATIONS INFORMATION Figure 19. Layer 3 PWR Plane Figure 20. Layer 4 Bottom Layer REF U5 LT1790ACS6-2.048 9V TO 10V 4 VI GND GND 1 2 JP1 HD1X3-100 J4 AIN 0V TO 4.096V C6 4.7F R14 0k VO AC R9 1k C8 10F VCCIO C9 4.7F C10 OPT C11 OPT C12 4.7F DC COUPLING 1 2 3 C18 OPT C7 OPT VDD VCM 6 + R15 49.9 C17 1F 3 2 1 U1 * 4 C19 47pF NPO JP2 VCM 1.024V 1 2 5 VDD REF OVDD AIN CSL SCK GND 3 SDO 231512 F21 8 CSL 7 SCK SDO 6 R16 33 2.048V HD1X3-100 R18 1k Figure 21. Partial DC1563 Demo Board Schematic 231512fa For more information www.linear.com/LTC2315-12 19 LTC2315-12 PACKAGE DESCRIPTION Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. TS8 Package 8-Lead Plastic TSOT-23 (Reference LTC DWG # 05-08-1637 Rev A) 0.40 MAX 2.90 BSC (NOTE 4) 0.65 REF 1.22 REF 1.4 MIN 3.85 MAX 2.62 REF 2.80 BSC 1.50 - 1.75 (NOTE 4) PIN ONE ID RECOMMENDED SOLDER PAD LAYOUT PER IPC CALCULATOR 0.22 - 0.36 8 PLCS (NOTE 3) 0.65 BSC 0.80 - 0.90 0.20 BSC 0.01 - 0.10 1.00 MAX DATUM `A' 0.30 - 0.50 REF 0.09 - 0.20 (NOTE 3) 1.95 BSC TS8 TSOT-23 0710 REV A NOTE: 1. DIMENSIONS ARE IN MILLIMETERS 2. DRAWING NOT TO SCALE 3. DIMENSIONS ARE INCLUSIVE OF PLATING 4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR 5. MOLD FLASH SHALL NOT EXCEED 0.254mm 6. JEDEC PACKAGE REFERENCE IS MO-193 231512fa 20 For more information www.linear.com/LTC2315-12 LTC2315-12 REVISION HISTORY REV DATE A 10/13 DESCRIPTION PAGE NUMBER Added pin-compatible family table 1 Changed TJMAX to 150C 2 Changed SINAD condition for -3dB Input Linear Bandwidth to 68dB 3, 16 Reordered/Renumbered Notes 3, 4, 5 231512fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of itsinformation circuits as described herein will not infringe on existing patent rights. For more www.linear.com/LTC2315-12 21 LTC2315-12 TYPICAL APPLICATION Low-Jitter Clock Timing with RF Sine Generator Using Clock Squaring/Level-Shifting Circuit and Re-Timing Flip-Flop VCC 0.1F 50 1k NC7SVU04P5X MASTER CLOCK VCC 1k PRE D > Q CONV CLR NL17SZ74 CONV ENABLE CONTROL LOGIC (FPGA, CPLD, DSP, ETC.) CS SCK LTC2315-12 NC7SVUO4P5X SDO 33 231512 TA03 RELATED PARTS PART NUMBER DESCRIPTION COMMENTS LTC2313-12 12-Bit, 2.5Msps Serial ADC 3V/5V, 14mW/25mW, 20ppm/C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC2312-12 12-Bit, 500ksps Serial ADC 3V/5V, 9mW/15mW, 20ppm/C Max Internal Reference, Single-Ended Input, 8-Lead TSOT-23 Package LTC1403/LTC1403-1 12-Bit, 2.8Msps Serial ADC 3V, 14mW, Unipolar/Bipolar Inputs, MSOP Package LTC1407/LTC1407-1 12-Bit, 3Msps Simultaneous Sampling ADC 3V, 2-Channel Differential, Unipolar/Bipolar Inputs, 14mW, MSOP Package LTC2355/LTC2356 12-/14-Bit, 3.5Msps Serial ADC 3.3V Supply, Differential, Input, 18mW, MSOP Package LTC2365/LTC2366 12-Bit, 1Msps/3Msps Serial Sampling ADC 3.3V Supply, 8mW, TSOT-23 Package LT6236/LT6237 Single/Dual Operation Amplifier with Low Wideband Noise 215MHz, 3.5mA/Amplifier, 1.1nV/Hz LT6200/LT6201 Single/Dual Operational Amplifiers 165MHz, 0.95nV/Hz LT6230/LT6231 Single/Dual Operational Amplifiers 215MHz, 3.5mA/Amplifier, 1.1nV/Hz LT1818/LT1819 Single/Dual Operational Amplifiers 400MHz, 9mA/Amplifier, 6nV/Hz ADCs Amplifiers References LTC6655-2.5/LTC6655-3.3 Precision Low Drift Low Noise Buffered Reference 2.5V/3.3V, 5ppm/C, 0.25ppm Peak-to-Peak Noise, MSOP-8 Package LT1461-3/LT1461-3.3V Precision Series Voltage Family 0.05% Initial Accuracy, 3ppm Drift 231512fa 22 Linear Technology Corporation 1630 McCarthy Blvd., Milpitas, CA 95035-7417 For more information www.linear.com/LTC2315-12 (408) 432-1900 FAX: (408) 434-0507 www.linear.com/LTC2315-12 LT 1013 REV A * PRINTED IN USA LINEAR TECHNOLOGY CORPORATION 2013