1
Features
•High-density, High-performance, Electrically-erasable
Complex Programmable Logic Device
– 3.0V to 3.6V Operating Range
– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 84, 100, 160 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources
•Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register within a COM Output
•Advanced Power Management Features
– Automatic 5 µA Standby for “L” Version
– Pin-controlled 100 µA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell
•Available in Commercial and Industrial Temperature Ranges
•Available in 84-lead PLCC and 100-lead PQFP and TQFP and
160-lead PQFP Packages
•Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
•JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
•Fast In-System Programmability (ISP) via JTAG
•PCI-compliant
•Security Fuse Feature
•Green (Pb/Halide-free/RoHS Compliant) Package Options
Enhanced Features
•Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
•Output Enable Product Terms
•Transparent-latch Mode
•Combinatorial Output with Registered Feedback within Any Macrocell
•Three Global Clock Pins
•ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
•Fast Registered Input from Product Term
•Programmable “Pin-keeper” Option
•VCC Power-up Reset Option
•Pull-up Option on JTAG Pins TMS and TDI
•Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts
High-
performance
EE PLD
ATF1508ASV
ATF1508ASVL
Rev. 1408H–PLD–7/05
2ATF1508ASV(L)
1408H–PLD–7/05
84-lead PLCC
Top View
100-lead TQFP
Top View
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
I/O/PD1
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
11
10
9
8
7
6
5
4
3
2
1
84
83
82
81
80
79
78
77
76
75
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
33
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
100-lead PQFP
Top View
160-lead PQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
I/O
I/O/PD1
I/O
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O/TMS
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD2
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
N/C
N/C
N/C
N/C
N/C
N/C
N/C
VCCIO
I/O/TDI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O/TMS
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
N/C
GND
I/O/TDO
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O/TCK
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
N/C
N/C
N/C
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
I/O
GND
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
GND
VCCINT
I/O
I/O/PD1
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
VCCIO
I/O
I/O
I/O/PD2
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
N/C
N/C
N/C
N/C
I/O
I/O
I/O
3
ATF1508ASV(L)
1408H–PLD–7/05
Block Diagram
6 to 12
4ATF1508ASV(L)
1408H–PLD–7/05
Description The ATF1508ASV(L) is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable technology. With 128
logic macrocells and up to 100 inputs, it easily integrates logic from several TTL, SSI,
MSI, LSI and classic PLDs. The ATF1508ASV(L)’s enhanced routing switch matrices
increase usable gate count and increase odds of successful pin-locked design
modifications.
The ATF1508ASV(L) has up to 96 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 128 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also gener-
ates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1508ASV(L) allows fast, efficient generation of complex logic func-
tions. The ATF1508ASV(L) contains eight such logic chains, each capable of creating
sum term logic with a fan-in of up to 40 product terms.
The ATF1508ASV(L) macrocell, shown in Figure 1, is flexible enough to support highly-
complex logic functions operating at high-speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
Unused macrocells are automatically disabled by the compiler to decrease power con-
sumption. A security fuse, when programmed, protects the contents of the
ATF1508ASV(L). Two bytes (16 bits) of User Signature are accessible to the user for
purposes such as storing project name, part number, revision or date. The User Signa-
ture is accessible regardless of the state of the security fuse.
The ATF1508ASV(L) device is an in-system programmable (ISP) device. It uses the
industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with
JTAG’s Boundary-scan Description Language (BSDL). ISP allows the device to be pro-
grammed without removing it from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to be made in the field via
software.
Product Terms and Select
Mux
Each ATF1508ASV(L) macrocell has five product terms. Each product term receives as
its inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
OR/XOR/CASCADE Logic The ATF1508ASV(L)’s logic structure is designed to efficiently support all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with little additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
5
ATF1508ASV(L)
1408H–PLD–7/05
Flip-flop The ATF1508ASV(L)’s flip-flop has very flexible data and control functions. The data
input can come from either the XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows creation of a buried registered
feedback within a combinatorial output macrocell. (This feature is automatically imple-
mented by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can
also be configured as a flow-through latch. In this mode, data passes through when the
clock is high and is latched when the clock is low.
The clock itself can either be the Global CLK Signal (GCK) or an individual product term.
The flip-flop changes state on the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be selected as a clock enable. When
the clock enable function is active and the enable signal (product term) is low, all clock
edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be either the Glo-
bal Clear (GCLEAR), a product term, or always off. AR can also be a logic OR of
GCLEAR with a product term. The asynchronous preset (AP) can be a product term or
always off.
Figure 1. ATF1508ASV(L) Macrocell
6ATF1508ASV(L)
1408H–PLD–7/05
Extra Feedback The ATF15xxSE Family macrocell output can be selected as registered or combinato-
rial. The extra buried feedback signal can be either combinatorial or a registered signal
regardless of whether the output is combinatorial or registered. (This enhancement
function is automatically implemented by the fitter software.) Feedback of a buried com-
binatorial output allows the creation of a second latch within a macrocell.
I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be
individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subset of the I/O macrocells. This selection is
automatically done by the fitter software when the I/O is configured as an input, all mac-
rocell resources are still available, including the buried feedback, expander and cascade
logic.
Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback sig-
nal from all 128 macrocells. The switch matrix in each logic block receives as its inputs
all signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.
Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to 16 macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback terms in each region allow generation of
high fan-in sum terms (up to 21 product terms) with little additional delay.
Open-collector Output Option This option enables the device output to provide control signals such as an interrupt that
can be asserted by any of the several devices.
7
ATF1508ASV(L)
1408H–PLD–7/05
Programmable Pin-
keeper Option for
Inputs and I/Os
The ATF1508ASV(L) offers the option of programming all input and I/O pins so that “pin-
keeper” circuits can be utilized. When any pin is driven high or low and then subse-
quently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Input Diagram
Speed/Power
Management
The ATF1508ASV(L) has several built-in speed and power management features. The
ATF1508ASV(L) contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power con-
sumption during inactive periods, but also provides proportional power-savings for most
applications running at system speeds below 5 MHz.
To further reduce power, each ATF1508ASV(L) macrocell has a reduced-power bit fea-
ture. This feature allows individual macrocells to be configured for maximum power-
savings. This feature may be selected as a design option.
I/O Diagram
8ATF1508ASV(L)
1408H–PLD–7/05
All ATF1508 also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down fea-
ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the AC
parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH and tSEXP.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
Design Software
Support
ATF1508ASV(L) designs are supported by several third-party tools. Automated fitters
allow logic synthesis using a variety of high-level description languages and formats.
Power-up Reset The ATF1508ASV is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from VCC crossing VRST, all registers will be ini-
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how VCC actually rises in the
system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3. The clock must remain stable during TD.
The ATF1508ASV has two options for the hysteresis about the reset level, VRST, Small
and Large. To ensure a robust operating environment in applications where the device
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on the command line after “file-
name.POF”. To allow the registers to be properly reinitialized with the Large hysteresis
option selected, the following condition is added:
4. If VCC falls below 2.0V, it must shut off completely before the device is turned on
again.
When the Large hysteresis option is active, ICC is reduced by several hundred micro-
amps as well.
Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1508ASV(L) fuse
patterns. Once programmed, fuse verify is inhibited. However, User Signature and
device ID remains accessible.
9
ATF1508ASV(L)
1408H–PLD–7/05
Programming ATF1508ASV(L) devices are in-system programmable (ISP) devices utilizing the 4-pin
JTAG protocol. This capability eliminates package handling normally required for pro-
gramming and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the
ATF1508ASV(L) via the PC. ISP is performed by using either a download cable, a com-
parable board tester or a simple microprocessor interface.
To allow ISP programming support by the Automated Test Equipment (ATE) vendors,
Serial Vector Format (SVF) files can be created by the Atmel ISP software. Conversion
to other ATE tester format beside SVF is also possible
ATF1508ASV(L) devices can also be programmed using standard third-party program-
mers. With third-party programmer, the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming
Protection
The ATF1508ASV(L) has a special feature that locks the device and prevents the inputs
and I/O from driving if the programming process is interrupted for any reason. The
inputs and I/O default to high-Z state during such a condition. In addition the pin-keeper
option preserves the former state during device programming.
All ATF1508ASV(L) devices are initially shipped in the erased state thereby making
them ready to use for ISP.
Note: For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
10 ATF1508ASV(L)
1408H–PLD–7/05
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
2. ICC3 refers to the current in the reduced-power mode when macrocell reduced-power is turned ON.
Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. The OGI pin (high-voltage pin
during programming) has a maximum capacitance of 12 pF.
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C -40°C - 85°C
VCC (3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
IIL Input or I/O Low
Leakage Current VIN = VCC -2 -10 µA
IIH
Input or I/O High
Leakage Current 210µA
IOZ
Tri-State Output
Off-State Current VO = VCC or GND -40 40 µA
ICC1
Power Supply
Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode Com. 115 mA
Ind. 135 mA
“L” Mode Com. 5 µA
Ind. 5 µA
ICC2 Power Supply Current,
Power-down Mode
VCC = Max
VIN = 0, VCC
“PD” Mode 0.1 5 mA
ICC3(2) Reduced-power Mode
Supply Current, Standby
VCC = Max
VIN = 0, VCC
Std Mode Com. 60 mA
Ind. 80 mA
VIL Input Low Voltage -0.3 0.8 V
VIH Input High Voltage 1.7 VCCIO + 0.3 V
VOL
Output Low Voltage (TTL) VIN = VIH or VIL
VCC = Min, IOL = 8 mA
Com. 0.45 V
Ind. 0.45 V
Output Low Voltage (CMOS) VIN = VIH or VIL
VCC = Min, IOL = 0.1 mA
Com. 0.2 V
Ind. 0.2 V
VOH
Output High Voltage
– 3.3V (TTL)
VIN = VIH or VIL
VCC = Min, IOH = -2.0 mA 2.4 V
Output High Voltage
– 3.3V (CMOS)
VIN = VIH or VIL
VCCIO = Min, IOH = -0.1 mA VCCIO - 0.2 V
Pin Capacitance
Typ Max Units Conditions
CIN 8pFV
IN = 0V; f = 1.0 MHz
CI/O 8pFV
OUT = 0V; f = 1.0 MHz
11
ATF1508ASV(L)
1408H–PLD–7/05
Timing Model
Absolute Maximum Ratings*
Temperature Under Bias.................................. -40°C to +85°C *NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note: 1. Minimum voltage is -0.6V DC, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is VCC + 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Input
Delay
t
IN
Switch
Matrix
t
UIM
Internal Output
Enable Delay
t
IOE
Global Control
Delay
t
GLOB
Logic Array
Delay
t
LAD
Register Control
Delay
t
LAC
t
IC
t
EN
Cascade Logic
Delay
t
PEXP
Fast Input
Delay
t
FIN
Register
Delay
t
SU
t
H
t
PRE
t
CLR
t
RD
t
COMB
t
FSU
t
FH
Output
Delay
t
OD1
t
OD2
t
OD3
t
XZ
t
ZX1
t
ZX2
t
ZX3
I/O Delay
t
IO
Foldback Term
Delay
t
SEXP
12 ATF1508ASV(L)
1408H–PLD–7/05
AC Characteristics(1)
Symbol Parameter
-15 -20
UnitsMin Max Min Max
tPD1 Input or Feedback to Non-registered Output 3 15 20 ns
tPD2 I/O Input or Feedback to Non-registered Feedback 3 12 16 ns
tSU Global Clock Setup Time 11 13.5 ns
tHGlobal Clock Hold Time 0 0 ns
tFSU Global Clock Setup Time of Fast Input 3 3 ns
tFH Global Clock Hold Time of Fast Input 1.0 2.0 MHz
tCOP Global Clock to Output Delay 9 12 ns
tCH Global Clock High Time 5 6 ns
tCL Global Clock Low Time 5 6 ns
tASU Array Clock Setup Time 5 7 ns
tAH Array Clock Hold Time 4 4 ns
tACOP Array Clock Output Delay 15 18.5 ns
tACH Array Clock High Time 6 8 ns
tACL Array Clock Low Time 6 8 ns
tCNT Minimum Clock Global Period 13 17 ns
fCNT Maximum Internal Global Clock Frequency 76.9 66 MHz
tACNT Minimum Array Clock Period 13 17 ns
fACNT Maximum Internal Array Clock Frequency 76.9 58.8 MHz
fMAX Maximum Clock Frequency 100 83.3 MHz
tIN Input Pad and Buffer Delay 2 2.5 ns
tIO I/O Input Pad and Buffer Delay 2 2.5 ns
tFIN Fast Input Delay 2 2 ns
tSEXP Foldback Term Delay 8 10 ns
tPEXP Cascade Logic Delay 1 1 ns
tLAD Logic Array Delay 6 8 ns
tLAC Logic Control Delay 3.5 4.5 ns
tIOE Internal Output Enable Delay 3 3 ns
tOD1 Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 5V; CL = 35 pF) 34ns
tOD2 Output Buffer and Pad Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) 34ns
tOD3 Output Buffer and Pad Delay
(Slow slew rate = ON; VCCIO = 5V or 3.3V; CL = 35 pF) 56ns
tZX1 Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 5.0V; CL = 35 pF) 79
13
ATF1508ASV(L)
1408H–PLD–7/05
Notes: 1. See ordering information for valid part numbers.
2. The tRPA parameter must be added to the tLAD, tLAC,tTIC, tACL, and tSEXP parameters for macrocells running in the reduced-
power mode.
Input Test Waveforms and Measurement Levels
tR, tF = 1.5 ns typical
tZX2 Output Buffer Enable Delay
(Slow slew rate = OFF; VCCIO = 3.3V; CL = 35 pF) 79ns
tZX3 Output Buffer Enable Delay
(Slow slew rate = ON; VCCIO = 5.0V/3.3V; CL = 35 pF) 10 11 ns
tXZ Output Buffer Disable Delay
(CL = 5 pF) 67ns
tSU Register Setup Time 5 6 ns
tHRegister Hold Time 4 5 ns
tFSU Register Setup Time of Fast Input 2 2 ns
tFH Register Hold Time of Fast Input 2 2 ns
tRD Register Delay 2 2.5 ns
tCOMB Combinatorial Delay 2 3 ns
tIC Array Clock Delay 6 7 ns
tEN Register Enable Time 6 7 ns
tGLOB Global Control Delay 2 3 ns
tPRE Register Preset Time 4 5 ns
tCLR Register Clear Time 4 5 ns
tUIM Switch Matrix Delay 2 2.5 ns
tRPA Reduced-Power Adder(2) 10 13 ns
AC Characteristics(1) (Continued)
Symbol Parameter
-15 -20
UnitsMin Max Min Max
14 ATF1508ASV(L)
1408H–PLD–7/05
Output AC Test Loads
Power-down Mode The ATF1508ASV(L) includes two pins for optional pin-controlled power-down feature.
When this mode is enabled, the PD pin acts as the power-down pin. When the PD1 and
PD2 pin is high, the device supply current is reduced to less than 5 mA. During power-
down, all output data and internal logic states are latched and held. Therefore, all regis-
tered and combinatorial output data remain valid. Any outputs that were in a high-Z state
at the onset will remain at high-Z. During power-down, all input signals except the
power-down pin are blocked. Input and I/O hold latches remain active to ensure that
pins do not float to indeterminate levels, further reducing system power. The power-
down pin feature is enabled in the logic design file. Designs using either power-down pin
may not use the PD pin logic array input. However, buried logic resources in this macro-
cell may still be used.
Notes: 1. For slow slew outputs, add tSSO.
2. Pin or product term.
3.0V
703
8060
Power Down AC Characteristics(1)(2)
Symbol Parameter
-15 -20
UnitsMin Max Min Max
tIVDH Valid I, I/O before PD High 15 20 ns
tGVDH Valid OE(2) before PD High 15 20 ns
tCVDH Valid Clock(2) before PD High 15 20 ns
tDHIX I, I/O Don’t Care after PD High 25 30 ns
tDHGX OE(2) Don’t Care after PD High 25 30 ns
tDHCX Clock(2) Don’t Care after PD High 25 30 ns
tDLIV PD Low to Valid I, I/O 1 1 µs
tDLGV PD Low to Valid OE (Pin or Term) 1 1 µs
tDLCV PD Low to Valid Clock (Pin or Term) 1 1 µs
tDLOV PD Low to Valid Output 1 1 µs
15
ATF1508ASV(L)
1408H–PLD–7/05
JTAG-BST Overview The JTAG-BST (JTAG boundary-scan testing) is controlled by the Test Access Port
(TAP) controller in the ATF1508ASV(L). The boundary-scan technique involves the
inclusion of a shift-register stage (contained in a boundary-scan cell) adjacent to each
component so that signals at component boundaries can be controlled and observed
using scan testing principles. Each input pin and I/O pin has its own Boundary-scan Cell
(BSC) in order to support boundary-scan testing. The ATF1508ASV(L) does not cur-
rently include a Test Reset (TRST) input pin because the TAP controller is automatically
reset at power-up. The six JTAG-BST modes supported include: SAMPLE/PRELOAD,
EXTEST, BYPASS and IDCODE. BST on the ATF1508ASV(L) is implemented using
the Boundary-scan Definition Language (BSDL) described in the JTAG specification
(IEEE Standard 1149.1). Any third-party tool that supports the BSDL format can be used
to perform BST on the ATF1508ASV(L).
The ATF1508ASV(L) also has the option of using four JTAG-standard I/O pins for in-
system programming (ISP). The ATF1508ASV(L) is programmable through the four
JTAG pins using programming-compatible with the IEEE JTAG Standard 1149.1. Pro-
gramming is performed by using 5V TTL-level programming signals from the JTAG ISP
interface. The JTAG feature is a programmable option. If JTAG (BST or ISP) is not
needed, then the four JTAG control pins are available as I/O pins.
JTAG Boundary-scan
Cell (BSC) Testing
The ATF1508ASV(L) contains up to 96 I/O pins and four input pins, depending on the
device type and package type selected. Each input pin and I/O pin has its own bound-
ary-scan cell (BSC) in order to support boundary-scan testing as described in detail by
IEEE Standard 1149.1. A typical BSC consists of three capture registers or scan regis-
ters and up to two update registers. There are two types of BSCs, one for input or I/O
pin, and one for the macrocells. The BSCs in the device are chained together through
the (BST) capture registers. Input to the capture register chain is fed in from the TDI pin
while the output is directed to the TDO pin. Capture registers are used to capture active
device data signals, to shift data in and out of the device and to load data into the update
registers. Control signals are generated internally by the JTAG TAP controller. The BSC
configuration for the input and I/O pins and macrocells are shown below.
BSC Configuration Pins and Macrocells (Except JTAG TAP Pins)
Note: The ATF1508ASV(L) has pull-up option on TMS and TDI pins. This feature is selected as a design option.
16 ATF1508ASV(L)
1408H–PLD–7/05
Boundary-scan
Definition Language
(BSDL) Models for
the ATF1508
These are now available in all package types via the Atmel web site. These models can
be used for Boundary-scan Test Operation in the ATF1508ASV(L) and have been
scheduled to conform to the IEEE 1149.1 standard.
BSC Configuration for Macrocell
0
1DQ
0
1
0
1
DQ DQ
Capture
DR
Capture
DR
Update
DR
0
1
0
1
DQ DQ
TDI
TDI
OUTJ
OEJ
Shift
Shift
Clock
Clock
Mode
TDO
TDO
Pin BSC
Macrocell BSC
Pin
Pin
17
ATF1508ASV(L)
1408H–PLD–7/05
OE (1, 2) Global OE pins
GCLR Global Clear pin
GCLK (1, 2, 3) Global Clock pins
PD (1, 2) Power-down pins
TDI, TMS, TCK, TDO JTAG pins used for boundary-scan testing or in-system programming
GND Ground pins
VCC VCC pins for the device
ATF1508ASV(L) Dedicated Pinouts
Dedicated Pin 84-lead J-lead 100-lead PQFP 100-lead TQFP 160-lead PQFP
INPUT/OE2/GCLK2 2 92 90 142
INPUT/GCLR 1 91 89 141
INPUT/OE1 84 90 88 140
INPUT/GCLK1 83 89 87 139
I/O/GCLK3 81 87 85 137
I/O/PD (1, 2) 12,45 3,43 1,41 63,159
I/O/TDI(JTAG) 14 6 4 9
I/O/TMS(JTAG) 23 17 15 22
I/O/TCK(JTAG) 62 64 62 99
I/O/TDO(JTAG) 71 75 73 112
GND 7,19,32,42,
47,59,72,82
13,28,40,45,
61,76,88,97
11,26,38,43,
59,74,86,95
17,42,60,66,95,
113,138,148
VCC 3,13,26,38,
43,53,66,78
5,20,36,41,
53,68,84,93
3,18,34,39,
51,66,82,91 8,26,55,61,79,104,133,143
N/C - - -
1,2,3,4,5,6,7,34,35,36,
37,38,39,40,44,45,46,
47,74,75,76,77,81,82,
83,84,85,86,87,114,
115,116,117,118,119,
120,124,125,126,127,
154,155,156,157
# of SIGNAL PINS 68 84 84 100
# USER I/O PINS 64 80 80 96
18 ATF1508ASV(L)
1408H–PLD–7/05
ATF1508ASV(L) I/O Pinouts
MC PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP MC PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
1 A - 4 2 160 33 C - 27 25 41
2A----34C----
3A/
PD1 12 3 1 159 35 C 31 26 24 33
4 A - - - 158 36 C - - - 32
5 A 11 2 100 153 37 C 30 25 23 31
6 A 10 1 99 152 38 C 29 24 22 30
7A----39C----
8 A 9 100 98 151 40 C 28 23 21 29
9 A - 99 97 150 41 C - 22 20 28
10A----42C----
11 A 8 98 96 149 43 C 27 21 19 27
12 A - - - 147 44 C - - - 25
13 A 6 96 94 146 45 C 25 19 17 24
14 A 5 95 93 145 46 C 24 18 16 23
15A----47C----
16 A 4 94 92 144 48 C/
TMS 23 17 15 22
17 B 22 16 14 21 49 D 41 39 37 59
18B----50D----
19 B 21 15 13 20 51 D 40 38 36 58
20 B - - - 19 52 D - - - 57
21 B 20 14 12 18 53 D 39 37 35 56
22 B - 12 10 16 54 D - 35 33 54
23B----55D----
24 B 18 11 9 15 56 D 37 34 32 53
25 B 17 10 8 14 57 D 36 33 31 52
26B----58D----
27 B 16 9 7 13 59 D 35 32 30 51
28 B - - - 12 60 D - - - 50
29 B 15 8 6 11 61 D 34 31 29 49
30 B - 7 5 10 62 D - 30 28 48
31B----63D----
32 B/
TDI 14 6 4 9 64 D 33 29 27 43
65 E 44 42 40 62 97 G 63 65 63 100
66E----98G----
19
ATF1508ASV(L)
1408H–PLD–7/05
67 E/
PD2 45 43 41 63 99 G 64 66 64 101
68 E - - - 64 100 G - - - 102
69 E 46 44 42 65 101 G 65 67 65 103
70 E - 46 44 67 102 G - 69 67 105
71E----103G----
72 E 48 47 45 68 104 G 67 70 68 106
73 E 49 48 46 69 105 G 68 71 69 107
74E----106G----
75 E 50 49 47 70 107 G 69 72 70 108
76 E - - - 71 108 G - - - 109
77 E 51 50 48 72 109 G 70 73 71 110
78 E - 51 49 73 110 G - 74 72 111
79E----111G----
80 E 52 52 50 78 112 G/
TDO 71 75 73 112
81 F - 54 52 80 113 H - 77 75 121
82F----114H----
83 F 54 55 53 88 115 H 73 78 76 122
84 F - - - 89 116 H - - - 123
85 F 55 56 54 90 117 H 74 79 77 128
86 F 56 57 55 91 118 H 75 80 78 129
87F----119H----
88 F 57 58 56 92 120 H 76 81 79 130
89 F - 59 57 93 121 H - 82 80 131
90F----122H----
91 F 58 60 58 94 123 H 77 83 81 132
92 F - - - 96 124 H - - - 134
93 F 60 62 60 97 125 H 79 85 83 135
94 F 61 63 61 98 126 H 80 86 84 136
95F----127H----
96 F/
TCK 62 64 62 99 128 H/
GCLK3 81 87 85 137
ATF1508ASV(L) I/O Pinouts (Continued)
MC PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP MC PLB
84-lead
J-lead
100-lead
PQFP
100-lead
TQFP
160-lead
PQFP
20 ATF1508ASV(L)
1408H–PLD–7/05
SUPPLY CURRENT VS. SUPPLY VOLTAGE
(TA = 25°C, F = 0)
0
100
200
2.50 2.75 3.00 3.25 3.50 3.75 4.00
SUPPLY VOLTAGE (V)
ICC (mA)
STANDARD POWER
REDUCED POWER
SUPPLY CURRENT VS. FREQUENCY
STANDARD POWER (TA = 25°C)
0.0
50.0
100.0
150.0
200.0
250.0
0.00 20.00 40.00 60.00 80.00 100.00
FREQUENCY (MHz)
ICC (mA)
STANDARD POWER
REDUCED POWER MODE
SUPPLY CURRENT VS. SUPPLY VOLTAGE
LOW POWER ("L") MODE
(TA = 25°C, F = 0)
0
1
2
3
4
5
6
7
8
9
10
2.50 2.75 3.00 3.25 3.50 3.75 4.00
SUPPLY VOLTAGE (V)
ICC (uA)
SUPPLY CURRENT VS. SUPPLY VOLTAGE
PIN-CONTROLLED POWER-DOWN MODE
(TA = 25°C, F = 0)
400
500
600
700
800
2.50 2.75 3.00 3.25 3.50 3.75 4.00
SUPPLY VOLTAGE (V)
ICC (uA)
STANDARD & REDUCED POWER MODE
SUPPLY CURRENT VS. FREQUENCY
LOW-POWER ("L") VERSION
(TA = 25°C)
0.0
25.0
50.0
75.0
100.0
125.0
0.00 5.00 10.00 15.00 20.00
FREQUENCY (MHz)
ICC (mA)
STANDARD POWER
REDUCED POWER
21
ATF1508ASV(L)
1408H–PLD–7/05
OUTPUT SOURCE CURRENT
VS. SUPPLY VOLTAGE (VOH = 2.4V, TA = 25°C)
-16
-14
-12
-10
-8
-6
-4
-2
0
2.75 3.00 3.25 3.50 3.75 4.00
SUPPLY VOLTAGE (V)
IOH
(mA)
OUTPUT SINK CURRENT
VS. SUPPLY VOLTAGE (VOL = 0.5V, TA = 25°C)
20
25
30
35
40
2.75 3.00 3.25 3.50 3.75 4.00
SUPPLY VOLTAGE (V)
IOL (mA)
INPUT CLAMP CURRENT
VS. INPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
-100
-80
-60
-40
-20
0
-1 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0
INPUT VOLTAGE (V)
INPUT CURRENT (mA)
OUTPUT SOURCE CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V,TA = 25°C)
-70
-60
-50
-40
-30
-20
-10
0
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
OUTPUT VOLTAGE (V)
IOH
(mA)
OUTPUT SINK CURRENT
VS. OUTPUT VOLTAGE (VCC = 3.3V, TA = 25°C)
0
20
40
60
80
100
0 0.5 1 1.5 2 2.5 3 3.5 4
OUTPUT VOLTAGE (V)
IOL (mA)
INPUT CURRENT vs. INPUT VOLTAGE
(VCC = 3.3V, TA = 25°C)
-10
-5
0
5
10
15
00.511.5 22.533.5
INPUT VOLTAGE (V)
INPUT CURRENT (uA)
22 ATF1508ASV(L)
1408H–PLD–7/05
Ordering Information
Note: 1. The last time buy is Sept. 30, 2005 for shaded parts.
Using “C” Product for Industrial
There is very little risk in using “C” devices for industrial applications because the VCC conditions for 3.3V products are
the same for commercial and industrial (there is only 15°C difference at the high end of the temperature range). To use
commercial product for industrial temperature ranges, de-rate ICC by 15%.
ATF1508ASV(L) Standard Package Options
tPD
(ns)
tCO1
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
15
8100
ATF1508ASV-15 JC84 84J
Commercial
(0°C to 70°C)
ATF1508ASV-15 QC100 100Q1
ATF1508ASV-15 AC100 100A
ATF1508ASV-15 QC160 160Q
8100
ATF1508ASV-15 JI84
ATF1508ASV-15 QI100
ATF1508ASV-15 AI100
ATF1508ASV-15 QI160
84J
100Q1
100A
160Q
Industrial
(-40°C to +85°C)
20
12 83.3
ATF1508ASVL-20 JC84
ATF1508ASVL-20 QC100
ATF1508ASVL-20 AC100
ATF1508ASVL-20 QC160
84J
100Q1
100A
160Q
Commercial
(0°C to 70°C)
12 83.3
ATF1508ASVL-20 JI84
ATF1508ASVL-20 QI100
ATF1508ASVL-20 AI100
ATF1508ASVL-20 QI160
84J
100Q1
100A
160Q
Industrial
(-40°C to +85°C)
ATF1508ASV(L) Green Package Options (Pb/Halide-free/RoHS Compliant)
tPD
(ns)
tCO1
(ns)
fMAX
(MHz) Ordering Code Package Operation Range
15 8 100 ATF1508ASV-15 JU84
ATF1508ASV-15 AU100
84J
100A
Industrial
(-40°C to +85°C)
20 12 83.3 ATF1508ASVL-20 JU84
ATF1508ASVL-20 AU100
84J
100A
Industrial
(-40°C to +85°C)
Package Type
84J 84-lead, Plastic J-leaded Chip Carrier (PLCC)
100Q1 100-lead, Plastic Quad Pin Flat Package (PQFP)
100A 100-lead, Very Thin Plastic Gull Wing Quad Flat Package (TQFP)
160Q 160-lead, Plastic Quad Pin Flat Package (PQFP)
23
ATF1508ASV(L)
1408H–PLD–7/05
Packaging Information
84J – PLCC
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
84J, 84-lead, Plastic J-leaded Chip Carrier (PLCC) B
84J
10/04/01
1.14(0.045) X 45˚ PIN NO. 1
IDENTIFIER
1.14(0.045) X 45˚
0.51(0.020)MAX
0.318(0.0125)
0.191(0.0075)
A2
45˚ MAX (3X)
A
A1
B1 D2/E2
B
e
E1 E
D1
D
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AF.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 30.099 – 30.353
D1 29.210 – 29.413 Note 2
E 30.099 – 30.353
E1 29.210 – 29.413 Note 2
D2/E2 27.686 – 28.702
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
24 ATF1508ASV(L)
1408H–PLD–7/05
100Q1 – PQFP
PIN 1 ID
A
0º~7º
A1
JEDEC STANDARD MS-022, GC-1
PIN 1
07/6/2005
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
100Q1, 100-lead, 14 x 20 mm Body, 3.2 mm Footprint, 0.65 mm Pitch,
Plastic Quad Flat Package (PQFP) C
100Q1
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
A – 3.04 3.4
A1 0.25 0.33 0.5
D 23.20 BSC
E 17.20 BSC
E1 14.00 BSC
B 0.22 – 0.40
C 0.11 – 0.23
D1 20 BSC
L 0.73 – 1.03
e 0.65 BSC
L
E1
C
D
D1
B
e
E
25
ATF1508ASV(L)
1408H–PLD–7/05
100A – TQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP) C
100A
10/5/2001
PIN 1 IDENTIFIER
0˚~7˚
PIN 1
L
C
A1 A2 A
D1
D
eE1 E
B
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 15.75 16.00 16.25
D1 13.90 14.00 14.10 Note 2
E 15.75 16.00 16.25
E1 13.90 14.00 14.10 Note 2
B 0.17 – 0.27
C 0.09 – 0.20
L 0.45 – 0.75
e 0.50 TYP
Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.08 mm maximum.
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL MIN NOM MAX NOTE
26 ATF1508ASV(L)
1408H–PLD–7/05
160Q – PQFP
2325 Orchard Parkway
San Jose, CA 95131
TITLE DRAWING NO.
R
REV.
160Q, 160-lead, 28 x 28 mm Body, 3.2 mm Footprint,
0.65 mm Pitch, Plastic Quad Flat Package (PQFP) B
160Q
10/23/03
31.45(1.238)
0.22(0.009)
0.40(0.016)
PIN 1 ID
0.65(0.0256)BSC
27.90(1.098)
28.10(1.106)SQ 4.10(0.161)MAX
0.25(0.010)
0.50(0.020)
0.73(0.029)
1.03(0.041)
0º~7º
0.11(0.004)
0.23(0.009)
30.95(1.218)
PIN 1
SQ
Dimensions in Millimeters and (Inches).
Controlling dimension: Millimeters.
JEDEC Standard MS-022 DC-1
27
ATF1508ASV(L)
1408H–PLD–7/05
Revision History
Revision Comments
1408H Corrected list of last buy parts.
1408G Green package options added.
Printed on recycled paper.
1408H–PLD–7/05 xM
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