* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
Document Number: MMPF0100Z
Rev. 12.0, 8/2016
NXP Semiconductors
Data sheet: Advance Information
© 2016 NXP B.V.
14 channel configurable power
management integrated circuit
The SMARTMOS PF0100Z AEC Q100 grade 2 automotive power management
integrated circuit (PMIC) provides a highly programmable/ configurable
architecture, with fully integrated power devices and minimal external
components. With up to six buck converters, six linear regulators, RTC supply,
and coin-cell charger, the PF0100Z can provide power for a complete system,
including applications processors, memory, and system peripherals, in a wide
range of applications. With on-chip one time programmable (OTP) memory, the
PF0100Z is available in pre-programmed standard versions, or non-
programmed to support custom programming. The PF0100Z is especially suited
to the i.MX 6 family of devices and is supported by full system level reference
designs, and pre-programmed versions of the device.
Features:
• Four to six buck converters, depending on configuration
• Single/dual phase/ parallel options
• DDR termination tracking mode option
• Boost regulator to 5.0 V output
• Six general purpose linear regulators
• Programmable output voltage, sequence, and timing
• OTP (one time programmable) memory for device configuration
• Coin cell charger and RTC supply
• DDR termination reference voltage
• Power control logic with processor interface and event detection
•I
2C control
• Individually programmable on, off, and standby modes
Figure 1. Simplified application diagram
POWER MANAGEMENT
PF0100Z
Applications:
•GPS
• Auto infotainment
• Heads up display (HUD)
• Rear displays
• Digital instrumentation cluster (DIC)
Automotive
ES SUFFIX (WF-TYPE)
98ASA00589D
56 QFN 8X8
VGEN3
100 mA
VGEN5
100 mA
Camera
Audio
Codec
Cluster/HUD
External AMP
Microphones
Speakers
Front USB
POD
Rear USB
POD
Rear Seat
Infotaiment
Sensors
i.MX 6X
I2C Communication I2C Communication
PF0100Z
Control Signals Parallel control/GPIOS
LICELL
Charger
COINCELL Main Supply
2.8 – 4.5 V
VGEN1
100 mA
VGEN2
250 mA
VGEN4
350 mA
VGEN6
200 mA
SWBST
600 mA
SW3A/B
2500 mA
SW1C
2000 mA
SW1A/B
2500 mA
SW2
2000 mA
SW4
1000 mA
GPS
MIPI
uPCIe
SATA - FLASH
NAND - NOR
Interfaces
Processor Core
Voltages
Camera
VREFDDR
DDR Memory DDR MEMORY
INTERFACE
SD-MMC/
NAND Mem.
SATA
HDD
WAM
GPS
MIPI
HDMI
LDVS Display
USB
Ethernet
CAN
2NXP Semiconductors
PF0100Z
Table of Contents
1 Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2.1 Power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.1 General Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3.2 Current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.1 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5.3.2 Control logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6 Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.1 Device start-up configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.1.2 One time programmability (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.1.3 OTP prototyping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.4 Reading OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.1.5 Programming OTP fuses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.2.1 Clock adjustment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3.1 Internal core voltage references . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6.3.2 VREFDDR voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 Modes of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.2 State machine flow summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
6.4.3 Power tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.4.4 Buck regulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.4.5 Boost regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.4.6 LDO regulators description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.4.7 VSNVS LDO/switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5.1 I2C device ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5.2 I2C operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
6.5.3 Interrupt handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.5.4 Interrupt bit summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6.5.5 Specific registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
6.5.6 Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
NXP Semiconductors 3
PF0100Z
7 Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.1.1 Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.1.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
7.2 PF0100Z layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.1 General board recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.2 Component placement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.3 General routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
7.2.4 Parallel routing requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.2.5 Switching regulator layout recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
7.3 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.3.1 Rating data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
7.3.2 Estimation of junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9 Reference section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
9.1 Reference documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
10 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
10.1 Document changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
4NXP Semiconductors
PF0100Z
ORDERABLE PARTS
1 Orderable parts
The PF0100Z is available with both pre-programmed and non-programmed OTP memory configurations. The non-programmed device
uses “NP” as the programming code. The pre-programmed devices are identified using the program codes from Table 1, which also list
the associated NXP reference designs where applicable. Details of the OTP programming for each device can be found in Table 9.
1.1 PF0100Z version differences
PF0100AZ is an improved version of the PF0100Z power management IC. Table 2 summarizes the difference between the two versions
and should be referred to when migrating from the PF0100Z to the PF0100AZ.
Table 1. Orderable part variations
Part Number Temperature (TA)Package Programming Reference designs Notes
MMPF0100NPAZES
-40 °C to 105 °C
56 QFN ES, 8x8 mm
0.5 mm pitch WF-Type
(wettable flank)
NP
MCIMX6QAICPU1
MCIMX6SAICPU1
MCIMX6DLAICPU1
(1), (2), (3)
MMPF0100F0AZES F0
MCIMX6Q-SDP
MCIMX6Q-SDB
MCIMX6DL-SDP (1), (2)
MMPF0100F6AZES F6 -
MMPF0100F8AZES F8 -
MMPF0100F9AZES F9 MCIMX6QPlusAICPU3
(1), (2), (3)
MMPF0100FAAZES FA -
Notes
1. For tape and reel add an R2 suffix to the part number.
2. These reference designs use the default startup configuration (VDDOTP = VCOREDIG), which is available on any OTP programmed part.
3. SW2 can support an output current rating of 2.5 A in NP, F9 and FA versions when SW2ILIM=0
Table 2. Differences between PF0100Z and PF0100AZ
Description PF0100Z PF0100AZ
Version identification
Reading SILICON REV register at address 0x03 will
return 0x11. DEVICEID register at address 0x00 will
read 0x10 in PF0100Z and PF0100AZ
Reading SILICON REV register at address 0x03 will
return 0x21. DEVICEID register at address 0x00 will
read 0x10 in PF0100Z and PF0100AZ
VSNVS current limit VSNVS current limit increased in the PF0100AZ. see VSNVS LDO/switch
OTP_FUSE_PORx register setting during OTP
programming
In the PF0100Z, FUSE_POR1, FUSE_POR2, and
FUSE_POR3 bits are XOR’ed into the
FUSE_POR_XOR bit. The FUSE_POR_XOR bit
has to be 1 for fuses to be loaded during startup.
This can be achieved by setting any one or all of the
FUSE_PORx bits during OTP programming.
In the PF0100AZ, the XOR function is removed. It is
required to set FUSE_POR1, FUSE_POR2, and
FUSE_POR3 bits during OTP programming.
Erratum ER19
Erratum ER19 applicable to PF0100Z. Applications
expecting to operate in the conditions mentioned in
ER19 need to implement an external workaround to
overcome the problem. Refer to the product errata
for details
Errata ER19 fixed in PF0100AZ. External
workaround not required
Erratum ER20 Erratum ER20 applicable to PF0100Z Errata ER20 fixed in PF0100AZ
Erratum ER22 Erratum ER22 applicable to PF0100Z Errata ER22 fixed in PF0100AZ. Workaround not
required
Ambient operating temperature -40 °C to 85 °C -40 °C to 105 °C
NXP Semiconductors 5
PF0100Z
INTERNAL BLOCK DIAGRAM
2 Internal block diagram
Figure 2. Simplified internal block diagram
VIN
INTB
LICELL
SWBSTFB
SWBSTIN
SWBSTLX
O/P
Drive
SWBST
600 mA
Boost
PWRON
STANDBY
ICTEST
SCL
SDA
VDDIO
SW3A/B
Single/Dual
DDR
2500 mA
Buck
VCOREDIG
VCOREREF
SDWNB
GNDREF
SW1CFB
SW1AIN
SW1C
2000 mA
Buck
SW1FB
SW1ALX
SW1BLX
SW1A/B
Single/Dual
2500 mA
Buck
SW1VSSSNS
VSNVS
VSNVS
Li Cell
Charger
RESETBMCU
SW2
2000 mA
Buck
VGEN1
100 mA
VGEN1
VIN1
VGEN2
250 mA
VGEN2
VGEN3
100 mA
VGEN3
VIN2
VGEN4
350 mA
VGEN4
VGEN5
100 mA
VGEN5
VIN3
VGEN6
200 mA
VGEN6
Best
of
Supply
OTP
SW4
1000 mA
Buck
VREFDDR
VDDOTP
VINREFDDR
VHALF
VCORE
PF0100Z
CONTROL
Clocks
32 kHz and 16 MHz
Initialization State Machine
I2C
Interface
Clocks and
resets
I2C Register
map
Trim-In-Package
O/P
Drive
O/P
Drive SW1BIN
SW1CLX
O/P
Drive SW1CIN
SW2FB
SW2LX
O/P
Drive SW2IN
SW2IN
SW3AIN
SW3AFB
SW3ALX
SW3BLX
O/P
Drive
O/P
Drive SW3BIN
SW3BFB
SW3VSSSNS
SW4IN
SW4FB
SW4LX
O/P
Drive
Supplies
Control
DVS Control
DVS CONTROL
Reference
Generation
Core Control logic
GNDREF1
6NXP Semiconductors
PF0100Z
PIN CONNECTIONS
3 Pin connections
3.1 Pinout diagram
Figure 3. Pinout diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
4344454647484950515253545556
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2827262524232221201918171615
INTB
SDWNB
RESETBMCU
STANDBY
ICTEST
SW1FB
SW1AIN
SW1ALX
SW1BLX
SW1BIN
SW1CLX
SW1CIN
SW1CFB
SW1VSSSNS
LICELL
VGEN6
VIN3
VGEN5
SW3AFB
SW3AIN
SW3ALX
SW3BLX
SW3BIN
SW3BFB
SW3VSSSNS
VREFDDR
VINREFDDR
VHALF
PWRON
VDDIO
SCL
SDA
VCOREREF
VCOREDIG
VIN
VCORE
GNDREF
VDDOTP
SWBSTLX
SWBSTIN
SWBSTFB
VSNVS
GNDREF1
VGEN1
VIN1
VGEN2
SW4FB
SW4IN
SW4LX
SW2LX
SW2IN
SW2IN
SW2FB
VGEN3
VIN2
VGEN4
EP
NXP Semiconductors 7
PF0100Z
PIN CONNECTIONS
3.2 Pin definitions
Table 3. PF0100Z pin definitions
Pin number Pin name Pin
function Max rating Type Definition
1 INTB O 3.6 V Digital Open drain interrupt signal to processor
2 SDWNB O 3.6 V Digital Open drain signal to indicate an imminent system shutdown
3 RESETBMCU O 3.6 V Digital Open drain reset output to processor. Alternatively can be used as a power
good output.
4 STANDBY I 3.6 V Digital Standby input signal from processor
5 ICTEST I 7.5 V Digital/
Analog Reserved pin. Connect to GND in application.
6SW1FB
(5) I 3.6 V Analog Output voltage feedback for SW1A/B. Route this trace separately from the
high current path and terminate at the output capacitance.
7SW1AIN
(5) I 4.8 V Analog Input to SW1A regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
8 SW1ALX (5) O 4.8 V Analog Regulator 1A switch node connection
9 SW1BLX (5) O 4.8 V Analog Regulator 1B switch node connection
10 SW1BIN (5) I 4.8 V Analog Input to SW1B regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
11 SW1CLX (5) O 4.8 V Analog Regulator 1C switch node connection
12 SW1CIN (5) I 4.8 V Analog Input to SW1C regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
13 SW1CFB (5) I 3.6V Analog Output voltage feedback for SW1C. Route this trace separately from the
high current path and terminate at the output capacitance.
14 SW1VSSSNS GND - GND Ground reference for regulators SW1ABC. It is connected externally to
GNDREF through a board ground plane.
15 GNDREF1 GND - GND Ground reference for regulators SW2 and SW4. It is connected externally to
GNDREF, via board ground plane.
16 VGEN1 O 2.5 V Analog VGEN1 regulator output, Bypass with a 2.2 μF ceramic output capacitor.
17 VIN1 I 3.6 V Analog VGEN1, 2 input supply. Bypass with a 1.0 μF decoupling capacitor as close
to the pin as possible.
18 VGEN2 O 2.5 V Analog VGEN2 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
19 SW4FB (5) I 3.6 V Analog Output voltage feedback for SW4. Route this trace separately from the high
current path and terminate at the output capacitance.
20 SW4IN (5) I 4.8 V Analog Input to SW4 regulator. Bypass with at least a 4.7 μF ceramic capacitor and
a 0.1 μF decoupling capacitor as close to the pin as possible.
21 SW4LX (5) O 4.8 V Analog Regulator 4 switch node connection
22 SW2LX (5) O 4.8 V Analog Regulator 2 switch node connection
23 SW2IN (5) I 4.8 V Analog Input to SW2 regulator. Connect pin 23 together with pin 24 and bypass with
at least a 4.7 μF ceramic capacitor and a 0.1 μF decoupling capacitor as
close to these pins as possible.
24 SW2IN (5) I 4.8 V Analog
25 SW2FB (5) I 3.6 V Analog Output voltage feedback for SW2. Route this trace separately from the high
current path and terminate at the output capacitance.
26 VGEN3 O 3.6 V Analog VGEN3 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
27 VIN2 I 3.6 V Analog VGEN3,4 input. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
28 VGEN4 O 3.6 V Analog VGEN4 regulator output, Bypass with a 4.7 μF ceramic output capacitor.
29 VHALF I 3.6 V Analog Half supply reference for VREFDDR
8NXP Semiconductors
PF0100Z
PIN CONNECTIONS
30 VINREFDDR I 3.6 V Analog VREFDDR regulator input. Bypass with at least 1.0 μF decoupling capacitor
as close to the pin as possible.
31 VREFDDR O 3.6 V Analog VREFDDR regulator output
32 SW3VSSSNS GND - GND Ground reference for the SW3 regulator. Connect to GNDREF externally via
the board ground plane.
33 SW3BFB (5) I 3.6 V Analog Output voltage feedback for SW3B. Route this trace separately from the
high current path and terminate at the output capacitance.
34 SW3BIN (5) I 4.8 V Analog Input to SW3B regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
35 SW3BLX (5) O 4.8 V Analog Regulator 3B switch node connection
36 SW3ALX (5) O 4.8 V Analog Regulator 3A switch node connection
37 SW3AIN (5) I 4.8 V Analog Input to SW3A regulator. Bypass with at least a 4.7 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
38 SW3AFB (5) I 3.6 V Analog Output voltage feedback for SW3A. Route this trace separately from the
high current path and terminate at the output capacitance.
39 VGEN5 O 3.6 V Analog VGEN5 regulator output. Bypass with a 2.2 μF ceramic output capacitor.
40 VIN3 I 4.8 V Analog VGEN5, six input. Bypass with a 1.0 μF decoupling capacitor as close to the
pin as possible.
41 VGEN6 O 3.6 V Analog VGEN6 regulator output. By pass with a 2.2 μF ceramic output capacitor.
42 LICELL I/O 3.6 V Analog Coin cell supply input/output
43 VSNVS O 3.6 V Analog LDO or coin cell output to processor
44 SWBSTFB (5) I 5.5 V Analog Boost regulator feedback. Connect this pin to the output rail close to the
load. Keep this trace away from other noisy traces and planes.
45 SWBSTIN (5) I 4.8 V Analog Input to SWBST regulator. Bypass with at least a 2.2 μF ceramic capacitor
and a 0.1 μF decoupling capacitor as close to the pin as possible.
46 SWBSTLX (5) O 7.5 V Analog SWBST switch node connection
47 VDDOTP I 10 V(4) Digital &
Analog Supply to program OTP fuses
48 GNDREF GND - GND Ground reference for the main band gap regulator.
49 VCORE O 3.6 V Analog Analog core supply
50 VIN I 4.8 V Analog Main chip supply
51 VCOREDIG O 1.5 V Analog Digital core supply
52 VCOREREF O 1.5 V Analog Main band gap reference
53 SDA I/O 3.6 V Digital I2C data line (open drain)
54 SCL I 3.6 V Digital I2C clock
55 VDDIO I 3.6 V Analog Supply for I2C bus
56 PWRON I 3.6 V Digital Power on/off from processor
- EP GND - GND
Expose pad. Functions as ground return for buck regulators. Tie this pad to
the inner and external ground planes through vias to allow effective thermal
dissipation.
Notes
4. 10 V Maximum voltage rating during OTP fuse programming. 7.5 V Maximum DC voltage rated otherwise.
5. Unused switching regulators should be connected as follows: Pins SWxLX and SWxFB should be unconnected and pin SWxIN should be
connected to VIN with a 0.1 μF bypass capacitor.
Table 3. PF0100Z pin definitions (continued)
Pin number Pin name Pin
function Max rating Type Definition
NXP Semiconductors 9
PF0100Z
GENERAL PRODUCT CHARACTERISTICS
4 General product characteristics
4.1 Absolute maximum ratings
Table 4. Absolute maximum ratings
All voltages are with respect to ground, unless otherwise noted. Exceeding these ratings may cause malfunction or permanent damage
to the device. The detailed maximum voltage rating per pin can be found in the pin list section.
Symbol Description Value Unit Notes
Electrical ratings
VIN Main input supply voltage -0.3 to 4.8 V
VDDOTP OTP programming input supply voltage -0.3 to 10 V
VLICELL Coin cell voltage -0.3 to 3.6 V
VESD
ESD ratings
Human body model
VSNVS pin
All other pins
Charge device model
±1800
±2000
±500
V(6)
Notes
6. ESD testing is performed in accordance with the human body model (HBM) (CZAP = 100 pF, RZAP = 1500 Ω), and the charge device model (CDM),
robotic (CZAP = 4.0 pF).
10 NXP Semiconductors
PF0100Z
GENERAL PRODUCT CHARACTERISTICS
4.2 Thermal characteristics
4.2.1 Power dissipation
During operation, the temperature of the die should not exceed the operating junction temperature noted in Table 5. To optimize the
thermal management and to avoid overheating, the PF0100Z provides thermal protection. An internal comparator monitors the die
temperature. Interrupts THERM110I, THERM120I, THERM125I, and THERM130I are generated when the respective thresholds specified
in Table 6 are crossed in either direction. The temperature range can be determined by reading the THERMxxxS bits in register
INTSENSE0.
In the event of excessive power dissipation, thermal protection circuitry shuts down the PF0100Z. This thermal protection acts above the
thermal protection threshold listed in Table 6. To avoid any unwanted power downs resulting from internal noise, the protection is
debounced for 8.0 ms. This protection should be considered as a fail-safe mechanism and therefore the system should be configured so
this protection is not tripped under normal conditions.
Table 5. Thermal ratings
Symbol Description (rating) Min. Max. Unit Notes
Thermal ratings
TA
Ambient operating temperature range
PF0100Z
PF0100AZ
-40
-40
85
105
°C
TJOperating junction temperature range -40 125 °C(7)
TST Storage temperature range -65 150 °C
TPPRT Peak package reflow temperature – Note 9 °C(8)(9)
QFN56 thermal resistance and package dissipation ratings
RθJA
Junction to ambient
Natural convection
Four layer board (2s2p)
Eight layer board (2s6p)
–
–
28
15
°C/W (10)(11)(12)
RθJMA
Junction to ambient (at 200 ft/min)
Four layer board (2s2p) – 22 °C/W (10)(12)
RθJB Junction to board – 10 °C/W (13)
RΘJCBOTTOM Junction to case bottom – 1.2 °C/W (14)
ΨJT Junction to package top
Natural convection – 2.0 °C/W (15)
Notes
7. Do not operate beyond 125 °C for extended periods of time. Operation above 150 °C may cause permanent damage to the IC. See Table 6 for
thermal protection features.
8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause a
malfunction or permanent damage to the device.
9. NXP’s package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For peak package reflow temperature and
moisture sensitivity levels (MSL), go to www.nxp.com, search by part number (remove prefixes/suffixes) and enter the core ID to view all orderable
parts, and review parametrics.
10. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient
temperature, air flow, power dissipation of other components on the board, and board thermal resistance.
11. The Board uses the JEDEC specifications for thermal testing (and simulation) JESD51-7 and JESD51-5.
12. Per JEDEC JESD51-6 with the board horizontal.
13. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top surface of the
board near the package.
14. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).
15. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature per JEDEC JESD51-
2. When the Greek letter (Ψ) is not available, the thermal characterization parameter is written as Psi-JT.
NXP Semiconductors 11
PF0100Z
GENERAL PRODUCT CHARACTERISTICS
4.3 Electrical characteristics
4.3.1 General Specifications
Table 6. Thermal protection thresholds
Parameter Min. Typ. Max. Units Notes
Thermal 110 °C threshold (THERM110) 100 110 120 °C
Thermal 120 °C threshold (THERM120) 110 120 130 °C
Thermal 125 °C threshold (THERM125) 115 125 135 °C
Thermal 130 °C threshold (THERM130) 120 130 140 °C
Thermal warning hysteresis 2.0 – 4.0 °C
Thermal protection threshold 130 140 150 °C
Table 7. General PMIC Static Characteristics
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, VDDIO = 1.7 V to 3.6 V, typical external component
values and full load current range, unless otherwise noted.
Pin name Parameter Load condition Min. Max. Unit
PWRON
VIL – 0.0 0.2 * VSNVS V
VIH – 0.8 * VSNVS 3.6 V
RESETBMCU
VOL -2.0 mA 0.0 0.4 V
VOH Open drain 0.7* VIN VIN V
SCL
VIL – 0.0 0.2 * VDDIO V
VIH – 0.8 * VDDIO 3.6 V
SDA
VIL – 0.0 0.2 * VDDIO V
VIH – 0.8 * VDDIO 3.6 V
VOL -2.0 mA 0.0 0.4 V
VOH Open drain 0.7*VDDIO VDDIO V
INTB
VOL -2.0 mA 0.0 0.4 V
VOH Open drain 0.7* VIN VIN V
SDWNB
VOL -2.0 mA 0.0 0.4 V
VOH Open drain 0.7* VIN VIN V
STANDBY
VIL – 0.0 0.2 * VSNVS V
VIH – 0.8 * VSNVS 3.6 V
VDDOTP
VIL –0.00.3V
VIH –1.11.7V
12 NXP Semiconductors
PF0100Z
GENERAL PRODUCT CHARACTERISTICS
4.3.2 Current consumption
The current consumption of the individual blocks is described in detail throughout this specification. For convenience, a summary table
follows for standard use cases.
Table 8. Current consumption summary
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Mode PF0100Z conditions System conditions Typ. Max. Unit Notes
Coin Cell
VSNVS from LICELL
All other blocks off
VIN = 0.0 V
VSNVSVOLT[2:0] = 110
No load on VSNVS 4.0 7.0 μA
(16),(18),
(21)
Off
MMPF0100Z
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN ≥ UVDET
No load on VSNVS, PMIC able to wake-up 16 21 μA(17),(18)
Off
MMPF0100AZ
VSNVS from VIN or LICELL
Wake-up from PWRON active
32 k RC on
All other blocks off
VIN ≥ UVDET
No load on VSNVS, PMIC able to wake-up 17 25 μA(17),(18)
Sleep
VSNVS from VIN
Wake-up from PWRON active
Trimmed reference active
SW3A/B PFM
Trimmed 16 MHz RC off
32 k RC on
VREFDDR disabled
TA = -40 °C to 85 °C
TA = -40 °C to 105 °C (PF0100AZ Only)
No load on VSNVS. DDR memories in self
refresh
122
122
220
250
μA(18)
Standby
MMPF0100Z
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
297
297
450 (19)
1000 (20)
μA(18)
NXP Semiconductors 13
PF0100Z
GENERAL PRODUCT CHARACTERISTICS
Figure 4. Current overtemperature waveforms
Standby
MMPF0100AZ
VSNVS from either VIN or LICELL
SW1A/B combined in PFM
SW1C in PFM
SW2 in PFM
SW3A/B combined in PFM
SW4 in PFM
SWBST off
Trimmed 16 MHz RC enabled
Trimmed reference active
VGEN1-6 enabled
VREFDDR enabled
TA = -40 °C to 85 °C
TA = -40 °C to 105 °C
No load on VSNVS. Processor enabled in
low power mode. All rails powered on
except boost (load = 0 mA)
297
297
450
550
μA(18)
Notes
16. Refer to Figure 4 for coin cell mode characteristics over temperature.
17. When VIN is below the UVDET threshold, in the range of 1.8 V ≤ VIN < 2.65 V, the quiescent current increases by 50 μA, typically.
18. For PFM operation, headroom should be 300 mV or greater.
19. From 0 °C to 85 °C
20. From -40 °C to 85 °C
21. Additional current may be drawn in the coin cell mode when RESETBMCU is pulled up to VSNVS due an internal path from RESETBMCU to VIN.
The additional current is <30 μA with a pull up resistor of 100 kΩ. The i.MX 6x processors have an internal pull up from the POR_B pin to the
VDD_SNVS_IN pin. For i.MX 6x applications, if additional current in the coin cell mode is not desired, use an external switch to disconnect the
RESETBMCU path when VIN is removed. For non-i.MX 6 applications, pull-up RESETBMCU to a rail that is off in the coin cell mode.
Table 8. Current consumption summary (continued)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VDDIO = 1.7 V to 3.6 V, LICELL = 1.8 V to 3.3 V,
VSNVS = 3.0 V, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VDDIO = 3.3 V, LICELL = 3.0 V, VSNVS = 3.0 V and 25 °C, unless otherwise noted.
Coin cell mode current (μA)
Coin cell mode
1
10
100
-40-20 0 20406080
Temperat ure (oC)
MMPF0100
MMPF0100A
Temperature (°C)
14 NXP Semiconductors
PF0100Z
GENERAL DESCRIPTION
5 General description
The PF0100Z is the power management integrated circuit (PMIC) designed primarily for use with NXP’s i.MX 6 series of application
processors.
5.1 Features
This section summarizes the PF0100Z features.
• Input voltage range to PMIC: 2.8 V - 4.5 V
• Buck regulators
• Four to six channel configurable
• SW1A/B/C, 4.5 A (single); 0.3 V to 1.875 V
• SW1A/B, 2.5 A (single/dual); SW1C 2.0 A (independent); 0.3 V to 1.875 V
•SW2, 2.0 A; 0.4 V to 3.3 V (2.5 A; 1.2 V to 3.3 V (22))
• SW3A/B, 2.5 A (single/dual); 0.4 V to 3.3 V
•SW3A, 1.25 A (independent); SW3B, 1.25 A (independent); 0.4 V to 3.3 V
•SW4, 1.0 A; 0.4 V to 3.3 V
• SW4, VTT mode provide DDR termination at 50% of SW3A
• Dynamic voltage scaling
• Modes: PWM, PFM, APS
• Programmable output voltage
• Programmable current limit
• Programmable soft start
• Programmable PWM switching frequency
• Programmable OCP with fault interrupt
• Boost regulator
• SWBST, 5.0 V to 5.15 V, 0.6 A, OTG support
• Modes: PFM and Auto
• OCP fault interrupt
•LDOs
• Six user programable LDO
• VGEN1, 0.80 V to 1.55 V, 100 mA
• VGEN2, 0.80 V to 1.55 V, 250 mA
• VGEN3, 1.8 V to 3.3 V, 100 mA
• VGEN4, 1.8 V to 3.3 V, 350 mA
• VGEN5, 1.8 V to 3.3 V, 100 mA
• VGEN6, 1.8 V to 3.3 V, 200 mA
• Soft start
• LDO/switch supply
• VSNVS (1.0/1.1/1.2/1.3/1.5/1.8/3.0 V), 400 μA
• DDR memory reference voltage
•VREFDDR, 0.6 V to 0.9 V, 1 0 mA
•16 MHz internal master clock
• OTP (one time programmable) memory for device configuration
• User programmable start-up sequence and timing
• Battery backed memory including coin cell charger
•I
2C interface
• User programmable standby, sleep, and off modes
Notes
22. SW2 capable of 2.5 A in NP/F9/FA versions
NXP Semiconductors 15
PF0100Z
GENERAL DESCRIPTION
5.2 Functional block diagram
Figure 5. Functional block diagram
5.3 Functional description
5.3.1 Power generation
The PF0100Z PMIC features four buck regulators (up to six independent outputs), one boost regulator, six general purpose LDOs, one
switch/LDO combination, and a DDR voltage reference to supply voltages for the application processor and peripheral devices.
The number of independent buck regulator outputs can be configured from four to six, thereby providing flexibility to operate with higher
current capability, or to operate as independent outputs for applications requiring more voltage rails with lower current demands. Further,
SW1 and SW3 regulators can be configured as single/dual phase and/or independent converters. One of the buck regulators, SW4, can
also operate as a tracking regulator when used for memory termination. The buck regulators provide the supply to processor cores and
to other low voltage circuits such as IO and memory. Dynamic voltage scaling is provided to allow controlled supply rail adjustments for
the processor cores and/or other circuitry.
Depending on the system power path configuration, the six general purpose LDO regulators can be directly supplied from the main input
supply or from the switching regulators to power peripherals, such as audio, camera, Bluetooth, Wireless LAN, etc. A specific VREFDDR
voltage reference is included to provide accurate reference voltage for DDR memories operating with or without VTT termination. The
VSNVS block behaves as an LDO, or as a bypass switch to supply the SNVS/SRTC circuitry on the i.MX processors; VSNVS may be
powered from VIN, or from a coin cell.
5.3.2 Control logic
The PF0100Z PMIC is fully programmable via the I2C interface. Additional communication is provided by direct logic interfacing including
interrupt and reset. Start-up sequence of the device is selected upon the initial OTP configuration explained in the Start-up section, or by
configuring the “try before buy” feature to test different power up sequences before choosing the final OTP configuration.
The PF0100Z PMIC has the interfaces for the power buttons and dedicated signaling interfacing with the processor. It also ensures supply
of critical internal logic and other circuits from the coin cell during brief interruptions from the main battery. A charger for the coin cell is
included as well.
Logic and control
Switching Regulators
SW1A/B/C
(0.3 V to 1.875 V)
Configurable 4.5 A or
2.5 A+2.0 A
Linear Regulators
SW2
(0.4 V to 3.3 V, 2.0 A)
SW3A/B
(0.4 V to 3.3 V)
Configurable 2.5 A or
1.25 A+1.25 A
SW4
(0.4 V to 3.3 V, 1.0 A)
Boost Regulator
(5.0 V to 5.15 V, 600 mA)
USB OTG Supply
VGEN1
(0.8 V to 1.55 V, 100 mA)
VGEN2
(0.8 V to 1.55 V, 250 mA)
VGEN3
(1.8 V to 3.3 V, 100 mA)
VGEN4
(1.8 V to 3.3 V, 350 mA)
VGEN5
(1.8 V to 3.3 V, 100 mA)
VGEN6
(1.8 V to 3.3 V, 200 mA)
Bias and references
Parallel MCU interface Regulator control
VSNVS
(1.0 V to 3.0 V, 400 μA)
RTC supply with coin cell
charger
PF0100Z functional internal block diagram
I2C communication and registers
Power generation
Fault detection and protection
DDR voltage reference
Current limit
Short-circuit
Internal core voltage reference
Thermal
OTP startup configuration
Sequence and
timing
OTP prototyping
(try before buy) Voltage
Phasing and
frequency selection
16 NXP Semiconductors
PF0100Z
GENERAL DESCRIPTION
5.3.2.1 Interface signals
5.3.2.1.1 PWRON
PWRON is an input signal to the IC generating a turn-on event. It can be configured to detect a level, or an edge using the PWRON_CFG
bit. Refer to section 6.4.2.1 Turn on events, page 30 for more details.
5.3.2.1.2 STANDBY
STANDBY is an input signal to the IC. When it is asserted, the part enters standby mode and when de-asserted, the part exits standby
mode. STANDBY can be configured as active high or active low using the STANDBYINV bit. Refer to the section 6.4.1.3 Standby mode,
page 28 for more details.
Note: When operating the PMIC at VIN ≤ 2.85 V and VSNVS is programmed for a 3.0 V output, a coin cell must be present to provide
VSNVS, or the PMIC does not reliably enter and exit the STANDBY mode.
5.3.2.1.3 RESETBMCU
RESETBMCU is an open-drain, active low output configurable for two modes of operation. In its default mode, it is de-asserted 2.0 ms to
4.0 ms after the last regulator in the start-up sequence is enabled; refer to Figure 6 as an example. In this mode, the signal can be used
to bring the processor out of reset, or as an indicator all supplies have been enabled; it is only asserted for a turn-off event.
When configured for its fault mode, RESETBMCU is de-asserted after the start-up sequence is completed only if no faults occurred during
start-up. At anytime, if a fault occurs and persists for 1.8 ms typically, RESETBMCU is asserted, LOW. The PF0100Z is turned off if the
fault persists for more than 100 ms typically. The PWRON signal restarts the part, though if the fault persists, the sequence described
previously is repeated. To enter the fault mode, set bit OTP_PG_EN of register OTP PWRGD EN to “1”. This register, 0xE8, is located on
Table 136. Extended page 1, page 106 of the register map. To test the fault mode, the bit may be set during TBB prototyping, or the mode
may be permanently chosen by programming OTP fuses.
5.3.2.1.4 SDWNB
SDWNB is an open drain, active low output notifying the processor of an imminent PMIC shut down. It is asserted low for one 32 kHz clock
cycle before powering down and then de-asserted in the OFF state.
5.3.2.1.5 INTB
INTB is an open-drain, active low output. It is asserted when any fault occurs, provided the fault interrupt is unmasked. INTB is de-asserted
after the fault interrupt is cleared by software, which requires writing a “1” to the fault interrupt bit.
NXP Semiconductors 17
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6 Functional block requirements and behaviors
6.1 Start-up
The PF0100Z can be configured to start-up from either the internal OTP configuration, or with a hard-coded configuration built in to the
device. The internal hard-coded configuration is enabled by connecting the VDDOTP pin to VCOREDIG through a 100 kΩ resistor. The
OTP configuration is enabled by connecting VDDOTP to GND.
For NP devices, selecting the OTP configuration causes the PF0100Z not to start-up. However, the PF0100Z can be controlled through
the I2C port for prototyping and programming. Once programmed, the NP device starts up with the customer programmed configuration.
6.1.1 Device start-up configuration
Table 9 shows the default configuration, which can be accessed on all devices as described previously, as well as the pre-programmed
OTP configurations.
Table 9. Start-up configuration
Registers
Default
configuration Pre-programmed OTP configuration
All devices F0 F6 F8 F9 FA
Default I2C Address 0x08 0x08 0x08 0x08 0x08 0x08
VSNVS_VOLT 3.0 V 3.0 V 3.0 V 3.0 V3.0 V3.0 V
SW1AB_VOLT 1.375 V 1.375 V 1.375 V 1.425 V 1.375 V 1.375 V
SW1AB_SEQ 1 1 2155
SW1C_VOLT 1.375 V 1.375 V 1.375 V 1.425 V 1.375 V 1.375 V
SW1C_SEQ 1 2 2255
SW2_VOLT 3.0 V 3.3 V 3.3 V 3.0 V 1.375 V 1.375 V
SW2_SEQ 2 5 4555
SW3A_VOLT 1.5 V 1.5 V 1.35 V 1.5 V 1.350 V 1.5 V
SW3A_SEQ 3 3 3366
SW3B_VOLT 1.5 V 1.5 V 1.35 V 1.5 V 1.350 V 1.5 V
SW3B_SEQ 3 3 3366
SW4_VOLT 1.8 V 3.15 V 1.8 V 3.15 V 1.825 V 1.825 V
SW4_SEQ 3 6 4 -77
SWBST_VOLT - 5.0 V 5.0 V - 5.0 V 5.0 V
SWBST_SEQ - 13 Off -1010
VREFDDR_SEQ 3 3 3366
VGEN1_VOLT - 1.5 V 1.2 V 1.5 V1.2 V1.2 V
VGEN1_SEQ - 9 5---
VGEN2_VOLT 1.5 V 1.5 V 1.5 V 1.5 V1.5 V1.5 V
VGEN2_SEQ 2 10 Off -88
VGEN3_VOLT - 2.5 V 2.8 V 2.5 V1.8 V1.8 V
VGEN3_SEQ - 11 5 -88
VGEN4_VOLT 1.8 V 1.8 V 1.8 V 1.8 V3.0 V3.0 V
VGEN4_SEQ 3 7 4-44
18 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN5_VOLT 2.5 V 2.8 V 3.3 V 2.8 V 2.5 V 2.5 V
VGEN5_SEQ 3 12 5 -88
VGEN6_VOLT 2.8 V 3.3 V 3.0 V 2.8 V 2.8 V 2.8 V
VGEN6_SEQ 3 8 1677
PU CONFIG, SEQ_CLK_SPEED 1.0 ms 2.0 ms 0.5 ms 2.0 ms 0.5 ms 0.5 ms
PU CONFIG, SWDVS_CLK 6.25 mV/μs 1.5625 mV/μs6.25 mV/μs25 mV/16 μs6.25 mV/μs 6.25 mV/μs
PU CONFIG, PWRON Level sensitive
SW1AB CONFIG SW1AB Single Phase, SW1C Independent Mode, 2.0 MHz SW1ABC Single Phase, 2.0 MHz
SW1C CONFIG 2.0 MHz
SW2 CONFIG 2.0 MHz
SW3A CONFIG SW3AB Single Phase, 2.0 MHz
SW3B CONFIG 2.0 MHz
SW4 CONFIG No VTT, 2.0 MHz
PG EN RESETBMCU in Default Mode
Table 9. Start-up configuration (continued)
Registers
Default
configuration Pre-programmed OTP configuration
All devices F0 F6 F8 F9 FA
NXP Semiconductors 19
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 6. Default start-up sequence
Table 10. Default start-up sequence timing
Parameter Description Min. Typ. Max. Unit Notes
tD1 Turn-on delay of VSNVS – 5.0 – ms (23)
tR1 Rise time of VSNVS – 3.0 – ms
tD2 User determined delay – 1.0 – ms
tR2 Rise time of PWRON – (24) –ms
tD3
Turn-on delay of first regulator
SEQ_CLK_SPEED[1:0] = 00 –2.0–
ms
SEQ_CLK_SPEED[1:0] = 01 –2.5– (25)
SEQ_CLK_SPEED[1:0] = 10 –4.0–
SEQ_CLK_SPEED[1:0] = 11 –7.0–
tR3 Rise time of regulators – 0.2 – ms (26)
*VSNVS starts from 1.0 V if LICELL is valid before VIN.
UVDET
LICELL
VIN
VSNVS
PWRON
SW1A/B
SW1C
SW2
VGEN2
SW3A/B
SW4
VREFDDR
VGEN4
VGEN5
VGEN6
RESETBMCU
td1
td3
td4
td4
tr1
tr3
tr3
tr3
td5tr4
tr2
td2
1V
20 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.1.2 One time programmability (OTP)
OTP allows the programming of start-up configurations for a variety of applications. Before permanently programming the IC by
programming fuses, a configuration may be prototyped by using the “try before buy” (TBB) feature. Further, an error correction code (ECC)
algorithm is available to correct a single bit error and to detect multiple bit errors when fuses are programmed.
The following parameters which can be configured by OTP are listed.
• General: I2C slave address, PWRON pin configuration, start-up sequence and timing
• Buck regulators: Output voltage, dual/single phase or independent mode configuration, switching frequency, and soft start ramp
rate
• Boost regulator and LDOs: Output voltage
NOTE: When prototyping or programming fuses, the user must ensure register settings are consistent with the hardware configuration.
This is most important for the buck regulators, where the quantity, size, and value of the inductors depend on the configuration (single/
dual phase or independent mode) and the switching frequency. Additionally, if an LDO is powered by a buck regulator, it is gated by the
buck regulator in the start-up sequence.
6.1.2.1 Start-up sequence and timing
Each regulator has 5-bits allocated to program its start-up time slot from a turn on event; therefore, each can be placed from position one
to thirty-one in the start-up sequence. The all zeros code indicates a regulator is not part of the start-up sequence and remains off. See
Table 11. The delay between each position is equal; however, four delay options are available. See Table 12. The start-up sequence
terminates at the last programmed regulator.
tD4
Delay between regulators
SEQ_CLK_SPEED[1:0] = 00 –0.5–
ms
SEQ_CLK_SPEED[1:0] = 01 –1.0–
SEQ_CLK_SPEED[1:0] = 10 –2.0–
SEQ_CLK_SPEED[1:0] = 11 –4.0–
tR4 Rise time of RESETBMCU – 0.2 – ms
tD5 Turn-on delay of RESETBMCU – 2.0 – ms
Notes
23. Assumes LICELL voltage is valid before VIN is applied. If LICELL is not valid before VIN is applied then VSNVS turn-on delay may extend to a
maximum of 24 ms.
24. Depends on the external signal driving PWRON.
25. Default configuration.
26. Rise time is a function of slew rate of regulators and nominal voltage selected.
Table 11. Start-up sequence
SWxx_SEQ[4:0]/
VGENx_SEQ[4:0]/
VREFDDR_SEQ[4:0]
Sequence
00000 Off
00001 SEQ_CLK_SPEED[1:0] * 1
00010 SEQ_CLK_SPEED[1:0] * 2
**
**
**
**
11111 SEQ_CLK_SPEED[1:0] * 31
Table 10. Default start-up sequence timing (continued)
Parameter Description Min. Typ. Max. Unit Notes
NXP Semiconductors 21
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.1.2.2 PWRON pin configuration
The PWRON pin can be configured as either a level sensitive input (PWRON_CFG = 0), or as an edge sensitive input (PWRON_CFG = 1).
As a level sensitive input, an active high signal turns on the part and an active low signal turns off the part, or puts it into sleep mode. As
an edge sensitive input, such as when connected to a mechanical switch, a falling edge turns on the part and if the switch is held low for
greater than or equal to 4.0 seconds, the part turns off or enters sleep mode.
6.1.2.3 I2C address configuration
The I2C device address can be programmed from 0x08 to 0x0F. This allows flexibility to change the I2C address to avoid bus conflicts.
Address bit, I2C_SLV_ADDR[3] in OTP_I2C_ADDR register is hard coded to “1” while the lower three LSBs of the I2C address
(I2C_SLV_ADDR[2:0]) are programmable as shown in Table 14.
6.1.2.4 Soft start ramp rate
The start-up ramp rate or soft start ramp rate can be chosen from the same options as shown in 6.4.4.2.1 Dynamic voltage scaling, page
34.
Table 12. Start-up Sequence Clock Speed
SEQ_CLK_SPEED[1:0] Time (μs)
00 500
01 1000
10 2000
11 4000
Table 13. PWRON configuration
PWRON_CFG Mode
0PWRON pin HIGH = ON
PWRON pin LOW = OFF or sleep mode
1PWRON pin pulled LOW momentarily = ON
PWRON pin LOW for 4.0 seconds = OFF or sleep mode
Table 14. I2C address configuration
I2C_SLV_ADDR[3]
hard coded I2C_SLV_ADDR[2:0] I2C device address
(Hex)
1 000 0x08
1 001 0x09
1 010 0x0A
1 011 0x0B
1 100 0x0C
1 101 0x0D
1 110 0x0E
1 111 0x0F
22 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.1.3 OTP prototyping
Before permanently programming fuses, it is possible to test the desired configuration by using the “try before buy” feature. With this
feature, the configuration is loaded from the OTP registers. These registers merely serve as temporary storage for the values to be written
to the fuses, for the values read from the fuses, or for the values read from the default configuration. To avoid confusion, these registers
are referred to as the TBBOTP registers. The portion of the register map concerning OTP is shown in Table 136 and Table 137.
The contents of the TBBOTP registers are initialized to zero when a valid VIN is first applied. The values then loaded into the TBBOTP
registers depend on the setting of the VDDOTP pin and on the value of the TBB_POR and FUSE_POR bits. Refer to Table 15.
• If VDDOTP = VCOREDIG (1.5 V), the values are loaded from the default configuration.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 1, the values are loaded from the fuses. In the MMPF0100Z, FUSE_POR1,
FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR must be 1 for fuses to be loaded.
This is achieved by setting any one or all of the FUSE_PORx bits. The XOR function is removed in the MMPF0100AZ. It is required
to set all of the FUSE_PORx bits to be able to load the fuses.
• If VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 0, the TBBOTP registers remain initialized at zero.
The initial value of TBB_POR is always “0”; only when VDDOTP = 0.0 V and TBB_POR is set to “1” are the values from the TBBOTP
registers maintained and not loaded from a different source.
The contents of the TBBOTP registers are modified by I2C. To communicate with I2C, VIN must be valid and VDDIO, to which SDA and
SCL are pulled up, must be powered by a 1.7 V to 3.6 V supply. VIN, or the coin cell voltage must be valid to maintain the contents of the
registers. To power on with the contents of the TBBOTP registers, the following conditions must exist; VIN is valid, VDDOTP = 0.0 V,
TBB_POR = 1, and there is a valid turn-on event. Refer to the application note AN4536 for an example of prototyping.
6.1.4 Reading OTP fuses
As described in the previous section, the contents of the fuses are loaded to the TBBOTP registers when the following conditions are met;
VIN is valid, VDDOTP = 0.0 V, TBB_POR = 0 and FUSE_POR = 1. If ECC were enabled at the time the fuses were programmed, the error
corrected values can be loaded into the TBBOTP registers if desired. Once the fuses are loaded and a turn-on event occurs, the PMIC
powers on with the configuration programmed in the fuses. For more details on reading the OTP fuses, see application note AN4536.
6.1.5 Programming OTP fuses
The programmable parameters are shown in the TBBOTP registers in the Table 136. Extended page 1, page 106 of the register map. The
PF0100AZ offers ECC, the control registers for which functions are located in Table 137. Extended page 2, page 110 of the register map.
There are ten banks of twenty-six fuses each which can be programmed. For more details on programming the OTP fuses, see application
note AN4536.
Table 15. Source of start-up sequence
VDDOTP(V) TBB_POR FUSE_POR Start-up sequence
0 0 0 None
0 0 1 OTP fuses
0 1 x TBBOTP registers
1.5 x x Factory defined
NXP Semiconductors 23
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.2 16 MHz and 32 kHz clocks
There are two clocks: a trimmed 16 MHz, RC oscillator and an untrimmed 32 kHz, RC oscillator. The 16 MHz oscillator is specified within
-8.0%/+8.0%. The 32 kHz untrimmed clock is only used in the following conditions:
• VIN < UVDET
• All regulators are in sleep mode
• All regulators are in PFM switching mode
A 32 kHz clock, derived from the 16 MHz trimmed clock, is used when accurate timing is needed under the following conditions:
• During start-up, VIN > UVDET
• PWRON_CFG = 1, for power button debounce timing
In addition, when the 16 MHz is active in the on mode, the debounce times in Table 26 are referenced to the 32 kHz derived from the
16 MHz clock. The exceptions are the LOWVINI and PWRONI interrupts, which are referenced to the 32 kHz untrimmed clock.
6.2.1 Clock adjustment
The 16 MHz clock and hence the switching frequency of the regulators, can be adjusted to improve the noise integrity of the system. By
changing the factory trim values of the 16 MHz clock, the user may add an offset as small as ±3% of the nominal frequency. Contact your
NXP representative for detailed information on this feature.
6.3 Bias and references block description
6.3.1 Internal core voltage references
All regulators use the main bandgap as the reference. The main bandgap is bypassed with a capacitor at VCOREREF. The bandgap and
the rest of the core circuitry are supplied from VCORE. The performance of the regulators is directly dependent on the performance of the
bandgap. No external DC loading is allowed on VCORE, VCOREDIG, or VCOREREF. VCOREDIG is kept powered as long as there is a
valid supply and/or valid coin cell. Table 17 shows the main characteristics of the core circuitry.
Table 16. 16 MHz clock specifications
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol Parameters Min. Typ. Max. Units Notes
VIN16MHz Operating voltage From VIN 2.8 – 4.5 V
f16MHZ 16 MHz clock frequency 14.7 16 17.2 MHz
f2MHZ 2.0 MHz clock frequency 1.84 – 2.15 MHz (27)
Notes
27. The 2.0 MHz clock is derived from the 16 MHz clock.
Table 17. Core voltages electrical specifications(29)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol Parameters Min. Typ. Max. Units Notes
VCOREDIG (digital core supply)
VCOREDIG
Output voltage
On mode (28)
Coin cell mode and off
–
–
1.5
1.3
–
–
V
VCORE (analog core supply)
VCORE
Output voltage
On mode and charging (28)
Off and Coin cell mode
–
–
2.775
0.0
–
–
V
24 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.3.1.1 External components
6.3.2 VREFDDR voltage reference
VREFDDR is an internal PMOS half supply voltage follower capable of supplying up to 10 mA. The output voltage is at one half the input
voltage. Its typically used as the reference voltage for DDR memories. A filtered resistor divider is utilized to create a low frequency pole.
This divider uses a voltage follower to drive the load.
Figure 7. VREFDDR block diagram
6.3.2.1 VREFDDR control register
The VREFDDR voltage reference is controlled by a single bit in VREFDDCRTL register in Table 19.
VCOREREF (bandgap / regulator reference)
VCOREREF Output voltage (28) –1.2– V
VCOREREFACC Absolute accuracy – 0.5 – %
VCOREREFTACC Temperature drift – 0.25 – %
Notes
28. 3.0 V < VIN < 4.5 V, no external loading on VCOREDIG, VCORE, or VCOREREF. Extended operation down to UVDET, but no system malfunction.
29. For information only
Table 18. External components for core voltages
Regulator Capacitor value (μF)
VCOREDIG 1.0
VCORE 1.0
VCOREREF 0.22
Table 17. Core voltages electrical specifications(29) (continued)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 2.8 V to 4.5 V, LICELL = 1.8 V to 3.3 V, and typical external
component values. Typical values are characterized at VIN = 3.6 V, LICELL = 3.0 V, and 25 °C, unless otherwise noted.
Symbol Parameters Min. Typ. Max. Units Notes
VINREFDDR
VREFDDR
VINREFDDR
CHALF1
Discharge
+
_
VHALF
VREFDDR
CHALF2
100 nf
100 nf
CREFDDR
1.0 uf
NXP Semiconductors 25
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.3.2.1.1 External components
6.3.2.1.2 VREFDDR specifications
Table 19. Register VREFDDCRTL - ADDR 0x6A
Name Bit # R/W Default Description
UNUSED 3:0 – 0x00 unused
VREFDDREN 4 R/W 0x00
Enable or disables VREFDDR output voltage
0 = VREFDDR disabled
1 = VREFDDR enabled
UNUSED 7:5 – 0x00 unused
Table 20. VREFDDR external components (30)
Capacitor Capacitance (μF)
VINREFDDR(31) to VHALF 0.1
VHALF to GND 0.1
VREFDDR 1.0
Notes
30. Use X5R or X7R capacitors.
31. VINREFDDR to GND, 1.0 μF minimum capacitance is provided by buck regulator output.
Table 21. VREFDDR electrical characteristics
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and
25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
VREFDDR
VINREFDDR Operating input voltage range 1.2 – 1.8 V
IREFDDR Operating load current range 0.0 – 10 mA
IREFDDRLIM
Current limit
IREFDDR when VREFDDR is forced to VINREFDDR/4 10.5 15 25 mA
IREFDDRQ Quiescent current – 8.0 – μA(32)
Active Mode – DC
VREFDDR
Output voltage
1.2 V < VINREFDDR < 1.8 V
0.0 mA < IREFDDR < 10 mA
–VINREFDDR/
2–V
VREFDDRTOL
Output voltage tolerance
1.2 V < VINREFDDR < 1.8 V
0.6 mA ≤ IREFDDR ≤ 10 mA
TA = -40 °C to 85 °C
TA = -40 °C to 105 °C (PF0100AZ only)
–1.0
-1.2
–
–
1.0
1.2
%
VREFDDRLOR
Load regulation
1.0 mA < IREFDDR < 10 mA
1.2 V < VINREFDDR < 1.8 V
–0.40–mV/mA
26 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Active mode – AC
tONREFDDR
Turn-on Time
Enable to 90% of end value
VINREFDDR = 1.2 V, 1.8 V
IREFDDR = 0.0 mA
– – 100 μs
tOFFREFDDR
Turn-off time
Disable to 10% of initial value
VINREFDDR = 1.2 V, 1.8 V
IREFDDR = 0.0 mA
––10ms
VREFDDROSH
Start-up overshoot
VINREFDDR = 1.2 V, 1.8 V
IREFDDR = 0.0 mA
–1.06.0%
VREFDDRTLR
Transient load response
VINREFDDR = 1.2 V, 1.8 V –5.0–mV
Notes
32. When VREFDDR is off there is a quiescent current of 1.5 μA typical.
Table 21. VREFDDR electrical characteristics (continued)
PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V and typical external
component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V, IREFDDR = 0.0 mA, VINREFDDR = 1.5 V, and
25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
NXP Semiconductors 27
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4 Power generation
6.4.1 Modes of operation
The operation of the PF0100Z can be reduced to five states, or modes: on, off, sleep, standby, and coin cell. Figure 8 shows the state
diagram of the PF0100Z, along with the conditions to enter and exit from each state.
Figure 8. State diagram
To complement the state diagram in Figure 8, a description of the states is provided in following sections. Note that VIN must exceed the
rising UVDET threshold to allow a power up. Refer to Table 28 for the UVDET thresholds. Additionally, I2C control is not possible in the
coin cell mode and the interrupt signal, INTB, is only active in sleep, standby, and on states.
6.4.1.1 On mode
The PF0100Z enters the on mode after a turn-on event. RESETBMCU is de-asserted, high, in this mode of operation.
6.4.1.2 Off mode
The PF0100Z enters the off mode after a turn-off event. A thermal shutdown event also forces the PF0100Z into the off mode. Only
VCOREDIG and VSNVS are powered in the mode of operation. To exit the off mode, a valid turn-on event is required. RESETBMCU is
asserted, low, in this mode.
PWRON = 0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON=1
& VIN > UVDET
(PWRON_CFG =0)
Or
PWRON= 0 < 4.0 sec
& VIN > UVDET
(PWRON_CFG=1)
ON
PWRON = 0
Any SWxOMODE bits=1
(PWRON_CFG=0)
Or
PWRON=0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON=1
& VIN > UVDET
(PWRON_CFG = 0)
Or
PWRON= 0 < 4.0 sec
& VIN > UVDET
(PWRON_CFG=1)
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
OFF
Sleep
Coin Cell
VIN < UVDET
VIN > UVDET
Thermal shudown
Standby
STANDBY asserted
VIN < UVDET
Thermal shutdown
Thermal shutdown
STANDBY de-asserted
PWRON = 0
Any SWxOMODE bits=1
(PWRON_CFG=0)
Or
PWRON=0 held >= 4.0 sec
Any SWxOMODE bits=1
& PWRONRSTEN = 1
(PWRON_CFG=1)
PWRON = 0
All SWxOMODE bits= 0
(PWRON_CFG = 0)
Or
PWRON = 0 held >= 4.0 sec
All SWxOMODE bits= 0
& PWRONRSTEN = 1
(PWRON_CFG = 1)
VIN < UVDET
VIN < UVDET
28 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.1.3 Standby mode
• Depending on STANDBY pin configuration, standby is entered when the STANDBY pin is asserted. This is typically used for low-
power mode of operation.
• When STANDBY is de-asserted, standby mode is exited.
A product may be designed to go into a low-power mode after periods of inactivity. The STANDBY pin is provided for board level control
of going in and out of such deep sleep modes (DSM).
When a product is in DSM, it may be able to reduce the overall platform current by lowering the regulator output voltage, changing the
operating mode of the regulators, or disabling some regulators. The configuration of the regulators in standby is pre-programmed through
the I2C interface.
Note that the STANDBY pin is programmable for active high or active low polarity, and decoding of a Standby event takes into account
the programmed input polarity, as shown in Table 22. When the PF0100Z is powered up first, regulator settings for the standby mode are
mirrored from the regulator settings for the on mode. To change the STANDBY pin polarity to active low, set the STANDBYINV bit via
software first, and then change the regulator settings for standby mode as required. For simplicity, STANDBY is generally referred to as
active high throughout this document.
Since STANDBY pin activity is driven asynchronously to the system, a finite time is required for the internal logic to qualify and respond
to the pin level changes. A programmable delay is provided to hold off the system response to a Standby event. This allows the processor
and peripherals some time after a standby instruction was received to terminate processes to facilitate seamless entering into standby
mode.
When enabled (STBYDLY = 01, 10, or 11) per Table 23, STBYDLY delays the standby initiated response for the entire IC, until the
STBYDLY counter expires. An allowance should be made for three additional 32 k cycles required to synchronize the standby event.
6.4.1.4 Sleep mode
• Depending on the PWRON pin configuration, sleep mode is entered when PWRON is de-asserted and SWxOMODE bit is set.
• To exit sleep mode, assert the PWRON pin.
In the sleep mode, the regulator uses the set point as programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/
B, and SW4. The activated regulators maintain settings for this mode and voltage until the next turn-on event. Table 24 shows the control
bits in sleep mode. During sleep mode, interrupts are active and the INTB pin reports any unmasked fault event.
Table 22. Standby pin and polarity control
STANDBY (pin)(34) STANDBYINV (I2C bit)(35) STANDBY control (33)
00 0
01 1
10 1
11 0
Notes
33. STANDBY = 0: System is not in standby, STANDBY = 1: System is in standby
34. The state of the STANDBY pin only has influence in on mode.
35. Bit 6 in power control register (ADDR - 0x1B)
Table 23. STANDBY delay - initiated response
STBYDLY[1:0](36) Function
00 No delay
01 One 32 k period (default)
10 Two 32 k periods
11 Three 32 k periods
Notes
36. Bits [5:4] in Power Control Register (ADDR - 0x1B)
NXP Semiconductors 29
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.1.5 Coin cell mode
In the coin cell state, the coin cell is the only valid power source (VIN = 0.0 V) to the PMIC. No turn-on event is accepted in the coin cell
state. Transition to the OFF state requires that VIN surpasses UVDET threshold. RESETBMCU is held low in this mode.
If the coin cell is depleted, a complete system reset occurs. At the next application of power and the detection of a turn-on event, the
system is re-initialized with all I2C bits including those reset on COINPORB, which are restored to their default states.
6.4.2 State machine flow summary
Table 25 provides a summary matrix of the PF0100Z flow diagram to show the conditions needed to transition from one state to another.
Table 24. Regulator mode control
SWxOMODE Off operational mode (sleep) (37)
0Off
1PFM
Notes
37. For sleep mode, an activated switching regulator, should use the off mode
set point as programmed by SW1xOFF[5:0] for SW1A/B/C and
SWxOFF[6:0] for SW2, SW3A/B, and SW4.
Table 25. State machine flow summary
STATE
Next state
OFF Coin cell Sleep Standby ON
Initial state
OFF XV
IN < UVDET X X
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
PWRON_CFG = 1
PWRON = 0 < 4.0 s
& VIN > UNDET
Coin cell VIN > UVDET X X X X
Sleep
Thermal Shutdown
VIN < UVDET X X
PWRON_CFG = 0
PWRON = 1 & VIN > UVDET
or
PWRON_CFG = 1
PWRON = 0 < 4.0 s &
VIN > UNDET
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
Standby
Thermal Shutdown
VIN < UVDET
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
X Standby de-asserted
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
ON
Thermal Shutdown
VIN < UVDET
PWRON_CFG = 0
PWRON = 0
Any SWxOMODE = 1
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
Any SWxOMODE = 1 &
PWRONRSTEN = 1
Standby
asserted X
PWRON_CFG = 0
PWRON = 0
All SWxOMODE = 0
or
PWRON_CFG = 1
PWRON = 0 ≥ 4.0 s
All SWxOMODE = 0 &
PWRONRSTEN = 1
30 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.2.1 Turn on events
From off and sleep modes, the PMIC is powered on by a turn-on event. The type of turn-on event depends on the configuration of PWRON.
PWRON may be configured as an active high when PWRON_CFG = 0, or as the input of a mechanical switch when PWRON_CFG = 1.
VIN must be greater than UVDET for the PMIC to turn-on. When PWRON is configured as an active high and PWRON is high (pulled up
to VSNVS) before VIN is valid, a VIN transition from 0.0 V to a voltage greater than UVDET is also a turn-on event. See the state diagram,
Figure 8, and the Table 25 for more details. Any regulator enabled in the sleep mode remains enabled when transitioning from sleep to
on, the regulator does not turn off and then on again to match the start-up sequence. The following is a more detailed description of the
PWRON configurations:
• If PWRON_CFG = 0, the PWRON signal is high and VIN > UVDET, the PMIC turns on; the interrupt and sense bits, PWRONI and
PWRONS respectively, are set.
• If PWRON_CFG = 1, VIN > UVDET and PWRON transitions from high to low, the PMIC turns on; the interrupt and sense bits,
PWRONI and PWRONS respectively, are set.
The sense bit shows the real time status of the PWRON pin. In this configuration, the PWRON input can be a mechanical switch
debounced through a programmable debouncer, PWRONDBNC[1:0], to avoid a response to a very short (unintentional) key press. The
interrupt is generated for both the falling and the rising edge of the PWRON pin. By default, a 30 ms interrupt debounce is applied to both
falling and rising edges. The falling edge debounce timing can be extended with PWRONDBNC[1:0] as defined in Table 26. The interrupt
is cleared by software, or when cycling through the off mode.
6.4.2.2 Turn off events
6.4.2.2.1 PWRON pin
The PWRON pin is used to power off the PF0100Z. The PWRON pin can be configured with OTP to power off the PMIC under the following
two conditions:
1. PWRON_CFG bit = 0, SWxOMODE bit = 0 and PWRON pin is low.
2. PWRON_CFG bit = 1, SWxOMODE bit = 0, PWRONRSTEN = 1 and PWRON is held low for longer than 4.0 seconds.
Alternatively, the system can be configured to restart automatically by setting the RESTARTEN bit.
6.4.2.2.2 Thermal protection
If the die temperature surpasses a given threshold, the thermal protection circuit powers off the PMIC to avoid damage. A turn-on event
does not power on the PMIC while it is in thermal protection. The part remains in off mode until the die temperature decreases below a
given threshold. There are no specific interrupts related to this other than the warning interrupt. See 4.2.1 Power dissipation, page 10 for
more detailed information.
6.4.2.2.3 Undervoltage detection
When the voltage at VIN drops below the undervoltage falling threshold, UVDET, the state machine transitions to the coin cell mode.
Table 26. PWRON hardware debounce bit settings
Bits State Turn on
debounce (ms)
Falling edge INT
debounce (ms)
Rising edge INT
debounce (ms)
PWRONDBNC[1:0]
00 0.0 31.25 31.25
01 31.25 31.25 31.25
10 125 125 31.25
11 750 750 31.25
Notes
38. The sense bit, PWRONS, is not debounced and follows the state of the PWRON pin.
NXP Semiconductors 31
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.3 Power tree
The PF0100Z PMIC features six buck regulators, one boost regulator, six general purpose LDOs, one switch/LDO combination, and a
DDR voltage reference to supply voltages for the application processor and peripheral devices. The buck regulators as well as the boost
regulator are supplied directly from the main input supply (VIN). The inputs to all of the buck regulators must be tied to VIN, whether they
are powered on or off. The six general use LDO regulators are directly supplied from the main input supply or from the switching regulators
depending on the application requirements. Since VREFDDR is intended to provide DDR memory reference voltage, it should be supplied
by any rail supplying voltage to DDR memories; the typical application recommends the use of SW3 as the input supply for VREFDDR.
VSNVS is supplied by either the main input supply or the coin cell. Refer to Table 27 for a summary of all power supplies provided by the
PF0100Z.
Figure 9 shows a simplified power map with various recommended options to supply the different block within the PF0100Z, as well as
the typical application voltage domain on the i.MX 6X processor. Note that each application power tree is dependent upon the system’s
voltage and current requirements, therefore a proper input voltage should be selected for the regulators.
The minimum operating voltage for the main VIN supply is 2.8 V, for lower voltages proper operation is not guaranteed. However at initial
power up, the input voltage must surpass the rising UVDET threshold before proper operation is guaranteed. Refer to the representative
tables and text specifying each supply for information on performance metrics and operating ranges. Table 28 summarizes the UVDET
thresholds.
Table 27. Power tree summary
Supply Output voltage (V) Step size (mV) Maximum load current (mA)
SW1A/B 0.3 - 1.875 25 2500
SW1C 0.3 - 1.875 25 2000
SW2 0.4 - 3.3 25/50 2000 (40)
SW3A/B 0.4 - 3.3 25/50 1250 (39)
SW4 0.5*SW3A_OUT, 0.4 - 3.3 25/50 1000
SWBST 5.00/5.05/5.10/5.15 50 600
VGEN1 0.80 – 1.55 50 100
VGEN2 0.80 – 1.55 50 250
VGEN3 1.8 – 3.3 100 100
VGEN4 1.8 – 3.3 100 350
VGEN5 1.8 – 3.3 100 100
VGEN6 1.8 – 3.3 100 200
VSNVS 1.0 - 3.0 NA 0.4
VREFDDR 0.5*SW3A_OUT NA 10
Notes
39. Current rating per independent phase, when SW3A/B is set in single or dual phase, current capability is up to 2500 mA.
40. SW2 capable of 2500 mA in NP/F9/FA versions
Table 28. UVDET threshold
UVDET threshold VIN
Rising 3.1 V
Falling 2.65 V
32 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 9. PF0100Z typical power map
SW2
VDDHIGH
(0.4 to 3.3 V), 2.0 A
VDDARM_IN
VDDSOC_IN
VDDHIGH_IN
VDD_DDR_IO
i.MX6X
MCU
LDO_3p0
SWBST
5.0 V, 0.6 A
SW3B
DDR IO
(0.4 to 3.3 V), 1.25 A
SW3A
DDR CORE
(0.4 to 3.3 V), 1.25 A
SW1C
SOC
(0.3 to 1.875 V), 2.0 A
SW1B
CORE
(0.3 to 1.875 V), 1.25 A
SW1A
CORE
(0.3 to 1.875 V), 1.25 A
USB_OTG
Peripherals
VGEN1
(0.80 to 1.55 V),
100 mA
VGEN2
(0.80 to 1.55 V),
250 mA
VGEN3
(1.8 to 3.3 V),
100 mA
VSNVS_IN
VGEN4
(1.8 to 3.3 V),
350 mA
VGEN5
(1.8 to 3.3 V),
100 mA
VGEN6
(1.8 to 3.3 V),
200 mA
DDR3
SW4
System/VTT
(0.4 to 3.3 V)
(0.5*VDDR)
1.0 A
VREFDDR
0.5*VDDR, 10 mA
Coincell
VIN
SW3A/B
VIN
SW2
SW4
VINMAX = 3.4 V
VIN
2.8 - 4.5 V
VINMAX = 3.6 V
VSNVS
1.0 to 3.0 V,
400 uA
MUX /
COIN
CHRG
VINMAX = 4.5 V
VIN
SW2
SW4
VIN
SW2
SW4
NXP Semiconductors 33
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4 Buck regulators
Each buck regulator is capable of operating in PFM, APS, and PWM switching modes.
6.4.4.1 Current limit
Each buck regulator has a programmable current limit. In an overcurrent condition, the current is limited cycle-by-cycle. If the current limit
condition persists for more than 8.0 ms, a fault interrupt is generated.
6.4.4.2 General control
To improve system efficiency the buck regulators can operate in different switching modes. Changing between switching modes can occur
by any of the following means: I2C programming, exiting/entering the standby mode, exiting/entering sleep mode, and load current
variation. Available switching modes for buck regulators are presented in Table 29.
During soft-start of the buck regulators, the controller transitions through the PFM, APS, and PWM switching modes. 3.0 ms (typical) after
the output voltage reaches regulation, the controller transitions to the selected switching mode. Depending on the particular switching
mode selected, additional ripple may be observed on the output voltage rail as the controller transitions between switching modes. Contact
your NXP representative for application considerations if you are using load switches in series with the buck regulator outputs. Table 30
summarizes the buck regulator programmability for normal and standby modes.
Transitioning between normal and standby modes can affect a change in switching modes as well as output voltage. The rate of the output
voltage change is controlled by the dynamic voltage scaling (DVS), explained in 6.4.4.2.1 Dynamic voltage scaling, page 34. For each
regulator, the output voltage options are the same for normal and standby modes.
Table 29. Switching mode description
Mode Description
OFF The regulator is switched off and the output voltage is discharged.
PFM In this mode, the regulator is always in PFM mode, which is useful at light loads for optimized efficiency.
PWM In this mode, the regulator is always in PWM mode operation regardless of load conditions.
APS In this mode, the regulator moves automatically between pulse skipping mode and PWM mode depending on load conditions.
Table 30. Regulator mode control
SWxMODE[3:0] Normal mode Standby mode
0000 Off Off
0001 PWM Off
0010 Reserved Reserved
0011 PFM Off
0100 APS Off
0101 PWM PWM
0110 PWM APS
0111 Reserved Reserved
1000 APS APS
1001 Reserved Reserved
1010 Reserved Reserved
1011 Reserved Reserved
1100 APS PFM
1101 PWM PFM
1110 Reserved Reserved
1111 Reserved Reserved
34 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
When in standby mode, the regulator outputs the voltage programmed in its standby voltage register and operates in the mode selected
by the SWxMODE[3:0] bits. Upon exiting standby mode, the regulator returns to its normal switching mode and its output voltage
programmed in its voltage register.
Any regulators whose SWxOMODE bit is set to “1” enters sleep mode if a PWRON turn-off event occurs, and any regulator whose
SWxOMODE bit is set to “0” is turned off. In sleep mode, the regulator outputs the voltage programmed in its off (sleep) voltage register
and operates in the PFM mode. The regulator exits the sleep mode when a turn-on event occurs. Any regulator whose SWxOMODE bit
is set to “1” remains on and changes to its normal configuration settings when exiting the sleep state to the on state. Any regulator whose
SWxOMODE bit is set to “0” powers up with the same delay in the start-up sequence as when powering on from off. At this point, the
regulator returns to its default ON state output voltage and switch mode settings.
Table 24 shows the control bits in sleep mode. When sleep mode is activated by the SWxOMODE bit, the regulator uses the set point as
programmed by SW1xOFF[5:0] for SW1A/B/C and by SWxOFF[6:0] for SW2, SW3A/B, and SW4.
6.4.4.2.1 Dynamic voltage scaling
To reduce overall power consumption, processor core voltages can be varied depending on the mode or activity level of the processor.
1. Normal operation: The output voltage is selected by I2C bits SW1x[5:0] for SW1A/B/C and SWx[6:0] for SW2, SW3A/B, and SW4.
A voltage transition initiated by I2C is governed by the DVS stepping rates shown in Table 33 and Table 34.
2. Standby mode: The output voltage can be higher, or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1xSTBY[5:0] for SW1A/B/C and by bits SWxSTBY[6:0] for SW2,
SW3A/B, and SW4. Voltage transitions initiated by a standby event are governed by the SW1xDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.
3. Sleep mode: The output voltage can be higher or lower than in normal operation, but is typically selected to be the lowest state
retention voltage of a given processor; it is selected by I2C bits SW1xOFF[5:0] for SW1A/B/C and by bits SWxOFF[6:0] for SW2,
SW3A/B, and SW4. Voltage transitions initiated by a turn-off event are governed by the SW1xDVSSPEED[1:0] and
SWxDVSSPEED[1:0] I2C bits shown in Table 33 and Table 34, respectively.
Table 31, Table 32, Table 33, and Table 34 summarize the set point control and DVS time stepping applied to all regulators.
Table 31. DVS control logic for SW1A/B/C
STANDBY Set point selected by
0 SW1x[5:0]
1 SW1xSTBY[5:0]
Table 32. DVS control logic for SW2, SW3A/B, and SW4
STANDBY Set point selected by
0 SWx[6:0]
1 SWxSTBY[6:0]
Table 33. DVS speed selection for SW1A/B/C
SW1xDVSSPEED[1:0] Function
00 25 mV step each 2.0 μs
01 (default) 25 mV step each 4.0 μs
10 25 mV step each 8.0 μs
11 25 mV step each 16 μs
NXP Semiconductors 35
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
The regulators have a strong sourcing capability and sinking capability in PWM mode, therefore the fastest rising and falling slopes are
determined by the regulator in PWM mode. However, if the regulators are programmed in PFM or APS mode during a DVS transition, the
falling slope can be influenced by the load. Additionally, as the current capability in PFM mode is reduced, controlled DVS transitions in
PFM mode could be affected. Critically timed DVS transitions are best assured with PWM mode operation.
The following diagram shows the general behavior for the regulators when initiated with I2C programming, or standby control. During the
DVS period the overcurrent condition on the regulator should be masked.
Figure 10. Voltage stepping with DVS
6.4.4.2.2 Regulator phase clock
The SWxPHASE[1:0] bits select the phase of the regulator clock as shown in Table 35. By default, each regulator is initialized at 90 ° out
of phase with respect to each other. For example, SW1x is set to 0 °, SW2 is set to 90 °, SW3A/B is set to 180 °, and SW4 is set to 270 °
by default at power up.
The SWxFREQ[1:0] register is used to set the desired switching frequency for each one of the buck regulators. Table 37 shows the
selectable options for SWxFREQ[1:0]. For each frequency, all phases will be available, this allows regulators operating at different
frequencies to have different relative switching phases. However, not all combinations are practical. For example, 2.0 MHz, 90 ° and
4.0 MHz, 180 ° are the same in terms of phasing. Table 36 shows the optimum phasing when using more than one switching frequency.
Table 34. DVS Speed Selection for SW2, SW3A/B, and SW4
SWxDVSSPEED[1:0] Function
SWx[6] = 0 or SWxSTBY[6] = 0
Function
SWx[6] = 1 or SWxSTBY[6] = 1
00 25 mV step each 2.0 μs 50 mV step each 4.0 μs
01 (default) 25 mV step each 4.0 μs 50 mV step each 8.0 μs
10 25 mV step each 8.0 μs 50 mV step each 16 μs
11 25 mV step each 16 μs 50 mV step each 32 μs
Table 35. Regulator phase clock selection
SWxPHASE[1:0] Phase of clock sent to regulator
(degrees)
00 0
01 90
10 180
11 270
Actual
Output Voltage
Example
Actual Output
Voltage
Possible
Output Voltage
Window
Internally
Controlled Steps
Output Voltage
with light Load
Initial
Set Point
Voltage
Change
Request
Internally
Controlled Steps
Output
Voltage
Requested
Set Point
Initiated by I2C Programming, Standby Control
Request for
Higher Voltage
Request for
Lower Voltage
36 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.2.3 Programmable maximum current
The maximum current, ISWxMAX, of each buck regulator is programmable. This allows the use of smaller inductors where lower currents
are required. Programmability is accomplished by choosing the number of paralleled power stages in each regulator. The
SWx_PWRSTG[2:0] bits in Table 137. Extended page 2, page 110 of the register map control the number of power stages. See Table 38
for the programmable options. Bit[0] must always be enabled to ensure the stage with the current sensor is chosen. The default setting,
SWx_PWRSTG[2:0] = 111, represents the highest maximum current. The current limit for each option is also scaled by the percentage of
power stages that are enabled.
Table 36. Optimum phasing
Frequencies Optimum phasing
1.0 MHz
2.0 MHz
0 °
180 °
1.0 MHz
4.0 MHz
0 °
180 °
2.0 MHz
4.0 MHz
0 °
180 °
1.0 MHz
2.0 MHz
4.0 MHz
0 °
90 °
90 °
Table 37. Regulator frequency configuration
SWxFREQ[1:0] Frequency
00 1.0 MHz
01 2.0 MHz
10 4.0 MHz
11 Reserved
Table 38. Programmable current configuration
Regulators Control bits % of power stages
enabled Rated current (A)
SW1AB
SW1AB_PWRSTG[2:0] ISW1ABMAX
0 0 1 40% 1.0
0 1 1 80% 2.0
1 0 1 60% 1.5
1 1 1 100% 2.5
SW1C
SW1C_PWRSTG[2:0] ISW1CMAX
0 0 1 43% 0.9
0 1 1 58% 1.2
1 0 1 86% 1.7
1 1 1 100% 2.0
SW2
SW2_PWRSTG[2:0] ISW2MAX
0 0 1 38% 0.75
0 1 1 75% 1.5
1 0 1 63% 1.25
1 1 1 100% 2.0
NXP Semiconductors 37
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.3 SW1A/B/C
SW1/A/B/C are 2.5 A to 4.5 A buck regulators which can be configured in various phasing schemes, depending on the desired cost/
performance trade-offs. The following configurations are available:
• SW1A/B/C single phase with one inductor
• SW1A/B as a single phase with one inductor and SW1C in independent mode with one inductor
• SW1A/B as a dual phase with two inductors and SW1C in independent mode with one inductor
The desired configuration is programmed by OTP by using SW1_CONFIG[1:0] bits in the register map Table 136. Extended page 1, page
106, as shown in Table 39.
.
6.4.4.3.1 SW1A/B/C single phase
In this configuration, all phases A, B, and C, are connected together to a single inductor, thus, providing up to 4.50 A current capability for
high current applications. The feedback and all other controls are accomplished by use of pin SW1CFB and SW1C control registers,
respectively. Figure 11 shows the connection for SW1A/B/C in single phase mode.
During single phase mode operation, all three phases use the same configuration for frequency, phase, and DVS speed set in the
SW1CCONF register. However, the same configuration settings for frequency, phase, and DVS speed setting on SW1AB registers should
be used. The SW1FB pin should be left floating in this configuration.
SW3A
SW3A_PWRSTG[2:0] ISW3AMAX
0 0 1 40% 0.5
0 1 1 80% 1.0
1 0 1 60% 0.75
1 1 1 100% 1.25
SW3B
SW3B_PWRSTG[2:0] ISW3BMAX
0 0 1 40% 0.5
0 1 1 80% 1.0
1 0 1 60% 0.75
1 1 1 100% 1.25
SW4
SW4_PWRSTG[2:0] ISW4MAX
0 0 1 50% 0.5
0 1 1 75% 0.75
1 0 1 75% 0.75
1 1 1 100% 1.0
Table 39. SW1 configuration
SW1_CONFIG[1:0] Description
00 A/B/C single phase
01 A/B single phase
C independent mode
10 A/B dual phase
C independent mode
11 Reserved
Table 38. Programmable current configuration (continued)
Regulators Control bits % of power stages
enabled Rated current (A)
38 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 11. SW1A/B/C single phase block diagram
6.4.4.3.2 SW1A/B single phase - SW1C independent mode
In this configuration, SW1A/B is connected as a single phase with a single inductor, while SW1C is used as an independent output, using
its own inductor and configurations parameters. This configuration allows reduced component count by using only one inductor for
SW1A/B. As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different
voltage set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 12 shows the
physical connection for SW1A/B in single phase and SW1C as an independent output.
Driver
Controller
SW1AIN
SW1ALX
SW1FB
ISENSE
COSW1A
CINSW1A
LSW1
I2C
Interface
SW1A/B/C
SW1AMODE
SW1AFAULT
VIN
Driver
Controller
SW1BIN
SW1BLX
ISENSE
CINSW1B
SW1BMODE
SW1BFAULT
VIN
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW1CIN
SW1CLX
SW1CFB
ISENSE
CINSW1C
EP
SW1CMODE
SW1CFAULT
VREF
DAC
I2C
VIN
NXP Semiconductors 39
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 12. SW1A/B single phase, SW1C independent mode block diagram
Both SW1ALX and SW1BLX nodes operate at the same DVS, frequency, and phase configured by the SW1ABCONF register, while
SW1CLX node operates independently, using the configuration in the SW1CCONF register.
6.4.4.3.3 SW1A/B dual phase - SW1C independent mode
In this mode, SW1A/B is connected in dual phase mode using one inductor per switching node, while SW1C is used as an independent
output using its own inductor and configuration parameters. This mode provides a smaller output voltage ripple on the SW1A/B output.
As mentioned before, SW1A/B and SW1C operate independently from one another, thus, they can be operated with a different voltage
set point for normal, standby, and sleep modes, as well as switching mode selection and on/off control. Figure 13 shows the physical
connection for SW1A/B in dual phase and SW1C as an independent output.
Driver
Controller
SW1AIN
SW1ALX
SW1FB
ISENSE
COSW1A
CINSW1A
LSW1A
I2C
Interface
SW1A/B
SW1AMODE
SW1AFAULT
VIN
Driver
Controller
SW1BIN
SW1BLX
ISENSE
CINSW1B
SW1BMODE
SW1BFAULT
VIN
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW1CIN
SW1CLX
SW1CFB
ISENSE
COSW1C
CINSW1C
LSW1C
EP
SW1C
SW1CMODE
SW1CFAULT
VREF
DAC
I2C
VIN
40 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 13. SW1A/B dual phase, SW1C independent mode block diagram
In this mode of operation, SW1ALX and SW1BLX nodes operate automatically at 180 ° phase shift from each other and use the same
frequency and DVS configured by SW1ABCONF register, while SW1CLX node operate independently using the configuration in the
SW1CCONF register.
VIN
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW1AIN
SW1ALX
SW1FB
ISENSE
COSW1A
CINSW1A
LSW1A
I2C
Interface
SW1AB
SW1AMODE
SW1AFAULT
VREF
DAC
I2C
Driver
Controller
SW1BIN
SW1BLX
ISENSE
COSW1B
CINSW1B
LSW1B
SW1BMODE
SW1BFAULT
VIN
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW1CIN
SW1CLX
SW1CFB
ISENSE
COSW1C
CINSW1C
LSW1C
EP
SW1C
SW1CMODE
SW1CFAULT
VREF
DAC
I2C
VIN
NXP Semiconductors 41
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.3.4 SW1A/B/C setup and control registers
SW1A/B and SW1C output voltages are programmable from 0.300 V to 1.875 V in steps of 25 mV. The output voltage set point is
independently programmed for normal, standby, and sleep mode by setting the SW1x[5:0], SW1xSTBY[5:0], and SW1xOFF[5:0] bits
respectively. Table 40 shows the output voltage coding for SW1A/B or SW1C.
Note: Voltage set points of 0.6 V and below are not supported.
Table 41 provides a list of registers used to configure and operate SW1A/B/C and a detailed description on each one of these register is
provided in Table 42 through Table 51.
Table 40. SW1A/B/C output voltage configuration
Set point
SW1x[5:0]
SW1xSTBY[5:0]
SW1xOFF[5:0]
SW1x output (V) Set point
SW1x[5:0]
SW1xSTBY[5:0]
SW1xOFF[5:0]
SW1x output (V)
0 000000 0.3000 32 100000 1.1000
1 000001 0.3250 33 100001 1.1250
2 000010 0.3500 34 100010 1.1500
3 000011 0.3750 35 100011 1.1750
4 000100 0.4000 36 100100 1.2000
5 000101 0.4250 37 100101 1.2250
6 000110 0.4500 38 100110 1.2500
7 000111 0.4750 39 100111 1.2750
8 001000 0.5000 40 101000 1.3000
9 001001 0.5250 41 101001 1.3250
10 001010 0.5500 42 101010 1.3500
11 001011 0.5750 43 101011 1.3750
12 001100 0.6000 44 101100 1.4000
13 001101 0.6250 45 101101 1.4250
14 001110 0.6500 46 101110 1.4500
15 001111 0.6750 47 101111 1.4750
16 010000 0.7000 48 110000 1.5000
17 010001 0.7250 49 110001 1.5250
18 010010 0.7500 50 110010 1.5500
19 010011 0.7750 51 110011 1.5750
20 010100 0.8000 52 110100 1.6000
21 010101 0.8250 53 110101 1.6250
22 010110 0.8500 54 110110 1.6500
23 010111 0.8750 55 110111 1.6750
24 011000 0.9000 56 111000 1.7000
25 011001 0.9250 57 111001 1.7250
26 011010 0.9500 58 111010 1.7500
27 011011 0.9750 59 111011 1.7750
28 011100 1.0000 60 111100 1.8000
29 011101 1.0250 61 111101 1.8250
30 011110 1.0500 62 111110 1.8500
31 011111 1.0750 63 111111 1.8750
42 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 41. SW1A/B/C register summary
Register Address Output
SW1ABVOLT 0x20 SW1AB output voltage set point in normal operation
SW1ABSTBY 0x21 SW1AB output voltage set point on standby
SW1ABOFF 0x22 SW1AB output voltage set point on sleep
SW1ABMODE 0x23 SW1AB switching mode selector register
SW1ABCONF 0x24 SW1AB DVS, phase, frequency and ILIM configuration
SW1CVOLT 0x2E SW1C output voltage set point in normal operation
SW1CSTBY 0x2F SW1C output voltage set point in standby
SW1COFF 0x30 SW1C output voltage set point in sleep
SW1CMODE 0x31 SW1C switching mode selector register
SW1CCONF 0x32 SW1C DVS, phase, frequency and ILIM configuration
Table 42. Register SW1ABVOLT - ADDR 0x20
Name Bit # R/W Default Description
SW1AB 5:0 R/W 0x00
Sets the SW1AB output voltage during normal
operation mode. See Table 40 for all possible
configurations.
UNUSED 7:6 – 0x00 unused
Table 43. Register SW1ABSTBY - ADDR 0x21
Name Bit # R/W Default Description
SW1ABSTBY 5:0 R/W 0x00
Sets the SW1AB output voltage during standby
mode. See Table 40 for all possible
configurations.
UNUSED 7:6 – 0x00 unused
Table 44. Register SW1ABOFF - ADDR 0x22
Name Bit # R/W Default Description
SW1ABOFF 5:0 R/W 0x00
Sets the SW1AB output voltage during sleep
mode. See Table 40 for all possible
configurations.
UNUSED 7:6 – 0x00 unused
Table 45. Register SW1ABMODE - ADDR 0x23
Name Bit # R/W Default Description
SW1ABMODE 3:0 R/W 0x80 Sets the SW1AB switching operation mode.
See Table 30 for all possible configurations.
UNUSED 4 – 0x00 UNUSED
SW1ABOMODE 5 R/W 0x00
Set status of SW1AB when in sleep mode
0 = OFF
1 = PFM
UNUSED 7:6 – 0x00 unused
NXP Semiconductors 43
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 46. Register SW1ABCONF - ADDR 0x24
Name Bit # R/W Default Description
SW1ABILIM 0 R/W 0x00
SW1AB current limit level selection
0 = High level current limit
1 = Low level current limit
UNUSED 1 R/W 0x00 Unused
SW1ABFREQ 3:2 R/W 0x00 SW1A/B switching frequency selector.
See Table 37.
SW1ABPHASE 5:4 R/W 0x00 SW1A/B phase clock selection.
See Table 35.
SW1ABDVSSPEED 7:6 R/W 0x00 SW1A/B DVS speed selection.
See Table 33.
Table 47. Register SW1CVOLT - ADDR 0x2E
Name Bit # R/W Default Description
SW1C 5:0 R/W 0x00
Sets the SW1C output voltage during normal
operation mode. See Table 40 for all possible
configurations.
UNUSED 7:6 – 0x00 unused
Table 48. Register SW1CSTBY - ADDR 0x2F
Name Bit # R/W Default Description
SW1CSTBY 5:0 R/W 0x00
Sets the SW1C output voltage during standby
mode. See Table 40 for all possible
configurations.
UNUSED 7:6 – 0x00 unused
Table 49. Register SW1COFF - ADDR 0x30
Name Bit # R/W Default Description
SW1COFF 5:0 R/W 0x00
Sets the SW1C output voltage during sleep
mode. See Table 40 for all possible
configurations.
UNUSED 7:6 – 0x00 unused
Table 50. Register SW1CMODE - ADDR 0x31
Name Bit # R/W Default Description
SW1CMODE 3:0 R/W 0x80 Sets the SW1C switching operation mode.
See Table 29 for all possible configurations.
UNUSED 4 – 0x00 unused
SW1COMODE 5 R/W 0x00
Set status of SW1C when in sleep mode
0 = OFF
1 = PFM
UNUSED 7:6 – 0x00 unused
44 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.3.5 SW1A/B/C external components
Table 51. Register SW1CCONF - ADDR 0x32
Name Bit # R/W Default Description
SW1CILIM 0 R/W 0x00
SW1C current limit level selection
0 = High level current limit
1 = Low level current limit
UNUSED 1 R/W 0x00 Unused
SW1CFREQ 3:2 R/W 0x00 SW1C switching frequency selector.
See Table 37.
SW1CPHASE 5:4 R/W 0x00 SW1C phase clock selection.
See Table 35.
SW1CDVSSPEED 7:6 R/W 0x00 SW1C DVS speed selection.
See Table 33.
Table 52. SW1A/B/C external component recommendations
Components Description
Mode
A/B/C single
phase
A/B single - C
independent mode
A/B dual - C
independent mode
CINSW1A(41) SW1A input capacitor 4.7 μF4.7 μF 4.7 μF
CIN1AHF(41) SW1A decoupling input capacitor 0.1 μF0.1 μF 0.1 μF
CINSW1B(41) SW1B input capacitor 4.7 μF4.7 μF 4.7 μF
CIN1BHF(41) SW1B decoupling input capacitor 0.1 μF0.1 μF 0.1 μF
CINSW1C(41) SW1C input capacitor 4.7 μF4.7 μF 4.7 μF
CIN1CHF(41) SW1C decoupling input capacitor 0.1 μF0.1 μF 0.1 μF
COSW1AB(41) SW1A/B output capacitor 6 x 22 μF4 x 22 μF 4 x 22 μF
COSW1C(41) SW1C output capacitor – 2 x 22 μF 2 x 22 μF
LSW1A SW1A inductor
1.0 μH
DCR = 12 mΩ
ISAT = 6.0 A
1.0 μH
DCR = 12 mΩ
ISAT = 4.5 A
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
LSW1B SW1B inductor – –
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
LSW1C SW1C inductor –
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
1.0 μH
DCR = 60 mΩ
ISAT = 2.4 A
Notes
41. Use X5R or X7R capacitors.
NXP Semiconductors 45
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.3.6 SW1A/B/C specifications
Table 53. SW1A/B/C electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
SW1A/B/C (single phase)
VINSW1A
VINSW1B
VINSW1C
Operating input voltage 2.8 – 4.5 V
VSW1ABC Nominal output voltage – Table 40 –V
VSW1ABCACC
Output voltage accuracy
• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 4.5 A
0.625 V ≤ VSW1ABC ≤ 1.450 V
1.475 V ≤ VSW1ABC ≤ 1.875 V
• PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1ABC < 150 mA
0.625 V < VSW1ABC < 0.675 V
0.7 V < VSW1ABC < 0.85 V
0.875 V < VSW1ABC < 1.875 V
-25
-3.0%
-65
-45
-3.0%
–
–
–
–
–
25
3.0%
65
45
3.0%
mV
%
ISW1ABC
Rated output load current,
2.8 V < VIN < 4.5 V, 0.625 V < VSW1ABC < 1.875 V – – 4500 mA
ISW1ABCLIM
Current limiter peak current detection
• Current through inductor
SW1ABILIM = 0
SW1ABILIM = 1
7.1
5.3
10.5
7.9
13.7
10.3
A
VSW1ABCOSH
Start-up overshoot
ISW1ABC = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1ABC = 1.875 V
––66mV
tONSW1ABC
Turn-on time
Enable to 90% of end value
ISW1x = 0 mA
DVS clk = 25 mV/4.0 μs, VIN = VINSW1x = 4.5 V,
VSW1ABC = 1.875 V
– – 500 µs
fSW1ABC
Switching frequency
SW1xFREQ[1:0] = 00
SW1xFREQ[1:0] = 01
SW1xFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
MHz
ηSW1ABC
Efficiency
•V
IN = 3.6 V, fSW1ABC = 2.0 MHz, LSW1ABC = 1.0 μH
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 850 mA
APS, PWM, 1.2 V, 1275 mA
APS, PWM, 1.2 V, 2125 mA
APS, PWM, 1.2 V, 4500 mA
–
–
–
–
–
–
77
82
86
84
80
70
–
–
–
–
–
–
%
ΔVSW1ABC Output ripple – 10 – mV
VSW1ABCLIR Line regulation (APS, PWM) – – 20 mV
VSW1ABCLOR DC load regulation (APS, PWM) – – 20 mV
VSW1ABCLOTR
Transient load regulation
• Transient load = 0 A to 2.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
–
–
–
–
50
50
mV
46 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW1A/B/C (single phase) (continued)
ISW1ABCQ
Quiescent current
PFM mode
APS mode
–
–
18
145
–
–
µA
RSW1ABCDIS Discharge resistance – 600 – W
SW1A/B (single/dual phasE)
VINSW1A
VINSW1B
Operating input voltage 2.8 – 4.5 V
VSW1AB Nominal output voltage – Table 40 –V
VSW1ABACC
Output voltage accuracy
• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 2.5 A
0.625 V ≤ VSW1AB ≤ 1.450 V
1.475 V ≤ VSW1AB ≤ 1.875 V
• PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW1AB < 150 mA
0.625 V < VSW1AB < 0.675 V
0.7 V < VSW1AB < 0.85 V
0.875 V < VSW1AB < 1.875 V
-25
-3.0%
-65
-45
-3.0%
-
-
–
–
–
25
3.0%
-65
-45
3.0%
mV
%
ISW1AB
Rated output load current,
2.8 V < VIN < 4.5 V, 0.625 V < VSW1AB < 1.875 V – – 2500 mA (43)
ISW1ABLIM
Current limiter peak current detection
• SW1A/B single phase (current through inductor)
SW1ABILIM = 0
SW1ABILIM = 1
• SW1A/B dual phase (current through inductor per phase)
SW1ABILIM = 0
SW1ABILIM = 1
4.5
3.3
2.2
1.6
6.5
4.9
3.2
2.4
8.5
6.4
4.3
3.2
A (43)
VSW1ABOSH
Start-up overshoot
ISW1AB = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
––66mV
tONSW1AB
Turn-on time
Enable to 90% of end value
ISW1AB = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1x = 4.5 V, VSW1AB = 1.875 V
– – 500 µs
fSW1AB
Switching frequency
SW1ABFREQ[1:0] = 00
SW1ABFREQ[1:0] = 01
SW1ABFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
MHz
ηSW1AB
Efficiency (single phase)
•V
IN = 3.6 V, fSW1AB = 2.0 MHz, LSW1AB = 1.0 μH
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 500 mA
APS, PWM, 1.2 V, 750 mA
APS, PWM, 1.2 V, 1250 mA
APS, PWM, 1.2 V, 2500 mA
–
–
–
–
–
–
82
84
86
87
83
75
–
–
–
–
–
–
%
ΔVSW1AB Output ripple –10–mV
VSW1ABLIR Line regulation (APS, PWM) – – 20 mV
Table 53. SW1A/B/C electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
NXP Semiconductors 47
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW1A/B (single/dual phase) (continued)
VSW1ABLOR DC load regulation (APS, PWM) – – 20 mV
VSW1ABLOTR
Transient load regulation
• Transient load = 0 A to 1.25 A, di/dt = 100 mA/μs
Overshoot
Undershoot
–
–
–
–
50
50
mV
ISW1ABQ
Quiescent current
PFM mode
APS mode
–
–
18
235
–
–
µA
RONSW1AP
SW1A P-MOSFET RDS(on)
VINSW1A = 3.3 V – 215 245 mΩ
RONSW1AN
SW1A N-MOSFET RDS(on)
VINSW1A = 3.3 V – 258 326 mΩ
ISW1APQ
SW1A P-MOSFET leakage current
VINSW1A = 4.5 V ––7.5µA
ISW1ANQ
SW1A N-MOSFET leakage current
VINSW1A = 4.5 V ––2.5µA
RONSW1BP
SW1B P-MOSFET RDS(on)
VINSW1B = 3.3 V – 215 245 mΩ
RONSW1BN
SW1B N-MOSFET RDS(on)
VINSW1B = 3.3 V – 258 326 mΩ
ISW1BPQ
SW1B P-MOSFET leakage current
VINSW1B = 4.5 V ––7.5µA
ISW1BNQ
SW1B N-MOSFET leakage current
VINSW1B = 4.5 V ––2.5µA
RSW1ABDIS Discharge Resistance – 600 – W
SW1C (independent)
VINSW1C Operating input voltage 2.8 – 4.5 V
VSW1C Nominal output voltage – Table 40 –V
VSW1CACC
Output voltage accuracy
• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW1C < 2.0 A
0.625 V ≤ VSW1C ≤ 1.450 V
1.475 V ≤ VSW1C ≤ 1.875 V
• PFM, steady state 2.8 V < VIN < 4.5 V, 0 < ISW1C < 50 mA
0.625 V < VSW1C < 0.675 V
0.7 V < VSW1C < 0.85 V
0.875 V < VSW1C < 1.875 V
-25
-3.0%
-65
-45
-3.0%
–
–
–
–
–
25
3.0%
65
45
3.0%
mV
ISW1C
Rated output load current
2.8 V < VIN < 4.5 V, 0.625 V < VSW1C < 1.875 V – – 2000 mA
ISW1CLIM
Current limiter peak current detection
• Current through inductor
SW1CILIM = 0
SW1CILIM = 1
2.6(42)
1.95
4.0
3.0
5.2
3.9
A
Table 53. SW1A/B/C electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
48 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
SW1C (independent) (continued)
VSW1COSH
Start-up overshoot
ISW1C = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V
––66mV
tONSW1C
Turn-on time
Enable to 90% of end value
ISW1C = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW1C = 4.5 V, VSW1C = 1.875 V
– – 500 µs
fSW1C
Switching frequency
SW1CFREQ[1:0] = 00
SW1CFREQ[1:0] = 01
SW1CFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
MHz
ηSW1C
Efficiency
•V
IN = 3.6 V, fSW1C = 2.0 MHz, LSW1C = 1.0 μH
PFM, 0.9 V, 1.0 mA
PFM, 1.2 V, 50 mA
APS, PWM, 1.2 V, 400 mA
APS, PWM, 1.2 V, 600 mA
APS, PWM, 1.2 V, 1000 mA
APS, PWM, 1.2 V, 2000 mA
–
–
–
–
–
–
77
78
86
84
78
68
–
–
–
–
–
–
%
ΔVSW1C Output ripple –10–mV
VSW1CLIR Line regulation (APS, PWM) – – 20 mV
VSW1CLOR DC load regulation (APS, PWM) – – 20 mV
VSW1CLOTR
Transient load regulation
• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
Overshoot
Undershoot
–
–
–
–
50
50
mV
ISW1CQ
Quiescent current
PFM mode
APS mode
–
–
22
145
–
–
µA
RONSW1CP
SW1C P-MOSFET RDS(on)
at VINSW1C = 3.3 V – 184 206 mΩ
RONSW1CN
SW1C N-MOSFET RDS(on)
at VINSW1C = 3.3 V – 211 260 mΩ
ISW1CPQ
SW1C P-MOSFET leakage current
VINSW1C = 4.5 V – – 10.5 µA
ISW1CNQ
SW1C N-MOSFET leakage current
VINSW1C = 4.5 V ––3.5µA
RSW1CDIS Discharge resistance – 600 – W
Notes
42. Supports the Coremark and 3D MM benchmark maximum current value of 2500 mA of the VDD_SOC_IN domain in the i.MX 6Dual/Quad
processors.
43. Current rating of SW1AB supports the power virus mode of operation of the i.MX 6X processor.
Table 53. SW1A/B/C electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V,
ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], typical external component values, fSW1x = 2.0 MHz, unless otherwise noted. Typical
values are characterized at VIN = VINSW1x = 3.6 V, VSW1x = 1.2 V, ISW1x = 100 mA, SW1x_PWRSTG[2:0] = [111], and 25 °C, unless
otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
NXP Semiconductors 49
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 14. SW1AB and SW1C efficiency waveforms
SW1AB single phase
SW1C independent mode
Efficiency (%)
SW1ABC single phase
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000 10000
PFM -Vout = 1.2V
APS - Vout = 1.2V
PWM - Vout = 1.2V
Efficiency (%)
Load current (mA)
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
PFM - Vout = 1.2V
APS - Vout = 1.2V
PWM - Vout = 1.2v
Load current (mA)
Efficiency (%)
0
10
20
30
40
50
60
70
80
90
100
1 10 100 1000
PFM - Vout = 1.2V
APS - Vout = 1.2V
PWM - Vout = 1.2v
Load current (mA)
Efficiency (%)
50 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.4 SW2
SW2 is a single phase, 2.0 A rated buck regulator (2.5 A in NP/F9/FA versions). Table 29 describes the modes, and Table 30 show the
options for the SWxMODE[3:0] bits. Figure 15 shows the block diagram and the external component connections for SW2 regulator.
Figure 15. SW2 block diagram
6.4.4.4.1 SW2 setup and control registers
SW2 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW2[6] in register SW2VOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW2[6] is
set to “0”, the output is limited to the lower output voltages from 0.400 V to 1.975 V with 25 mV increments, as determined by bits SW2[5:0].
Likewise, once bit SW2[6] is set to “1”, the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V with 50 mV
increments, as determined by bits SW2[5:0].
To optimize the performance of the regulator, it is recommended that only voltages from 2.000 V to 3.300 V be used in the high range,
and the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW2[5:0], SW2STBY[5:0]
and SW2OFF[5:0] bits, respectively. However, the initial state of bit SW2[6] is copied into bits SW2STBY[6], and SW2OFF[6] bits.
Therefore, the output voltage range remains the same in all three operating modes. Table 54 shows the output voltage coding valid for
SW2.
Note: Voltage set points of 0.6 V and below are not supported.
Table 54. SW2 output voltage configuration
Low output voltage range(44) High output voltage range
Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output
0 0000000 0.4000 64 1000000 0.8000
1 0000001 0.4250 65 1000001 0.8500
2 0000010 0.4500 66 1000010 0.9000
3 0000011 0.4750 67 1000011 0.9500
4 0000100 0.5000 68 1000100 1.0000
5 0000101 0.5250 69 1000101 1.0500
6 0000110 0.5500 70 1000110 1.1000
7 0000111 0.5750 71 1000111 1.1500
8 0001000 0.6000 72 1001000 1.2000
9 0001001 0.6250 73 1001001 1.2500
10 0001010 0.6500 74 1001010 1.3000
11 0001011 0.6750 75 1001011 1.3500
12 0001100 0.7000 76 1001100 1.4000
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW2IN
SW2LX
SW2FB
ISENSE
COSW2
CINSW2
LSW2
I2C
Interface
EP
SW2
SW2MODE
SW2FAULT
VREF
DAC
I2C
VIN
NXP Semiconductors 51
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
13 0001101 0.7250 77 1001101 1.4500
14 0001110 0.7500 78 1001110 1.5000
15 0001111 0.7750 79 1001111 1.5500
16 0010000 0.8000 80 1010000 1.6000
17 0010001 0.8250 81 1010001 1.6500
18 0010010 0.8500 82 1010010 1.7000
19 0010011 0.8750 83 1010011 1.7500
20 0010100 0.9000 84 1010100 1.8000
21 0010101 0.9250 85 1010101 1.8500
22 0010110 0.9500 86 1010110 1.9000
23 0010111 0.9750 87 1010111 1.9500
24 0011000 1.0000 88 1011000 2.0000
25 0011001 1.0250 89 1011001 2.0500
26 0011010 1.0500 90 1011010 2.1000
27 0011011 1.0750 91 1011011 2.1500
28 0011100 1.1000 92 1011100 2.2000
29 0011101 1.1250 93 1011101 2.2500
30 0011110 1.1500 94 1011110 2.3000
31 0011111 1.1750 95 1011111 2.3500
32 0100000 1.2000 96 1100000 2.4000
33 0100001 1.2250 97 1100001 2.4500
34 0100010 1.2500 98 1100010 2.5000
35 0100011 1.2750 99 1100011 2.5500
36 0100100 1.3000 100 1100100 2.6000
37 0100101 1.3250 101 1100101 2.6500
38 0100110 1.3500 102 1100110 2.7000
39 0100111 1.3750 103 1100111 2.7500
40 0101000 1.4000 104 1101000 2.8000
41 0101001 1.4250 105 1101001 2.8500
42 0101010 1.4500 106 1101010 2.9000
43 0101011 1.4750 107 1101011 2.9500
44 0101100 1.5000 108 1101100 3.0000
45 0101101 1.5250 109 1101101 3.0500
46 0101110 1.5500 110 1101110 3.1000
47 0101111 1.5750 111 1101111 3.1500
48 0110000 1.6000 112 1110000 3.2000
49 0110001 1.6250 113 1110001 3.2500
50 0110010 1.6500 114 1110010 3.3000
51 0110011 1.6750 115 1110011 Reserved
52 0110100 1.7000 116 1110100 Reserved
53 0110101 1.7250 117 1110101 Reserved
Table 54. SW2 output voltage configuration (continued)
Low output voltage range(44) High output voltage range
Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output
52 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Setup and control of SW2 is done through I2C registers listed in Table 55, and a detailed description of each one of the registers is provided
in Tables 56 to Table 60.
54 0110110 1.7500 118 1110110 Reserved
55 0110111 1.7750 119 1110111 Reserved
56 0111000 1.8000 120 1111000 Reserved
57 0111001 1.8250 121 1111001 Reserved
58 0111010 1.8500 122 1111010 Reserved
59 0111011 1.8750 123 1111011 Reserved
60 0111100 1.9000 124 1111100 Reserved
61 0111101 1.9250 125 1111101 Reserved
62 0111110 1.9500 126 1111110 Reserved
63 0111111 1.9750 127 1111111 Reserved
Notes
44. For voltages less than 2.0 V, only use set points 0 to 63.
Table 55. SW2 register summary
Register Address Description
SW2VOLT 0x35 Output voltage set point on normal operation
SW2STBY 0x36 Output voltage set point on standby
SW2OFF 0x37 Output voltage set point on sleep
SW2MODE 0x38 Switching mode selector register
SW2CONF 0x39 DVS, phase, frequency, and ILIM configuration
Table 56. Register SW2VOLT - ADDR 0x35
Name Bit # R/W Default Description
SW2 5:0 R/W 0x00 Sets the SW2 output voltage during normal operation
mode. See Table 54 for all possible configurations.
SW2 6 R 0x00
Sets the operating output voltage range for SW2. Set
during OTP or TBB configuration only. See Table 54
for all possible configurations.
UNUSED 7 – 0x00 unused
Table 57. Register SW2STBY - ADDR 0x36
Name Bit # R/W Default Description
SW2STBY 5:0 R/W 0x00 Sets the SW2 output voltage during standby mode.
See Table 54 for all possible configurations.
SW2STBY 6 R 0x00
Sets the operating output voltage range for SW2 on
standby mode. This bit inherits the value configured
on bit SW2[6] during OTP or TBB configuration. See
Table 54 for all possible configurations.
UNUSED 7 – 0x00 unused
Table 54. SW2 output voltage configuration (continued)
Low output voltage range(44) High output voltage range
Set Point SW2[6:0] SW2 Output Set Point SW2[6:0] SW2 Output
NXP Semiconductors 53
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.4.2 SW2 external components
Table 58. Register SW2OFF - ADDR 0x37
Name Bit # R/W Default Description
SW2OFF 5:0 R/W 0x00 Sets the SW2 output voltage during sleep mode. See
Table 54 for all possible configurations.
SW2OFF 6 R 0x00
Sets the operating output voltage range for SW2 on
sleep mode. This bit inherits the value configured on
bit SW2[6] during OTP or TBB configuration. See
Table 54 for all possible configurations.
UNUSED 7 – 0x00 unused
Table 59. Register SW2MODE - ADDR 0x38
Name Bit # R/W Default Description
SW2MODE 3:0 R/W 0x80 Sets the SW2 switching operation mode.
See Table 29 for all possible configurations.
UNUSED 4 – 0x00 unused
SW2OMODE 5 R/W 0x00
Set status of SW2 when in sleep mode
0 = OFF
1 = PFM
UNUSED 7:6 – 0x00 unused
Table 60. Register SW2CONF - ADDR 0x39
Name Bit # R/W Default Description
SW2ILIM 0 R/W 0x00
SW2 current limit level selection (45)
0 = High level current limit
1 = Low level current limit
UNUSED 1 R/W 0x00 unused
SW2FREQ 3:2 R/W 0x00 SW2 switching frequency selector.
See Table 37.
SW2PHASE 5:4 R/W 0x00 SW2 phase clock selection.
See Table 35.
SW2DVSSPEED 7:6 R/W 0x00 SW2 DVS speed selection.
See Table 34.
Notes
45. SW2ILIM = 0 must be used in NP/F9/FA versions if 2.5 A output load current is desired
Table 61. SW2 external component recommendations
Components Description Values
CINSW2(46) SW2 input capacitor 4.7 μF
CIN2HF(46) SW2 decoupling input capacitor 0.1 μF
COSW2(46) SW2 output capacitor 2 x 22 μF
LSW2 SW2 inductor
1.0 μH
DCR = 50 mΩ
ISAT = 2.65 A
Notes
46. Use X5R or X7R capacitors.
54 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.4.3 SW2 specifications
Table 62. SW2 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V,
ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values
are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise
noted.
Symbol Parameter Min. Typ. Max. Unit Notes
Switch mode supply SW2
VINSW2 Operating input voltage 2.8 – 4.5 V (47)
VSW2 Nominal output voltage – Table 54 –V
VSW2ACC
Output voltage accuracy
• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW2 < 2.0 A
0.625 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
• PFM, 2.8 V < VIN < 4.5 V, 0 < ISW2 ≤ 50 mA
0.625 V < VSW2 < 0.675 V
0.7 V < VSW2 < 0.85 V
0.875 V < VSW2 < 1.975 V
2.0 V < VSW2 < 3.3 V
-25
-3.0%
-6.0%
-65
-45
-3.0%
-3.0%
–
–
–
–
–
–
–
25
3.0%
6.0%
65
45
3.0%
3.0%
mV
%
ISW2
Rated output load current
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW2 < 3.3 V
• 2.8 V < VIN < 4.5 V, 1.2 V < VSW2 < 3.3 V, SW2LIM = 0
–
–
–
–
2000
2500
mA (48)
(49)
ISW2LIM
Current limiter peak current detection
• Current through inductor
SW2ILIM = 0
SW2ILIM = 1
2.8
2.1
4.0
3.0
5.2
3.9
A
VSW2OSH
Start-up overshoot
ISW2 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW2 = 4.5 V
––66mV
tONSW2
Turn-on time
Enable to 90% of end value
ISW2 = 0.0 mA
DVS clk = 50 mV/8 μs, VIN = VINSW2 = 4.5 V
– – 550 µs
fSW2
Switching frequency
SW2FREQ[1:0] = 00
SW2FREQ[1:0] = 01
SW2FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
MHz
ηSW2
Efficiency
•V
IN = 3.6 V, fSW2 = 2.0 MHz, LSW2 = 1.0 μH
PFM, 3.15 V, 1.0 mA
PFM, 3.15 V, 50 mA
APS, PWM, 3.15 V, 400 mA
APS, PWM, 3.15 V, 600 mA
APS, PWM, 3.15 V, 1000 mA
APS, PWM, 3.15 V, 2000 mA
–
–
–
–
–
–
94
95
96
94
92
88
–
–
–
–
–
–
%
ΔVSW2 Output ripple –10–mV
VSW2LIR Line regulation (APS, PWM) – – 20 mV
VSW2LOR DC load regulation (APS, PWM) – – 20 mV
VSW2LOTR
Transient load regulation
• Transient load = 0.0 mA to 1.0 A, di/dt = 100 mA/μs
Overshoot
Undershoot
–
–
–
–
50
50
mV
NXP Semiconductors 55
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 16. SW2 efficiency waveforms
Switch mode supply SW2 (continued)
ISW2Q
Quiescent current
PFM mode
APS mode (low output voltage settings)
APS mode (high output voltage settings)
–
–
–
23
145
305
–
–
–
µA
RONSW2P
SW2 P-MOSFET RDS(on)
at VIN = VINSW2 = 3.3 V – 190 209 mΩ
RONSW2N
SW2 N-MOSFET RDS(on)
at VIN = VINSW2 = 3.3 V – 212 255 mΩ
ISW2PQ
SW2 P-MOSFET leakage current
VIN = VINSW2 = 4.5 V ––12µA
ISW2NQ
SW2 N-MOSFET leakage current
VIN = VINSW2 = 4.5 V ––4.0µA
RSW2DIS Discharge resistance – 600 – W
Notes
47. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V.
48. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW2 - VSW2) = ISW2* (DCR of Inductor +RONSW2P + PCB trace resistance).
49. Applies to NP/F9/FA versions
Table 62. SW2 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V,
ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], typical external component values, fSW2 = 2.0 MHz, unless otherwise noted. Typical values
are characterized at VIN = VINSW2 = 3.6 V, VSW2 = 3.15 V, ISW2 = 100 mA, SW2_PWRSTG[2:0] = [111], and 25 °C, unless otherwise
noted.
Symbol Parameter Min. Typ. Max. Unit Notes
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
PFM - Vout = 3.15V
APS - Vout = 3.15V
PWM - Vout = 3.15V
Efficiency (%)
Load current (mA)
56 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5 SW3A/B
SW3A/B are 1.25 A to 2.5 A rated buck regulators, depending on the configuration. Table 29 describes the available switching modes and
Table 30 show the actual configuration options for the SW3xMODE[3:0] bits.
SW3A/B can be configured in various phasing schemes, depending on the desired cost/performance trade-offs. The following
configurations are available:
• A single phase
• A dual phase
• Independent regulators
The desired configuration is programmed in OTP by using the SW3_CONFIG[1:0] bits.Table 63 shows the options for the SW3CFG[1:0]
bits.
6.4.4.5.1 SW3A/B single phase
In this configuration, SW3ALX and SW3BLX are connected in single phase with a single inductor a shown in Figure 17. This configuration
reduces cost and component count. Feedback is taken from the SW3AFB pin and the SW3BFB pin must be left open. Although control is
from SW3A, registers of both regulators, SW3A and SW3B, must be identically set.
Figure 17. SW3A/B single phase block diagram
Table 63. SW3 configuration
SW3_CONFIG[1:0] Description
00 A/B single phase
01 A/B single phase
10 A/B dual phase
11 A/B independent
Driver
Controller
SW3AIN
SW3ALX
SW3AFB
ISENSE
COSW3A
CINSW3A
LSW3A
I2C
Interface
SW3
SW3AMODE
SW3AFAULT
VIN
Driver
Controller
SW3BIN
SW3BLX
ISENSE
CINSW3B
EP
SW3BMODE
SW3BFAULT
VIN
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
SW3BFB
NXP Semiconductors 57
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5.2 SW3A/B dual phase
SW3A/B can be connected in dual phase configuration using one inductor per switching node, as shown in Figure 18. This mode allows
a smaller output voltage ripple. Feedback is taken from pin SW3AFB and pin SW3BFB must be left open. Although control is from SW3A,
registers of both regulators, SW3A and SW3B, must be identically set. In this configuration, the regulators switch 180 degrees apart.
Figure 18. SW3A/B dual phase block diagram
6.4.4.5.3 SW3A - SW3B independent outputs
SW3A and SW3B can be configured as independent outputs as shown in Figure 19, providing flexibility for applications requiring more
voltage rails with less current capability. Each output is configured and controlled independently by its respective I2C registers as shown
in Table 65.
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW3AIN
SW3ALX
SW3AFB
ISENSE
COSW3A
CINSW3A
LSW3A
I2C
Interface
SW3
SW3AMODE
SW3AFAULT
VREF
DAC
I2C
VIN
Driver
Controller
SW3BIN
SW3BLX
ISENSE
COSW3B
CINSW3B
LSW3B
EP
SW3BMODE
SW3BFAULT
VIN
EA
Z1
Z2
Internal
Compensation
VREF
DAC
I2C
SW3BFB
58 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 19. SW3A/B independent output block diagram
6.4.4.5.4 SW3A/B setup and control registers
SW3A/B output voltage is programmable from 0.400 V to 3.300 V; however, bit SW3x[6] in register SW3xVOLT is read-only during normal
operation. Its value is determined by the default configuration, or may be changed by using the OTP registers. Therefore, once SW3x[6]
is set to “0”, the output is limited to the lower output voltages from 0.40 V to 1.975 V with 25 mV increments, as determined by bits
SW3x[5:0]. Likewise, once bit SW3x[6] is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V to 3.300 V
with 50 mV increments, as determined by bits SW3x[5:0].
In order to optimize the performance of the regulator, it is recommended that only voltages from 2.00 to 3.300 V be used in the high range
and the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW3x[5:0],
SW3xSTBY[5:0], and SW3xOFF[5:0] bits respectively; however, the initial state of the SW3x[6] bit is copied into the SW3xSTBY[6] and
SW3xOFF[6] bits. Therefore, the output voltage range remains the same on all three operating modes. Table 64 shows the output voltage
coding valid for SW3x.
Note: Voltage set points of 0.6 V and below are not supported.
Table 64. SW3A/B output voltage configuration
Low output voltage range(50) High output voltage range
Set point SW3x[6:0] SW3x output Set point SW3x[6:0] sw3x output
0 0000000 0.4000 64 1000000 0.8000
1 0000001 0.4250 65 1000001 0.8500
2 0000010 0.4500 66 1000010 0.9000
3 0000011 0.4750 67 1000011 0.9500
4 0000100 0.5000 68 1000100 1.0000
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW3AIN
SW3ALX
SW3AFB
ISENSE
COSW3A
CINSW3A
LSW3A
I2C
Interface
SW3A
SW3AMODE
SW3AFAULT
VREF
DAC
I2C
VIN
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW3BIN
SW3BLX
SW3BFB
ISENSE
COSW3B
CINSW3B
LSW3B
EP
SW3B
SW3BMODE
SW3BFAULT
VREF
DAC
I2C
VIN
NXP Semiconductors 59
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
5 0000101 0.5250 69 1000101 1.0500
6 0000110 0.5500 70 1000110 1.1000
7 0000111 0.5750 71 1000111 1.1500
8 0001000 0.6000 72 1001000 1.2000
9 0001001 0.6250 73 1001001 1.2500
10 0001010 0.6500 74 1001010 1.3000
11 0001011 0.6750 75 1001011 1.3500
12 0001100 0.7000 76 1001100 1.4000
13 0001101 0.7250 77 1001101 1.4500
14 0001110 0.7500 78 1001110 1.5000
15 0001111 0.7750 79 1001111 1.5500
16 0010000 0.8000 80 1010000 1.6000
17 0010001 0.8250 81 1010001 1.6500
18 0010010 0.8500 82 1010010 1.7000
19 0010011 0.8750 83 1010011 1.7500
20 0010100 0.9000 84 1010100 1.8000
21 0010101 0.9250 85 1010101 1.8500
22 0010110 0.9500 86 1010110 1.9000
23 0010111 0.9750 87 1010111 1.9500
24 0011000 1.0000 88 1011000 2.0000
25 0011001 1.0250 89 1011001 2.0500
26 0011010 1.0500 90 1011010 2.1000
27 0011011 1.0750 91 1011011 2.1500
28 0011100 1.1000 92 1011100 2.2000
29 0011101 1.1250 93 1011101 2.2500
30 0011110 1.1500 94 1011110 2.3000
31 0011111 1.1750 95 1011111 2.3500
32 0100000 1.2000 96 1100000 2.4000
33 0100001 1.2250 97 1100001 2.4500
34 0100010 1.2500 98 1100010 2.5000
35 0100011 1.2750 99 1100011 2.5500
36 0100100 1.3000 100 1100100 2.6000
37 0100101 1.3250 101 1100101 2.6500
38 0100110 1.3500 102 1100110 2.7000
39 0100111 1.3750 103 1100111 2.7500
40 0101000 1.4000 104 1101000 2.8000
41 0101001 1.4250 105 1101001 2.8500
42 0101010 1.4500 106 1101010 2.9000
43 0101011 1.4750 107 1101011 2.9500
44 0101100 1.5000 108 1101100 3.0000
45 0101101 1.5250 109 1101101 3.0500
Table 64. SW3A/B output voltage configuration (continued)
Low output voltage range(50) High output voltage range
Set point SW3x[6:0] SW3x output Set point SW3x[6:0] sw3x output
60 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 65 provides a list of registers used to configure and operate SW3A/B. A detailed description on each of these register is provided
on Tables 66 through Table 75.
46 0101110 1.5500 110 1101110 3.1000
47 0101111 1.5750 111 1101111 3.1500
48 0110000 1.6000 112 1110000 3.2000
49 0110001 1.6250 113 1110001 3.2500
50 0110010 1.6500 114 1110010 3.3000
51 0110011 1.6750 115 1110011 Reserved
52 0110100 1.7000 116 1110100 Reserved
53 0110101 1.7250 117 1110101 Reserved
54 0110110 1.7500 118 1110110 Reserved
55 0110111 1.7750 119 1110111 Reserved
56 0111000 1.8000 120 1111000 Reserved
57 0111001 1.8250 121 1111001 Reserved
58 0111010 1.8500 122 1111010 Reserved
59 0111011 1.8750 123 1111011 Reserved
60 0111100 1.9000 124 1111100 Reserved
61 0111101 1.9250 125 1111101 Reserved
62 0111110 1.9500 126 1111110 Reserved
63 0111111 1.9750 127 1111111 Reserved
Notes
50. For voltages less than 2.0 V, only use set points 0 to 63.
Table 65. SW3AB register summary
Register Address Output
SW3AVOLT 0x3C SW3A output voltage set point on normal operation
SW3ASTBY 0x3D SW3A output voltage set point on standby
SW3AOFF 0x3E SW3A output voltage set point on sleep
SW3AMODE 0x3F SW3A switching mode selector register
SW3ACONF 0x40 SW3A DVS, phase, frequency and ILIM configuration
SW3BVOLT 0x43 SW3B output voltage set point on normal operation
SW3BSTBY 0x44 SW3B output voltage set point on standby
SW3BOFF 0x45 SW3B output voltage set point on sleep
SW3BMODE 0x46 SW3B switching mode selector register
SW3BCONF 0x47 SW3B DVS, phase, frequency and ILIM configuration
Table 64. SW3A/B output voltage configuration (continued)
Low output voltage range(50) High output voltage range
Set point SW3x[6:0] SW3x output Set point SW3x[6:0] sw3x output
NXP Semiconductors 61
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 66. Register SW3AVOLT - ADDR 0x3C
Name Bit # R/W Default Description
SW3A 5:0 R/W 0x00
Sets the SW3A output voltage (Independent) or
SW3A/B output voltage (single/dual phase),
during normal operation mode. See Table 64 for
all possible configurations.
SW3A 6 R 0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase).
Set during OTP or TBB configuration only. See
Table 64 for all possible configurations.
UNUSED 7 – 0x00 unused
Table 67. Register SW3ASTBY - ADDR 0x3D
Name Bit # R/W Default Description
SW3ASTBY 5:0 R/W 0x00
Sets the SW3A output voltage (independent) or
SW3A/B output voltage (single/dual phase),
during standby mode. See Table 64 for all
possible configurations.
SW3ASTBY 6 R 0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase) on
standby mode. This bit inherits the value
configured on bit SW3A[6] during OTP or TBB
configuration. See Table 64 for all possible
configurations.
UNUSED 7 – 0x00 unused
Table 68. Register SW3AOFF - ADDR 0x3E
Name Bit # R/W Default Description
SW3AOFF 5:0 R/W 0x00
Sets the SW3A output voltage (independent) or
SW3A/B output voltage (single/dual phase),
during sleep mode. See Table 64 for all possible
configurations.
SW3AOFF 6 R 0x00
Sets the operating output voltage range for SW3A
(independent) or SW3A/B (single/dual phase) on
sleep mode. This bit inherits the value configured
on bit SW3A[6] during OTP or TBB configuration.
See Table 64 for all possible configurations.
UNUSED 7 – 0x00 unused
Table 69. Register SW3AMODE - ADDR 0x3F
Name Bit # R/W Default Description
SW3AMODE 3:0 R/W 0x80
Sets the SW3A (Independent) or SW3A/B (single/
dual phase) switching operation mode.
See Table 29 for all possible configurations.
UNUSED 4 – 0x00 unused
SW3AOMODE 5 R/W 0x00
Set status of SW3A (independent) or SW3A/B
(single/dual phase) when in sleep mode.
0 = OFF
1 = PFM
UNUSED 7:6 – 0x00 unused
62 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 70. Register SW3ACONF - ADDR 0x40
Name Bit # R/W Default Description
SW3AILIM 0 R/W 0x00
SW3A current limit level selection
0 = High level current limit
1 = Low level current limit
UNUSED 1 R/W 0x00 unused
SW3AFREQ 3:2 R/W 0x00 SW3A switching frequency selector. See
Table 37.
SW3APHASE 5:4 R/W 0x00 SW3A phase clock selection. See Table 35.
SW3ADVSSPEED 7:6 R/W 0x00 SW3A DVS speed selection. See Table 34.
Table 71. Register SW3BVOLT - ADDR 0x43
Name Bit # R/W Default Description
SW3B 5:0 R/W 0x00
Sets the SW3B output voltage (independent)
during normal operation mode. See Table 64 for
all possible configurations.
SW3B 6 R 0x00
Sets the operating output voltage range for SW3B
(independent). Set during OTP or TBB
configuration only. See Table 64 for all possible
configurations.
UNUSED 7 – 0x00 unused
Table 72. Register SW3BSTBY - ADDR 0x44
Name Bit # R/W Default Description
SW3BSTBY 5:0 R/W 0x00
Sets the SW3B output voltage (Independent)
during standby mode. See Table 64 for all
possible configurations.
SW3BSTBY 6 R 0x00
Sets the operating output voltage range for SW3B
(independent) on standby mode. This bit inherits
the value configured on bit SW3B[6] during OTP
or TBB configuration. See Table 64 for all
possible configurations.
UNUSED 7 – 0x00 unused
Table 73. Register SW3BOFF - ADDR 0x45
Name Bit # R/W Default Description
SW3BOFF 5:0 R/W 0x00
Sets the SW3B output voltage (independent)
during sleep mode. See Table 64 for all possible
configurations.
SW3BOFF 6 R 0x00
Sets the operating output voltage range for SW3B
(independent) on sleep mode. This bit inherits the
value configured on bit SW3B[6] during OTP or
TBB configuration. See Table 64 for all possible
configurations.
UNUSED 7 – 0x00 unused
NXP Semiconductors 63
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5.5 SW3A/B external components
Table 74. Register SW3BMODE - ADDR 0x46
Name Bit # R/W Default Description
SW3BMODE 3:0 R/W 0x80
Sets the SW3B (Independent) switching
operation mode. See Table 29 for all possible
configurations.
UNUSED 4 – 0x00 unused
SW3BOMODE 5 R/W 0x00
Set status of SW3B (Independent) when in sleep
mode.
0 = OFF
1 = PFM
UNUSED 7:6 – 0x00 unused
Table 75. Register SW3BCONF - ADDR 0x47
Name Bit # R/W Default Description
SW3BILIM 0 R/W 0x00
SW3B current limit level selection
0 = High level current limit
1 = Low level current limit
UNUSED 1 R/W 0x00 unused
SW3BFREQ 3:2 R/W 0x00 SW3B switching frequency selector. See Table 37.
SW3BPHASE 5:4 R/W 0x00 SW3B phase clock selection. See Table 35.
SW3BDVSSPEED 7:6 R/W 0x00 SW3B DVS speed selection. See Table 34.
Table 76. SW3A/B external component requirements
Mode
Components Description SW3A/B single
phase
SW3A/B dual
phase
SW3A independent
SW3B independent
CINSW3A(51) SW3A input capacitor 4.7 μF4.7 μF4.7 μF
CIN3AHF(51) SW3A decoupling input capacitor 0.1 μF0.1 μF0.1 μF
CINSW3B(51) SW3B input capacitor 4.7 μF4.7 μF4.7 μF
CIN3BHF(51) SW3B decoupling input capacitor 0.1 μF0.1 μF0.1 μF
COSW3A(51) SW3A output capacitor 4 x 22 μF 2 x 22 μF 2 x 22 μF
COSW3B(51) SW3B output capacitor – 2 x 22 μF 2 x 22 μF
LSW3A SW3A inductor
1.0 μH
DCR = 50 mΩ
ISAT = 3.9 A
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
LSW3B SW3B inductor –
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
Notes
51. Use X5R or X7R capacitors.
64 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.5.6 SW3A/B specifications
Table 77. SW3A/B electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V,
ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
Switch mode supply SW3a/B
VINSW3x Operating input voltage 2.8 – 4.5 V (52)
VSW3x Nominal output voltage - Table 64 -V
VSW3xACC
Output voltage accuracy
• PWM, APS 2.8 V < VIN < 4.5 V, 0 < ISW3x < ISW3xMAX
0.625 V < VSW3x < 0.85 V
0.875 V < VSW3x < 1.975 V
2.0 V < VSW3x < 3.3 V
• PFM , steady state (2.8 V < VIN < 4.5 V, 0 < ISW3x < 50 mA)
0.625 V < VSW3x < 0.675 V
0.7 V < VSW3x < 0.85 V
0.875 V < VSW3x < 1.975 V
2.0 V < VSW3x < 3.3 V
-25
-3.0%
-6.0%
-65
-45
-3.0%
-3.0%
–
–
–
–
–
–
–
25
3.0%
6.0%
65
45
3.0%
3.0%
mV
%
ISW3x
Rated output load current
• 2.8 V < VIN < 4.5 V, 0.625 V < VSW3x < 3.3 V
PWM, APS mode single/dual phase
PWM, APS mode independent (per phase)
–
–
–
–
2500
1250
mA (53)
ISW3xLIM
Current limiter peak current detection
• Single phase (current through inductor)
SW3xILIM = 0
SW3xILIM = 1
• Independent mode or dual phase (current through inductor per
phase)
SW3xILIM = 0
SW3xILIM = 1
3.5
2.7
1.8
1.3
5.0
3.8
2.5
1.9
6.5
4.9
3.3
2.5
A
VSW3xOSH
Start-up overshoot
ISW3x = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
––66mV
tONSW3x
Turn-on time
Enable to 90% of end value
ISW3x = 0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW3x = 4.5 V
– – 500 µs
fSW3x
Switching frequency
SW3xFREQ[1:0] = 00
SW3xFREQ[1:0] = 01
SW3xFREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
MHz
ηSW3AB
Efficiency (single phase)
•f
SW3 = 2.0 MHz, LSW3x 1.0 μH
PFM, 1.5 V, 1.0 mA
PFM, 1.5 V, 50 mA
APS, PWM 1.5 V, 500 mA
APS, PWM 1.5 V, 750 mA
APS, PWM 1.5 V, 1250 mA
APS, PWM 1.5 V, 2500 mA
–
–
–
–
–
–
84
85
89
89
85
80
–
–
–
–
–
–
%
ΔVSW3x Output ripple – 10 – mV
NXP Semiconductors 65
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Switch mode supply SW3a/B (continued)
VSW3xLIR Line regulation (APS, PWM) – – 20 mV
VSW3xLOR DC load regulation (APS, PWM) – – 20 mV
VSW3xLOTR
Transient load regulation
• Transient load = 0.0 mA to ISW3x/2, di/dt = 100 mA/μs
Overshoot
Undershoot
–
–
–
–
50
50
mV
ISW3xQ
Quiescent current
PFM mode (single/dual phase)
APS mode (single/dual phase)
PFM mode (independent mode)
APS mode (SW3A independent mode)
APS mode (SW3B independent mode)
–
–
–
–
–
22
300
50
250
150
–
–
–
–
–
µA
RONSW3AP
SW3A P-MOSFET RDS(on)
at VIN = VINSW3A = 3.3 V – 215 245 mΩ
RONSW3AN
SW3A N-MOSFET RDS(on)
at VIN = VINSW3A = 3.3 V – 258 326 mΩ
ISW3APQ
SW3A P-MOSFET leakage current
VIN = VINSW3A = 4.5 V ––7.5µA
ISW3ANQ
SW3A N-MOSFET leakage current
VIN = VINSW3A = 4.5 V ––2.5µA
RONSW3BP
SW3B P-MOSFET RDS(on)
at VIN = VINSW3B = 3.3 V – 215 245 mΩ
RONSW3BN
SW3B N-MOSFET RDS(on)
at VIN = VINSW3B = 3.3 V – 258 326 mΩ
ISW3BPQ
SW3B P-MOSFET leakage current
VIN = VINSW3B = 4.5 V ––7.5µA
ISW3BPQ
SW3B N-MOSFET leakage current
VIN = VINSW3B = 4.5 V ––2.5µA
RSW3xDIS Discharge resistance – 600 – W
Notes
52. When output is set to > 2.6 V the output will follow the input down when VIN gets near 2.8 V.
53. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW3x - VSW3x) = ISW3x* (DCR of Inductor +RONSW3xP + PCB trace resistance).
Table 77. SW3A/B electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V,
ISW3x = 100 mA, SW3x_PWRSTG[2:0] = [111], typical external component values, fSW3x = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW3x = 3.6 V, VSW3x = 1.5 V, ISW3x = 100 mA,
SW3x_PWRSTG[2:0] = [111], and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
66 NXP Semiconductors
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 20. SW3AB single phase efficiency waveforms
6.4.4.6 SW4
SW4 is a 1.0 A rated single phase buck regulator capable of operating in two modes. In its default mode, it operates as a normal buck
regulator with a programmable output between 0.400 V and 3.300 V. It is capable of operating in the three available switching modes:
PFM, APS, and PWM, described on Table 29 and configured by the SW4MODE[3:0] bits, as shown in Table 30.
If the system requires DDR memory termination, SW4 can be used in its VTT mode. In the VTT mode, its reference voltage tracks the
output voltage of SW3A, scaled by 0.5. Furthermore, when in VTT mode, only the PWM switching mode is allowed. The VTT mode can
be configured by use of VTT bit in the OTP_SW4_CONFIG register.
Figure 21 shows the block diagram and the external component connections for the SW4 regulator.
Figure 21. SW4 block diagram
6.4.4.6.1 SW4 setup and control registers
To set the SW4 in regulator or VTT mode, bit VTT of the register OTP_SW4_CONF register on Table 136. Extended page 1, page 106,
is programmed during OTP or TBB configuration; setting bit VTT to “1” enables SW4 to operate in VTT mode and “0” in Regulator mode.
See 6.1.2 One time programmability (OTP), page 20 for detailed information on OTP configuration.
In regulator mode, the SW4 output voltage is programmable from 0.400 V to 3.300 V; however, bit SW4[6] in the SW4VOLT register is
read-only during normal operation. Its value is determined by the default configuration, or may be changed by using the OTP registers.
Once SW4[6] is set to “0”, the output is limited to the lower output voltages, from 0.400 V to 1.975 V with 25 mV increments, as determined
by the SW4[5:0] bits. Likewise, once the SW4[6] bit is set to "1", the output voltage is limited to the higher output voltage range from 0.800 V
to 3.300 V with 50 mV increments, as determined by the SW4[5:0] bits.
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
PFM - Vout = 1.5V
APS - Vout = 1.5V
PWM - Vout = 1.5V
Efficiency (%)
Load current (mA)
Driver
Controller
EA
Z1
Z2
Internal
Compensation
SW4IN
SW4LX
SW4FB
ISENSE
COSW4
CINSW4
LSW4
I2C
Interface
EP
SW4
SW4MODE
SW4FAULT
VREF
DAC
I2C
VIN
NXP Semiconductors 67
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
To optimize the performance of the regulator, it is recommended that only voltages from 2.000 V to 3.300 V be used in the high range and
that that the lower range be used for voltages from 0.400 V to 1.975 V.
The output voltage set point is independently programmed for normal, standby, and sleep mode by setting the SW4[5:0], SW4STBY[5:0],
and SW4OFF[5:0] bits, respectively. However, the initial state of the SW4[6] bit is copied into bits SW4STBY[6], and SW4OFF[6] bits, so
the output voltage range remains the same on all three operating modes. Table 78 shows the output voltage coding valid for SW4.
Note: Voltage set points of 0.6 V and below are not supported, except in VTT mode.
Table 78. SW4 output voltage configuration
Low output voltage range(54) High output voltage range
Set Point SW4[6:0] SW4 output Set Point SW4[6:0] SW4 output
0 0000000 0.4000 64 1000000 0.8000
1 0000001 0.4250 65 1000001 0.8500
2 0000010 0.4500 66 1000010 0.9000
3 0000011 0.4750 67 1000011 0.9500
4 0000100 0.5000 68 1000100 1.0000
5 0000101 0.5250 69 1000101 1.0500
6 0000110 0.5500 70 1000110 1.1000
7 0000111 0.5750 71 1000111 1.1500
8 0001000 0.6000 72 1001000 1.2000
9 0001001 0.6250 73 1001001 1.2500
10 0001010 0.6500 74 1001010 1.3000
11 0001011 0.6750 75 1001011 1.3500
12 0001100 0.7000 76 1001100 1.4000
13 0001101 0.7250 77 1001101 1.4500
14 0001110 0.7500 78 1001110 1.5000
15 0001111 0.7750 79 1001111 1.5500
16 0010000 0.8000 80 1010000 1.6000
17 0010001 0.8250 81 1010001 1.6500
18 0010010 0.8500 82 1010010 1.7000
19 0010011 0.8750 83 1010011 1.7500
20 0010100 0.9000 84 1010100 1.8000
21 0010101 0.9250 85 1010101 1.8500
22 0010110 0.9500 86 1010110 1.9000
23 0010111 0.9750 87 1010111 1.9500
24 0011000 1.0000 88 1011000 2.0000
25 0011001 1.0250 89 1011001 2.0500
26 0011010 1.0500 90 1011010 2.1000
27 0011011 1.0750 91 1011011 2.1500
28 0011100 1.1000 92 1011100 2.2000
29 0011101 1.1250 93 1011101 2.2500
30 0011110 1.1500 94 1011110 2.3000
31 0011111 1.1750 95 1011111 2.3500
32 0100000 1.2000 96 1100000 2.4000
33 0100001 1.2250 97 1100001 2.4500
34 0100010 1.2500 98 1100010 2.5000
68 NXP Semiconductors
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Full setup and control of SW4 is done through the I2C registers listed on Table 79, and a detailed description of each one of the registers
is provided in Tables 80 to Table 84.
35 0100011 1.2750 99 1100011 2.5500
36 0100100 1.3000 100 1100100 2.6000
37 0100101 1.3250 101 1100101 2.6500
38 0100110 1.3500 102 1100110 2.7000
39 0100111 1.3750 103 1100111 2.7500
40 0101000 1.4000 104 1101000 2.8000
41 0101001 1.4250 105 1101001 2.8500
42 0101010 1.4500 106 1101010 2.9000
43 0101011 1.4750 107 1101011 2.9500
44 0101100 1.5000 108 1101100 3.0000
45 0101101 1.5250 109 1101101 3.0500
46 0101110 1.5500 110 1101110 3.1000
47 0101111 1.5750 111 1101111 3.1500
48 0110000 1.6000 112 1110000 3.2000
49 0110001 1.6250 113 1110001 3.2500
50 0110010 1.6500 114 1110010 3.3000
51 0110011 1.6750 115 1110011 Reserved
52 0110100 1.7000 116 1110100 Reserved
53 0110101 1.7250 117 1110101 Reserved
54 0110110 1.7500 118 1110110 Reserved
55 0110111 1.7750 119 1110111 Reserved
56 0111000 1.8000 120 1111000 Reserved
57 0111001 1.8250 121 1111001 Reserved
58 0111010 1.8500 122 1111010 Reserved
59 0111011 1.8750 123 1111011 Reserved
60 0111100 1.9000 124 1111100 Reserved
61 0111101 1.9250 125 1111101 Reserved
62 0111110 1.9500 126 1111110 Reserved
63 0111111 1.9750 127 1111111 Reserved
Notes
54. For voltages less than 2.0 V, only use set points 0 to 63.
Table 79. SW4 register summary
Register Address Description
SW4VOLT 0x4A Output voltage set point on normal operation
SW4STBY 0x4B Output voltage set point on standby
SW4OFF 0x4C Output voltage set point on sleep
SW4MODE 0x4D Switching mode selector register
SW4CONF 0x4E DVS, phase, frequency and ILIM configuration
Table 78. SW4 output voltage configuration (continued)
Low output voltage range(54) High output voltage range
Set Point SW4[6:0] SW4 output Set Point SW4[6:0] SW4 output
NXP Semiconductors 69
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 80. Register SW4VOLT - ADDR 0x4A
Name Bit # R/W Default Description
SW4 5:0 R/W 0x00
Sets the SW4 output voltage during normal
operation mode. See Table 78 for all possible
configurations.
SW4 6 R 0x00
Sets the operating output voltage range for SW4.
Set during OTP or TBB configuration only. See
Table 78 for all possible configurations.
UNUSED 7 – 0x00 unused
Table 81. Register SW4STBY - ADDR 0x4B
Name Bit # R/W Default Description
SW4STBY 5:0 R/W 0x00
Sets the SW4 output voltage during standby
mode. See Table 78 for all possible
configurations.
SW4STBY 6 R 0x00
Sets the operating output voltage range for SW4
on standby mode. This bit inherits the value
configured on bit SW4[6] during OTP or TBB
configuration. See Table 78 for all possible
configurations.
UNUSED 7 – 0x00 unused
Table 82. Register SW4OFF - ADDR 0x4C
Name Bit # R/W Default Description
SW4OFF 5:0 R/W 0x00 Sets the SW4 output voltage during sleep mode.
See Table 78 for all possible configurations.
SW4OFF 6 R 0x00
Sets the operating output voltage range for SW4
on sleep mode. This bit inherits the value
configured on bit SW4[6] during OTP or TBB
configuration. See Table 78 for all possible
configurations.
UNUSED 7 – 0x00 unused
Table 83. Register SW4MODE - ADDR 0x4D
Name Bit # R/W Default Description
SW4MODE 3:0 R/W 0x80 Sets the SW4 switching operation mode.
See Table 29 for all possible configurations.
UNUSED 4 – 0x00 unused
SW4OMODE 5 R/W 0x00
Set status of SW4 when in sleep mode
0 = OFF
1 = PFM
UNUSED 7:6 – 0x00 unused
70 NXP Semiconductors
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.4.6.2 SW4 external components
6.4.4.6.3 SW4 specifications
Table 84. Register SW4CONF - ADDR 0x4E
Name Bit # R/W Default Description
SW4ILIM 0 R/W 0x00
SW4 current limit level selection
0 = High level Current limit
1 = Low level Current limit
UNUSED 1 R/W 0x00 unused
SW4FREQ 3:2 R/W 0x00 SW4 switching frequency selector. See Table 37.
SW4PHASE 5:4 R/W 0x00 SW4 phase clock selection. See Table 35.
SW4DVSSPEED 7:6 R/W 0x00 SW4 DVS speed selection. See Table 34.
Table 85. SW4 external component requirements
Components Description Values
CINSW4(55) SW4 input capacitor 4.7 μF
CIN4HF(55) SW4 decoupling input capacitor 0.1 μF
COSW4(55) SW4 output capacitor 2 x 22 μF
LSW4 SW4 inductor
1.0 μH
DCR = 60 mΩ
ISAT = 3.0 A
Notes
55. Use X5R or X7R capacitors.
Table 86. SW4 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V,
ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
Switch Mode Supply SW4
VINSW4 Operating input voltage 2.8 – 4.5 V (56)
VSW4
Nominal output voltage
Normal operation
VTT mode
–
–
Table 78
VSW3AFB/2
–
–
V
VSW4ACC
Output voltage accuracy
• PWM, APS, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
0.625 V < VSW4 < 0.85 V
0.875 V < VSW4 < 1.975 V
2.0 V < VSW4 < 3.3 V
• PFM, steady state, 2.8 V < VIN < 4.5 V, 0 < ISW4 < 50 mA
0.625 V < VSW4 < 0.675 V
0.7 V < VSW4 < 0.85 V
0.875 V < VSW4 < 1.975 V
2.0 V < VSW4 < 3.3 V
• VTT mode , 2.8 V < VIN < 4.5 V, 0 < ISW4 < 1.0 A
-25
-3.0%
-6.0%
-65
-45
-3.0%
-3.0%
-40
–
–
–
–
–
–
–
–
25
3.0%
6.0%
65
45
3.0%
3.0%
40
mV
%
NXP Semiconductors 71
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Switch mode supply SW4 (continued)
ISW4
Rated output load current
2.8 V < VIN < 4.5 V, 0.625 V < VSW4 < 3.3 V – – 1000 mA (57)
ISW4LIM
Current limiter peak current detection
Current through inductor
SW4ILIM = 0
SW4ILIM = 1
1.4
1.0
2.0
1.5
3.0
2.4
A
VSW4OSH
Start-up overshoot
ISW4 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V
––66mV
tONSW4
Turn-on time
Enable to 90% of end value
ISW4 = 0.0 mA
DVS clk = 25 mV/4 μs, VIN = VINSW4 = 4.5 V
– – 500 µs
fSW4
Switching frequency
SW4FREQ[1:0] = 00
SW4FREQ[1:0] = 01
SW4FREQ[1:0] = 10
–
–
–
1.0
2.0
4.0
–
–
–
MHz
ηSW4
Efficiency
•f
SW4 = 2.0 MHz, LSW4 = 1.0 μH
PFM, 1.8 V, 1.0 mA
PFM, 1.8 V, 50 mA
APS, PWM 1.8 V, 200 mA
APS, PWM 1.8 V, 500 mA
APS, PWM 1.8 V, 1000 mA
PWM 0.75 V, 200 mA
PWM 0.75 V, 500 mA
PWM 0.75 V, 1000 mA
–
–
–
–
–
–
–
–
81
78
87
88
84
78
76
66
–
–
–
–
–
–
–
–
%
ΔVSW4 Output ripple – 10 – mV
VSW4LIR Line regulation (APS, PWM) – – 20 mV
VSW4LOR DC load regulation (APS, PWM) – – 20 mV
VSW4LOTR
Transient load regulation
• Transient load = 0.0 mA to 500 mA, di/dt = 100 mA/μs
Overshoot
Undershoot
–
–
–
–50
50
mV
ISW4Q
Quiescent current
PFM mode
APS mode
–
–
22
145
–
–
µA
RONSW4P
SW4 P-MOSFET RDS(on)
at VIN = VINSW4 = 3.3 V – 236 274 mΩ
RONSW4N
SW4 N-MOSFET RDS(on)
at VIN = VINSW4 = 3.3 V – 293 378 mΩ
ISW4PQ
SW4 P-MOSFET leakage current
VIN = VINSW4 = 4.5 V ––6.0µA
ISW4NQ
SW4 N-MOSFET leakage current
VIN = VINSW4 = 4.5 V ––2.0µA
Table 86. SW4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V,
ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
72 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 22. SW4 efficiency waveforms
6.4.5 Boost regulator
SWBST is a boost regulator with a programmable output from 5.0 V to 5.15 V. SWBST can supply the VUSB regulator for the USB PHY
in OTG mode, as well as the VBUS voltage. Note that the parasitic leakage path for a boost regulator causes the SWBSTOUT and
SWBSTFB voltage to be a Schottky drop below the input voltage whenever SWBST is disabled. The switching NMOS transistor is
integrated on-chip. Figure 23 shows the block diagram and component connection for the boost regulator.
RSW4DIS Discharge Resistance – 600 – W
Notes
56. When the output is set to > 2.6 V, the output follows the input down when VIN gets near 2.8 V.
57. The higher output voltages available depend on the voltage drop in the conduction path as given by the following equation:
(VINSW4 - VSW4) = ISW4* (DCR of Inductor +RONSW4P + PCB trace resistance).
Table 86. SW4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V,
ISW4 = 100 mA, SW4_PWRSTG[2:0] = [101], typical external component values, fSW4 = 2.0 MHz, single/dual phase and independent
mode, unless otherwise noted. Typical values are characterized at VIN = VINSW4 = 3.6 V, VSW4 = 1.8 V, ISW4 = 100 mA,
SW4_PWRSTG[2:0] = [101], and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
Efficiency (%)
Load current (mA)
0
10
20
30
40
50
60
70
80
90
100
0.1 1 10 100 1000
PFM - Vout = 1.8V
APS - Vout = 1.8V
PWM -Vout = 1.8V
PWM -Vout = 0.75V
NXP Semiconductors 73
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 23. Boost Regulator Architecture
6.4.5.1 SWBST setup and control
Boost regulator control is done through a single register SWBSTCTL described in Table 87. SWBST is included in the power-up sequence
if its OTP power-up timing bits, SWBST_SEQ[4:0], are not all zeros.
Table 87. Register SWBSTCTL - ADDR 0x66
Name Bit # R/W Default Description
SWBST1VOLT 1:0 R/W 0x00
Set the output voltage for SWBST
00 = 5.000 V
01 = 5.050 V
10 = 5.100 V
11 = 5.150 V
SWBST1MODE 3:2 R 0x02
Set the switching mode on normal operation
00 = OFF
01 = PFM
10 = Auto (Default)(58)
11 = APS
UNUSED 4 – 0x00 unused
SWBST1STBYMODE 6:5 R/W 0x02
Set the switching mode on standby
00 = OFF
01 = PFM
10 = Auto (Default)(58)
11 = APS
UNUSED 7 – 0x00 unused
Notes
58. In auto mode, the controller automatically switches between PFM and APS modes depending on the load current.
The SWBST regulator starts up by default in the auto mode, if SWBST is part of the startup sequence.
SWBSTLX
VOBST
Driver
Controller
EA
Z1
Z2
Internal
Compensation
I2C
Interface
SWBSTMODE
VREFUV
VREF
EP
VIN
LBST
CINBST
DBST
SWBSTFB
RSENSE
SC
VREFSC
SWBSTFAULT
OC
UV
COSWBST
SWBSTIN
74 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.5.2 SWBST external components
6.4.5.3 SWBST specifications
Table 88. SWBST external component requirements
Components Description Values
CINBST(59) SWBST input capacitor 10 μF
CINBSTHF(59) SWBST decoupling input capacitor 0.1 μF
COBST(59) SWBST output capacitor 2 x 22 μF
LSBST SWBST inductor 2.2 μH
DBST SWBST boost diode 1.0 A, 20 V Schottky
Notes
59. Use X5R or X7R capacitors.
Table 89. SWBST electrical specifications
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at
VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol Parameters Min. Typ. Max. Units Notes
Switch mode supply SWBST
VINSWBST Input voltage range 2.8 – 4.5 V
VSWBST Nominal output voltage – Table 87 –V
VSWBSTACC
Output voltage accuracy
2.8 V ≤ VIN ≤ 4.5 V
0 < ISWBST < ISWBSTMAX
-4.0 – 3.0 %
ΔVSWBST
Output ripple
2.8 V ≤ VIN ≤ 4.5 V
0 < ISWBST < ISWBSTMAX, excluding reverse recovery of Schottky
diode
– – 120 mV Vp-p
VSWBSTLOR
DC load regulation
0 < ISWBST < ISWBSTMAX
–0.5 –mV/mA
VSWBSTLIR
DC line regulation
2.8 V ≤ VIN ≤ 4.5 V, ISWBST = ISWBSTMAX
– 50 – mV
ISWBST
Continuous load current
2.8 V ≤ VIN ≤ 3.0 V
3.0 V ≤ VIN ≤ 4.5 V
–
–
–
–
500
600
mA
ISWBSTQ
Quiescent current
auto – 222 289 μA
RDSONBST MOSFET on resistance – 206 306 mΩ
ISWBSTLIM Peak current limit 1400 2200 3200 mA (60)
VSWBSTOSH
Start-up overshoot
ISWBST = 0.0 mA – – 500 mV
VSWBSTTR
Transient load response
ISWBST from 1.0 mA to 100 mA in 1.0 µs
Maximum transient amplitude
– – 300 mV
VSWBSTTR
Transient load response
ISWBST from 100 mA to 1.0 mA in 1.0 µs
Maximum transient amplitude
– – 300 mV
NXP Semiconductors 75
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6 LDO regulators description
This section describes the LDO regulators provided by the PF0100Z. All regulators use the main bandgap as reference. Refer to 6.3 Bias
and references block description, page 23 for further information on the internal reference voltages.
A low-power mode is automatically activated by reducing bias currents when the load current is less than I_Lmax/5. However, the lowest
bias currents may be attained by forcing the part into its low-power mode by setting the VGENxLPWR bit. The use of this bit is only
recommended when the load is expected to be less than I_Lmax/50, otherwise performance may be degraded. When a regulator is
disabled, the output is discharged by an internal pull-down. The pull-down is also activated when RESETBMCU is low.
Figure 24. General LDO block diagram
Switch mode supply SWBST (continued)
tSWBSTTR
Transient load response
ISWBST from 1.0 mA to 100 mA in 1.0 µs
Time to settle 80% of transient
– – 500 µs
tSWBSTTR
Transient load response
ISWBST from 100 mA to 1.0 mA in 1.0 µs
Time to settle 80% of transient
––20ms
ISWBSTHSQ
NMOS Off leakage
SWBSTIN = 4.5 V, SWBSTMODE [1:0] = 00 –1.05.0µA
tONSWBST
Turn-on time
Enable to 90% of VSWBST, ISWBST = 0.0 mA ––2.0ms
fSWBST Switching frequency – 2.0 – MHz
ηSWBST
Efficiency
ISWBST = ISWBSTMAX
–86– %
Notes
60. Only in auto mode.
Table 89. SWBST electrical specifications (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V,
ISWBST = 100 mA, typical external component values, fSWBST = 2.0 MHz, otherwise noted. Typical values are characterized at
VIN = VINSWBST = 3.6 V, VSWBST = 5.0 V, ISWBST = 100 mA, and 25 °C, unless otherwise noted.
Symbol Parameters Min. Typ. Max. Units Notes
VGENx
VINx
VINx
VGENx
CGENx
VGENxEN
VGENxLPWR
VREF
VGENx
I2C
Interface
Discharge
+
_
76 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.1 Transient response waveforms
Idealized stimulus and response waveforms for transient line and transient load tests are depicted in Figure 25. Note that the transient line
and load response refers to the overshoot, or undershoot only, excluding the DC shift.
Figure 25. Transient waveforms
6.4.6.2 Short-circuit protection
All general purpose LDOs have short-circuit protection capability. The short-circuit protection (SCP) system includes debounced fault
condition detection, regulator shutdown, and processor interrupt generation, to contain failures and minimize the chance of product
damage. If a short-circuit condition is detected, the LDO is disabled by resetting its VGENxEN bit, while at the same time, an interrupt
VGENxFAULTI is generated to flag the fault to the system processor. The VGENxFAULTI interrupt is maskable through the
VGENxFAULTM mask bit.
The SCP feature is enabled by setting the REGSCPEN bit. If this bit is not set, the regulators do not automatically disable upon a short-
circuit detection. However, the current limiter continues to limit the output current of the regulator. By default, the REGSCPEN is not set;
therefore, at start-up none of the regulators are disabled if an overloaded condition occurs. A fault interrupt, VGENxFAULTI, is generated
in an overload condition regardless of the state of the REGSCPEN bit. See Table 90 for SCP behavior configuration.
Table 90. Short-circuit behavior
REGSCPEN[0] Short-circuit behavior
0 Current limit
1 Shutdown
10 us 10 us
VINx
Transient Line Stimulus
VINx_INITIAL
VINx_FINAL
1.0 us 1.0 us
IMAX/10
IMAX
ILOAD
Transient Load Stimulus
Undershoot
IL = IMAX/10
VOUT
VOUT Transient Load Response
IL = IMAX
Overshoot
Undershoot
VOUT
VOUT Transient Line Response
Overshoot
VINx_INITIAL
VINx_FINAL
NXP Semiconductors 77
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.3 LDO regulator control
Each LDO is fully controlled through its respective VGENxCTL register. This register enables the user to set the LDO output voltage
according to Table 91 for VGEN1 and VGEN2; and uses the voltage set point on Table 92 for VGEN3 through VGEN6.
Besides the output voltage configuration, the LDOs can be enabled or disabled at anytime during normal mode operation, as well as be
programmed to stay “ON” or be disabled when the PMIC enters standby mode. Each regulator has associated I2C bits for this. Table 93
presents a summary of all valid combinations of the control bits on VGENxCTL register and the expected behavior of the LDO output.
Table 91. VGEN1, VGEN2 output voltage configuration
Set point VGENx[3:0] VGENx output (V)
0 0000 0.800
1 0001 0.850
2 0010 0.900
3 0011 0.950
4 0100 1.000
5 0101 1.050
6 0110 1.100
7 0111 1.150
8 1000 1.200
9 1001 1.250
10 1010 1.300
11 1011 1.350
12 1100 1.400
13 1101 1.450
14 1110 1.500
15 1111 1.550
Table 92. VGEN3/ 4/ 5/ 6 output voltage configuration
Set point VGENx[3:0] VGENx output (V)
0 0000 1.80
1 0001 1.90
2 0010 2.00
3 0011 2.10
4 0100 2.20
5 0101 2.30
6 0110 2.40
7 0111 2.50
8 1000 2.60
9 1001 2.70
10 1010 2.80
11 1011 2.90
12 1100 3.00
13 1101 3.10
14 1110 3.20
15 1111 3.30
78 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
For more detail information, Table 94 through Table 99 provide a description of all registers necessary to operate all six general purpose
LDO regulators.
Table 93. LDO control
VGENxEN VGENxLPWR VGENxSTBY STANDBY(61) VGENxOUT
0XXXOff
10 0XOn
1 1 0 X Low Power
1X 10On
10 11Off
1 1 1 1 Low Power
Notes
61. STANDBY refers to a standby event as described earlier.
Table 94. Register VGEN1CTL - ADDR 0x6C
Name Bit # R/W Default Description
VGEN1 3:0 R/W 0x80 Sets VGEN1 output voltage.
See Table 91 for all possible configurations.
VGEN1EN 4 – 0x00
Enables or disables VGEN1 output
0 = OFF
1 = ON
VGEN1STBY 5 R/W 0x00 Set VGEN1 output state when in standby. Refer
to Table 93.
VGEN1LPWR 6 R/W 0x00 Enable low-power mode for VGEN1. Refer to
Table 93.
UNUSED 7 – 0x00 unused
Table 95. Register VGEN2CTL - ADDR 0x6D
Name Bit # R/W Default Description
VGEN2 3:0 R/W 0x80 Sets VGEN2 output voltage.
See Table 91 for all possible configurations.
VGEN2EN 4 – 0x00
Enables or disables VGEN2 output
0 = OFF
1 = ON
VGEN2STBY 5 R/W 0x00 Set VGEN2 output state when in standby. Refer
to Table 93.
VGEN2LPWR 6 R/W 0x00 Enable low-power mode for VGEN2. Refer to
Table 93.
UNUSED 7 – 0x00 unused
NXP Semiconductors 79
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 96. Register VGEN3CTL - ADDR 0x6E
Name Bit # R/W Default Description
VGEN3 3:0 R/W 0x80 Sets VGEN3 output voltage.
See Table 92 for all possible configurations.
VGEN3EN 4 – 0x00
Enables or disables VGEN3 output
0 = OFF
1 = ON
VGEN3STBY 5 R/W 0x00 Set VGEN3 output state when in standby. Refer
to Table 93.
VGEN3LPWR 6 R/W 0x00 Enable low-power mode for VGEN3. Refer to
Table 93.
UNUSED 7 – 0x00 unused
Table 97. Register VGEN4CTL - ADDR 0x6F
Name Bit # R/W Default Description
VGEN4 3:0 R/W 0x80 Sets VGEN4 output voltage.
See Table 92 for all possible configurations.
VGEN4EN 4 – 0x00
Enables or disables VGEN4 output
0 = OFF
1 = ON
VGEN4STBY 5 R/W 0x00 Set VGEN4 output state when in standby. Refer
to Table 93.
VGEN4LPWR 6 R/W 0x00 Enable low-power mode for VGEN4. Refer to
Table 93.
UNUSED 7 – 0x00 unused
Table 98. Register VGEN5CTL - ADDR 0x70
Name Bit # R/W Default Description
VGEN5 3:0 R/W 0x80 Sets VGEN5 output voltage.
See Table 92 for all possible configurations.
VGEN5EN 4 – 0x00
Enables or disables VGEN5 output
0 = OFF
1 = ON
VGEN5STBY 5 R/W 0x00 Set VGEN5 output state when in standby. Refer
to Table 93.
VGEN5LPWR 6 R/W 0x00 Enable low-power mode for VGEN5. Refer to
Table 93.
UNUSED 7 – 0x00 unused
80 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.4 External components
Table 100 lists the typical component values for the general purpose LDO regulators.
6.4.6.5 LDO specifications
6.4.6.5.1 VGEN1
Table 99. Register VGEN6CTL - ADDR 0x71
Name Bit # R/W Default Description
VGEN6 3:0 R/W 0x80 Sets VGEN6 output voltage.
See Table 92 for all possible configurations.
VGEN6EN 4 – 0x00
Enables or disables VGEN6 output
0 = OFF
1 = ON
VGEN6STBY 5 R/W 0x00 Set VGEN6 output state when in standby. Refer
to Table 93.
VGEN6LPWR 6 R/W 0x00 Enable low-power mode for VGEN6. Refer to
Table 93.
UNUSED 7 – 0x00 unused
Table 100. LDO external components
Regulator Output capacitor (μF)(62)
VGEN1 2.2
VGEN2 4.7
VGEN3 2.2
VGEN4 4.7
VGEN5 2.2
VGEN6 2.2
Notes
62. Use X5R/X7R ceramic capacitors.
Table 101. VGEN1 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
VGEN1
VIN1 Operating input voltage 1.75 – 3.40 V
VGEN1NOM Nominal output voltage – Table 91 –V
IGEN1 Operating load current 0.0 – 100 mA
VGEN1 DC
VGEN1TOL
Output voltage tolerance
1.75 V < VIN1 < 3.4 V
0.0 mA < IGEN1 < 100 mA
VGEN1[3:0] = 0000 to 1111
-3.0 – 3.0 %
NXP Semiconductors 81
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN1LOR
Load regulation
(VGEN1 at IGEN1 = 100 mA) - (VGEN1 at IGEN1 = 0.0 mA)
For any 1.75 V < VIN1 < 3.4 V
–0.15–mV/mA
VGEN1LIR
Line regulation
(VGEN1 at VIN1 = 3.4 V) - (VGEN1 at VIN1 = 1.75 V)
For any 0.0 mA < IGEN1 < 100 mA
–0.30–mV/mA
IGEN1LIM
Current limit
IGEN1 when VGEN1 is forced to VGEN1NOM/2 122 167 200 mA
IGEN1OCP
Overcurrent protection threshold
IGEN1 required to cause the SCP function to disable LDO when
REGSCPEN = 1
115 – 200 mA
IGEN1Q
Quiescent current
No load, Change in IVIN and IVIN1
When VGEN1 enabled
–14–μA
VGEN1 AC and transient
PSRRVGEN1
PSRR
•I
GEN1 = 75 mA, 20 Hz to 20 kHz
VGEN1[3:0] = 0000 - 1101
VGEN1[3:0] = 1110, 1111
50
37
60
45
–
–
dB (63)
NOISEVGEN1
Output noise density
VIN1 = 1.75 V, IGEN1 = 75 mA
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
–
–
–
-108
-118
-124
-100
-108
-112
dBV/ √Hz
SLWRVGEN1
Turn-on slew rate
• 10% to 90% of end value
• 1.75 V ≤ VIN1 ≤ 3.4 V, IGEN1 = 0.0 mA
VGEN1[3:0] = 0000 to 0111
VGEN1[3:0] = 1000 to 1111
–
–
–
–
12.5
16.5
mV/μs
GEN1tON
Turn-on time
Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
IGEN1 = 0.0 mA
60 – 500 μs
GEN1tOFF
Turn-off time
Disable to 10% of initial value, VIN1 = 1.75 V
IGEN1 = 0.0 mA
––10ms
GEN1OSHT
Start-up overshoot
VIN1 = 1.75 V, 3.4 V, IGEN1 = 0.0 mA –1.02.0%
VGEN1LOTR
Transient load response
•V
IN1 = 1.75 V, 3.4 V
IGEN1 = 10 mA to 100 mA in 1.0 μs. Peak of overshoot or
undershoot of VGEN1 with respect to final value
• Refer to Figure 25
––3.0%
Table 101. VGEN1 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
82 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.2 VGEN2
VGEN1LITR
Transient line response
•I
GEN1 = 75 mA
VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN1[3:0] = 0000 to 1101
VIN1INITIAL = VGEN1+0.3 V to VIN1FINAL = VGEN1+0.8 V for
VGEN1[3:0] = 1110, 1111
• Refer to Figure 25
–5.08.0mV
Notes
63. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
Table 102. VGEN2 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
VGEN2
VIN1 Operating input voltage 1.75 – 3.40 V
VGEN2NOM Nominal output voltage – Table 91 –V
IGEN2 Operating load current 0.0 – 250 mA
VGEN2 active mode - DC
VGEN2TOL
Output voltage tolerance
1.75 V < VIN1 < 3.4 V
0.0 mA < IGEN2 < 250 mA
VGEN2[3:0] = 0000 to 1111
-3.0 – 3.0 %
VGEN2LOR
Load regulation
(VGEN2 at IGEN2 = 250 mA) - (VGEN2 at IGEN2 = 0.0 mA)
For any 1.75 V < VIN1 < 3.4 V
–0.05–mV/mA
VGEN2LIR
Line regulation
(VGEN2 at VIN1 = 3.4 V) - (VGEN2 at VIN1 = 1.75 V)
For any 0.0 mA < IGEN2 < 250 mA
–0.50–mV/mA
IGEN2LIM
Current limit
IGEN2 when VGEN2 is forced to VGEN2NOM/2
PF0100Z
PF0100AZ
333
305
417
417
510
510
mA
IGEN2OCP
Overcurrent protection threshold
IGEN2 required to cause the SCP function to disable LDO when
REGSCPEN = 1
PF0100Z
PF0100AZ
300
290
–
–
500
500
mA
IGEN2Q
Quiescent current
No load, Change in IVIN and IVIN1
When VGEN2 enabled
–16–μA
Table 101. VGEN1 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN1[3:0] = 1111, IGEN1 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, IN1 = 3.0 V, VGEN1[3:0] = 1111, IGEN1 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
NXP Semiconductors 83
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN2 AC and transient
PSRRVGEN2
PSRR (64)
•I
GEN2 = 187.5 mA, 20 Hz to 20 kHz
VGEN2[3:0] = 0000 - 1101
VGEN2[3:0] = 1110, 1111
50
37
60
45
–
–
dB
NOISEVGEN2
Output noise density
•V
IN1 = 1.75 V, IGEN2 = 187.5 mA
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
–
–
–
-108
-118
-124
-100
-108
-112
dBV/√Hz
SLWRVGEN2
Turn-on slew rate
• 10% to 90% of end value
•1.75 V ≤ VIN1 ≤ 3.4 V, IGEN2 = 0.0 mA
VGEN2[3:0] = 0000 to 0111
VGEN2[3:0] = 1000 to 1111
–
–
–
–
12.5
16.5
mV/μs
GEN2tON
Turn-on time
Enable to 90% of end value, VIN1 = 1.75 V, 3.4 V
IGEN2 = 0.0 mA
60 – 500 μs
GEN2tOFF
Turn-off time
Disable to 10% of initial value, VIN1 = 1.75 V
IGEN2 = 0.0 mA
––10ms
GEN2OSHT
Start-up overshoot
VIN1 = 1.75 V, 3.4 V, IGEN2 = 0.0 mA –1.02.0%
VGEN2LOTR
Transient load response
VIN1 = 1.75 V, 3.4 V
IGEN2 = 25 mA to 250 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN2 with respect to final
value
Refer to Figure 25
––3.0%
VGEN2LITR
Transient line response
IGEN2 = 187.5 mA
VIN1INITIAL = 1.75 V to VIN1FINAL = 2.25 V for
VGEN2[3:0] = 0000 to 1101
VIN1INITIAL = VGEN2+0.3 V to VIN1FINAL = VGEN2+0.8 V for
VGEN2[3:0] = 1110, 1111
Refer to Figure 25
–5.08.0mV
Notes
64. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test.
Table 102. VGEN2 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN1 = 3.0 V,
VGEN2[3:0] = 1111, IGEN2 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6V, VIN1 = 3.0 V, VGEN2[3:0] = 1111, IGEN2 = 10mA and 25°C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
84 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.3 VGEN3
Table 103. VGEN3 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
VGEN3
VIN2
Operating input voltage
1.8 V ≤ VGEN3NOM ≤ 2.5 V
2.6 V ≤ VGEN3NOM ≤ 3.3 V
2.8
VGEN3NO
M+ 0.250
–
–
3.6
3.6
V
(65)
VGEN3NOM Nominal output voltage – Table 92 –V
IGEN3 Operating load current 0.0 – 100 mA
VGEN3 DC
VGEN3TOL
Output voltage tolerance
VIN2MIN < VIN2 < 3.6 V
0.0 mA < IGEN3 < 100 mA
VGEN3[3:0] = 0000 to 1111
-3.0 – 3.0 %
VGEN3LOR
Load regulation
(VGEN3 at IGEN3 = 100 mA) - (VGEN3 at IGEN3 = 0.0 mA)
For any VIN2MIN < VIN2 < 3.6 V
–0.07–mV/mA
VGEN3LIR
Line regulation
(VGEN3 at VIN2 = 3.6 V) - (VGEN3 at VIN2MIN )
For any 0.0 mA < IGEN3 < 100 mA
–0.8–mV/mA
IGEN3LIM
Current limit
IGEN3 when VGEN3 is forced to VGEN3NOM/2 127 167 200 mA
IGEN3OCP
Overcurrent protection threshold
IGEN3 required to cause the SCP function to disable LDO when
REGSCPEN = 1
120 – 200 mA
IGEN3Q
Quiescent current
No load, Change in IVIN and IVIN2
When VGEN3 enabled
–13–μA
VGEN3 AC and transient
PSRRVGEN3
PSRR
•I
GEN3 = 75 mA, 20 Hz to 20 kHz
VGEN3[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
VGEN3[3:0] = 0000 - 1000, VIN2 = VGEN3NOM + 1.0 V
35
55
40
60
–
–
dB (66)
NOISEVGEN3
Output noise density
•V
IN2 = VIN2MIN, IGEN3 = 75 mA
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
SLWRVGEN3
Turn-on slew rate
• 10% to 90% of end value
•VIN2
MIN ≤ VIN2 ≤ 3.6 V, IGEN3 = 0.0 mA
VGEN3[3:0] = 0000 to 0011
VGEN3[3:0] = 0100 to 0111
VGEN3[3:0] = 1000 to 1011
VGEN3[3:0] = 1100 to 1111
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
GEN3tON
Turn-on time
Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
IGEN3 = 0.0 mA
60 – 500 μs
NXP Semiconductors 85
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.4 VGEN4
VGEN3 AC and transient (continued)
GEN3tOFF
Turn-off time
Disable to 10% of initial value, VIN2 = VIN2MIN
IGEN3 = 0.0 mA
––10ms
GEN3OSHT
Start-up overshoot
VIN2 = VIN2MIN, 3.6 V, IGEN3 = 0.0 mA –1.02.0%
VGEN3LOTR
Transient load response
VIN2 = VIN2MIN, 3.6 V
IGEN3 = 10 mA to 100 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN3 with respect to final
value. Refer to Figure 25
––3.0%
VGEN3LITR
Transient line response
IGEN3 = 75 mA
VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for
GEN3[3:0] = 0000 to 0111
VIN2INITIAL = VGEN3+0.3 V to VIN2FINAL = VGEN3+0.8 V for
VGEN3[3:0] = 1000 to 1010
VIN2INITIAL = VGEN3+0.25 V to VIN2FINAL = 3.6 V for
VGEN3[3:0] = 1011 to 1111
Refer to Figure 25
–5.08.0mV
Notes
65. When the LDO Output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V, for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
66. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.
Table 104. VGEN4 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
VGEN4
VIN2
Operating input voltage
1.8 V ≤ VGEN4NOM ≤ 2.5 V
2.6 V ≤ VGEN4NOM ≤ 3.3 V
2.8
VGEN4NO
M+ 0.250
–
–
3.6
3.6
V
(67)
VGEN4NOM Nominal output voltage – Table 92 –V
IGEN4 Operating load current 0.0 – 350 mA
VGEN4 DC
VGEN4TOL
Output voltage tolerance
VIN2MIN < VIN2 < 3.6 V
0.0 mA < IGEN4 < 350 mA
VGEN4[3:0] = 0000 to 1111
-3.0 – 3.0 %
VGEN4LOR
Load regulation
(VGEN4 at IGEN4 = 350 mA) - (VGEN4 at IGEN4 = 0.0 mA )
For any VIN2MIN < VIN2 < 3.6 V
–0.07–mV/mA
Table 103. VGEN3 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN3[3:0] = 1111, IGEN3 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN3[3:0] = 1111, IGEN3 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min. Typ. Max. Unit Notes
86 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN4 DC (continued)
VGEN4LIR
Line regulation
(VGEN4 at 3.6 V) - (VGEN4 at VIN2MIN)
For any 0.0 mA < IGEN4 < 350 mA
–0.80–mV/mA
IGEN4LIM
Current limit
IGEN4 when VGEN4 is forced to VGEN4NOM/2 435 584.5 700 mA
IGEN4OCP
Overcurrent protection threshold
IGEN4 required to cause the SCP function to disable LDO when
REGSCPEN = 1
420 – 700 mA
IGEN4Q
Quiescent current
No load, change in IVIN and IVIN2
When VGEN4 enabled
–13–μA
VGEN4 AC and transient
PSRRVGEN4
PSRR
•I
GEN4 = 262.5 mA, 20 Hz to 20 kHz
VGEN4[3:0] = 0000 - 1110, VIN2 = VIN2MIN + 100 mV
VGEN4[3:0] = 0000 - 1000, VIN2 = VGEN4NOM + 1.0 V
35
55
40
60
–
–
dB (68)
NOISEVGEN4
Output noise density
•V
IN2 = VIN2MIN, IGEN4 = 262.5 mA
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
SLWRVGEN4
Turn-on slew rate
• 10% to 90% of end value
•VIN2
MIN ≤ VIN2 ≤ 3.6 V, IGEN4 = 0.0 mA
VGEN4[3:0] = 0000 to 0011
VGEN4[3:0] = 0100 to 0111
VGEN4[3:0] = 1000 to 1011
VGEN4[3:0] = 1100 to 1111
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
GEN4tON
Turn-on time
Enable to 90% of end value, VIN2 = VIN2MIN, 3.6 V
IGEN4 = 0.0 mA
60 – 500 μs
GEN4tOFF
Turn-off time
Disable to 10% of initial value, VIN2 = VIN2MIN
IGEN4 = 0.0 mA
––10ms
GEN4OSHT
Start-up overshoot
VIN2 = VIN2MIN, 3.6 V, IGEN4 = 0.0 mA –1.02.0%
VGEN4LOTR
Transient load response
VIN2 = VIN2MIN, 3.6 V
IGEN4 = 35 mA to 350 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN4 with respect to final
value. Refer to Figure 25
––3.0%
Table 104. VGEN4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
NXP Semiconductors 87
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.5 VGEN5
VGEN4 AC and transient (continued)
VGEN4LITR
Transient line response
IGEN4 = 262.5 mA
VIN2INITIAL = 2.8 V to VIN2FINAL = 3.3 V for
VGEN4[3:0] = 0000 to 0111
VIN2INITIAL = VGEN4+0.3 V to VIN2FINAL = VGEN4+0.8 V for
VGEN4[3:0] = 1000 to 1010
VIN2INITIAL = VGEN4+0.25 V to VIN2FINAL = 3.6 V for
VGEN4[3:0] = 1011 to 1111
Refer to Figure 25
–5.08.0mV
Notes
67. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
68. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN2MIN refers to the minimum allowed input voltage for a particular output voltage.
Table 105. VGEN5 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
VGEN5
VIN3
Operating input voltage
1.8 V ≤ VGEN5NOM ≤ 2.5 V
2.6 V ≤ VGEN5NOM ≤ 3.3 V
2.8
VGEN5NO
M+ 0.250
–
–
4.5
4.5
V
(69)
VGEN5NOM Nominal output voltage – Table 92 –V
IGEN5 Operating load current 0.0 – 100 mA
VGEN5 active mode – DC
VGEN5TOL
Output voltage tolerance
VIN3MIN < VIN3 < 4.5 V
0.0 mA < IGEN5 < 100 mA
VGEN5[3:0] = 0000 to 1111
-3.0 – 3.0 %
VGEN5LOR
Load regulation
(VGEN5 at IGEN5 = 100 mA) - (VGEN5 at IGEN5 = 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 mV
– 0.10 – mV/mA
VGEN5LIR
Line regulation
(VGEN5 at VIN3 = 4.5 V) - (VGEN5 at VIN3MIN)
For any 0.0 mA < IGEN5 < 100 mA
– 0.50 – mV/mA
IGEN5LIM
Current limit
IGEN5 when VGEN5 is forced to VGEN5NOM/2 122 167 200 mA
IGEN5OCP
Overcurrent protection threshold
IGEN5 required to cause the SCP function to disable LDO when
REGSCPEN = 1
120 – 200 mA
Table 104. VGEN4 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN2 = 3.6 V,
VGEN4[3:0] = 1111, IGEN4 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN2 = 3.6 V, VGEN4[3:0] = 1111, IGEN4 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
88 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
VGEN5 active mode – DC (continued)
IGEN5Q
Quiescent current
No load, change in IVIN and IVIN3
When VGEN5 enabled
–13–μA
VGEN5 AC and transient
PSRRVGEN5
PSRR
•I
GEN5 = 75 mA, 20 Hz to 20 kHz
VGEN5[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
VGEN5[3:0] = 0000 - 1111, VIN3 = VGEN5NOM + 1.0 V
35
52
40
60
–
–
dB (70)
NOISEVGEN5
Output noise density
•V
IN3 = VIN3MIN, IGEN5 = 75 mA
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
SLWRVGEN5
Turn-on slew rate
• 10% to 90% of end value
•VIN3
MIN ≤ VIN3 ≤ 4.5 mV, IGEN5 = 0.0 mA
VGEN5[3:0] = 0000 to 0011
VGEN5[3:0] = 0100 to 0111
VGEN5[3:0] = 1000 to 1011
VGEN5[3:0] = 1100 to 1111
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
GEN5tON
Turn-on time
Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
IGEN5 = 0.0 mA
60 – 500 μs
GEN5tOFF
Turn-off time
Disable to 10% of initial value, VIN3 = VIN3MIN
IGEN5 = 0.0 mA
––10ms
GEN5OSHT
Start-up overshoot
VIN3 = VIN3MIN, 4.5 V, IGEN5 = 0.0 mA –1.02.0%
VGEN5LOTR
Transient load response
VIN3 = VIN3MIN, 4.5 V
IGEN5 = 10 to 100 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN5 with respect to final
value.
Refer to Figure 25
––3.0%
VGEN5LITR
Transient line response
IGEN5 = 75 mA
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for VGEN5[3:0] = 0000 to
0111
VIN3INITIAL = VGEN5+0.3 V to VIN3FINAL = VGEN5+0.8 V for
VGEN5[3:0] = 1000 to 1111
Refer to Figure 25
-5.08.0mV
Notes
69. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage need to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
70. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.
Table 105. VGEN5 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN5[3:0] = 1111, IGEN5 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN5[3:0] = 1111, IGEN5 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
NXP Semiconductors 89
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.6.5.6 VGEN6
Table 106. VGEN6 electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
VGEN6
VIN3
Operating input voltage
1.8 V ≤ VGEN6NOM ≤ 2.5 V
2.6 V ≤ VGEN6NOM ≤ 3.3 V
2.8
VGEN6NO
M+ 0.250
–
–
4.5
4.5
V
(71)
VGEN6NOM Nominal output voltage – Table 92 –V
IGEN6 Operating load current 0.0 – 200 mA
VGEN6 DC
VGEN6TOL
Output voltage tolerance
VIN3MIN < VIN3 < 4.5 V
0.0 mA < IGEN6 < 200 mA
VGEN6[3:0] = 0000 to 1111
-3.0 – 3.0 %
VGEN6LOR
Load regulation
(VGEN6 at IGEN6 = 200 mA) - (VGEN6 at IGEN6 = 0.0 mA)
For any VIN3MIN < VIN3 < 4.5 V
–0.10–mV/mA
VGEN6LIR
Line regulation
(VGEN6 at VIN3 = 4.5 V) - (VGEN6 at VIN3MIN)
For any 0.0 mA < IGEN6 < 200 mA
–0.50–mV/mA
IGEN6LIM
Current limit
IGEN6 when VGEN6 is forced to VGEN6NOM/2
PF0100Z
PF0100AZ
232
232
333
333
400
475
mA
IGEN6OCP
Overcurrent protection threshold
IGEN6 required to cause the SCP function to disable LDO when
REGSCPEN = 1
PF0100Z
PF0100AZ
220
220
–
–
400
475
mA
IGEN6Q
Quiescent current
No load, change in IVIN and IVIN3
When VGEN6 enabled
–13–μA
VGEN6 AC and transient
PSRRVGEN6
PSRR
•I
GEN6 = 150 mA, 20 Hz to 20 kHz
VGEN6[3:0] = 0000 - 1111, VIN3 = VIN3MIN + 100 mV
VGEN6[3:0] = 0000 - 1111, VIN3 = VGEN6NOM + 1.0 V
35
52
40
60
–
–
dB (72)
NOISEVGEN6
Output noise density
•V
IN3 = VIN3MIN, IGEN6 = 150 mA
100 Hz – <1.0 kHz
1.0 kHz – <10 kHz
10 kHz – 1.0 MHz
–
–
–
-114
-129
-135
-102
-123
-130
dBV/√Hz
SLWRVGEN6
Turn-on slew rate
• 10% to 90% of end value
•VIN3
MIN ≤ VIN3 ≤ 4.5 V. IGEN6 = 0.0 mA
VGEN6[3:0] = 0000 to 0011
VGEN6[3:0] = 0100 to 0111
VGEN6[3:0] = 1000 to 1011
VGEN6[3:0] = 1100 to 1111
–
–
–
–
–
–
–
–
22.0
26.5
30.5
34.5
mV/μs
90 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.7 VSNVS LDO/switch
VSNVS powers the low-power, SNVS/RTC domain on the processor. It derives its power from either VIN, or coin cell, and cannot be
disabled. When powered by both, VIN takes precedence when above the appropriate comparator threshold. When powered by VIN,
VSNVS is an LDO capable of supplying seven voltages: 3.0, 1.8, 1.5, 1.3, 1.2, 1.1, and 1.0 V. The bits VSNVSVOLT[2:0] in register
VSNVS_CONTROL determine the output voltage. When powered by coin cell, VSNVS is an LDO capable of supplying 1.8, 1.5, 1.3, 1.2,
1.1, or 1.0 V as shown in Table 107. If the 3.0 V option is chosen with the coin cell, VSNVS tracks the coin cell voltage by means of a
switch, whose maximum resistance is 100 Ω. In this case, the VSNVS voltage is simply the coin cell voltage minus the voltage drop across
the switch, which is 40 mV at a rated maximum load current of 400 μA.
The default setting of the VSNVSVOLT[2:0] is 110, or 3.0 V, unless programmed otherwise in OTP. However, when the coin cell is applied
for the very first time, VSNVS outputs 1.0 V. Only when VIN is applied thereafter, VSNVS transitions to its default, or the programmed value
if different. Upon subsequent removal of VIN, with the coin cell attached, VSNVS changes configuration from an LDO to a switch for the
“110” setting, and remains as an LDO for the other settings, continuing to output the same voltages as when VIN is applied, providing
certain conditions are met as described in Table 107.
VGEN6 AC and transient (continued)
GEN6tON
Turn-on time
Enable to 90% of end value, VIN3 = VIN3MIN, 4.5 V
IGEN6 = 0.0 mA
60 – 500 μs
GEN6tOFF
Turn-off time
Disable to 10% of initial value, VIN3 = VIN3MIN
IGEN6 = 0.0 mA
––10ms
GEN6OSHT
Start-up overshoot
VIN3 = VIN3MIN, 4.5 V, IGEN6 = 0 mA –1.02.0%
VGEN6LOTR
Transient load response
VIN3 = VIN3MIN, 4.5 V
IGEN6 = 20 to 200 mA in 1.0 μs
Peak of overshoot or undershoot of VGEN6 with respect to final
value. Refer to Figure 25
––3.0%
VGEN6LITR
Transient line response
IGEN6 = 150 mA
VIN3INITIAL = 2.8 V to VIN3FINAL = 3.3 V for
VGEN6[3:0] = 0000 to 0111
VIN3INITIAL = VGEN6+0.3 V to VIN3FINAL = VGEN6+0.8 V for
VGEN6[3:0] = 1000 to 1111
Refer to Figure 25
–5.08.0mV
Notes
71. When the LDO output voltage is set above 2.6 V, the minimum allowed input voltage needs to be at least the output voltage plus 0.25 V for proper
regulation due to the dropout voltage generated through the internal LDO transistor.
72. The PSRR of the regulators is measured with the perturbing signal at the input of the regulator. The power management IC is supplied separately
from the input of the regulator and does not contain the perturbed signal. During measurements, care must be taken not to operate in the dropout
region of the regulator under test. VIN3MIN refers to the minimum allowed input voltage for a particular output voltage.
Table 106. VGEN6 electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VIN3 = 3.6 V,
VGEN6[3:0] = 1111, IGEN6 = 10 mA, typical external component values, unless otherwise noted. Typical values are characterized at
VIN = 3.6 V, VIN3 = 3.6 V, VGEN6[3:0] = 1111, IGEN6 = 10 mA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
NXP Semiconductors 91
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Figure 26. VSNVS supply switch architecture
Table 107 provides a summary of the VSNVS operation at a different VIN input voltage and with or without coin cell connected to the
system.
6.4.7.0.1 VSNVS control
The VSNVS output level is configured through the VSNVSVOLT[2:0]bits on VSNVSCTL register as shown in table Table 108.
6.4.7.0.2 VSNVS external components
Table 107. VSNVS modes of operation
VSNVSVOLT[2:0] VIN Mode
110 > VTH1 VIN LDO 3.0 V
110 < VTL1 Coin cell switch
000 – 101 > VTH0 VIN LDO
000 – 101 < VTL0 Coin cell LDO
Table 108. Register VSNVSCTL - ADDR 0x6B
Name Bit # R/W Default Description
VSNVSVOLT 2:0 R/W 0x80
Configures VSNVS output voltage.(73)
000 = 1.0 V
001 = 1.1 V
010 = 1.2 V
011 = 1.3 V
100 = 1.5 V
101 = 1.8 V
110 = 3.0 V
111 = RSVD
UNUSED 7:3 – 0x00 unused
Notes
73. Only valid when a valid input voltage is present.
Table 109. VSNVS external components
Capacitor Value (μF)
VSNVS 0.47
LDO\
PF0100Z
VSNVS
Coin Cell
1.8 - 3.3 V
VIN
2.25 V (VTL0) -
4.5 V
LICELL
Charger
LDO/SWITCH
VREF
+
_
Z
Input
Sense/
Selector
I2C Interface
92 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.7.0.3 VSNVS specifications
Table 110. VSNVS electrical characteristics
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,
ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
VSNVS
VINSNVS
Operating input voltage
Valid coin cell range
Valid VIN
1.8
2.25
–
–
3.3
4.5
V
ISNVS
Operating load current
VINMIN < VIN < VINMAX
5.0 – 400 μA
VSNVS DC, LDO
VSNVS
Output voltage
•5.0
μA < ISNVS < 400 μA (off)
3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
VTL0/VTH < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
•5.0
μA < ISNVS < 400 μA (on)
3.20 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
UVDET < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
•5
.0 μA < ISNVS < 400 μA (coin cell mode)
2.84 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = 110
1.8 V < VCOIN < 3.3 V, VSNVSVOLT[2:0] = [000] - [101]
-5.0%
-8.0%
-5.0%
-4.0%
VCOIN-0.04
-8.0%
3.0
1.0 - 1.8
3.0
1.0 - 1.8
–
1.0 - 1.8
7.0%
7.0%
5.0%
4.0%
VCOIN
7.0%
V
(77)
VSNVSDROP
Dropout voltage
2.85 V < VIN < 2.9 V, VSNVSVOLT[2:0] = 110
5.0 μA < ISNVS < 400 μA
––50mV
ISNVSLIM
Current limit
PF0100Z
VIN > VTH1, VSNVSVOLT[2:0] = 110
VIN > VTL0, VSNVSVOLT[2:0] = 000 to 101
VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101
PF0100AZ
VIN > VTH1, VSNVSVOLT[2:0] = 110
VIN > VTL0, VSNVSVOLT[2:0] = 000 to 101
VIN < VTL0, VSNVSVOLT[2:0] = 000 to 101
750
500
480
1100
500
480
–
–
–
–
–
–
5900
5900
3600
6750
6750
4500
μA
VTH0
VIN threshold (coin cell powered to VIN powered) VIN going high with
valid coin cell
VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.25 2.40 2.55
V
VTL0
VIN threshold (VIN powered to coin cell powered) VIN going low with
valid coin cell
VSNVSVOLT[2:0] = 000, 001, 010, 011, 100, 101 2.20 2.35 2.50
V
VHYST1 VIN threshold hysteresis for VTH1-VTL1 5.0 – – mV
VHYST0 VIN threshold hysteresis for VTH0-VTL0 5.0 – – mV
VSNVSCROSS
Output voltage during crossover
VSNVSVOLT[2:0] = 110
VCOIN > 2.9 V
Switch to LDO: VIN > 2.825 V, ISNVS = 100 μA
LDO to Switch: VIN < 3.05 V, ISNVS = 100 μA
2.7 – – V (74)
NXP Semiconductors 93
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.7.1 Coin cell battery backup
The LICELL pin provides for a connection of a coin cell backup battery or a “super” capacitor. If the voltage at VIN goes below the VIN
threshold (VTL1 and VTL0), contact-bounced, or removed, the coin cell maintained logic is powered by the voltage applied to LICELL. The
supply for internal logic and the VSNVS rail switch over to the LICELL pin when VIN goes below VTL1 or VTL0, even in the absence of a
voltage at the LICELL pin, resulting in clearing of memory and turning off VSNVS. Applications concerned about this behavior can tie the
LICELL pin to any system voltage between 1.8 V and 3.0 V. A small capacitor should be placed from LICELL to ground under all
circumstances.
VSNVS AC and transient
tONSNVS
Turn-on time (load capacitor, 0.47 μF)
VIN = UVDET to 90% of VSNVS
VCOIN = 0.0 V, ISNVS = 5.0 μA
VSNVSVOLT[2:0] = 000 to 110
––24ms
(75), (76)
VSNVSOSH
Start-up overshoot
VSNVSVOLT[2:0] = 000 to 110
ISNVS = 5.0 μA
dVIN/dt = 50 mV/μs
–4070mV
VSNVSLITR
Transient line response ISNVS = 75% of ISNVSMAX
3.2 V < VIN < 4.5 V, VSNVSVOLT[2:0] = 110
2.45 V < VIN < 4.5 V, VSNVSVOLT[2:0] = [000] - [101]
–
–
32
22
–
–mV
VSNVSLOTR
Transient load response
VSNVSVOLT[2:0] = 110
3.1 V (UVDETL)< VIN ≤ 4.5 V
ISNVS = 75 to 750 μA
VSNVSVOLT[2:0] = 000 to 101
2.45 V < VIN ≤ 4.5 V
VTL0 > VIN, 1.8 V ≤ VCOIN ≤ 3.3 V
ISNVS = 40 μA to 400 μA
Refer to Figure 25
2.8
–
–
1.0
–
2.0
V
%
VSNVS DC, switch
VINSNVS
Operating input voltage
Valid coin cell range 1.8 – 3.3 V
ISNVS Operating load current 5.0 – 400 μA
RDSONSNVS
Internal switch RDS(on)
VCOIN = 2.6 V – – 100 W
VTL1 VIN threshold (VIN powered to coin cell powered)
VSNVSVOLT[2:0] = 110 2.725 2.90 3.00 V
(74)
VTH1 VIN threshold (coin cell powered to VIN powered)
VSNVSVOLT[2:0] = 110 2.775 2.95 3.1 V
Notes
74. During crossover from VIN to LICELL, the VSNVS output voltage may drop to 2.7 V before going to the LICELL voltage. Though this is outside
the specified DC voltage level for the VDD_SNVS_IN pin of the i.MX 6, this momentary drop does not cause a malfunction. The i.MX 6’s RTC
continues to operate through the transition, and as a worst case may switch to the internal RC oscillator for a few clock cycles before switching
back to the external crystal oscillator.
75. The start-up of VSNVS is not monotonic. It first rises to 1.0 V and then settles to its programmed value within the specified tr1 time.
76. From coin cell insertion to VSNVS = 1.0 V, the delay time is typically 400 ms.
77. For 1.8 V ISNVS limited to 100 μA for VCOIN < 2.1 V
Table 110. VSNVS electrical characteristics (continued)
All parameters are specified at PF0100Z TA = -40 °C to 85 °C, PF0100AZ TA = -40 °C to 105 °C, VIN = 3.6 V, VSNVS = 3.0 V,
ISNVS = 5.0 μA, typical external component values, unless otherwise noted. Typical values are characterized at VIN = 3.6 V,
VSNVS = 3.0 V, ISNVS = 5.0 μA, and 25 °C, unless otherwise noted.
Symbol Parameter Min Typ Max Unit Notes
94 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.4.7.1.1 Coin cell charger control
The coin cell charger circuit functions as a current-limited voltage source, resulting in the CC/CV taper characteristic typically used for
rechargeable Lithium-Ion batteries. The coin cell charger is enabled via the COINCHEN bit, while the coin cell voltage is programmable
through the VCOIN[2:0] bits on register COINCTL in Table 112. The coin cell charger voltage is programmable. In the on state, the charger
current is fixed at ICOINHI. In sleep and standby modes, the charger current is reduced to a typical 10 μA. In the off state, coin cell charging
is not available as the main battery could be depleted unnecessarily. The coin cell charging is stopped when VIN is below UVDET.
6.4.7.1.2 External components
6.4.7.1.3 Coin cell specifications
Table 111. Coin cell charger voltage
VCOIN[2:0] VCOIN (V)(78)
000 2.50
001 2.70
010 2.80
011 2.90
100 3.00
101 3.10
110 3.20
111 3.30
Notes
78. Coin cell voltages selected based on the
type of LICELL used on the system.
Table 112. Register COINCTL - ADDR 0x1A
Name Bit # R/W Default Description
VCOIN 2:0 R/W 0x00
Coin cell charger output voltage selection.
See Table 111 for all options selectable through
these bits.
COINCHEN 3 R/W 0x00 Enable or disable the coin cell charger
UNUSED 7:4 – 0x00 unused
Table 113. Coin cell charger external components
Component Value Units
LICELL bypass capacitor 100 nF
Table 114. Coin cell charger specifications
Parameter Typ Unit
Voltage accuracy 100 mV
Coin cell charge current in on mode ICOINHI 60 μA
Current accuracy 30 %
NXP Semiconductors 95
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5 Control interface I2C block description
The PF0100Z contains an I2C interface port which allows access by a processor, or any I2C master, to the register set. Via these registers
the resources of the IC can be controlled. The registers also provide status information about how the IC is operating. The SCL and SDA
lines should be routed away from noisy signals and planes to minimize noise pick up. To prevent reflections in the SCL and SDA traces
from creating false pulses, the rise and fall times of the SCL and SDA signals must be greater than 20 ns. This can be accomplished by
reducing the drive strength of the I2C master, via software. The i.MX6 I2C driver defaults to a 40 Ω drive strength. It is recommended to
use a drive strength of 80 Ω or higher to increase the edge times. Alternatively, this can be accomplished by using small capacitors from
SCL and SDA to ground. For example, use 5.1 pF capacitors from SCL and SDA to ground for bus pull-up resistors of 4.8 kΩ.
6.5.1 I2C device ID
I2C interface protocol requires a device ID for addressing the target IC on a multi-device bus. To allow flexibility in addressing for bus
conflict avoidance, fuse programmability is provided to allow configuration for the lower 3 address LSB(s). Refer to 6.1.2 One time
programmability (OTP), page 20 for more details. This product supports 7-bit addressing only; support is not provided for 10-bit or general
call addressing. Note, when the TBB bits for the I2C slave address are written, the next access to the chip, must then use the new slave
address; these bits take affect right away.
6.5.2 I2C operation
The I2C mode of the interface is implemented generally following the fast mode definition which supports up to 400 kbits/s operation
(exceptions to the standard are noted to be 7-bit only addressing and no support for General Call addressing.) Timing diagrams, electrical
specifications, and further details can be found in the I2C specification, which is available for download at:
http://www.nxp.com/acrobat_download/literature/9398/39340011.pdf
I2C read operations are also performed in byte increments separated by an ACK. Read operations also begin with the MSB and each byte
will be sent out unless a STOP command or NACK is received prior to completion.
The following examples show how to write and read data to and from the IC. The host initiates and terminates all communication. The
host sends a master command packet after driving the start condition. The device responds to the host if the master command packet
contains the corresponding slave address. In the following examples, the device is shown always responding with an ACK to
transmissions from the host. If at any time a NACK is received, the host should terminate the current transaction and retry the transaction.
Figure 27. I2C write example
Figure 28. I2C read example
Devic e
A
ddress
Register Addre ss
Packe
t
T
y
pe
START
R
/
W
Host SD
A
A
C
K
Slave SD
A
A
C
K
M
aster Driven Data
(
byte
0)
07
STOP
Host can
also drive
anothe
r
Start instead
of Stop
A
C
K
0
07 07
Device
Address Register Address Device Address
Packet
Type
START 0
R/W
1623 815
07
A
C
K
STOP
A
C
K
A
C
K
START
07
R/W
NA
CK
PMIC Driven Data
Host can also
drive another
Start instead of
Stop
1
Host SDA
Slave SDA
96 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.3 Interrupt handling
The system is informed about important events based on interrupts. Unmasked interrupt events are signaled to the processor by driving
the INTB pin low.
Each interrupt is latched so even if the interrupt source becomes inactive, the interrupt remains set until cleared. Each interrupt can be
cleared by writing a “1” to the appropriate bit in the interrupt status register; this also causes the INTB pin to go high. If there are multiple
interrupt bits set the INTB pin remains low until all are either masked or cleared. If a new interrupt occurs while the processor clears an
existing interrupt bit, the INTB pin remains low.
Each interrupt can be masked by setting the corresponding mask bit to a 1. As a result, when a masked interrupt bit goes high, the INTB
pin does not go low. A masked interrupt can still be read from the interrupt status register. This gives the processor the option of polling
for status from the IC. The IC powers up with all interrupts masked, so the processor must initially poll the device to determine if any
interrupts are active. Alternatively, the processor can unmask the interrupt bits of interest. If a masked interrupt bit was already high, the
INTB pin goes low after unmasking.
The sense registers contain status and input sense bits so the system processor can poll the current state of interrupt sources. They are
read only, and not latched or clearable.
Interrupts generated by external events are debounced; therefore, the event needs to be stable throughout the debounce period before
an interrupt is generated. Nominal debounce periods for each event are documented in the INT summary Table 115. Due to the
asynchronous nature of the debounce timer, the effective debounce time can vary slightly.
6.5.4 Interrupt bit summary
Table 115 summarizes all interrupt, mask, and sense bits associated with INTB control. For more detailed behavioral descriptions, refer
to the related chapters.
Table 115. Interrupt, Mask and Sense Bits
Interrupt Mask Sense Purpose Trigger Debounce time (ms)
LOWVINI LOWVINM LOWVINS Low input voltage detect
Sense is 1 if below 2.80 V threshold H to L 3.9(79)
PWRONI PWRONM PWRONS Power on button event H to L 31.25(79)
Sense is 1 if PWRON is high. L to H 31.25
THERM110 THERM110M THERM110S Thermal 110 °C threshold
Sense is 1 if above threshold Dual 3.9
THERM120 THERM120M THERM120S Thermal 120 °C threshold
Sense is 1 if above threshold Dual 3.9
THERM125 THERM125M THERM125S Thermal 125 °C threshold
Sense is 1 if above threshold Dual 3.9
THERM130 THERM130M THERM130S Thermal 130 °C threshold
Sense is 1 if above threshold Dual 3.9
SW1AFAULTI SW1AFAULTM SW1AFAULTS Regulator 1A overcurrent limit
Sense is 1 if above current limit L to H 8.0
SW1BFAULTI SW1BFAULTM SW1BFAULTS Regulator 1B overcurrent limit
Sense is 1 if above current limit L to H 8.0
SW1CFAULTI SW1CFAULTM SW1CFAULTS Regulator 1C overcurrent limit
Sense is 1 if above current limit L to H 8.0
SW2FAULTI SW2FAULTM SW2FAULTS Regulator 2 overcurrent limit
Sense is 1 if above current limit L to H 8.0
SW3AFAULTI SW3AFAULTM SW3AFAULTS Regulator 3A overcurrent limit
Sense is 1 if above current limit L to H 8.0
SW3BFAULTI SW3BFAULTM SW3BFAULTS Regulator 3B overcurrent limit
Sense is 1 if above current limit L to H 8.0
SW4FAULTI SW4FAULTM SW4FAULTS Regulator 4 overcurrent limit
Sense is 1 if above current limit L to H 8.0
NXP Semiconductors 97
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
A full description of all interrupt, mask, and sense registers is provided in Tables 116 to 127.
SWBSTFAULTI SWBSTFAULTM SWBSTFAULTS SWBST overcurrent limit
Sense is 1 if above current limit L to H 8.0
VGEN1FAULTI VGEN1FAULTM VGEN1FAULTS VGEN1 overcurrent limit
Sense is 1 if above current limit L to H 8.0
VGEN2FAULTI VGEN2FAULTM VGEN2FAULTS VGEN2 overcurrent limit
Sense is 1 if above current limit L to H 8.0
VGEN3FAULTI VGEN3FAULTM VGEN3FAULTS VGEN3 overcurrent limit
Sense is 1 if above current limit L to H 8.0
VGEN4FAULTI VGEN4FAULTM VGEN4FAULTS VGEN4 overcurrent limit
Sense is 1 if above current limit L to H 8.0
VGEN5FAULTI VGEN5FAULTM VGEN1FAULTS VGEN5 overcurrent limit
Sense is 1 if above current limit L to H 8.0
VGEN6FAULTI VGEN6FAULTM VGEN6FAULTS VGEN6 overcurrent limit
Sense is 1 if above current limit L to H 8.0
OTP_ECCI OTP_ECCM OTP_ECCS 1 or 2 bit error detected in OTP registers
Sense is 1 if error detected L to H 8.0
Notes
79. Debounce timing for the falling edge can be extended with PWRONDBNC[1:0].
Table 116. Register INTSTAT0 - ADDR 0x05
Name Bit # R/W Default Description
PWRONI 0 R/W1C 0 Power on interrupt bit
LOWVINI 1 R/W1C 0 Low-voltage interrupt bit
THERM110I 2 R/W1C 0 110 °C thermal interrupt bit
THERM120I 3 R/W1C 0 120 °C thermal interrupt bit
THERM125I 4 R/W1C 0 125 °C thermal interrupt bit
THERM130I 5 R/W1C 0 130 °C thermal interrupt bit
UNUSED 7:6 – 00 unused
Table 117. Register INTMASK0 - ADDR 0x06
Name Bit # R/W Default Description
PWRONM 0 R/W1C 1 Power on interrupt mask bit
LOWVINM 1 R/W1C 1 Low-voltage interrupt mask bit
THERM110M 2 R/W1C 1 110 °C thermal interrupt mask bit
THERM120M 3 R/W1C 1 120 °C thermal interrupt mask bit
THERM125M 4 R/W1C 1 125 °C thermal interrupt mask bit
THERM130M 5 R/W1C 1 130 °C thermal interrupt mask bit
UNUSED 7:6 – 00 unused
Table 115. Interrupt, Mask and Sense Bits (continued)
Interrupt Mask Sense Purpose Trigger Debounce time (ms)
98 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 118. Register INTSENSE0 - ADDR 0x07
Name Bit # R/W Default Description
PWRONS 0 R 0
Power on sense bit
0 = PWRON low
1 = PWRON high
LOWVINS 1 R 0
Low-voltage sense bit
0 = VIN > 2.8 V
1 = VIN ≤ 2.8 V
THERM110S 2 R 0
110 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM120S 3 R 0
120 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM125S 4 R 0
125 °C thermal sense bit
0 = Below threshold
1 = Above threshold
THERM130S 5 R 0
130 °C thermal sense bit
0 = Below threshold
1 = Above threshold
UNUSED 6 – 0 unused
VDDOTPS 7 R 00
Additional VDDOTP voltage sense pin
0 = VDDOTP grounded
1 = VDDOTP to VCOREDIG or greater
Table 119. Register INTSTAT1 - ADDR 0x08
Name Bit # R/W Default Description
SW1AFAULTI 0 R/W1C 0 SW1A overcurrent interrupt bit
SW1BFAULTI 1 R/W1C 0 SW1B overcurrent interrupt bit
SW1CFAULTI 2 R/W1C 0 SW1C overcurrent interrupt bit
SW2FAULTI 3 R/W1C 0 SW2 overcurrent interrupt bit
SW3AFAULTI 4 R/W1C 0 SW3A overcurrent interrupt bit
SW3BFAULTI 5 R/W1C 0 SW3B overcurrent interrupt bit
SW4FAULTI 6 R/W1C 0 SW4 overcurrent interrupt bit
UNUSED 7 – 0 unused
Table 120. Register INTMASK1 - ADDR 0x09
Name Bit # R/W Default Description
SW1AFAULTM 0 R/W 1 SW1A overcurrent interrupt mask bit
SW1BFAULTM 1 R/W 1 SW1B overcurrent interrupt mask bit
SW1CFAULTM 2 R/W 1 SW1C overcurrent interrupt mask bit
SW2FAULTM 3 R/W 1 SW2 overcurrent interrupt mask bit
SW3AFAULTM 4 R/W 1 SW3A overcurrent interrupt mask bit
SW3BFAULTM 5 R/W 1 SW3B overcurrent interrupt mask bit
SW4FAULTM 6 R/W 1 SW4 overcurrent interrupt mask bit
UNUSED 7 – 0 unused
NXP Semiconductors 99
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 121. Register INTSENSE1 - ADDR 0x0A
Name Bit # R/W Default Description
SW1AFAULTS 0 R 0
SW1A overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW1BFAULTS 1 R 0
SW1B overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW1CFAULTS 2 R 0
SW1C overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW2FAULTS 3 R 0
SW2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW3AFAULTS 4 R 0
SW3A overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW3BFAULTS 5 R 0
SW3B overcurrent sense bit
0 = Normal operation
1 = Above current limit
SW4FAULTS 6 R 0
SW4 overcurrent sense bit
0 = Normal operation
1 = Above current limit
UNUSED 7 – 0 unused
Table 122. Register INTSTAT3 - ADDR 0x0E
Name Bit # R/W Default Description
SWBSTFAULTI 0 R/W1C 0 SWBST overcurrent limit interrupt bit
UNUSED 6:1 – 0x00 unused
OTP_ECCI 7 R/W1C 0 OTP error interrupt bit
Table 123. Register INTMASK3 - ADDR 0x0F
Name Bit # R/W Default Description
SWBSTFAULTM 0 R/W 1 SWBST overcurrent limit interrupt mask bit
UNUSED 6:1 – 0x00 unused
OTP_ECCM 7 R/W 1 OTP error interrupt mask bit
Table 124. Register INTSENSE3 - ADDR 0x10
Name Bit # R/W Default Description
SWBSTFAULTS 0 R 0
SWBST overcurrent limit sense bit
0 = Normal operation
1 = Above current limit
UNUSED 6:1 – 0x00 unused
OTP_ECCS 7 R 0
OTP error sense bit
0 = No error detected
1 = OTP error detected
100 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
Table 125. Register INTSTAT4 - ADDR 0x11
Name Bit # R/W Default Description
VGEN1FAULTI 0 R/W1C 0 VGEN1 overcurrent interrupt bit
VGEN2FAULTI 1 R/W1C 0 VGEN2 overcurrent interrupt bit
VGEN3FAULTI 2 R/W1C 0 VGEN3 overcurrent interrupt bit
VGEN4FAULTI 3 R/W1C 0 VGEN4 overcurrent interrupt bit
VGEN5FAULTI 4 R/W1C 0 VGEN5 overcurrent interrupt bit
VGEN6FAULTI 5 R/W1C 0 VGEN6 overcurrent interrupt bit
UNUSED 7:6 – 00 unused
Table 126. Register INTMASK4 - ADDR 0x12
Name Bit # R/W Default Description
VGEN1FAULTM 0 R/W 1 VGEN1 overcurrent interrupt mask bit
VGEN2FAULTM 1 R/W 1 VGEN2 overcurrent interrupt mask bit
VGEN3FAULTM 2 R/W 1 VGEN3 overcurrent interrupt mask bit
VGEN4FAULTM 3 R/W 1 VGEN4 overcurrent interrupt mask bit
VGEN5FAULTM 4 R/W 1 VGEN5 overcurrent interrupt mask bit
VGEN6FAULTM 5 R/W 1 VGEN6 overcurrent interrupt mask bit
UNUSED 7:6 – 00 unused
Table 127. Register INTSENSE4 - ADDR 0x13
Name Bit # R/W Default Description
VGEN1FAULTS 0 R 0
VGEN1 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN2FAULTS 1 R 0
VGEN2 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN3FAULTS 2 R 0
VGEN3 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN4FAULTS 3 R 0
VGEN4 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN5FAULTS 4 R 0
VGEN5 overcurrent sense bit
0 = Normal operation
1 = Above current limit
VGEN6FAULTS 5 R 0
VGEN6 overcurrent sense bit
0 = Normal operation
1 = Above current limit
UNUSED 7:6 – 00 unused
NXP Semiconductors 101
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.5 Specific registers
6.5.5.1 IC and version identification
The IC and other version details can be read via identification bits. These are hard-wired on chip and described in Tables 128 to 130.
6.5.5.2 Embedded memory
There are four register banks of general purpose embedded memory to store critical data. The data written to MEMA[7:0], MEMB[7:0],
MEMC[7:0], and MEMD[7:0] is maintained by the coin cell when the main battery is deeply discharged, removed, or contact-bounced. The
contents of the embedded memory are reset by COINPORB. The banks can be used for any system need for bit retention with coin cell
backup.
Table 128. Register DEVICEID - ADDR 0x00
Name Bit # R/W Default Description
DEVICEID 3:0 R 0x00 Die version.
0000 = PF0100
UNUSED 7:4 – 0x01 Unused
Table 129. Register SILICON REV- ADDR 0x03
Name Bit # R/W Default Description
METAL_LAYER_REV 3:0 R 0x00
Represents the metal mask revision
Pass 0.0 = 0000
.
.
Pass 0.15 = 1111
FULL_LAYER_REV 7:4 R 0x01
Represents the full mask revision
Pass 1.0 = 0001
.
.
Pass 15.0 = 1111
Table 130. Register FABID - ADDR 0x04
Name Bit # R/W Default Description
FIN 1:0 R 0x00 Allows for characterizing different options within
the same reticule
FAB 3:2 R 0x00 Represents the wafer manufacturing facility
Unused 7:0 R 0x00 unused
Table 131. Register MEMA ADDR 0x1C
Name Bit # R/W Default Description
MEMA 7:0 R/W 0 Memory bank A
Table 132. Register MEMB ADDR 0x1D
Name Bit # R/W Default Description
MEMB 7:0 R/W 0 Memory bank B
102 NXP Semiconductors
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.6 Register Bitmap
The register map is comprised of thirty-two pages, and its address and data fields are each eight bits wide. Only the first two pages can
be accessed. On each page, registers 0 to 0x7F are referred to as 'functional', and registers 0x80 to 0xFF as 'extended'. On each page,
the functional registers are the same, but the extended registers are different. To access registers in Table 136. Extended page 1, page
106, one must first write 0x01 to the page register at address 0x7F, and to access registers Table 137. Extended page 2, page 110, one
must first write 0x02 to the page register at address 0x7F. To access the Table 135. Functional page, page 103 from one of the extended
pages, no write to the page register is necessary.
Registers missing in the sequence are reserved; reading from them returns a value 0x00, and writing to them has no effect. The contents
of all registers are given in the tables defined in this chapter; each table is structure as follows:
Name: Name of the bit.
Bit #: The bit location in the register (7-0)
R/W: Read / Write access and control
• R is read-only access
• R/W is read and write access
• RW1C is read and write access with write 1 to clear
Reset: Reset signals are color coded based on the following legend.
Default: The value after reset, as noted in the default column of the memory map.
• Fixed defaults are explicitly declared as 0 or 1.
• “X” corresponds to Read / Write bits initialized at start-up, based on the OTP fuse settings or default if VDDOTP = 1.5 V. Bits are
subsequently I2C modifiable, when their reset has been released. “X” may also refer to bits which may have other dependencies.
For example, some bits may depend on the version of the IC, or a value from an analog block, for instance the sense bits for the
interrupts.
Table 133. Register MEMC ADDR 0x1E
Name Bit # R/W Default Description
MEMC 7:0 R/W 0 Memory bank C
Table 134. Register MEMD ADDR 0x1F
Name Bit # R/W Default Description
MEMD 7:0 R/W 0 Memory bank D
Bits reset by SC and VCOREDIG_PORB
Bits reset by PWRON or loaded default or OTP configuration
Bits reset by DIGRESETB
Bits reset by PORB or RESETBMCU
Bits reset by VCOREDIG_PORB
Bits reset by POR or OFFB
NXP Semiconductors 103
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
6.5.6.1 Register map
Table 135. Functional page
Add Register
Name R/W Default
BITS[7:0]
7 6 5 4 3 2 1 0
00 DeviceID R8'b0001_0000
– – – – DEVICE ID [3:0]
00 0 1 0 0 0 0
03 SILICONREVID R8'b0001_0000
FULL_LAYER_REV[3:0] METAL_LAYER_REV[3:0]
XX X X X X X X
04 FABID R8'b0000_0000
–– – – FAB[1:0] FIN[1:0]
00 0 0 0 0 0 0
05 INTSTAT0 RW1C 8'b0000_0000
––THERM130I THERM125I THERM120I THERM110I LOWVINI PWRONI
00 0 0 0 0 0 0
06 INTMASK0 R/W 8'b0011_1111
––THERM130M THERM125M THERM120M THERM110M LOWVINM PWRONM
00 1 1 1 1 1 1
07 INTSENSE0 R8'b00xx_xxxx
VDDOTPS RSVD THERM130S THERM125S THERM120S THERM110S LOWVINS PWRONS
00 x x x x x x
08 INTSTAT1 RW1C 8'b0000_0000
–SW4FAULTI SW3BFAULTI SW3AFAULTI SW2FAULTI SW1CFAULTI SW1BFAULTI SW1AFAULTI
00 0 0 0 0 0 0
09 INTMASK1 R/W 8'b0111_1111
–SW4FAULTM SW3BFAULTM SW3AFAULTM SW2FAULTM SW1CFAULTM SW1BFAULTM SW1AFAULTM
01 1 1 1 1 1 1
0A INTSENSE1 R8'b0xxx_xxxx
– SW4FAULTS SW3BFAULTS SW3AFAULTS SW2FAULTS SW1CFAULTS SW1BFAULTS SW1AFAULTS
0x x x x x x x
0E INTSTAT3 RW1C 8'b0000_0000
OTP_ECCI–– ––– –SWBSTFAULTI
00 0 0 0 0 0 0
0F INTMASK3 R/W 8'b1000_0001
OTP_ECCM–– ––– –SWBSTFAULTM
10 0 0 0 0 0 1
10 INTSENSE3 R8'b0000_000x
OTP_ECCS – – – – – – SWBSTFAULTS
00 0 0 0 0 0 x
11 INTSTAT4 RW1C 8'b0000_0000
––
VGEN6FAULTI VGEN5FAULTI VGEN4FAULTI VGEN3FAULTI VGEN2FAULTI VGEN1FAULTI
00 0 0 0 0 0 0
12 INTMASK4 R/W 8'b0011_1111
––
VGEN6
FAULTM
VGEN5
FAULTM
VGEN4
FAULTM
VGEN3
FAULTM
VGEN2
FAULTM
VGEN1
FAULTM
00 1 1 1 1 1 1
13 INTSENSE4 R8'b00xx_xxxx
––
VGEN6
FAULTS
VGEN5
FAULTS
VGEN4
FAULTS
VGEN3
FAULTS
VGEN2
FAULTS
VGEN1
FAULTS
00 x x x x x x
1A COINCTL R/W 8'b0000_0000
–– – –
COINCHEN VCOIN[2:0]
00 0 0 0 0 0 0
104 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
1B PWRCTL R/W 8'b0001_0000
REGSCPEN STANDBYINV STBYDLY[1:0] PWRONBDBNC[1:0] PWRONRSTEN RESTARTEN
000 100 0 0
1C MEMA R/W 8'b0000_0000
MEMA[7:0]
000 000 0 0
1D MEMB R/W 8'b0000_0000
MEMB[7:0]
000 000 0 0
1E MEMC R/W 8'b0000_0000
MEMC[7:0]
000 000 0 0
1F MEMD R/W 8'b0000_0000
MEMD[7:0]
000 000 0 0
20 SW1ABVOLT R/W/M 8'b00xx_xxxx
–– SW1AB[5:0]
00 x x x x x x
21 SW1ABSTBY R/W 8'b00xx_xxxx
–– SW1ABSTBY[5:0]
00 x x x x x x
22 SW1ABOFF R/W 8'b00xx_xxxx
–– SW1ABOFF[5:0]
00 x x x x x x
23 SW1ABMODE R/W 8'b0000_1000
––SW1ABOMODE – SW1ABMODE[3:0]
000 010 0 0
24 SW1ABCONF R/W 8'bxx00_xx00
SW1ABDVSSPEED[1:0] SW1BAPHASE[1:0] SW1ABFREQ[1:0] – SW1ABILIM
xx 0 0 x x 0 0
2E SW1CVOLT R/W 8'b00xx_xxxx
–– SW1C[5:0]
00 x x x x x x
2F SW1CSTBY R/W 8'b00xx_xxxx
–– SW1CSTBY[5:0]
00 x x x x x x
30 SW1COFF R/W 8'b00xx_xxxx
–– SW1COFF[5:0]
00 x x x x x x
31 SW1CMODE R/W 8'b0000_1000
––SW1COMODE – SW1CMODE[3:0]
000 010 0 0
32 SW1CCONF R/W 8'bxx00_xx00
SW1CDVSSPEED[1:0] SW1CPHASE[1:0] SW1CFREQ[1:0] – SW1CILIM
xx 0 0 x x 0 0
35 SW2VOLT R/W 8'b0xxx_xxxx
–SW2[6:0]
0x x x x x x x
36 SW2STBY R/W 8'b0xxx_xxxx
–SW2STBY[6:0]
0x x x x x x x
37 SW2OFF R/W 8'b0xxx_xxxx
–SW2OFF[6:0]
0x x x x x x x
Table 135. Functional page (continued)
Add Register
Name R/W Default
BITS[7:0]
7 6 5 4 3 2 1 0
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
38 SW2MODE R/W 8'b0000_1000
––SW2OMODE – SW2MODE[3:0]
00 0 0 1 0 0 0
39 SW2CONF R/W 8'bxx01_xx00
SW2DVSSPEED[1:0] SW2PHASE[1:0] SW2FREQ[1:0] – SW2ILIM
xx 0 1 x x 0 0
3C SW3AVOLT R/W 8'b0xxx_xxxx
–SW3A[6:0]
0x x x x x x x
3D SW3ASTBY R/W 8'b0xxx_xxxx
–SW3ASTBY[6:0]
0x x x x x x x
3E SW3AOFF R/W 8'b0xxx_xxxx
–SW3AOFF[6:0]
0x x x x x x x
3F SW3AMODE R/W 8'b0000_1000
SW3AOMODE – SW3AMODE[3:0]
00 0 0 1 0 0 0
40 SW3ACONF R/W 8'bxx10_xx00
SW3ADVSSPEED[1:0] SW3APHASE[1:0] SW3AFREQ[1:0] – SW3AILIM
xx 1 0 x x 0 0
43 SW3BVOLT R/W 8'b0xxx_xxxx
–SW3B[6:0]
0x x x x x x x
44 SW3BSTBY R/W 8'b0xxx_xxxx
–SW3BSTBY[6:0]
0x x x x x x x
45 SW3BOFF R/W 8'b0xxx_xxxx
–SW3BOFF[6:0]
0x x x x x x x
46 SW3BMODE R/W 8'b0000_1000
––SW3BOMODE – SW3BMODE[3:0]
00 0 0 1 0 0 0
47 SW3BCONF R/W 8'bxx10_xx00
SW3BDVSSPEED[1:0] SW3BPHASE[1:0] SW3BFREQ[1:0] – SW3BILIM
xx 1 0 x x 0 0
4A SW4VOLT R/W 8'b0xxx_xxxx
–SW4[6:0]
0x x x x x x x
4B SW4STBY R/W 8'b0xxx_xxxx
–SW4STBY[6:0]
0x x x x x x x
4C SW4OFF R/W 8'b0xxx_xxxx
–SW4OFF[6:0]
0x x x x x x x
4D SW4MODE R/W 8'b0000_1000
––SW4OMODE – SW4MODE[3:0]
00 0 0 1 0 0 0
4E SW4CONF R/W 8'bxx11_xx00
SW4DVSSPEED[1:0] SW4PHASE[1:0] SW4FREQ[1:0] – SW4ILIM
xx 1 1 x x 0 0
Table 135. Functional page (continued)
Add Register
Name R/W Default
BITS[7:0]
7 6 5 4 3 2 1 0
106 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
66 SWBSTCTL R/W 8'b0xx0_10xx
–SWBST1STBYMODE[1:0] – SWBST1MODE[1:0] SWBST1VOLT[1:0]
0xx 010 x x
6A VREFDDRCTL R/W 8'b000x_0000
–– –VREFDDREN – – – –
00 0 x 0 0 0 0
6B VSNVSCTL R/W 8'b0000_0xxx
–– – – – VSNVSVOLT[2:0]
000 000 x x
6C VGEN1CTL R/W 8'b000x_xxxx
–VGEN1LPWR VGEN1STBY VGEN1EN VGEN1[3:0]
00 0 x x x x x
6D VGEN2CTL R/W 8'b000x_xxxx
–VGEN2LPWR VGEN2STBY VGEN2EN VGEN2[3:0]
00 0 x x x x x
6E VGEN3CTL R/W 8'b000x_xxxx
–VGEN3LPWR VGEN3STBY VGEN3EN VGEN3[3:0]
00 0 x x x x x
6F VGEN4CTL R/W 8'b000x_xxxx
–VGEN4LPWR VGEN4STBY VGEN4EN VGEN4[3:0]
00 0 x x x x x
70 VGEN5CTL R/W 8'b000x_xxxx
–VGEN5LPWR VGEN5STBY VGEN5EN VGEN5[3:0]
00 0 x x x x x
71 VGEN6CTL R/W 8'b000x_xxxx
–VGEN6LPWR VGEN6STBY VGEN6EN VGEN6[3:0]
00 0 x x x x x
7F Page Register R/W 8'b0000_0000
–– – PAGE[4:0]
000 000 0 0
Table 136. Extended page 1
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
80 OTP FUSE READ
EN R/W 8'b000x_xxx0
–– – – –––
OTP FUSE
READ EN
00 0 x xxx0
84 OTP LOAD MASK R/W 8'b0000_0000
START RL PWBRTN FORCE PWRCTL RL PWRCTL RL OTP RL OTP ECC RL OTP
FUSE
RL TRIM
FUSE
00 0 0 0000
8A OTP ECC SE1 R8'bxxx0_0000
– – – ECC5_SE ECC4_SE ECC3_SE ECC2_SE ECC1_SE
xx x 00000
8B OTP ECC SE2 R8'bxxx0_0000
– – – ECC10_SE ECC9_SE ECC8_SE ECC7_SE ECC6_SE
xx x 00000
8C OTP ECC DE1 R8'bxxx0_0000
– – – ECC5_DE ECC4_DE ECC3_DE ECC2_DE ECC1_DE
xx x 00000
Table 135. Functional page (continued)
Add Register
Name R/W Default
BITS[7:0]
7 6 5 4 3 2 1 0
NXP Semiconductors 107
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FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
8D OTP ECC DE2 R8'bxxx0_0000
– – – ECC10_DE ECC9_DE ECC8_DE ECC7_DE ECC6_DE
xx x 00000
A0 OTP SW1AB VOLT R/W 8'b00xx_xxxx
–– SW1AB_VOLT[5:0]
00 x x xxxx
A1 OTP SW1AB SEQ R/W 8'b000x_xxXx
–SW1AB_SEQ[4:0]
00 0 x xxXx
A2 OTP SW1AB
CONFIG R/W 8'b0000_xxxx
–– – –SW1_CONFIG[1:0] SW1AB_FREQ[1:0]
00 0 0xxxx
A8 OTP SW1C VOLT R/W 8'b00xx_xxxx
–– SW1C_VOLT[5:0]
00 x x xxxx
A9 OTP SW1C SEQ R/W 8'b000x_xxxx
–SW1C_SEQ[4:0]
00 0 x xxxx
AA OTP SW1C
CONFIG R/W 8'b0000_00xx
–– – – ––SW1C_FREQ[1:0]
00 0 0 00xx
AC OTP SW2 VOLT R/W 8'b0xxx_xxxx
–SW2_VOLT[5:0]
0x x x xxxx
AD OTP SW2 SEQ R/W 8'b000x_xxxx
–– SW2_SEQ[4:0]
00 0 x xxxx
AE OTP SW2 CONFIG R/W 8'b0000_00xx
–– – – –– SW2_FREQ[1:0]
00 0 0 00xx
B0 OTP SW3A VOLT R/W 8'b0xxx_xxxx
–SW3A_VOLT[6:0]
0x x x xxxx
B1 OTP SW3A SEQ R/W 8'b000x_xxxx
–– SW3A_SEQ[4:0]
00 0 x xxxx
B2 OTP SW3A
CONFIG R/W 8'b0000_xxxx
–– – –SW3_CONFIG[1:0] SW3A_FREQ[1:0]
00 0 0xxxx
B4 OTP SW3B VOLT R/W 8'b0xxx_xxxx
–SW3B_VOLT[6:0]
0x x x xxxx
B5 OTP SW3B SEQ R/W 8'b000x_xxxx
–– SW3B_SEQ[4:0]
00 0 x xxxx
B6 OTP SW3B
CONFIG R/W 8'b0000_00xx
–– – – ––
SW3B_CONFIG[1:0]
00 0 0 00xx
Table 136. Extended page 1 (continued)
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
108 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
B8 OTP SW4 VOLT R/W 8'b00xx_xxxx
–SW4_VOLT[6:0]
00 x x xxxx
B9 OTP SW4 SEQ R/W 8'b000x_xxxx
–– – SW4_SEQ[4:0]
00 0 x xxxx
BA OTP SW4 CONFIG R/W 8'b000x_xxxx
–– – VTT – – SW4_FREQ[1:0]
00 0 x xxxx
BC OTP SWBST VOLT R/W 8'b0000_00xx
–– – – ––SWBST_VOLT[1:0]
00 0 0 00xx
BD OTP SWBST SEQ R/W 8'b0000_xxxx
–– – SWBST_SEQ[4:0]
00 0 0 xxxx
C0 OTP VSNVS VOLT R/W 8'b0000_0xxx
–– – – – VSNVS_VOLT[2:0]
00 0 0 00xx
C4 OTP VREFDDR
SEQ R/W 8'b000x_x0xx
–– – VREFDDR_SEQ[4:0]
00 0 x x0xx
C8 OTP VGEN1 VOLT R/W 8'b0000_xxxx
–– – – VGEN1_VOLT[3:0]
00 0 0 xxxx
C9 OTP VGEN1 SEQ R/W 8'b000x_xxxx
–– – VGEN1_SEQ[4:0]
00 0 x xxxx
CC OTP VGEN2 VOLT R/W 8'b0000_xxxx
–– – – VGEN2_VOLT[3:0]
00 0 0 xxxx
CD OTP VGEN2 SEQ R/W 8'b000x_xxxx
–– – VGEN2_SEQ[4:0]
00 0 x xxxx
D0 OTP VGEN3 VOLT R/W 8'b0000_xxxx
–– – – VGEN3_VOLT[3:0]
00 0 0 xxxx
D1 OTP VGEN3 SEQ R/W 8'b000x_xxxx
–– – VGEN3_SEQ[4:0]
00 0 x xxxx
D4 OTP VGEN4 VOLT R/W 8'b0000_xxxx
–– – – VGEN4_VOLT[3:0]
00 0 0 xxxx
D5 OTP VGEN4 SEQ R/W 8'b000x_xxxx
–– – VGEN4_SEQ[4:0]
00 0 x xxxx
Table 136. Extended page 1 (continued)
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
NXP Semiconductors 109
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
D8 OTP VGEN5 VOLT R/W 8'b0000_xxxx
–– – – VGEN5_VOLT[3:0]
00 0 0xxxx
D9 OTP VGEN5 SEQ R/W 8'b000x_xxxx
–– – VGEN5_SEQ[4:0]
00 0 x xxxx
DC OTP VGEN6 VOLT R/W 8'b0000_xxxx
–– – – VGEN6_VOLT[3:0]
00 0 0xxxx
DD OTP VGEN6 SEQ R/W 8'b000x_xxxx
–– – VGEN6_SEQ[4:0]
00 0 x xxxx
E0 OTP PU CONFIG1 R/W 8'b000x_xxxx
–– –
PWRON_
CFG1 SWDVS_CLK1[1:0] SEQ_CLK_SPEED1[1:0]
00 0 x xxxx
E1 OTP PU CONFIG2 R/W 8'b000x_xxxx
–– –
PWRON_
CFG2 SWDVS_CLK2[1:0] SEQ_CLK_SPEED2[1:0]
00 0 x xxxx
E2 OTP PU CONFIG3 R/W 8'b000x_xxxx
–– –
PWRON_
CFG3 SWDVS_CLK3[1:0] SEQ_CLK_SPEED3[1:0]
00 0 x xxxx
E3 OTP PU CONFIG
XOR R 8'b000x_xxxx
–– –
PWRON_CFG
_XOR SWDVS_CLK3_XOR SEQ_CLK_SPEED_XOR
00 0 x xxxx
E4 (80) OTP FUSE POR1 R/W 8'b0000_00x0
TBB_POR SOFT_FUSE_
POR ––––FUSE_POR1 –
00 0 0 00x0
E5 OTP FUSE POR1 R/W 8'b0000_00x0
RSVD RSVD – – – – FUSE_POR2 –
00 0 0 00x0
E6 OTP FUSE POR1 R/W 8'b0000_00x0
RSVD RSVD – – – – FUSE_POR3 –
00 0 0 00x0
E7 OTP FUSE POR
XOR R 8'b0000_00x0
RSVD RSVD – – – – FUSE_POR_X
OR –
00 0 0 00x0
E8 OTP PWRGD EN R/W/M 8'b0000_000x
–– – – –––OTP_PG_EN
00 0 0 00x0
F0 OTP EN ECCO R/W 8'b000x_xxxx
–– –
EN_ECC_
BANK5
EN_ECC_
BANK4
EN_ECC_
BANK3
EN_ECC_
BANK2
EN_ECC_
BANK1
00 0 x xxxx
F1 OTP EN ECC1 R/W 8'b000x_xxxx
–– –
EN_ECC_
BANK10
EN_ECC_
BANK9
EN_ECC_
BANK8
EN_ECC_
BANK7
EN_ECC_
BANK6
00 0 x xxxx
Table 136. Extended page 1 (continued)
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
110 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
F4 OTP SPARE2_4 R/W 8'b0000_xxxx
–– – – RSVD
00 0 0 xxxx
F5 OTP SPARE4_3 R/W 8'b0000_0xxx
–– – – – RSVD
00 0 0 0xxx
F6 OTP SPARE6_2 R/W 8'b0000_00xx
–– – – –– RSVD
00 0 0 00xx
F7 OTP SPARE7_1 R/W 8'b0000_0xxx
–– – – –– – RSVD
00 0 0 0xxx
FE OTP DONE R/W 8'b0000_000x
–– – – –––OTP_DONE
00 0 0 000x
FF OTP I2C ADDR R/W 8'b0000_0xxx
–– – –
I2C_SLV
ADDR[3] I2C_SLV ADDR[2:0]
00 0 0 1xxx
Notes
80. In the PF0100Z FUSE_POR1, FUSE_POR2, and FUSE_POR3 are XOR’ed into the FUSE_POR_XOR bit. The FUSE_POR_XOR has to be 1 for
fuses to be loaded. This can be achieved by setting any one or all of the FUSE_PORx bits. In the PF0100AZ, the XOR function is removed. It is
required to set all of the FUSE_PORx bits to be able to load the fuses.
Table 137. Extended page 2
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
81 SW1AB PWRSTG R/W 8'b1111_1111
RSVD RSVD RSVD RSVD RSVD SW1AB_PWRSTG[2:0]
11 1 11111
82 PWRSTG RSVD R8'b0000_0000
PWRSTGRSVD
00 0 00000
83 SW1C PWRSTG R8'b1111_1111
RSVD RSVD RSVD RSVD RSVD SW1C_PWRSTG[2:0]
11 1 11111
84 SW2 PWRSTG R8'b1111_1111
RSVD RSVD RSVD RSVD RSVD SW2_PWRSTG[2:0]
11 1 11111
85 SW3A PWRSTG R8'b1111_1111
RSVD RSVD RSVD RSVD RSVD SW3A_PWRSTG[2:0]
11 1 11111
86 SW3B PWRSTG R8'b1111_1111
RSVD RSVD RSVD RSVD RSVD SW3B_PWRSTG[2:0]
11 1 11111
87 SW4 PWRSTG R8'b0111_1111
FSLEXT_
THERM_
DISABLE
PWRGD_
SHDWN_
DISABLE
RSVD RSVD RSVD SW4_PWRSTG[2:0]
00 1 11111
88 PWRCTRL OTP
CTRL R/W 8'b0000_0001
–– – –––
PWRGD_EN OTP_
SHDWN_EN
00 0 00001
Table 136. Extended page 1 (continued)
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
NXP Semiconductors 111
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
8D I2C WRITE
ADDRESS TRAP R/W 8'b0000_0000
I2C_WRITE_ADDRESS_TRAP[7:0]
00 0 00000
8E I2C TRAP PAGE R/W 8'b0000_0000
LET_IT_ ROLL RSVD RSVD I2C_TRAP_PAGE[4:0]
00 0 00000
8F I2C TRAP CNTR R/W 8'b0000_0000
I2C_WRITE_ADDRESS_COUNTER[7:0]
00 0 00000
90 IO DRV R/W 8'b00xx_xxxx
SDA_DRV[1:0] SDWNB_DRV[1:0] INTB_DRV[1:0] RESETBMCU_DRV[1:0]
00 x xxxxx
D0 OTP AUTO ECC0 R/W 8'b0000_0000
–– –
AUTO_ECC
_BANK5
AUTO_ECC
_BANK4
AUTO_ECC_B
ANK3
AUTO_ECC
_BANK2
AUTO_ECC_B
ANK1
00 0 00000
D1 OTP AUTO ECC1 R/W 8'b0000_0000
–– –
AUTO_ECC_B
ANK10
AUTO_ECC
_BANK9
AUTO_ECC_B
ANK8
AUTO_ECCBA
NK7
AUTO_ECC_B
ANK6
00 0 00000
D8 Reserved –8'b0000_0000 Reserved(81)
D9 Reserved –8'b0000_0000 Reserved(81)
E1 OTP ECC CTRL1 R/W 8'b0000_0000
ECC1_EN_
TBB
ECC1_CALC_
CIN ECC1_CIN_TBB[5:0]
00 0 00000
E2 OTP ECC CTRL2 R/W 8'b0000_0000
ECC2_EN_
TBB
ECC2_CALC_
CIN ECC2_CIN_TBB[5:0]
00 0 00000
E3 OTP ECC CTRL3 R/W 8'b0000_0000
ECC3_EN_
TBB
ECC3_CALC_
CIN ECC3_CIN_TBB[5:0]
00 0 00000
E4 OTP ECC CTRL4 R/W 8'b0000_0000
ECC4_EN_
TBB
ECC4_CALC_
CIN ECC4_CIN_TBB[5:0]
00 0 00000
E5 OTP ECC CTRL5 R/W 8'b0000_0000
ECC5_EN_
TBB
ECC5_CALC_
CIN ECC5_CIN_TBB[5:0]
00 0 00000
E6 OTP ECC CTRL6 R/W 8'b0000_0000
ECC6_EN_
TBB
ECC6_CALC_
CIN ECC6_CIN_TBB[5:0]
00 0 00000
E7 OTP ECC CTRL7 R/W 8'b0000_0000
ECC7_EN_
TBB
ECC7_CALC_
CIN ECC7_CIN_TBB[5:0]
00 0 00000
E8 OTP ECC CTRL8 R/W 8'b0000_0000
ECC8_EN_
TBB
ECC8_CALC_
CIN ECC8_CIN_TBB[5:0]
00 0 00000
Table 137. Extended page 2 (continued)
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
112 NXP Semiconductors
PF0100Z
FUNCTIONAL BLOCK REQUIREMENTS AND BEHAVIORS
E9 OTP ECC CTRL9 R/W 8'b0000_0000
ECC9_EN_
TBB
ECC9_CALC_
CIN ECC9_CIN_TBB[5:0]
00 0 00000
EA OTP ECC CTRL10 R/W 8'b0000_0000
ECC10_EN_T
BB
ECC10_CALC
_CIN ECC10_CIN_TBB[5:0]
00 0 00000
F1 OTP FUSE CTRL1 R/W 8'b0000_0000
–– – –
ANTIFUSE1_E
N
ANTIFUSE1_L
OAD
ANTIFUSE1_R
WBYPASS1
00 0 00 0 00
F2 OTP FUSE CTRL2 R/W 8'b0000_0000
–– – –
ANTIFUSE2_E
N
ANTIFUSE2_L
OAD
ANTIFUSE2_R
WBYPASS2
00 0 00 0 00
F3 OTP FUSE CTRL3 R/W 8'b0000_0000
–– – –
ANTIFUSE3_E
N
ANTIFUSE3_L
OAD
ANTIFUSE3_R
WBYPASS3
00 0 00 0 00
F4 OTP FUSE CTRL4 R/W 8'b0000_0000
–– – –
ANTIFUSE4_E
N
ANTIFUSE4_L
OAD
ANTIFUSE4_R
WBYPASS4
00 0 00 0 00
F5 OTP FUSE CTRL5 R/W 8'b0000_0000
–– – –
ANTIFUSE5_E
N
ANTIFUSE5_L
OAD
ANTIFUSE5_R
WBYPASS5
00 0 00 0 00
F6 OTP FUSE CTRL6 R/W 8'b0000_0000
–– – –
ANTIFUSE6_E
N
ANTIFUSE6_L
OAD
ANTIFUSE6_R
WBYPASS6
00 0 00 0 00
F7 OTP FUSE CTRL7 R/W 8'b0000_0000
–– – –
ANTIFUSE7_E
N
ANTIFUSE7_L
OAD
ANTIFUSE7_R
WBYPASS7
00 0 00 0 00
F8 OTP FUSE CTRL8 R/W 8'b0000_0000
–– – –
ANTIFUSE8_E
N
ANTIFUSE8_L
OAD
ANTIFUSE8_R
WBYPASS8
00 0 00 0 00
F9 OTP FUSE CTRL9 R/W 8'b0000_0000
–– – –
ANTIFUSE9_E
N
ANTIFUSE99_
LOAD
ANTIFUSE9_R
WBYPASS9
00 0 00 0 00
FA OTP FUSE CTRL10 R/W 8'b0000_0000
–– – –
ANTIFUSE10_
EN
ANTIFUSE10_
LOAD
ANTIFUSE10_
RW BYPASS10
00 0 00000
Notes
81. Do not write in reserved registers.
Table 137. Extended page 2 (continued)
Address Register Name TYPE Default
BITS[7:0]
7 6 5 4 3 2 1 0
NXP Semiconductors 113
PF0100Z
TYPICAL APPLICATIONS
7 Typical applications
7.1 Introduction
Figure 29 provides a typical application diagram of the PF0100Z PMIC together with its functional components. For details on component
references and additional components such as filters, refer to the individual sections.
7.1.1 Application diagram
Figure 29. Typical application schematic
VIN
INTB
LICELL
SWBSTFB
SWBSTIN
SWBSTLX
O/P
Drive
SWBST
600 mA
Boost
PWRON
STANDBY
ICTEST
Output Pin
Input Pin
Bi-directional Pin
Package Pin Legend
SCL
SDA
VDDIO SW3A/B
Single/Dual
DDR
2500 mA
Buck
VCOREDIG
VCOREREF
SDWNB
GNDREF
100nF
Coin Cell
Battery
1uF
220nF
Vin
2 x 22uF
SWBST
Output
2.2uH 10uF
Vin
To/From
AP
SW1CFB
SW1AIN
SW1C
2000 mA
Buck
SW1FB
SW1ALX
SW1BLX
SW1A/B
Single/Dual
2500 mA
Buck
SW1VSSSNS
1.0uH
4 x22uF
SW1AB Output
Vin 4.7uF
VSNVS
VSNVS
0.47uF
Li Cell
Charger
RESETBMCU
SW2
2000 mA
Buck
VGEN1
100mA
VGEN1
VIN1
2.2uF
VGEN2
250mA
VGEN2
4.7uF
VGEN3
100mA
VGEN3
VIN2
2.2uF
VGEN4
350mA
VGEN4
4.7uF
VGEN5
100mA
VGEN5
VIN3
2.2uF
VGEN6
200mA
VGEN6
2.2uF
Best
of
Supply
OTP
100k
SW4
1000 mA
Buck
VREFDDR
1uF
VDDOTP
VINREFDDR
VHALF
100nF
100nF
VCORE
100k
100k
4.7k
PF0100
CONTROL
Clocks
32kHz and 16MHz
Initialization State Machine
I2C
Interface
Clocks and
resets
I2C
Register
map
Trim-In-Package
4.7k
1uF
O/P
Drive
O/P
Drive
Vin
SW1BIN
4.7uF
SW1CLX
O/P
Drive SW1CIN
4.7uF
1.0uH
SW1C Output
2 x 22uF
Vin
SW2FB
SW2LX
O/P
Drive
SW2IN
4.7uF
1.0uH
SW2 Output
2 x 22uF
Vin
SW2IN
SW3AIN
SW3AFB
SW3ALX
SW3BLX
1.0uH 2 x 22uF
SW3A Output
Vin 4.7uF
O/P
Drive
O/P
Drive SW3BIN
4.7uF
Vin
SW3B Output
SW3BFB
2 x 22uF
1.0uH
SW3VSSSNS
SW4IN
SW4FB
SW4LX 1.0uH 2 x 22uF
SW4 Output
Vin 4.7uF
O/P
Drive
Supplies
Control
DVS Control
DVS CONTROL
Reference
Generation
VSW3A
Vin
Core Control logic
VIN1
VIN2
VIN3
VDDOTP
VSW2
VSW2VSW2
1.0uF
1.0uF
1.0uF
GNDREF1
2.2uF
1uF
100k
VSW2
VDDIO
To
MCU
0.1uF
114 NXP Semiconductors
PF0100Z
TYPICAL APPLICATIONS
7.1.2 Bill of materials
The following table provides a complete list of the recommended components on a full featured system using the PF0100Z Device. Critical
components such as inductors, transistors, and diodes are provided with a recommended part number, but equivalent components may
be used.
Table 138. Bill of materials (82)
Value Qty Description Part# Manufacturer Component/pin
PMIC
1 Power management IC MMPF0100Z NXP
Buck, SW1AB - (0.300-1.875 V), 2.5 A
1.0 μH1
4 x 4 x 2.1
ISAT = 4.5 A for 10% drop, DCRMAX = 11.9 mΩXFL4020-102MEB Coilcraft Output inductor
1.0 μH–
5 x 5 x 1.5
ISAT = 3.6 A for 10% drop, DCRMAX = 50 mΩLPS5015_102ML Coilcraft Output inductor
optional
1.0 μH–
2.5 x 2.0 x 1.2
ISAT = 4.5 A
DCRMAX = 42 mΩ
DFE252012PD-1R0M TOKO Output inductor
(optional)
22 μF 4 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
4.7 μF 2 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden SW1AIN, SW1BIN
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
Buck, SW1C- (0.300-1.875 V), 2.0 A
1.0 μH1
4 x 4 x 1.2
ISAT = 2.8 A for 10% drop, DCRMAX = 60 mΩLPS4012-102NL Coilcraft Output inductor
1.0 μH–
3 x 3 x1.2
ISAT = 2.5 A for 10% drop, DCRMAX = 42 mΩXFL3012-102ML Coilcraft Output inductor
optional
1.0 μH–
2.5 x 2.0 x 1.2
ISAT = 4.5 A
DCRMAX = 42 mΩ
DFE252012PD-1R0M TOKO Output inductor
(optional)
22 μF 2 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
4.7 μF 1 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
Buck, SW1ABC - (0.300-1.875 V), 4.5 A
1.0 μH1
4.2 x 4.2 x 2
ISAT = 5.1 A for 10% drop, DCRMAX = 29 mΩFDSD0420D-1R0M TOKO Inc. Output inductor
22 μF 6 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
4.7 μF 2 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
NXP Semiconductors 115
PF0100Z
TYPICAL APPLICATIONS
Buck, SW2 - (0.400-3.300 V), 2.0 A
1.0 μH1
4 x 4 x 1.2
ISAT = 2.8 A for 10% drop, DCRMAX = 60 mΩLPS4012-102NL Coilcraft Output inductor
1.0 μH–
3x 3 x 1.2
ISAT = 2.5 A for 10% drop, DCRMAX = 42 mΩXFL3012-102ML Coilcraft Output inductor
optional
1.0 μH–
2.5 x 2.0 x 1.2
ISAT = 4.5 A
DCRMAX = 42 mΩ
DFE252012PD-1R0M TOKO Output inductor
(optional)
22 μF 2 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
4.7 μF 1 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
Buck, SW3AB - (0.400-3.300 V), 2.5 A
1.0 μH1
4 x 4 x 2.1
ISAT = 4.5 A for 10% drop, DCRMAX = 11.9 mΩXFL4020-102MEB Coilcraft Output inductor
1.0 μH–
5 x 5 x 1.5
ISAT = 3.6 A for 10% drop, DCRMAX = 50 mΩLPS5015_102ML Coilcraft Output inductor
optional
1.0 μH–
2.5 x 2.0 x 1.2
ISAT = 4.5 A
DCRMAX = 42 mΩ
DFE252012PD-1R0M TOKO Output inductor
(optional)
22 μF 4 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
4.7 μF 2 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden SW3AIN, SW3BIN
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
Buck, SW4 - (0.400-3.300V), 1A
1.0 μH1
2.5 x 2 x 1
ISAT = 1.8 A for 30% drop, DCRMAX = 84 mΩVLS252010ET-1R0N TDK Output inductor
1.0 μH–
2.5 x 2.0 x 1.2
ISAT = 4.5 A
DCRMAX = 42 mΩ
DFE252012PD-1R0M TOKO Output inductor
(optional)
1.0 μH-
2.2 x 2.1 x 1
ISAT = 1.2 A for 10% drop, DCRMAX = 89 mΩXPL2010_102ML Coilcraft Output inductor
optional
22 μF 2 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
4.7 μF 1 10 V X5R 0603 LMK107BJ475KA-T Taiyo Yuden Input capacitance
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
Table 138. Bill of materials (82) (continued)
Value Qty Description Part# Manufacturer Component/pin
116 NXP Semiconductors
PF0100Z
TYPICAL APPLICATIONS
BOOST, SWBST - 5.0 V, 600 mA
2.2 μH–
3 x 3 x 1.5
ISAT = 2.0 A for 10% drop, DCRMAX = 110 mΩLPS3015-222ML Coilcraft Output Inductor
2.2 μH–
2.5 x 2.0 x 1.2
ISAT = 3.3 A
DCRMAX = 84 mΩ
DFE252012PD-2R2M TOKO Output inductor
(optional)
22 μF 2 10 V X5R 0805 LMK212BJ226MG-T Taiyo Yuden Output capacitance
10 μF 1 10 V X5R 0805 C2012X5R1A106MT TDK Input capacitance
2.2 μF 1 6.3 V X5R 0402 C0402C225M9PACTU Kemet Input capacitance
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet Input capacitance
1.0 A 1 20 V SOD-123FL MBR120VLSFT1G ON Semiconductor Schottky diode
LDO, VGEN1 - (0.80-1.55), 100 mA
2.2 μF 1 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America Input capacitance
LDO, VGEN2 - (0.80-1.55), 250 mA
4.7 μF 1 6.3 V X5R 0402 C0402X5R6R3-475MNP Venkel Output capacitance
LDO, VGEN3 - (1.80-3.30), 100 mA
2.2 μF 1 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America Input capacitance
LDO, VGEN4 - (1.80-3.30), 350 mA
4.7 μF 1 6.3 V X5R 0402 C0402X5R6R3-475MNP Venkel Output capacitance
LDO, VGEN5 - (1.80-3.30), 150 mA
2.2 μF 1 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America Input capacitance
LDO, VGEN6 - (1.80-3.30), 200 mA
2.2 μF 1 6.3 V X5R 0402 C0402C225M9PACTU Kemet Output capacitance
LDO/Switch VSNVS - (1.1-3.3), 200 mA
0.47 μF 1 6.3 V X5R 0402 C1005X5R0J474K TDK Output capacitance
Reference, VREFDDR - (0.20-1.65V), 10 mA
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America Output capacitance
0.1 μF 2 10 V X5R 0402 C0402C104K8PAC Kemet VHALF,
VINREFDDR
Internal references, VCOREDIG, VCOREREF, VCORE
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VCOREDIG
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VCORE
0.22 μF 1 10 V X5R 0402 GRM155R61A224KE19D Murata VCOREREF
Coin cell
0.1 μF 1 10 V X5R 0402 C0402C104K8PAC Kemet LICELL
Table 138. Bill of materials (82) (continued)
Value Qty Description Part# Manufacturer Component/pin
NXP Semiconductors 117
PF0100Z
TYPICAL APPLICATIONS
7.2 PF0100Z layout guidelines
7.2.1 General board recommendations
1. It is recommended to use an eight layer board stack-up arranged as follows:
• High current signal
•GND
• Signal
•Power
•Power
• Signal
•GND
• High current signal
2. Allocate TOP and BOTTOM PCB Layers for POWER ROUTING (high current signals), copper-pour the unused area.
3. Use internal layers sandwiched between two GND planes for the SIGNAL routing.
7.2.2 Component placement
It is desirable to keep all component related to the power stage as close to the PMIC as possible, specially decoupling input and output
capacitors.
7.2.3 General routing requirements
1. Some recommended things to keep in mind for manufacturability:
• Via in pads require a 4.5 mil minimum annular ring. Pad must be 9.0 mils larger than the hole
• Maximum copper thickness for lines less than 5.0 mils wide is 0.6 oz copper
• Minimum allowed spacing between line and hole pad is 3.5 mils
• Minimum allowed spacing between line and line is 3.0 mils
2. Care must be taken with SWxFB pins traces. These signals are susceptible to noise and must be routed far away from power,
clock, or high power signals, like the ones on the SWxIN, SWx, SWxLX, SWBSTIN, SWBST, and SWBSTLX pins. They could be
also shielded.
3. Shield feedback traces of the regulators and keep them as short as possible (trace them on the bottom so the ground and power
planes shield these traces).
4. Avoid coupling traces between important signal/low noise supplies (like REFCORE, VCORE, VCOREDIG) from any switching node
(i.e. SW1ALX, SW1BLX, SW1CLX, SW2LX, SW3ALX, SW3BLX, SW4LX, and SWBSTLX).
5. Make sure all components related to a specific block are referenced to the corresponding ground.
Miscellaneous
0.1 μF 1 10 V X5R 0402 CD402C104K8PAC Kemet VDDIO
1.0 μF 1 10 V X5R 0402 CC0402KRX5R6BB105 Yageo America VIN
100 kΩ1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER PWRON
100 kΩ1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER RESETBMCU
100 kΩ1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER SDWN
100 kΩ1 1/16 W 0402 RK73H1ETTP1003F KOA SPEER INTB
Notes
82. NXP does not assume liability, endorse, or warrant components from external manufacturers referenced in circuit drawings or tables. While NXP
offers component recommendations in this configuration, it is the customer’s responsibility to validate their application.
Table 138. Bill of materials (82) (continued)
Value Qty Description Part# Manufacturer Component/pin
118 NXP Semiconductors
PF0100Z
TYPICAL APPLICATIONS
7.2.4 Parallel routing requirements
1. I2C signal routing
• CLK is the fastest signal of the system, so it must be given special care.
• To avoid contamination of these delicate signals by nearby high power or high frequency signals, it is a good practice to
shield them with ground planes placed on adjacent layers. Make sure the ground plane is uniform throughout the whole
signal trace length.
Figure 30. Recommended shielding for critical signals.
• These signals can be placed on an outer layer of the board to reduce their capacitance with respect to the ground plane.
• Care must be taken with these signals not to contaminate analog signals, as they are high frequency signals. Another good
practice is to trace them perpendicularly on different layers, so there is a minimum area of proximity between signals.
7.2.5 Switching regulator layout recommendations
1. Per design, the switching regulators in PF0100Z are designed to operate with only one input bulk capacitor. However, it is
recommended to add a high-frequency filter input capacitor (CIN_hf), to filter out any noise at the regulator input. This capacitor
should be in the range of 100 nF and should be placed right next to or under the IC, closest to the IC pins.
2. Make high-current ripple traces low-inductance (short, high W/L ratio).
3. Make high-current traces wide or copper islands.
4. Make high-current traces symetrical for dual–phase regulators (SW1, SW3).
NXP Semiconductors 119
PF0100Z
TYPICAL APPLICATIONS
Figure 31. Generic buck regulator architecture
Figure 32. Recommended layout for buck regulators
7.3 Thermal information
7.3.1 Rating data
The thermal rating data of the packages has been simulated with the results listed in Table 5.
Junction to ambient thermal resistance nomenclature: the JEDEC specification reserves the symbol RθJA or θJA (Theta-JA) strictly for
junction-to-ambient thermal resistance on a 1s test board in natural convection environment. RθJMA or θJMA (Theta-JMA) is used for both
junction-to-ambient on a 2s2p test board in natural convection and for junction-to-ambient with forced convection on both 1s and 2s2p
test boards. It is anticipated the generic name, Theta-JA, continues to be commonly used.
The JEDEC standards can be consulted at http://www.jedec.org.
Diver Controller
SWxIN
SWxLX
SWxFB
COUT
CIN
L
SWx
VIN
Compensation
CIN_HF
SWxIN
Inductor
CIN
C
OUT
CIN_HF
SWxLX
GND
SWxFB
120 NXP Semiconductors
PF0100Z
TYPICAL APPLICATIONS
7.3.2 Estimation of junction temperature
An estimation of the chip junction temperature TJ can be obtained from the equation:
TJ = TA + (RθJA x PD)
with:
TA = Ambient temperature for the package in °C
RθJA = Junction to ambient thermal resistance in °C/W
PD = Power dissipation in the package in W
The junction to ambient thermal resistance is an industry standard value provideing a quick and easy estimation of thermal performance.
Unfortunately, there are two values in common usage: the value determined on a single layer board RθJA and the value obtained on a four
layer board RθJMA. Actual application PCBs show a performance close to the simulated four layer board value although this may be
somewhat degraded in case of significant power dissipated by other components placed close to the device.
At a known board temperature, the junction temperature TJ is estimated using the following equation
TJ = TB + (RθJB x PD) with
TB = Board temperature at the package perimeter in °C
RθJB = Junction to board thermal resistance in °C/W
PD = Power dissipation in the package in W
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction temperature can be made.
See 6 Functional block requirements and behaviors, page 17 for more details on thermal management.
NXP Semiconductors 121
PF0100Z
PACKAGING
8 Packaging
8.1 Packaging dimensions
Package dimensions are provided in package drawings. To find the most current package outline drawing, go to www.nxp.com and
perform a keyword search for the drawing’s document number. See the 4.2 Thermal characteristics, page 10 for specific thermal
characteristics for each package.
Table 139. Package drawing information
Package Suffix Package outline drawing number
56 QFN 8x8 mm - 0.5 mm pitch. WF-Type (wettable flank) ES 98ASA00589D
122 NXP Semiconductors
PF0100Z
PACKAGING
NXP Semiconductors 123
PF0100Z
PACKAGING
124 NXP Semiconductors
PF0100Z
PACKAGING
126 NXP Semiconductors
PF0100Z
REVISION HISTORY
10 Revision history
10.1 Document changes
Revision Date Description of Changes
1.0 11/2012 • Initial release
2.0 1/2013
• Deleted unneeded rows from Ordering information and updated part number
• Changed Note 2
• Added Note 4 to Pin Definitions and assigned it to the applicable pin names
• Corrected Functional Block diagram
• Corrected pin name in section 7.1
• Deleted unnecessary columns in Table 9
• Added section 7.2.1 and fixed TOC
• Corrected FF row in Table 136
• Corrected schematics 10, 11, 12, 14, 16, 17, 18, 20, and 22
• Corrected page one package isometric
• Added warning to note 6
• Changed graphics on figures 13, 15, 19, and 21
• Deleted original note 64.
• Deleted reference to ICOINLO in Coin Cell Charger Control
• Updated figure 28
• Corrected part number in BOM
• Corrected #4 in General Routing Requirements
• Added AN4622 to Reference Documents
3.0 2/2013
• Separated VSNS pin for HBM page 9
• Reworded sentence in Programming OTP fuses
• Added 2.0 MHz clock frequency
• Changed min. for VREFDDR Current Limit
• Changed min. for VGEN1 DC Current Limit
• Changed min. for VGEN1 DC Overcurrent Protection Threshold
• Changed max. for VGEN2 ACTIVE MODE - DC Current Limit
• Changed min. for VGEN3 DC Current Limit
• Changed min. for VGEN4 DC Current Limit
• Changed min. for VGEN5 ACTIVE MODE - DC Current Limit
• Changed min. for VGEN6 DC Current Limit
• Changed min. for VGEN6 DC Overcurrent Protection Threshold
• Changed max. for VSNVS DC, LDO VIN Threshold, VIN going high with valid coin cell
• Changed max. for VSNVS DC, LDO VIN Threshold, VIN going low with valid coin cell
• Added note to VSNVS AC AND TRANSIENT Turn-on Time, and deleted notation of conditions
• Register D8 and D9 in table 137 marked as reserved.
• Added Figure 4
• Updated table 8. Current consumption summary.
NXP Semiconductors 127
PF0100Z
REVISION HISTORY
4.0 4/2014
• Added new package name and drawing for PF0100AZ
• Added Table 2 listing differences between PF0100Z and PF0100AZ
• Corrected VDDOTP maximum rating
• Corrected SWBSTFB maximum rating
• Updated Table 8 to included PF0100AZ specifications
• Updated Figure 4
• Added note of FUSE_POR-XOR bit for PF0100AZ in OTP prototyping
• Corrected 2.0 MHz clock minimum specification from 1.85 MHz to 1.84 MHz in 16 MHz and 32 kHz
clocks
• Corrected inductor Isat for SW1ABC single phase mode from 4.5 A to 6.0 A
• Tightened accuracy specification in PFM mode for all the switching regulators
• Corrected typical efficiency specifications for all switching regulators
• Added note to clarify SWBST default operation in Auto mode
• Added current limit specifications for VGEN2, VGEN6, and VSNVS for PF0100AZ
• Corrected conditions for VSNVS turn-on time specifications
• Changed VTH1 maximum specification from 3.05 V to 3.1 V
• Updated Control interface I2C block description to include note about SCL/SDA drive strength
• Corrected default values of bits in INTMASK0 register in Table 118
• Corrected default value of 4 MSBs in Table 128
• Corrected default value of bits in SILICONREVID register in Table 126
• Updated Typical Application Schematic to add bypass capacitor on VDDIO pin
• Added capacitor at VDDIO pin in Bill of Material table
• Noted that voltage settings 0.6 V and below are not supported
• VSNVS Turn On Delay (td1) spec corrected from 15 ms to 5.0 ms
• Updated per GPCN 16220
5.0 10/2014
• Updated as per PB 16482
• Increased ambient operating temperature of MMPF0100NPAZES device
• Added additional specification line items for Standby current, Sleep current, and VREFDDR accuracy
for the extended temperature operation
• Added new part number MMPF0100F8AZES
• Updated Table 9
6.0 11/2014
• Corrected the temperature range for the device MMPF0100F8AZES in Table 1
• Updated Table 23
• Updated Bill of Materials Table 138
7.0 7/2015 • Added new part numbers MMPF0100F9AZES and MMPF0100FAAZES to Table 1
• Updated Table 9
8.0 10/2015
• Added MMPF0100F0AZES to Table 1
• Updated Table 9
• Updated Table 52
• Updated Table 137
10/2015 • Fixed typo on page 1
9.0 12/2015
• Removed MMPF0100NPZES from Orderable part variations. No longer manufactured.
• Added MMPF0100F6AZES to Orderable part variations
• Updated Table 9 for MMPF0100F6AZES
10.0 3/2016 • Updated SW2 current capability from 2000 mA to 2500 mA for F9/FA versions
11.0 5/2016 • Changed Table 9 row - Default I2C Address from 0x80 to 0x08 for F0, F9, and FA
12.0 8/2016 • Added NP version to OTP's with SW2 current capability of 2500 mA
• Added BOM for SW1ABC
Revision Date Description of Changes
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Document Number: MMPF0100Z
Rev. 12.0
8/2016
