TECHNICAL NOTE HIGH GRADE Specification HIGH RELIABILITY series Microwire BUS Serial EEPROMs Supply voltage 2.7V~5.5V Operating temperature -40C~+125C type BR93H56-W, BR93H66-W, BR93H76-W, BR93H86-W Description BR93H -W series is a serial EEPROM of serial 3-line interface method. Features . Withstands electrostatic voltage 8kV, (twice more than other series) (HBM method typ.) . Wide action range -40 C ~ +125 C (-40C ~ +85C, -40C ~ +105C in other series) * Conforming to Microwire BUS . Highly reliable connection by Au pad and Au wire * Address auto increment function at read action * Write mistake prevention function Write prohibition at power on Write prohibition by command code Write mistake prevention circuit at low voltage . Program cycle auto delete and auto end function . Program condition display by READY / BUSY . Low current consumption At write action (5V) : 0.6mA (Typ.) At read action (5V) : 0.6mA (Typ.) At standby action (5V) : 0.1A (Typ.) . Built-in noise filter CS, SK, DI terminals . Compact package SOP8, SOP-J8 . High reliability by ROHM original Double-Cell structure . High reliability ultrafine CMOS process . Data rewrite up to 1,000,000 times . Data kept for 40 years* Easily connectable with serial port BR93H series . Data at shipment all addresses FFFFh Capacity Bit format Type Power source voltage SOP8 2Kbit 128 x 16 BR93H56-W 2.7V ~ 5.5V 4Kbit 256 x 16 BR93H66-W 2.7V ~ 5.5V 8Kbit 512 x 16 BR93H76-W 2.7V ~ 5.5V 16Kbit 1K x 16 BR93H86-W 2.7V ~ 5.5V F Package type RF SOP-J8 FJ RFJ SSOP-B8 FV RFV TSSOP-B8 FVT RFVT MSOP8 TSSOP-B8J RFVM RFVJ Ver.B Oct. 2005 Absolute Maximum Ratings (Ta=25C) Parameter Impressed voltage Symbol Limits Unit VCC -0.3 ~ +6.5 V Pd Permissible dissipation Storage temperature range Action temperature range Terminal voltage SOP8 (RF) 450 (*1) SOP-J8 (RFJ) 450 (*2) Parameter Symbol Limits Unit Power source voltage VCC 2.7 ~ 5.5 V Input voltage VIN 0 ~ VCC V mW -65 ~ +150 C Topr -40 ~ +125 C - -0.3 ~ VCC+0.3 V Tstg Recommended operating conditions * When using at Ta = 25C or higher, 3.6mW (*1, *2) to be reduced per 1C. Electrical characteristics (Unless otherwise specified, Ta = -40 ~ +125C, Vcc = 2.7V ~ 5.5V) Item Limits Symbol Min. Typ. Unit Conditions Max. 0.3x Vcc Vcc +0.3 Measurement circuit "L" input voltage VIL -0.3 - "H" input voltage VIH 0.7x Vcc - "L" output voltage 1 VOL1 0 - 0.4 V IOL=2.1mA,4.0 Vcc 5.5V Fig. 4 "L" output voltage 2 VOL2 0 - 0.2 V IOL=100A Fig. 4 "H" output voltage 1 VOH1 2.4 - Vcc V IOH=-0.4mA,4.0 Vcc 5.5V Fig. 5 "H" output voltage 2 VOH2 Vcc -0.2 - Vcc V IOH=-100A Fig. 5 Input leak current ILI -10 - 10 A VIN=0 ~ Vcc Fig. 6 Output leak current ILO -10 - 10 A VOUT=0 ~ Vcc,CS=0V Fig. 7 ICC1 - - 3.0 mA fSK=1.25MHz,tE/W=10ms (WRITE) Fig. 8 ICC2 - - 1.5 mA fSK=1.25MHz (READ) Fig. 8 ICC3 - - 4.5 mA fSK=1.25MHz,tE/W=10ms (WRAL) Fig. 8 ISB - 0.1 10 A CS=0V,DO=OPEN Fig. 9 Current consumption at operation Standby current V V This IC is not designed to be radiation-resistant. 2/16 Operation timing characteristics (Ta=-40C ~ +125C, Vcc=2.7V ~ 5.5V) Item Symbol Min. Typ. Max. Unit fSK - - 1.25 MHz SK "H" time tSKH 250 - - ns SK "L" time tSKL 250 - - ns CS "L" time tCS 200 - - ns CS setup time tCSS 200 - - ns DI setup time tDIS 100 - - ns CS hold time tCSH 0 - - ns DI hold time tDIH 100 - - ns Data "1" output delay time tPD1 - - 300 ns Data "0" output delay time tPD0 - - 300 ns Time from CS to output establishment tSV - - 200 ns Time from CS to High-Z tDF - - 200 ns Write cycle time tE/W - 7 10 ms SK frequency Memory cell characteristics (Vcc=2.7V ~ 5.5V) Limits Number of data rewrite times *1 Unit Conditions - Times Ta 85C - - Times Ta 105C 300,000 - - Times Ta 125C 40 - - Years Ta 25C 10 - - Years Ta 50C Min. Typ. Max. 1,000,000 - 500,000 Data hold years *1 * 1 NOT 100%TESTED Sync data input / output timing CS tCSS tSKH tSKL tCSH SK tDIS tDIH DI tPD0 tPD1 DO (READ) tDF DO (WRITE) STATUS VALID Fig.1 Sync data input / output timing diagram Data is taken by DI in sync with the rise of SK. At read action, data is output from DO in sync with the rise of SK. The status signal at write (READY / BUSY) is output after tCS from the fall of CS after write command input. This is at the DO area where CS is "H", and valid until the next command start bit is input. While CS is "L", DO becomes High-Z. After each mode execution is competed, set CS to "L" once for internal circuit reset, and execute the following action mode. 3/16 Characteristic data 4.5 4 4 3.5 SPEC 3 2.5 Ta=125C 2 Ta=25C 1.5 1 Ta=-40C 0.5 1 L OUTPUT VOLTAGE : VOL (V) 4.5 L INPUT VOLTAGE : VIL (V) H INPUT VOLTAGE : VIH (V) The following characteristic data are Typ. values. 3.5 3 2.5 Ta=125C 2 Ta=25C 1.5 1 SPEC Ta=-40C 0.5 0.8 0.6 Ta=125C 0.4 Ta=25C SPEC 0.2 Ta=-40C 0 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 0 6 Fig.2 H input voltage VIH (CS,SK,DI) 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 0 6 Fig.3 L input voltage VIL (CS,SK,DI) 1 0 1 2 3 4 L OUTPUT CURRENT : IOL (mA) 5 Fig.4 L output voltage VOL-IOL (VCC=2.7V) 5 5 0.6 Ta=125C SPEC 0.4 Ta=25C 0.2 Ta=-40C 0 1 2 3 4 L OUTPUT CURRENT : IOL (mA) Ta=125C 1 0 0.4 0.8 1.2 H OUTPUT CURRENT : IOH (mA) 8 6 4 Ta=125C 2 2 Ta=25C Ta=-40C 3 4 5 SUPPLY VOLTAGE : VCC (V) 10 8 6 4 Ta=125C Ta=25C 2 Ta=-40C 2 3 4 5 SUPPLY VOLTAGE : VCC (V) CURRENT CONSUMPTION AT OPERATING : ICC3 (WRAL) (mA) Ta=125C Ta=25C 0.4 Ta=-40C 02 3 4 5 SUPPLY VOLTAGE : VCC (V) 0 3.5 3 2.5 2 Ta=-40C 1.5 Ta=125C 1 Ta=25C SPEC 3 2.5 2 Ta=-40C 1.5 1 Ta=125C Ta=25C 0.5 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 8 6 4 Ta=25C Ta=125C Ta=-40C 2 0 6 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 300 SPEC SPEC 250 8 6 4 250 L SK TIME : tSKL (ns) H SK TIME : tSKH (ns) Ta=25C Ta=125C 200 150 Ta=125C 100 200 150 Ta=125C 100 Ta=25C Ta=25C SPEC 6 Fig.13 Consumption current at standby operation ISB 300 12 6 SPEC 10 0.5 Ta=-40C 10 1.6 12 4 0 6 14 2 0.4 0.8 1.2 H OUTPUT CURRENT : IOH (mA) SPEC 4.5 Fig.11 Consumption current at READ operation Fig.12 Consumption current at WRAL operation ICC2 (READ,fSK=1.25MHz) ICC3 (WRAL,fSK=1.25MHz) SK FREQUENCY : fSK (MHz) 1 Fig.10 Current consumption at WRITE operation ICC1 (WRITE,fSK=1.25MHz) 5 0.8 SPEC 0 6 Fig.9 Output leak current ILO (DO) 1.6 1.2 2 3.5 SPEC 0 6 SPEC Ta=125C 3 0 1.6 CURRENT CONSUMPTION AT WRITING : ICC1 (WRITE) (mA) 10 OUTPUT LEAK CURRENT : ILO (A) INPUT LEAK CURRENT : ILI (A) SPEC 12 SPEC Fig.8 Input leak current ILI (CS,SK,DI) CURRENT CONSUMPTION AT READING : ICC2 (READ) (mA) 2 Ta=25C 4 Fig.6 H output voltage VOH-IOH (VCC=2.7V) Fig.7 H output voltage VOH-IOH (VCC=4.0V) 12 0 Ta=25C Ta=-40C 3 0 5 Fig.5 L output voltage VOL-IOL (VCC=4.0V) 4 STAND BY CURRENT : ISB (A) 0 H OUTPUT VOLTAGE : VOH (V) 0.8 H OUTPUT VOLTAGE : VOH (V) L OUTPUT VOLTAGE : VOL (V) Ta=-40C 50 50 Ta=-40C 0 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.14 SK frequency fSK 6 0 Ta=-40C 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.15 SK high time tSKH 4/16 6 0 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.16 SK low time tSKL 6 300 150 Ta=125C Ta=25C 100 Ta=-40C 50 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 200 Ta=125C 150 Ta=25C 100 Ta=-40C 50 0 6 2 40 Ta=125C 0 -50 -100 -150 -200 -250 -300 Ta=25C -350 Ta=125C -400 Ta=-40C Ta=-40C -450 6 2 300 250 200 Ta=125C Ta=25C 100 50 Ta=-40C 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 6 Fig.23 Data "0" output delay time tPD0 WRITE CYCLE TIME : tE/W (ms) 2 3 4 5 SUPPLY VOLTAGE : VCC (V) SPEC 300 250 200 Ta=125C 150 100 Ta=25C Ta=-40C 50 0 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 6 SPEC 150 Ta=125C 100 Ta=25C 50 Ta=-40C 0 6 350 SPEC 200 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 6 Fig.24 Time from CS to output establishment tSV SPEC Ta=125C Ta=25C 6 Ta=-40C 4 2 3 4 5 SUPPLY VOLTAGE : VCC (V) Ta=-40C 250 10 2 Ta=25C Fig.22 Data "1" output delay time tPD1 250 12 8 6 TIME BETWEEN CS AND OUTPUT HIGH-Z : tDF (ns) SPEC 150 3 4 5 SUPPLY VOLTAGE : VCC (V) Fig.21 CS hold time tCSH TIME BETWEEN CS AND OUTPUT : tSV (ns) Fig.20 DI hold time tDIH 350 0 DATA "1" OUTPUT DELAY TIME : tPD1 (ns) CS HOLD TIME : tCSH (ns) DI HOLD TIME : tDIH (ns) 60 3 4 5 SUPPLY VOLTAGE : VCC (V) Ta=125C 40 Fig.19 DI setup time tDIS 0 80 2 60 0 6 SPEC SPEC Ta=25C 80 Fig.18 CS setup time tCSS 100 DATA "0" OUTPUT DELAY TIME : tPD0 (ns) 3 4 5 SUPPLY VOLTAGE : VCC (V) 50 20 100 20 Fig.17 CS low time tCS 120 0 DI SETUP TIME : tDIS (ns) CS SETUP TIME : tCSS (ns) CS LOW TIME : tcs (ns) SPEC 200 -20 SPEC SPEC 250 0 120 250 6 Fig.26 Write cycle time tE/W 5/16 200 150 Ta=125C 100 Ta=25C Ta=-40C 50 0 2 3 4 5 SUPPLY VOLTAGE : VCC (V) 6 Fig.25 Time from CS to High-Z tDF Block diagram Command decode CS Power source voltage detection Control Clock generation SK Write prohibition Command register DI DO High voltage occurrence Address buffer 7bit 8bit 9bit 10bit Address decoder 7bit 8bit 9bit 10bit Data register 16bit R/W amplifier 16bit 2,048bit 4,096bit 8,192bit 16,384bit EEPROM Dummy bit Fig.27 Block diagram Pin assignment and function NC TEST GND VCC TEST2 TEST1 GND BR93H56RF-W:SOP8 BR93H56RFJ-W:SOP-J8 BR93H66RF-W:SOP8 BR93H66RFJ-W:SOP-J8 BR93H76RF-W:SOP8 BR93H76RFJ-W:SOP-J8 BR93H86RF-W:SOP8 BR93H86RFJ-W:SOP-J8 CS CS VCC SK DI DO SK DI DO Fig.28 Pin assignment diagram Pin name Input / output Vcc - Power source GND - All input / output reference voltage, 0V CS Input Chip select input SK Input Serial clock input DI Input Start bit, ope code, address, and serial data input DO Output TEST - TEST terminal, GND or OPEN NC - Non connected terminal, Vcc, GND or OPEN TEST1 - TEST terminal, GND or OPEN TEST2 - TEST terminal, Vcc, GND or OPEN Function Serial data output, READY / BUSY internal condition display output 6/16 Command mode Data A9, A8, A7, A6, A5, A4, A3, A2, A1,A0 D15~D0 (READ DATA) 1 10 1 00 (*2) 1 01 (*2,3) 1 00 0 1 * * * * * B0 0 1 * * * * * B2, B1,B0 1 00 0 0 * * * * * 0 0 * * * * * * * * (*1) Write enable (WEN) Write (WRITE) Write disable (WDS) . Address BR93H76/86-W Ope code Read (READ) Write all (WRAL) Address BR93H56/66-W Start bit Command A7, A6, A5, A4, A3, A2, A1, A0, 1 1 * * * * * * 1 1 * * * * * * * * A7, A6, A5, A4, A3, A2, A1, A0, A9, A8, A7, A6, A5, A4, A3, A2, A1,A0 * Input the address and the data in MSB. . As for *, input either VIH or VIL. * Start bit Acceptance of all the commands of this IC starts at recognition of the start bit. The start bit refers to the first "1" input after the rise of CS. D15~D0 (WRITE DATA) D15~D0 (WRITE DATA) A7 - B0 of BR93H56-W becomes Don't Care. A9 - B2 of BR93H76-W becomes Don't Care. (*1) : For read, by continuous SK clock input after setting the read command, data output of the set address starts, and address data in significant order are continuously output in sequence. (Auto increment function) (*2) : When the read and the write all commands are executed, data written in the selected memory cell is automatically deleted, and input data is written. (*3) : For the write all command, data written in memory cell of the areas designated by B2, B1, and B0, are automatically deleted, and input data is written in bulk. Write all area B2 B1 B0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 . Write area 000h ~ 07Fh 080h ~ 0FFh 100h ~ 17Fh 180h ~ 1FFh 200h ~ 27Fh 280h ~ 2FFh 300h ~ 37Fh 380h ~ 3FFh Designation of B2, B1, and B0 H56 * H66 * H76 * H86 * * * B0 B1 B0 B2 B1 B0 The write all command is written in bulk in 2Kbit unit. The write area can be selected up to 3bit. Confirm the settings and write areas of the above B2, B1, and B0. Description of operations Communications of the Microwire Bus are carried out by SK (serial clock), DI (serial data input), DO (serial data output), and CS (chip select) for device selection.When connecting one EEPROM to a microcontroller, connect as shown in Fig. 29 (a) or Fig. 29 (b). When using the input and output common I/O port of the microcontroller, connect DI and DO via a resistor, as shown in Fig. 29 (b) (Refer to pages 13 and 14.). Connection by 3 lines is available.For plural connections, refer to Fig. 29 (c). CS CS CS CS SK SK SK SK DO DI DIO DI DI DO Fig.29(a) Connection by 4 lines CS SK DI DO Microcontroller Microcontroller DO CS SK DI DO Microcontroller CS3 CS1 CS0 SK DO DI BR93H CS SK DI DO BR93H Fig.29(b) Connection by 3 lines Fig29.(c) Connection example of plural devices Fig.29 Connection method with microcontroller Communications of the Microwire Bus are started by the first "1" input after the rise of CS. This input is called a start bit. After input of the start bit, input ope code, address, and data. Address and data are input all in MSB. "0" input after the rise of CS to the start bit input is all ignored. Therefore, when there is limitation in the PIO bit width of the microcontroller, input "0" before the start bit input, to control the bit width. 7/16 Timing chart 1) Read cycle (READ) CS *1 SK 1 2 DI 1 1 4 n Am 0 n+1 BR93H56/66-W : n=27, m=7 BR93H76/86-W : n=29, m=9 A0 A1 * ( 2) DO 0 D15 D14 D1 D0 (*2) The following address data output (auto increment function) D15 D14 High-Z *1 Start bit When data "1" is input for the first time after the rise of CS, this is recognized as a start bit. And when "1" is input after plural "0" are input, it is recognized as a start bit, and the following operation is started. This is common to all the commands to described hereafter. Fig.30 Read cycle When the read command is acknowledged, the data (16 bits) for the input address is output serially. The data is synchronized with the SK rise during A0 acquisition and a i0i (dummy bit) is output. All further data is output in synchronization with the SK pulse rises. This IC has an address auto increment function, active only at read command. In this function the above address data is read sequentially by continuously inputting SK clock. During the auto increment, keep CS at "H". 2) Write cycle (WRITE) CS tCS 1 SK DI 1 2 0 4 1 Am STATUS BR93H56/66-W : n=27,m=7 BR93H76/86-W : n=29,m=9 n A1 A0 D15 D14 D1 D0 tSV BUSY READY DO High-Z tE/W In this command, input 16bit data (D15 ~ D0) are written to designated addresses (Am ~ A0). The actual write starts by the fall of CS from the rise of D0 taken SK clock (n-th clock from the start bit input), to the rise of the (n+1)-th clock. When STATUS is not detected, (CS = "L" fixed) Max. 10ms in conformity with tE/W, and when STATUS is detected (CS = "H"), all commands are not accepted for areas where "L" (BUSY) is output from D0, therefore, do not input any command. Write is not made even if CS is started after input of clock after (n+1)-th clocks. Note ) Take tSKH or more from the rise of the n-th clock to the fall of CS. Fig.31 Write cycle 8/16 3) Write all cycle (WRAL) tCS CS 1 SK 1 DI 2 0 5 0 m 1 0 STATUS BR93H56/66-W : n=27,m=9 BR93H76/86-W : n=29,m=11 n B2 B1 B0 D15 D1 D0 tSV DO BUSY READY High-Z tE/W Fig.32 Write all cycle In this command, input 16bit data is written simultaneously to designated block for 128 words. Data is writen in bulk at a write time of only Max. 10ms in conformity with tE/W. When writing data to all addresses, designate each block by B2, B1, and B0, and execute write. Write time is Max. 10ms. The actual write starts by the fall of CS from the rise of D0 taken at SK clock (n-th clock from the start bit input), to the rise of the (n+1)-th clock. When CS is ended after clock input after the rise of the (n+1)-th clock, command is cancelled, and write is not completed.Note: Take tSKH or more from the rise of the n-th clock to the fall of CS. Designation of B2, B1, and B0 H56 * * * H66 * * B0 H76 * H86 B1 B0 B2 B1 B0 4) Write enable (WEN) / disable (WDS) cycle CS SK 1 2 3 4 5 6 7 8 n ENABLE = 1 1 DISABLE= 0 0 DI 1 0 0 BR93H56/66-W : n=11 BR93H76/86-W : n=13 DO High-Z Fig.33 Write enable / disable cycle At power on, this IC is in write disable status by the internal RESET circuit. Before executing the write command, it is necessary to execute the write enable command. And, once this command is executed, it is valid until the write disable command is executed or the power is turned off. However, the read command is valid irrespective of write enable / disable command. input to SK after 6 clocks of this command is available by either "H" or "L", but be sure to input it. When the write enable command is executed after power on, write enable status gets in. When the write disable command is executed then, the IC gets in write disable status as same as at power on, and then the write command is cancelled thereafter in software manner. However, the read command is executable. In write enable status, even when the write command is input by mistake, write is started. To prevent such a mistake, it is recommended to execute the write disable command after completion of write. 9/16 Application 1) Method to cancel each command READ Start bit Ope code 1 bit 1 Address * 2 bits Data 8 bits 16 bits Cancel is available in all areas in read mode. u Method to cancel : cancel by CS = "L" *1 Address is 8 bits in BR93H56-W, and BR93H66-W. Address is 10 bits in BR93H76-W, and BR93H86-W. Fig.34 READ cancel available timing Rise of a27 clock *2 SK WRITE, WRAL DI Start bit Ope code 1 bit 2 bits 26 D1 a Address *1 27 28 D0 b Enlarged figure c tE/W Data 8 bits a 29 16 bits b c *2 a : from start bit to 27 clock rise Cancel by CS = "L" *2 b : 27 clock rise and after Cancellation is not available by any means. If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. *1 Address is 8 bits in BR93H56-W, and BR93H66-W. Address is 10 bits in BR93H76-W, and BR93H86-W. *2 27 clocks in BR93H56-W, and BR93H66-W 29 clocks in BR93H76-W, and BR93H86-W *3 28 clocks in BR93H56-W, and BR93H66-W 30 clocks in BR93H76-W, and BR93H86-W Note 1) If Vcc is made OFF in this area, designated address data is not guaranteed, therefore write once again. Note 2) If CS is started at the same timing as that of the SK rise, write execution / cancel becomes unstable, therefore, it is recommended to fall in SK = "L" area. As for SK rise, recommend timing of tCSS/tCSH or higher. *3 c : 28 clock rise and after Cancel by CS = "L" However, when write is started in b area (CS is ended), cancellation is not available by any means. And when SK clock is input continuously, cancellation is not available. Fig.35 WRITE, WRAL cancel available timing 2) Equivalent circuit Output circuit DO OEint. Fig.36 DO output equivalent circuit Input circuit RESETint. LPF CS CSint. TEST1 (TEST) TESTint. EN Fig.39 TEST1 (TEST) input equivalent circuit Fig.37 CS input equivalent circuit TEST2 EN SK DI LPF SK(DI)int. Fig.40 TEST2 input equivalent circuit Fig.38 SK, DI input equivalent circuit 10/16 3) I/O peripheral circuit 3-1) Pull down CS. By making CS = "L" at power ON/OFF, mistake in action and mistake write are prevented. Refer to the item 6) Notes at power ON/OFF in page 15. Pull down resistance Rpd of CS pin To prevent operation and write error at power ON/OFF, CS pull down resistance is necessary. Select an appropriate resistance value from microcontroller VOH, IOH, and VIL characteristics of this IC. Rpd Microcontroller VOHM EEPROM IOHM "H" output Rpd . . . VIHE . . . Example) When Vcc = 5V, VIHE = 2V, VOHM = 2.4V, IOHM = 2mA, from the equation , VIHE VOHM VOHM IOHM Rpd 2.4 2x10-3 Rpd 1.2 (k ) "L" input With the value of Rpd to satisfy the above equation, VOHM becomes 2.4V or higher, and with VIHE (= 2.0V), the equation is also satisfied. Fig.41 CS pull down resistance . . . VIHE : EEPROM VIH specifications VOHM : microcontroller VOH specifications IOHM : microcontroller IOH specifications 3-2) DO is available in both pull up and pull down. DO output become "High-Z" in other READY / BUSY output timing than after data output at read command and write command. When malfunction occurs at "High-Z" input of the microcontroller port connected to DO, it is necessary to pull down and pull up DO. When there is no influence upon the microcontroller actions, DO may be OPEN. If DO is OPEN, and at timing to output status READY, at timing of CS = "H", SK = "H", DI = "H", EEPROM recognizes this as a start bit, resets READY output, and DO = "High-Z", therefore, READY signal cannot be detected. To avoid such output, pull up DO pin for improvement. CS CS SK "H" SK Enlarged DI DO D0 DI High-Z READY DO High-Z BUSY BUSY CS=SK=DI="H" When DO=OPEN Improvement by DO pull up Fig.42 READY output timing at DO = OPEN DO BUSY READY CS=SK=DI="H" When DO=pull up Pull up resistance Rpu and pull down resistance Rpd of DO pin As for pull up and pull down resistance value, select an appropriate value to this resistance value from microcontroller VIH, VIL, and VOH, IOH, VOL, IOL characteristics of this IC. VCC-VOLE . . . Rpu IOLE Microcontroller EEPROM VOLE VILM . . . Rpu VILM IOLE VOLE Example) When Vcc = 5V, VOLE = 0.4V, IOLE = 2.1mA, VILM = 0.8V, from the equation , Rpu 5-0.4 2.1x10-3 Rpu 2.2 (k ) "L" input "L" output With the value of Rpu to satisfy the above equation, VOLE becomes 0.4V or below, and with VILM (= 0.8V), the equation is also satisfied. . . . Fig43 DO pull up resistance 11/16 VOLE : EEPROM VOL specifications IOLE : EEPROM IOL specifications VILM : microcontroller VIL specifications Rpd EEPROM VOHE Microcontroller VIHM VOHE IOHE "H" input "H" output Rpd VOHE IOHE VIHM . . . . . . Example) When Vcc = 5V, VOHE = Vcc ~ 0.2V, IOHE = 0.1mA, VIHM = VCCx0.7V, from the equation , 5-0.2 Rpd 0.1x10-3 Rpd 48 (k ) With the value of Rpd to satisfy the above equation, VOHE becomes 2.4V or higher, and with VIHM (= 3.5V), the equation is also satisfied. . VOHE : EEPROM VOH specifications . IOHE : EEPROM IOH specifications . VIHM : microcontroller VIH specifications Fig.44 DO pull down resistance READY / BUSY status display (DO terminal) (common to BR93H56-W, BR93H66-W, BR93H76-W, BR93H86-W) This display outputs the internal status signal. When CS is started after tCS (Min. 200ns) from CS fall after write command input, "H" or "L" is output. R/B display = "L" (BUSY) = write under execution (D0 status) After the timer circuit in the IC works and creates the period of tE/W, this time circuit completes automatically. And write to the memory cell is made in the period of tE/W, and during this period, other command is not accepted. R/B display = "H" (READY) = command wait status (D0 status) Even after tE/W (Max. 10ms) from write of the memory cell, the following command is accepted. Therefore, CS = "H" in the period of tE/W, and when input is in SK, DI, malfunction may occur, therefore, DI = "L" in the area CS = "H". (Especially, in the case of shared input port, attention is required.) Do not input any command while status signal is output. Command input in BUSY area is cancelled, but command input in READY area is accepted. Therefore, status READY output is cancelled, and malfunction and mistake write may be made. CS STATUS SK CLOCK DI WRITE INSTRUCTION tSV DO High-Z READY BUSY Fig.45 R/B status output timing chart 4) When to directly connect DI and DO This IC has independent input terminal DI and output terminal DO, and separate signals are handled on timing chart, meanwhile, by inserting a resistance R between these DI and DO terminals, it is possible to carry out control by 1 control line. EEPROM Microcontroller DI/O PORT DI R DO Fig.46 DI, DO control line common connection 12/16 Data collision of microcontroller DI/DO output and DO output and feedback of DO output to DI input Drive from the microcontroller DI/O output to DI input on I/O timing, and signal output from DO output occur at the same time in the following points. 4-1) 1 clock cycle to take in A0 address data at read command Dummy bit "0" is output to DO terminal. When address data A0 = "1" input, through current route occurs. "H" EEPROM CS input EEPROM SK input A0 A1 EEPROM DI input Collision of DI input and DO output D15 0 EEPROM DO output D14 D13 High-Z A0 A1 Microcontroller DI/O port High-Z Microcontroller input Microcontroller output Fig.47 Collision timing at read data output at DI, DO direct connection 4-2) Timing of CS = "H" after write command. DO terminal in READY / BUSY function output. When the next start bit input is recognized, "HIGH-Z" enters. Particularly, at command input after write, when CS input is started with microcontroller DI/O output "L" READY output "H" is output from DO terminal, and a through current path occurs. Feedback input at timing of these 4-1) and 4-2) does not cause disorder in basic operations, if resistance R is inserted. EEPROM CS input Write command EEPROM SK input Write command EEPROM DI input Write command EEPROM DO output Write command READY READY Microcontroller DI/O port Write command Microcontroller output READY High-Z BUSY Collision of DI input and status DO output BUSY Microcontroller input Microcontroller output Fig.48 Collision timing at DI, DO direct connection Selection of resistance value R The resistance R becomes through current limit resistance at data collision. When through current flows, noises of power source line and instantaneous stop of power source may occur. When allowable through current is defined as I, the following relation should be satisfied. Determine allowable current value with consideration of impedance and of power source line in set. Insert resistance R, and set the value R to satisfy EEPROM input level VIH/VIL, even under influence of voltage decline due to leak current. Insertion of R will not cause any influence upon basic operations. 4-3) Address data A0 = "1" input, dummy bit "0" output timing (When microcontroller DI/O output is "H", EEPROM DO outputs "L", and "H" is input to DI) * Make the through current to EEPROM 10mA or below. * See to it that the input level VIH of EEPROM should satisfy the following. Microcontroller EEPROM Conditions VOHM VOHM DI/O PORT "H" output DI At this moment, if VOLE = 0V, VOHM VOHM R IOHM VIHE IOHM x R + VOLE R * VIHE * VOLE * VOHM * IOHM DO VOLE IOHM x R VOHM . . IOHM . : EEPROM VIH specifications : EEPROM VOL specifications : Microcontroller VOH specifications : Microcontroller IOH specifications "L" output Fig.49 Circuit at DI, DO direct connection (Microcontroller DI/O "H" output, EEPROM "L" output) 13/16 4-4) DO status READY output timing (When the microcontroller DI/O is "L", EEPROM DO outputs "H", and "L" is input to DI) .Set the EEPROM input level VIL so as to satisfy the following. Microcontroller "L" output EEPROM DI/O PORT Conditions DI VOLM VOLM VILE VOLM VOHE - IOLM x R At this moment, if VOHE=VCC IOHM R VOLM DO VOHE VCC - VOLM R "H" output . VILE . VOHE . VOLM . IOLM VCC - IOLM x R . . . IOLM : EEPROM VIL specifications : EEPROM VOH specifications : Microcontroller VOL specifications : Microcontroller IOL specifications Example) When Vcc = 5, VOHM = 5V, IOHM = 0.4mA, VOLM = 5V, IOLM = 0.4mA , From the equation R VOHM IOHM R R 5 0.4x10-3 R From the equation R 12.5 [k ] R . . . , VCC - VOLM IOLM 5 - 0.4 2.1x10-3 2.2 [k ] . . . Therefore, from the equations R and , 12.5 [k ] Fig.50 Circuit at DI, DO direct connection (Microcontroller DI/O "L" output, EEPROM "H" output) 5) Notes at test pin wrong input There is no influence of external input upon TEST2 pin. For TEST1 (TEST) pin, input must be GND or OPEN. If H level is input, the following may occur: 1. At WEN, WDS, READ command input There is no influence by TEST1 (TEST) pin. 2. WRITE, WRAL command input * BR93H56-W, BR93H66-W, address 8 bits BR93H76-W,BR93H86-W, address 10 bits Start bit Ope code Address 1 bit 2 bits 8 bits * Data tE/W 16 bits a Fig.51 TEST1 (TEST) pin wrong input timing Write start CS rise timing a. There is no influence by TEST1 (TEST) pin. a. If H during write execution, it may not be written correctly. And H area remains BUSY and READY does not go back. Avoid noise input, and at use, be sure to connect it to GND terminal or set it OPEN. 14/16 6) Notes on power ON/OFF . At power ON/OFF, set CS "L". When CS is "H", IC gets in input accept status (active). At power ON, set CS "L" to prevent malfunction from noise. (When CS is in "L" status, all inputs are cancelled.) At power decline low power status may prevail. Therefore, at power OFF, set CS "L" to prevent malfunction from noise. VCC VCC GND VCC CS GND Bad example Good example Fig.51 Timing at power ON/OFF (Bad example) CS pin is pulled up to Vcc. In this case, CS becomes "H" (active status). EEPROM may malfunction or have write error due to noises. This is true even when CS input is High-Z. (Good example) It is "L" at power ON/OFF. Set 10ms or higher to recharge at power OFF.When power is turned on without following the above condition, IC internal circuit may not be reset. POR circuit This IC has a POR (Power On Reset) circuit as a mistake write countermeasure.After POR is activated, write disable status is active. The POR circuit is active only when power is ON, and does not work when power is OFF. However, if CS is "H" at power ON/OFF, it may enable write status due to noise.For secure actions, observe the following conditions: 1 Set CS = "L". 2 Turn on power so as to satisfy the recommended conditions of tR, tOFF, Vbot for POR circuit operation. tR Recommended conditions of tR, tOFF, Vbot VCC tR tOFF tOFF Vbot 10ms or below 10ms or higher 0.3V or below Vbot 100ms or below 10ms or higher 0.2V or below 0 Fig.52 Rise waveform diagram LVCC circuit LVCC (Vcc - Lockout) circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. = 1.9V) or below, it prevent data rewrite. 7) Noise countermeasures Vcc noise (bypass capacitor) When noise or surge gets in the power source line, malfunction may occur. Therefore, it is recommended to attach a by pass capacitor (0.1F) between IC Vcc and GND to remove noise or surge. Attach it as close to the IC as possible.It is also recommended to attach a bypass capacitor between board Vcc and GND. SK noise When the rise time (tR) of SK is long, and noise exists, malfunction may occur due to clock bit displacement. To avoid this, a Schmitt trigger circuit is built into SK input. The hysteresis width of this circuit is set to about 0.2V (at Vcc = 5V). If noises exists at SK input, set the noise amplitude to 0.2Vp-p or below.It is recommended to set the rise time (tR) of SK to 100ns or below. If the rise time is 100ns or higher, take sufficient noise countermeasures. Set the clock rise and fall time as small as possible. Cautions on use (1) Numbers and data in entries are representative design values and are not guaranteed values of the items. (2) Although ROHM is confident that the example application circuit reflects the best possible recommendations, be sure to verify circuit characteristics for your particular application. Modification of constants for other externally connected circuits may cause variations in both static and transient characteristics for external components as well as this Rohm IC. Allow for sucircuit constants. (3) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings, such as the applied voltage or operating temperature range (Topr), may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure, such as a fuse, should be implemented when using the IC at times where the absolute maximum ratings may be exceeded. (4) GND potential Ensure a minimum GND pin potential in all operating conditions. Make sure that no pins are at a voltage below the GND at any time, regardless of whether it is a transient signal or not. (5) Heat design In consideration of allowable loss in actual use condition, carry out heat design with sufficient margin. (6) Short circuit between terminals and erroneous mounting Pay attention to the assembly direction of the ICs. Wrong mounting direction or shorts between terminals, GND, or other components on the circuits, can damage the IC. (7) Operation in strong electromagnetic field Using the ICs in a strong electromagnetic field can cause operation malfunction 15/16 Selection of order type BR 93 ROHM type BUS type name 93 : Microwire H 56 Operating temperature L : -40C ~ +85 C A : -40C ~ +105 C H : -40C ~ +125 C RF - W Package type Capacity Microwire BUS RF:SOP RFJ:SOP-J(JEDEC) 56=2K 66=4K 76=8K 86=16K E2 Double cell Taping type name E2 : reel shape emboss taping Package specifications SOP8/SOP-J8 <External appearance> <Package specifications> * SOP8 * SOP-J8 5.00.2 1 2 3 4 1234 1234 1234 1234 1234 1234 0.20.1 1234 1.27 0.420.1 0.45Min. 0.17 +0.1 -0.05 0.1 1234 1.27 0.420.1 6.00.3 3.90.2 4 8 7 6 5 1.3750.1 0.175 6.20.3 4.40.2 1 1.50.1 0.11 4.90.2 5 0.3Min. 8 Package type Emboss taping Package quantity 2500pcs Package direction E2 (When the reel is gripped by the left hand, and the tape is pulled out by the right hand, No.1 pin of the product is at the left top.) 0.1 Pin No.1 Reel Pulling side * For ordering, specify a number of multiples of the package quantity. The contents described herein are correct as of October, 2005 The contents described herein are subject to change without notice. For updates of the latest information, please contact and confirm with ROHM CO.,LTD. Any part of this application note must not be duplicated or copied without our permission. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams and information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. The products described herein utilize silicon as the main material. The products described herein are not designed to be X ray proof. Published by Application Engineering Group Catalog No. 05T820A '05.10 ROHM(c)2000 TSU Appendix Notes No technical content pages of this document may be reproduced in any form or transmitted by any means without prior permission of ROHM CO.,LTD. The contents described herein are subject to change without notice. The specifications for the product described in this document are for reference only. Upon actual use, therefore, please request that specifications to be separately delivered. Application circuit diagrams and circuit constants contained herein are shown as examples of standard use and operation. Please pay careful attention to the peripheral conditions when designing circuits and deciding upon circuit constants in the set. Any data, including, but not limited to application circuit diagrams information, described herein are intended only as illustrations of such devices and not as the specifications for such devices. ROHM CO.,LTD. disclaims any warranty that any use of such devices shall be free from infringement of any third party's intellectual property rights or other proprietary rights, and further, assumes no liability of whatsoever nature in the event of any such infringement, or arising from or connected with or related to the use of such devices. Upon the sale of any such devices, other than for buyer's right to use such devices itself, resell or otherwise dispose of the same, no express or implied right or license to practice or commercially exploit any intellectual property rights or other proprietary rights owned or controlled by ROHM CO., LTD. is granted to any such buyer. Products listed in this document are no antiradiation design. The products listed in this document are designed to be used with ordinary electronic equipment or devices (such as audio visual equipment, office-automation equipment, communications devices, electrical appliances and electronic toys). Should you intend to use these products with equipment or devices which require an extremely high level of reliability and the malfunction of which would directly endanger human life (such as medical instruments, transportation equipment, aerospace machinery, nuclear-reactor controllers, fuel controllers and other safety devices), please be sure to consult with our sales representative in advance. It is our top priority to supply products with the utmost quality and reliability. However, there is always a chance of failure due to unexpected factors. Therefore, please take into account the derating characteristics and allow for sufficient safety features, such as extra margin, anti-flammability, and fail-safe measures when designing in order to prevent possible accidents that may result in bodily harm or fire caused by component failure. ROHM cannot be held responsible for any damages arising from the use of the products under conditions out of the range of the specifications or due to non-compliance with the NOTES specified in this catalog. Thank you for your accessing to ROHM product informations. More detail product informations and catalogs are available, please contact your nearest sales office. ROHM Customer Support System www.rohm.com Copyright (c) 2007 ROHM CO.,LTD. THE AMERICAS / EUPOPE / ASIA / JAPAN Contact us : webmaster@ rohm.co. jp 21, Saiin Mizosaki-cho, Ukyo-ku, Kyoto 615-8585, Japan TEL : +81-75-311-2121 FAX : +81-75-315-0172 Appendix1-Rev2.0