SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
D
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
D
Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
D
Inputs Accept Voltages to 5.5 V
D
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, and Ceramic Flat (W) Packages,
Ceramic Chip Carriers (FK), and DIPs (J)
description
The SN54LVC74A dual positive-edge-triggered
D-type flip-flop is designed for 2.7-V to 3.6-V VCC
operation and the SN74LVC74A dual positive-
edge-triggered D-type flip-flop is designed for
1.65-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR)
inputs sets or resets the outputs, regardless of the
levels of the other inputs. When PRE and CLR are
inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on
the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not directly related
to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without
affecting the levels at the outputs.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN54L VC74A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LVC74A is characterized for operation from –40°C to 85°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
VCC
2CLR
2D
2CLK
2PRE
2Q
2Q
SN54LVC74A ...J OR W PACKAGE
SN74LVC74A . . . D, DB, OR PW PACKAGE
(TOP VIEW)
3212019
910111213
4
5
6
7
8
18
17
16
15
14
2D
NC
2CLK
NC
2PRE
1CLK
NC
1PRE
NC
1Q
1D
1CLR
NC
2Q
2Q V
2CLR
1Q
GND
NC
SN54LVC74A . . . FK PACKAGE
(TOP VIEW)
CC
NC – No internal connection
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS OUTPUTS
PRE CLR CLK D Q Q
L H X X H L
HLXXLH
LLXXH
†
H
†
HH↑HHL
HH↑LLH
HHLXQ
0
Q
0
†
This configuration is unstable; that is, it does not
persist when PRE or CLR returns to its inactive
(high) level.
logic symbol‡
S
4
3
1CLK
1D
2
1D
R
1
1Q
5
6
C1
10
11
2CLK 12
2D 13
2Q
9
8
1PRE
2PRE
1CLR
2CLR
1Q
2Q
‡This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW, and W packages.
logic diagram, each flip-flop (positive logic)
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
PRE
CLK
D
CLR
Q
Q
C
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply-voltage range, VCC –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input-voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output-voltage range, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, IOK (VO < 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): D package 127°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DB package 158°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PW package 170°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of VCC is provided in the recommended operating conditions table.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
SN54LVC74A SN74LVC74A
UNIT
MIN MAX MIN MAX
UNIT
VCC
Su
pp
ly voltage
Operating 2 3.6 1.65 3.6
V
V
CC
S
u
ppl
y v
oltage
Data retention only 1.5 1.5
V
VCC = 1.65 V to 1.95 V 0.65×VCC
VIH High-level input voltage VCC = 2.3 V to 2.7 V 1.7 V
VCC = 2.7 V to 3.6 V 2 2
VCC = 1.65 V to 1.95 V 0.35×VCC
VIL Low-level input voltage VCC = 2.3 V to 2.7 V 0.7 V
VCC = 2.7 V to 3.6 V 0.8 0.8
VIInput voltage 0 5.5 0 5.5 V
VOOutput voltage 0 VCC 0 VCC V
VCC = 1.65 V –4
IOH
High level out
p
ut current
VCC = 2.3 V –8
mA
I
OH
High
-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 2.7 V –12 –12
mA
VCC = 3 V –24 –24
VCC = 1.65 V 4
IOL
Low level out
p
ut current
VCC = 2.3 V 8
mA
I
OL
Lo
w-
le
v
el
o
u
tp
u
t
c
u
rrent
VCC = 2.7 V 12 12
mA
VCC = 3 V 24 24
∆t/∆vInput transition rise or fall rate 0 10 0 10 ns/V
TAOperating free-air temperature –55 125 –40 85 °C
NOTE 4: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs
, literature number SCBA004.
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
V
SN54LVC74A SN74LVC74A
UNIT
PARAMETER
TEST
CONDITIONS
V
CC MIN TYP†MAX MIN TYP†MAX
UNIT
IOH = 100 µA
1.65 V to 3.6 V VCC–0.2
I
OH = –
100
µ
A
2.7 V to 3.6 V VCC–0.2
IOH = –4 mA 1.65 V 1.2
VOH IOH = –8 mA 2.3 V 1.7 V
IOH =12mA
2.7 V 2.2 2.2
I
OH = –
12
mA
3 V 2.4 2.4
IOH = –24 mA 3 V 2.2 2.2
IOL = 100 µA
1.65 V to 3.6 V 0.2
I
OL =
100
µ
A
2.7 V to 3.6 V 0.2
VOL
IOL = 4 mA 1.65 V 0.45
V
V
OL IOL = 8 mA 2.3 V 0.7
V
IOL = 12 mA 2.7 V 0.4 0.4
IOL = 24 mA 3 V 0.55 0.55
IIVI = 5.5 V or GND 3.6 V ±5±5µA
ICC VI = VCC or GND, IO = 0 3.6 V 10 10 µA
∆ICC One input at VCC – 0.6 V,
Other inputs at VCC or GND 2.7 V to 3.6 V 500 500 µA
CiVI = VCC or GND 3.3 V 5 5 pF
†All typical values are at VCC = 3.3 V, TA = 25°C.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 3)
SN54LVC74A
VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX
fclock Clock frequency 83 100 MHz
t
Pulse duration
PRE or CLR low 3.3 3.3
ns
t
w
P
u
lse
d
u
ration
CLK high or low 3.3 3.3
ns
t
Setup time before CLK↑
Data 3.4 3
ns
t
su
S
e
t
up
ti
me
b
e
f
ore
CLK↑
PRE or CLR inactive 2.2 2
ns
thHold time, data after CLK↑1 1 ns
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figures 1 through 3)
SN74LVC74A
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fclock Clock frequency † † 83 100 MHz
t
Pulse duration
PRE or CLR low † † 3.3 3.3
ns
t
w
P
u
lse
d
u
ration
CLK high or low † † 3.3 3.3
ns
t
Setup time before CLK↑
Data † † 3.4 3
ns
t
su
S
e
t
up
ti
me
b
e
f
ore
CLK↑
PRE or CLR inactive † † 2.2 2
ns
thHold time, data after CLK↑††1 0 ns
†This information was not available at the time of publication.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 3)
SN54LVC74A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX
fmax 83 100 MHz
CLK
QorQ
6 1 5.2
ns
pd PRE or CLR
Q
or
Q
6.4 1 5.4
ns
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
SN74LVC74A
PARAMETER FROM
(INPUT) TO
(OUTPUT) VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 2.7 V VCC = 3.3 V
± 0.3 V UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
fmax † † 83 100 MHz
tpd
CLK
QorQ
† † † † 6 1 5.2
ns
t
p
d
PRE or CLR
Q
or
Q
† † † † 6.4 1 5.4
ns
tsk(o)‡1ns
†This information was not available at the time of publication.
‡Skew between any two outputs of the same package switching in the same direction
operating characteristics, TA = 25°C
PARAMETER TEST
CONDITIONS
VCC = 1.8 V
± 0.15 V VCC = 2.5 V
± 0.2 V VCC = 3.3 V
± 0.3 V UNIT
CONDITIONS
TYP TYP TYP
Cpd Power dissipation capacitance per flip-flop f = 10 MHz † † 27 pF
†This information was not available at the time of publication.
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
1k Ω
1k Ω
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at Open
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
Open
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 1. Load Circuit and Voltage Waveforms
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
VCC/2
VCC/2
VCC/2VCC/2
VCC/2VCC/2
VCC/2
VCC/2
VOH
VOL
th
tsu
From Output
Under Test
CL = 30 pF
(see Note A)
LOAD CIRCUIT
S1 Open
GND
500 Ω
500 Ω
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 2 × VCC
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
0 V
VOL + 0.15 V
VOH – 0.15 V
0 V
VCC
0 V
0 V
tw
VCC VCC
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
2 × VCC
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2 ns, tf ≤2 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
0 V
VCC
VCC/2
tPHL
VCC/2 VCC/2 VCC
0 V
VOH
VOL
Input
Output
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VCC/2 VCC/2
tPLH
2 × VCC
VCC
Figure 2. Load Circuit and Voltage Waveforms
SN54LVC74A, SN74LVC74A
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCAS287H – JANUARY 1993 – REVISED JUNE 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
VOH
VOL
th
tsu
From Output
Under Test
CL = 50 pF
(see Note A)
LOAD CIRCUIT
S1 6 V
Open
GND
500 Ω
500 Ω
tPLH tPHL
Output
Control
(low-level
enabling)
Output
W aveform 1
S1 at 6 V
(see Note B)
Output
W aveform 2
S1 at GND
(see Note B)
tPZL
tPZH
tPLZ
tPHZ
1.5 V1.5 V
1.5 V 1.5 V 2.7 V
0 V
1.5 V 1.5 V VOH
VOL
0 V
1.5 V VOL + 0.3 V
1.5 V VOH – 0.3 V
0 V
1.5 V 2.7 V
0 V
1.5 V 1.5 V 0 V
2.7 V
0 V
1.5 V 1.5 V
tw
Input
2.7 V 2.7 V
3 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
Timing
Input
Data
Input
Output
Input
tpd
tPLZ/tPZL
tPHZ/tPZH
Open
6 V
GND
TEST S1
NOTES: A. CL includes probe and jig capacitance.
B. W aveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
W aveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤10 MHz, ZO = 50 Ω, tr ≤2.5 ns, tf ≤2.5 ns.
D. The outputs are measured one at a time with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
Figure 3. Load Circuit and Voltage Waveforms
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated