DATA SHEET PRELIMINARY ASIC S1L60000 Series May 2000 S1L60000 SERIES HIGH DENSITY GATE ARRAY DESCRIPTION The EEA S1L60000 Series is a family of ultra high-speed VLSI CMOS gate arrays utilizing a 0.25m "sea-of-gates" architecture. * * * Ultra-high-speed, high density and low power consumption Low voltage operation: 2.5V and 2.0V Number of raw gates: 2,519,604 gates FEATURES * Process 0.25m 3/4 layer metalization CMOS process * Integration A maximum of 2,519,604 gates (2 input NAND gate equivalent) * Operating Speed Internal gates: 107ps (2.5V Typ), 140 ps (2.0V Typ) (2-input pair NAND, F/O = 1, Typical wire load) Input buffer: 260 ps (3.3V Typ), Built-in level shifter used. 270 ps (2.5V Typ), 360 ps (2.0 Typ) (F/O = 2, Typical wire load) Output buffer: 1.5ns (3.3V Typ) Built-in level shifter used. 1.6ns (2.5V Typ), 2.3ns (2.0V Typ) (CL=15 pF) * I/F Levels CMOS/LVTTL compatible * Input Modes CMOS, LVTTL, CMOS Schmitt, LVTTL Schmitt, PCI-3V Built-in pull-up and pull-down resistor can be usable. (2 types for each resistor value) * Output Modes Normal, 3-state, bi-directional, PCI-3V * Output Drive IOL = 0.1, 1, 3, 6, 12, 24 mA selectable (built-in level shifter is used at 3.3V) IOL = 0.1, 1,3,6,9,18mA selectable (at 2.5V) IOL = 0.05,0.3,1,1,3,6mA selectable (at 2.0V) * RAM Asynchronous 1-port, asynchronous 2-port * Dual Power Operation supported by using level-shifter circuit Internal logic: Operation supported by low voltage. I/O Buffer: Built-in interfaces of both high and low voltages possible. Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 8 1 DATA SHEET ASIC S1L60000 Series Master Structure The S1L60000 Series comprises 10 types of masters, from which the customer is able to select the master most suitable. Master Total BC (Raw Gates) S1L60093 S1L60173 S1L60283 S1L60403 S1L60593 S1L60833 S1L61233 S1L61583 S1L61903 S1L62513 99220 171720 284394 400290 595362 831572 1234820 1587754 1902960 2519604 Number of Pads 112 148 188 224 272 284 344 388 424 488 Number of Columns (X) Number of Rows (Y) 605 795 1023 1213 1481 1747 2129 2413 2643 3043 Cell Utilization Ratio (U)*1 3-layer 4-layer metal metal 164 216 278 330 402 476 580 658 720 828 80 80 70 70 70 65 65 65 60 60 90 90 85 85 85 80 80 80 75 75 NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only as an estimate ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS Absolute Maximum Ratings (For single Power Supplies): (Vss = 0V) Item Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature * Symbol Limits Unit VDD VI VO IOUT TSTG -0.3 to 3.0 *1 -0.3 to VDD + 0.5 *1 -0.3 to VDD + 0.5 30 -65 to 150 V V V mA C *1: Possible to use from -0.3V to 4.0V of N channel open drain bi-directional buffers and input buffer. 2 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 DATA SHEET ASIC S1L60000 Series May 2000 Absolute Maximum Ratings (For Dual Power Supplies): (Vss = 0V) Item Power Supply Voltage Input Voltage Output Voltage Output Current/Pin Storage Temperature Symbol *3 HVDD *3 LVDD HVI LVI HVO LVO IOUT TSTG Limits Unit -0.3 to 4.0 -0.3 t0 3.0 *1 -0.3 to HVDD + 0.5 DD *1 -0.3 toLV + 0.5 *1 -0.3 to HVDD + 0.5 *1 -0.3 to LVDD + 0.5 *2 30 (+/- 50 ) -65 to 150 V V V V V V mA C * *1: Possible to use from -0.3V to 4.0V of N channel open drain bi-directional buffers and input buffer. *2. Possible to use 24mA of output buffer. *3. HVDD >LVDD. Recommended Operating Conditions (For Single Power Supplies: VDD= 2.5V) Item Power Supply Voltage Input Voltage Ambient Temperature Normal Input for Rising Edge Input Normal Input for Falling Edge Input Schmitt Input for Rising Edge Input Schmitt Input for Falling Edge Input Symbol Min Typ Max Unit VDD VI Ta 2.30 VSS 0 -40 ----- 2.50 -25 25 ----- 2.70 *1 VDD *2 70 *3 85 50 50 5 5 V V C ns ns ms ms tri tfi tri tfi *1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers *2: The ambient temperature range is recommended for Tj = 0 to 85 oC. *3: The ambient temperature range is recommended for Tj = -40 to 125 oC. Recommended Operating Conditions (For Single Power Supplies): Item Power Supply Voltage Input Voltage Ambient Temperature Normal Input for Rising Edge Input Normal Input for Falling Edge Input Schmitt Input for Rising Edge Input Schmitt Input for Falling Edge Input Symbol Min Typ Max Unit VDD VI Ta 1.80 VSS 0 -40 ----- 2.00 -25 25 ----- 2.20 *1 VDD *2 70 *3 85 100 100 10 10 V V C tri tfi tri tfi ns ns ms ms *1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers *2: The ambient temperature range is recommended for Tj = 0 to 85 oC. *3: The ambient temperature range is recommended for Tj = -40 to 125 oC. Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 8 3 DATA SHEET ASIC S1L60000 Series Recommended Operating Conditions (For Dual Power Supplies): Item Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage) Input Voltage Ambient Temperature Normal Input for Rising Edge Input Normal Input for Falling Edge Input Schmitt Input for Rising Edge Input Schmitt Input for Falling Edge Input Symbol Min Typ Max Unit HVDD LVDD HVI LVI Ta 3.00 2.30 VSS VSS 0 -40 ----- 3.30 2.50 --25 25 ----- 3.60 2.70 *1 HVDD *1 LVDD *2 70 *3 85 50 50 5 5 V V V ns ns ms ms Htri Htfi Htri Htfi C *1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers *2: The ambient temperature range is recommended for Tj = 0 to 85 oC *3: The ambient temperature range is recommended to Tj = -40 to 125 oC. Recommended Operating Conditions (For Dual Power Supplies): Item Power Supply Voltage (High Voltage) Power Supply Voltage (Low Voltage) Input Voltage Ambient Temperature Normal Input for Rising Edge Input Normal Input for Falling Edge Input Schmitt Input for Rising Edge Input Schmitt Input for Falling Edge Input Symbol Min Typ Max Unit HVDD LVDD HVI LVI Ta 3.00 1.80 VSS VSS 0 -40 --------- 3.30 2.00 --25 25 --------- 3.60 2.20 *1 HVDD *1 LVDD *2 70 *3 85 50 100 50 100 5 10 5 10 V V V Htri Ltri Htfi Ltfi Htri Ltri Htfi Ltfi C ns ns ms ms *1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers *2: The ambient temperature range is recommended for Tj = 0 to 85 oC *3: The ambient temperature range is recommended to Tj = -40 to 125 oC. 4 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 DATA SHEET ASIC S1L60000 Series May 2000 Electrical Characteristics of the S1L60000 Series: (HVDD = 3.3V in common, VSS = OV, Ta = -40 to 85oC) Symbol Conditions Min Typ Max Unit Input Leakage Current Off State Leakage Current High Level Output Voltage Item ILI IOZ VOH -5 -5 HVDD -0.4 ---- 5 5 -- A A V Low Level Output Voltage VOL -- -- 0.4 V High Level Input Voltage VIH1 --IOH = -0.1mA (Type S), -1mA (Type M), -3mA (Type 1), -6mA (Type 2), -12mA (Type 3), -24mA (Type 4) HVDD = Min IOL = 0.1mA (Type S), 1mA (Type M), 3mA (Type 1), 6mA (Type 2), 12mA (Type 3), 24mA (Type 4) HVDD= Min CMOS Level, HVDD = Max 2.2 -- -- V Low Level Input Voltage Possitive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage High Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage High Level Input Voltage Low Level Input Voltage High Level Output Current VIL1 VT1+ VT1VH1 VIH2 VIL2 VT2+ VT2VH2 VIH3 VIL3 IOH3 -1.4 0.6 0.3 2.0 -1.1 0.6 0.1 1.8 -- ------------ 0.8 2.7 1.8 --0.8 2.4 1.8 --0.9 V V V V V V V V V V V -36 -- --- --115 mA mA 48 -30 --60 mA mA Type 2 60 120 Type 1 30 60 Type 2 60 120 -- -- -137 (120) 144 (240) 288 (120) 144 (240) 288 -20 -- -- 17 A -350 -- -- A 210 -- -- A ---- ---- 8 10 10 pF pF pF Low Level Output Current Pull-up Resistance Pull-down Resistance IOL3 RUP RPD High Level Maintenance Current Low Level Maintenance Current High Level Reversal Current IBHHO Low Level Reversal Current IBHLO Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance IBHH IBHL CI CO CIO CMOS Level, HVDD = Min CMOS Schmitt CMOS Schmitt CMOS Schmitt LVTTL Level, HVDD = Max LVTTL Level, HVDD = Min LVTTL Schmitt LVTTL Schmitt LVTTL Schmitt PCI Level, HVDD + Max PCI Level, HVDD = Min PCI Response, VOH = 0.90V, HVDD = Min VOH = 2.52V, HVDD = Max PCI Response VOH = 1.80V, HVDD = Min VOL = .065V, HVDD = Max VI = 0V Type 1 VI =HVDD Bus Hold Response, VIN = 2.0V, HVDD = Min Bus Hold Response, VIN = 0.8V, HVDD = Min Bus Hold Response, VIN = 0.8V, HVDD = Max Bus Hold Response, VIN = 2.0V, HVDD = Max f = 1Mhz, VDD = 0V f = 1Mhz, VDD = 0V f = 1Mhz, VDD = 0V Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 8 K K A 5 DATA SHEET ASIC S1L60000 Series Electrical Characteristics of the S1L60000 Series: (VDD = 2.0V 0.2V, VSS = 0V, Ta = -40 to 85C) Symbol Conditions Min Typ Max Unit Input Leakage Current Off State Leakage Current High Level Output Voltage Item ILI IOZ VOH -5 -5 VDD -0.4 ---- 5 5 -- A A V Low Level Output Voltage VOL -- -- 0.4 V High Level Input Voltage Low Level Input Voltage High Level Input Voltage Low Level Input Voltage Hysteresis Voltage Pull-up Resistance VIH1 VIL1 VT1+ VT1VH1 RUP --IOH = -0.1mA (Type S), -1mA (Type M), -3mA (Type 1), -6mA (Type 2), -9mA (Type 3), -18mA (Type 4) VDD = Min IOL = 0.1mA (Type S), 1mA (Type M), 3mA (Type 1), 6mA (Type 2), 9mA (Type 3), 18mA (Type 4) VDD = Min CMOS Level, VDD = Max CMOS Level, VDD = Min CMOS Schmitt CMOS Schmitt CMOS Schmitt VI = 0V Type 1 1.7 -0.8 0.5 0 20 -----50 V V V V V Type 2 40 100 Type 1 20 50 Type 2 40 100 -- -- -0.7 1.9 1.3 -(100) 120 (200) 240 (100) 120 (200) 240 -5 -- -- 5 A -280 -- -- A 170 -- -- A ---- ---- 8 10 10 pF pF pF Pull-down Resistance High Level Maintenance Current Low Level Maintenance Current High Level Reversal Current IBHHO Low Level Reversal Current IBHLO Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance * RPD IBHH IBHL CI CO CIO VI = VDD Bus Hold Response, VIN = 1.7V, VDD = Min Bus Hold Response, VIN = 0.7V, VDD = Min Bus Hold Response, VIN = 0.3V, VDD = Max Bus Hold Response, VIN = 1.6V, VDD = Max f = 1Mhz, VDD = 0V f = 1Mhz, VDD = 0V f = 1Mhz, VDD = 0V K K A The values parenthesized means in case of Ta = 0 to 70oC 6 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 DATA SHEET ASIC S1L60000 Series May 2000 Electrical Characteristics of the S1L60000 Series: (VDD = 2.0V 0.2V, VSS = 0V, Ta = -40 to 85C) Item ILI IOZ VOH Low Level Output Voltage VOL High Level Input Voltage Low Level Input Voltage Positive Trigger Voltage Negative Trigger Voltage Hysteresis Voltage Pull-up Resistance VIH1 VIL1 VT1+ VT1VH1 RUP Pull-down Resistance RPD High Level Maintenance Current Low Level Maintenance Current High Level Reversal Current IBHH IBHHO Low Level Reversal Current IBHLO Input Terminal Capacitance Output Terminal Capacitance Input/Output Terminal Capacitance * Symbol Input Leakage Current Off State Leakage Current High Level Output Voltage IBHL CI CO CIO Conditions --IOH = -0.05mA (Type S), -0.3mA (Type M), -1mA (Type 1), -2mA (Type 2), -3mA (Type 3), -6mA (Type 4) VDD = Min IOL = 0.05mA (Type S), 0.3mA (Type M), 1mA (Type 1), 2mA (Type 2), 3A (Type 3), 6mA (Type 4) VDD = Min CMOS Level, VDD = Max CMOS Level, VDD = Min CMOS Schmitt CMOS Schmitt CMOS Schmitt VI = 0V Type 1 Type 2 VI = VDD Type 1 Type 2 Bus Hold Response, VIN = 1.7V, VDD = Min Bus Hold Response, VIN = 0.7V, VDD = Min Bus Hold Response, VIN = 0.3V, VDD = Max Bus Hold Response, VIN = 1.6V, VDD = Max f = 1Mhz, VDD = 0V f = 1Mhz, VDD = 0V f = 1Mhz, VDD = 0V Min Typ Max Unit -5 -5 VDD -0.2 ---- 5 5 -- A A V -- -- 0.2 V 1.6 -0.4 0.3 0 30 60 30 60 -- -----70 140 70 140 -- -0.3 1.6 1.4 -200 400 200 400 -2 V V V V V K A -- -- 2 A -100 -- -- A 100 -- -- A ---- ---- 8 10 10 pF pF pF K The values parenthesized means in case of Ta = 0 to 70oC Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 8 7 DATA SHEET ASIC S1L60000 Series Quiescent Current (For Single Power Supplies) 2.5V 0.2V IDDS Max Master S1L60093 / 60173 / 60283 S1L60403 / 60593 / 60833 S1L61233 / 61583 S1L61903 / 62513 120 330 630 1000 2.0V 0.2V IDDS Max (Tj = 85oC) Unit A A A A 90 270 510 800 Quiescent Current (For Dual Power Supplies) Master S1L60093 / 60173 / 60283 S1L60403 / 60593 / 60833 S1L61233 / 61583 S1L61903 / 62513 3.3V 0.3V HIDDS Max 21 35 48 60 2.5V 0.2V LIDDS Max 120 330 630 1000 3.3V 0.3V HIDDS Max 21 35 48 60 (Tj = 85oC) 2.0V 0.2V Unit LIDDS Max 90 270 510 800 A A A A 8 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 DATA SHEET GATE ARRAY DEVELOPMENT FLOW CUSTOMER ASIC S1L60000 Series May 2000 EEA Product Plan Functional Spec. Circuit Design Test Pattern Design Logical Check (Simulation) Timing Check (Simulation) Delay Analyzing NG Verification EWS OK G/A Development Request Simulation File * Schematic * Pin assignment * Timing wave form * Marking diagram * P/O NG Verification * OK Place & Route Delay Analyzing Simulation List Post Simulation Customer Spec. (Sign Off) Make Masks NG Verification OK TS (Test Sample) Fabrication NG Check ES (Engr. Sample) Fabrication OK NG Check OK ET(TS) Approve the Prototype ES(TS) Proto. Approval MP Setup Delivery Spec. Spec. Delivery Approval Delivery Spec. Publication Approve Delivery Spec. MP NOTE: ( ) is based on customer's requirement. Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 8 9 ASIC S1L60000 Series DATA SHEET EEA CUSTOMER ENGINEERING To help customers implement their design of EEA ASIC's, we offer training at our design centers and at customer sites when required. When a design is started, an EEA engineer is assigned to the project and will remain with the project through its completion. EEA engineers will work with the customer on design, software and other technical issues. When the design files are transferred to EEA, the assigned engineer will verify the design's integrity and prepare it for place and route. The EEA Customer Engineering Group provides all technical customer-support services including: * * * * * * * Pre-Sale Technical Support Customer Training Design Assistance Custom Cell Development Place and Route Scan Insertion and ATPG Netlist Conversion and Synthesis * * * * * * * Software Documentation Simulation Support Turnkey Design Design Verification Static Timing Analysis JTAG Insertion Test Vector Conversion EDA/CAE SUPPORT * Schematic Capture Viewlogic (Synopsys): Viewdraw EEA: Auklet (ECS) * Synthesis * * Synopsys: DesignCompiler Exemplar Logic: Leonardo Simulation DFT Cadence: Verilog-XL Synopsys: VSS (VHDL) Avant!: Polaris (Purespeed) Viewlogic (Synopsys): Viewsim Modeltech: V-System (VHDL) Synopsys: TestCompiler+ Viewlogic (Synopsys): TestGen (Sunrise) * Place & Route Cadence: GateEnsemble Avant!: Aquarius-GA (Apollo) * Delay Calculation (Post-Route) EEA: Peacock (EXDT) 10 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 DATA SHEET ASIC S1L60000 Series May 2000 EDA/CAE SUPPORT (continued) * Static Timing Synopsys: PrimeTime (DesignTime) Viewlogic (Synopsys): Motive * Layout Verification Cadence: Dracula/LVS This page is intentionally left blank. Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200 8 11 ASIC S1L60000 Series DATA SHEET NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of EEA. EEA reserves the right to make changes to this material without notice. EEA does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions there of may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency. EPSON implies SEIKO EPSON CORPORATION and EPSON affiliated company. EEA Systems Inc. 1998 All Rights Reserved, Rev. 0.1 Trademark & Company Name XNF is registered trademark of Synopsys Inc. All other product names mentioned herein are trademarks and/or registered trademarks of their respective owners. For additional information about EEA ASIC products and services, or to discuss a solution tailored to your specific requirements, call your local EEA sales office or contact the factory. Corporate Headquarters Northwest Regional Sales Office & Design Center 150 River Oaks Parkway San Jose, CA 95134 Phone: (408)922-0200 Fax: (408)922-0238 Northeast Regional Sales Office 301 Edgewater Place, Suite 120, Wakefield, MA 01880 Phone: (617)246-3600 Fax: (617)246-5443 Southeast Regional Sales Office 4300 Six Forks Road, Suite 430, Raleigh, NC 27609 Phone: (919)781-7667 Fax: (919)781-6778 Central Regional Sales Office 1450 E. American Lane, #1550 Schaumburg, IL 60173 Phone: (847)517-7667 Fax: (847)517-7601 http://www.eea.epson.com 12 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200