1
DATA SHEET
ASIC
S1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
S1L60000 SERIES HIGH DENSITY GATE ARRAY
§ DESCRIPTION
The EEA S1L60000 Series is a family of ultra high-speed VLSI CMOS gate arrays utilizing a
0.25µm “sea-of-gates” architecture.
• Ultra-high-speed, high density and low power consumption
• Low voltage operation: 2.5V and 2.0V
• Number of raw gates: 2,519,604 gates
§ FEATURES
• Process 0.25µm 3/4 layer metalization CMOS process
• Integration A maximum of 2,519,604 gates (2 input NAND gate equivalent)
• Operating Speed Internal gates: 107ps (2.5V Typ), 140 ps (2.0V Typ)
(2-input pair NAND, F/O = 1, Typical wire load)
Input buffer: 260 ps (3.3V Typ), Built-in level shifter used.
270 ps (2.5V Typ), 360 ps (2.0 Typ)
(F/O = 2, Typical wire load)
Output buffer: 1.5ns (3.3V Typ) Built-in level shifter used.
1.6ns (2.5V Typ), 2.3ns (2.0V Typ) (CL=15 pF)
• I/F Levels CMOS/LVTTL compatible
• Input Modes CMOS, LVTTL, CMOS Schmitt, LVTTL Schmitt, PCI-3V
Built-in pull-up and pull-down resistor can be usable.
(2 types for each resistor value)
• Output Modes Normal, 3-state, bi-directional, PCI-3V
• Output Drive IOL = 0.1, 1, 3, 6, 12, 24 mA selectable
(built-in level shifter is used at 3.3V)
IOL = 0.1, 1,3,6,9,18mA selectable (at 2.5V)
IOL = 0.05,0.3,1,1,3,6mA selectable (at 2.0V)
• RAM Asynchronous 1-port, asynchronous 2-port
• Dual Power Operation supported by using level-shifter circuit
Internal logic: Operation supported by low voltage.
I/O Buffer: Built-in interfaces of both high and low voltages
possible.
PRELIMINARY
2 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200
ASIC
S1L60000 Series
DATA SHEET
§ Master Structure
The S1L60000 Series comprises 10 types of masters, from which the customer is able to select the
master most suitable.
Cell Utilization Ratio
(U)*1
Master Total
BC
(Raw Gates)
Number
of
Pads
Number
of
Columns (X)
Number
of
Rows (Y) 3-layer
metal 4-layer
metal
S1L60093 99220 112 605 164 80 90
S1L60173 171720 148 795 216 80 90
S1L60283 284394 188 1023 278 70 85
S1L60403 400290 224 1213 330 70 85
S1L60593 595362 272 1481 402 70 85
S1L60833 831572 284 1747 476 65 80
S1L61233 1234820 344 2129 580 65 80
S1L61583 1587754 388 2413 658 65 80
S1L61903 1902960 424 2643 720 60 75
S1L62513 2519604 488 3043 828 60 75
NOTE: *1: This is the value when there are no cells, such as RAM cells. The cell use efficiency is dependent not only on the scope of
the circuits, but also on the number of signals, the number of branches per signal, etc.; thus, use the values in this table only
as an estimate
§ ELECTRICAL CHARACTERISTICS AND SPECIFICATIONS
Absolute Maximum Ratings (For single Power Supplies): (Vss = 0V)
Item Symbol Limits Unit
Power Supply Voltage VDD -0.3 to 3.0 V
Input Voltage VI-0.3 to VDD + 0.5*1 V
Output Voltage VO-0.3 to VDD + 0.5*1 V
Output Current/Pin IOUT ± 30 mA
Storage Temperature TSTG -65 to 150 °C
**1: Possible to use from –0.3V to 4.0V of N channel open drain bi-directional buffers and input buffer.
3
DATA SHEET
ASIC
S1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
Absolute Maximum Ratings (For Dual Power Supplies): (Vss = 0V)
Item Symbol Limits Unit
Power Supply Voltage HVDD*3
LVDD*3 -0.3 to 4.0
-0.3 t0 3.0 V
V
Input Voltage HVI
LVI
-0.3 to HVDD + 0.5*1
-0.3 toLVDD + 0.5*1 V
V
Output Voltage HVO
LVO
-0.3 to HVDD + 0.5*1
-0.3 to LVDD + 0.5*1 V
V
Output Current/Pin IOUT ± 30 (+/- 50*2)mA
Storage Temperature TSTG -65 to 150 °C
**1: Possible to use from –0.3V to 4.0V of N channel open drain bi-directional buffers and input buffer.
*2. Possible to use 24mA of output buffer.
*3. HVDD >LVDD.
Recommended Operating Conditions (For Single Power Supplies: VDD= 2.5V)
Item Symbol Min Typ Max Unit
Power Supply Voltage VDD 2.30 2.50 2.70 V
Input Voltage VIVSS -- VDD*1 V
Ambient Temperature Ta0
-40 25
25 70*2
85*3 °C
Normal Input for Rising Edge Input tri -- -- 50 ns
Normal Input for Falling Edge Input tfi -- -- 50 ns
Schmitt Input for Rising Edge Input tri -- -- 5ms
Schmitt Input for Falling Edge Input tfi -- -- 5ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85 oC.
*3: The ambient temperature range is recommended for Tj = -40 to 125 oC.
Recommended Operating Conditions (For Single Power Supplies):
Item Symbol Min Typ Max Unit
Power Supply Voltage VDD 1.80 2.00 2.20 V
Input Voltage VIVSS -- VDD *1 V
Ambient Temperature Ta0
-40 25
25 70*2
85*3 °C
Normal Input for Rising Edge Input tri -- -- 100 ns
Normal Input for Falling Edge Input tfi -- -- 100 ns
Schmitt Input for Rising Edge Input tri -- -- 10 ms
Schmitt Input for Falling Edge Input tfi -- -- 10 ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85 oC.
*3: The ambient temperature range is recommended for Tj = -40 to 125 oC.
4 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200
ASIC
S1L60000 Series
DATA SHEET
Recommended Operating Conditions (For Dual Power Supplies):
Item Symbol Min Typ Max Unit
Power Supply Voltage (High Voltage) HVDD 3.00 3.30 3.60 V
Power Supply Voltage (Low Voltage) LVDD 2.30 2.50 2.70 V
HVIVSS -- HVDD*1
Input Voltage LVIVSS -- LVDD*1 V
Ambient Temperature Ta0
-40 25
25 70*2
85*3 °C
Normal Input for Rising Edge Input Htri -- -- 50 ns
Normal Input for Falling Edge Input Htfi -- -- 50 ns
Schmitt Input for Rising Edge Input Htri -- -- 5ms
Schmitt Input for Falling Edge Input Htfi -- -- 5ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85 oC
*3: The ambient temperature range is recommended to Tj = -40 to 125 oC.
Recommended Operating Conditions (For Dual Power Supplies):
Item Symbol Min Typ Max Unit
Power Supply Voltage (High Voltage) HVDD 3.00 3.30 3.60 V
Power Supply Voltage (Low Voltage) LVDD 1.80 2.00 2.20 V
HVIVSS -- HVDD*1
Input Voltage LVIVSS -- LVDD*1 V
Ambient Temperature Ta0
-40 25
25 70*2
85*3 °C
Htri -- -- 50Normal Input for Rising Edge Input Ltri -- -- 100 ns
Htfi -- -- 50Normal Input for Falling Edge Input Ltfi -- -- 100 ns
Htri -- -- 5Schmitt Input for Rising Edge Input Ltri -- -- 10 ms
Htfi -- -- 5Schmitt Input for Falling Edge Input Ltfi -- -- 10 ms
*1: Possible to use 3.6V of N channel open drain bi-directional buffers and input buffers
*2: The ambient temperature range is recommended for Tj = 0 to 85 oC
*3: The ambient temperature range is recommended to Tj = -40 to 125 oC.
5
DATA SHEET
ASIC
S1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
Electrical Characteristics of the S1L60000 Series:
(HVDD = 3.3V in common, VSS = OV, Ta = -40 to 85oC)
Item Symbol Conditions Min Typ Max Unit
Input Leakage Current ILI -- -5 -- 5µA
Off State Leakage Current IOZ -- -5 -- 5µA
High Level Output Voltage VOH IOH = -0.1mA (Type S), -1mA (Type
M), -3mA (Type 1), -6mA (Type 2),
-12mA (Type 3), -24mA (Type 4)
HVDD = Min
HVDD
-0.4 -- -- V
Low Level Output Voltage VOL IOL = 0.1mA (Type S), 1mA (Type
M), 3mA (Type 1), 6mA (Type 2),
12mA (Type 3), 24mA (Type 4)
HVDD= Min
-- -- 0.4 V
High Level Input Voltage VIH1 CMOS Level, HVDD = Max 2.2 -- -- V
Low Level Input Voltage VIL1 CMOS Level, HVDD = Min -- -- 0.8 V
Possitive Trigger Voltage VT1+ CMOS Schmitt 1.4 -- 2.7 V
Negative Trigger Voltage VT1- CMOS Schmitt 0.6 -- 1.8 V
Hysteresis Voltage VH1 CMOS Schmitt 0.3 -- -- V
High Level Input Voltage VIH2 LVTTL Level, HVDD = Max 2.0 -- -- V
Low Level Input Voltage VIL2 LVTTL Level, HVDD = Min -- -- 0.8 V
Positive Trigger Voltage VT2+ LVTTL Schmitt 1.1 -- 2.4 V
Negative Trigger Voltage VT2- LVTTL Schmitt 0.6 -- 1.8 V
Hysteresis Voltage VH2 LVTTL Schmitt 0.1 -- -- V
High Level Input Voltage VIH3 PCI Level, HVDD + Max 1.8 -- -- V
Low Level Input Voltage VIL3 PCI Level, HVDD = Min -- -- 0.9 V
High Level Output Current IOH3 PCI Response,
VOH = 0.90V, HVDD = Min
VOH = 2.52V, HVDD = Max -36
-- --
-- --
-115 mA
mA
Low Level Output Current IOL3 PCI Response
VOH = 1.80V, HVDD = Min
VOL = .065V, HVDD = Max 48
-- --
-- --
137 mA
mA
Type 1 30 60 (120)
144
Pull-up Resistance RUP VI = 0V
Type 2 60 120 (240)
288
KΩ
Type 1 30 60 (120)
144
Pull-down Resistance RPD VI =HVDD
Type 2 60 120 (240)
288
KΩ
High Level Maintenance
Current IBHH Bus Hold Response,
VIN = 2.0V, HVDD = Min -- -- -20 µA
Low Level Maintenance
Current IBHL Bus Hold Response,
VIN = 0.8V, HVDD = Min -- -- 17 µA
High Level Reversal Current IBHHO Bus Hold Response,
VIN = 0.8V, HVDD = Max -350 -- -- µA
Low Level Reversal Current IBHLO Bus Hold Response,
VIN = 2.0V, HVDD = Max 210 -- -- µA
Input Terminal Capacitance CIf = 1Mhz, VDD = 0V -- -- 8pF
Output Terminal Capacitance COf = 1Mhz, VDD = 0V -- -- 10 pF
Input/Output Terminal
Capacitance CIO f = 1Mhz, VDD = 0V -- -- 10 pF
6 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200
ASIC
S1L60000 Series
DATA SHEET
Electrical Characteristics of the S1L60000 Series:
(VDD = 2.0V ± 0.2V, VSS = 0V, Ta = -40 to 85°C)
Item Symbol Conditions Min Typ Max Unit
Input Leakage Current ILI -- -5 -- 5µA
Off State Leakage Current IOZ -- -5 -- 5µA
High Level Output Voltage VOH IOH = -0.1mA (Type S), -1mA (Type
M), -3mA (Type 1), -6mA (Type 2),
-9mA (Type 3), -18mA (Type 4)
VDD = Min
VDD
-0.4 -- -- V
Low Level Output Voltage VOL IOL = 0.1mA (Type S), 1mA (Type
M), 3mA (Type 1), 6mA (Type 2),
9mA (Type 3), 18mA (Type 4)
VDD = Min
-- -- 0.4 V
High Level Input Voltage VIH1 CMOS Level, VDD = Max 1.7 -- -- V
Low Level Input Voltage VIL1 CMOS Level, VDD = Min -- -- 0.7 V
High Level Input Voltage VT1+ CMOS Schmitt 0.8 -- 1.9 V
Low Level Input Voltage VT1- CMOS Schmitt 0.5 -- 1.3 V
Hysteresis Voltage VH1 CMOS Schmitt 0-- -- V
Type 1 20 50 (100)
120
Pull-up Resistance RUP VI = 0V
Type 2 40 100 (200)
240
KΩ
Type 1 20 50 (100)
120
Pull-down Resistance RPD VI = VDD
Type 2 40 100 (200)
240
KΩ
High Level Maintenance
Current IBHH Bus Hold Response,
VIN = 1.7V, VDD = Min -- -- -5 µA
Low Level Maintenance
Current IBHL Bus Hold Response,
VIN = 0.7V, VDD = Min -- -- 5µA
High Level Reversal Current IBHHO Bus Hold Response,
VIN = 0.3V, VDD = Max -280 -- -- µA
Low Level Reversal Current IBHLO Bus Hold Response,
VIN = 1.6V, VDD = Max 170 -- -- µA
Input Terminal Capacitance CIf = 1Mhz, VDD = 0V -- -- 8pF
Output Terminal Capacitance COf = 1Mhz, VDD = 0V -- -- 10 pF
Input/Output Terminal
Capacitance CIO f = 1Mhz, VDD = 0V -- -- 10 pF
*The values parenthesized means in case of Ta = 0 to 70oC
7
DATA SHEET
ASIC
S1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
Electrical Characteristics of the S1L60000 Series:
(VDD = 2.0V ± 0.2V, VSS = 0V, Ta = -40 to 85°C)
Item Symbol Conditions Min Typ Max Unit
Input Leakage Current ILI -- -5 -- 5µA
Off State Leakage Current IOZ -- -5 -- 5µA
High Level Output Voltage VOH IOH = -0.05mA (Type S), -0.3mA
(Type M), -1mA (Type 1), -2mA
(Type 2), -3mA (Type 3), -6mA
(Type 4)
VDD = Min
VDD
-0.2 -- -- V
Low Level Output Voltage VOL IOL = 0.05mA (Type S), 0.3mA
(Type M), 1mA (Type 1), 2mA
(Type 2), 3A (Type 3), 6mA (Type
4)
VDD = Min
-- -- 0.2 V
High Level Input Voltage VIH1 CMOS Level, VDD = Max 1.6 -- -- V
Low Level Input Voltage VIL1 CMOS Level, VDD = Min -- -- 0.3 V
Positive Trigger Voltage VT1+ CMOS Schmitt 0.4 -- 1.6 V
Negative Trigger Voltage VT1- CMOS Schmitt 0.3 -- 1.4 V
Hysteresis Voltage VH1 CMOS Schmitt 0-- -- V
Type 1 30 70 200Pull-up Resistance RUP VI = 0V Type 2 60 140 400 KΩ
Type 1 30 70 200Pull-down Resistance RPD VI = VDD Type 2 60 140 400 KΩ
High Level Maintenance
Current IBHH Bus Hold Response,
VIN = 1.7V, VDD = Min -- -- -2 µA
Low Level Maintenance
Current IBHL Bus Hold Response,
VIN = 0.7V, VDD = Min -- -- 2µA
High Level Reversal Current IBHHO Bus Hold Response,
VIN = 0.3V, VDD = Max -100 -- -- µA
Low Level Reversal Current IBHLO Bus Hold Response,
VIN = 1.6V, VDD = Max 100 -- -- µA
Input Terminal Capacitance CIf = 1Mhz, VDD = 0V -- -- 8pF
Output Terminal Capacitance COf = 1Mhz, VDD = 0V -- -- 10 pF
Input/Output Terminal
Capacitance CIO f = 1Mhz, VDD = 0V -- -- 10 pF
*The values parenthesized means in case of Ta = 0 to 70oC
8 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200
ASIC
S1L60000 Series
DATA SHEET
Quiescent Current (For Single Power Supplies)
(Tj = 85oC)
Master 2.5V ±0.2V
IDDS Max 2.0V ±0.2V
IDDS Max Unit
S1L60093 / 60173 / 60283 120 90
µA
S1L60403 / 60593 / 60833 330 270
µA
S1L61233 / 61583 630 510
µA
S1L61903 / 62513 1000 800
µA
Quiescent Current (For Dual Power Supplies)
(Tj = 85oC)
Master 3.3V ±0.3V
HIDDS Max 2.5V ± 0.2V
LIDDS Max 3.3V ±0.3V
HIDDS Max 2.0V ±0.2V
LIDDS Max Unit
S1L60093 / 60173 / 60283 21 120 21 90
µA
S1L60403 / 60593 / 60833 35 330 35 270
µA
S1L61233 / 61583 48 630 48 510
µA
S1L61903 / 62513 60 1000 60 800
µA
9
DATA SHEET
ASIC
S1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
Delivery Spec.
Approval
GATE ARRAY DEVELOPMENT FLOW
CUSTOMER
Product Plan
Functional Spec.
Circuit Design
Test Pattern Design
Logical Check
(Simulation)
Verification
ET(TS) Approve
the Prototype
Approve
Delivery Spec.
Delivery Spec.
ES(TS) Proto.
Approval
Customer Spec.
(Sign Off)
Simulation List
MP
Delivery Spec.
Publication
MP Setup
ES (Engr. Sample)
Fabrication
TS (Test Sample)
Fabrication
Make Masks
Post Simulation
Place & Route
Timing Check
(Simulation)
NOTE: ( ) is based on customer’s requirement.
Verification
Verification
G/A Development
Request
Simulation
File
•
Schematic
• Pin assignment
• Timing wave form
• Marking diagram
• P/O
Check
Check
OK
NG
OK
NG
OK
NG
NG EWS
OK NG
OK
Delay Analyzing
Delay Analyzing
*
10 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200
ASIC
S1L60000 Series
DATA SHEET
§ EEA CUSTOMER ENGINEERING
To help customers implement their design of EEA ASIC’s, we offer training at our design centers
and at customer sites when required.
When a design is started, an EEA engineer is assigned to the project and will remain with the
project through its completion. EEA engineers will work with the customer on design, software and
other technical issues. When the design files are transferred to EEA, the assigned engineer will
verify the design’s integrity and prepare it for place and route. The EEA Customer Engineering
Group provides all technical customer-support services including:
• Pre-Sale Technical Support •Software Documentation
• Customer Training •Simulation Support
• Design Assistance •Turnkey Design
• Custom Cell Development •Design Verification
• Place and Route •Static Timing Analysis
• Scan Insertion and ATPG •JTAG Insertion
• Netlist Conversion and Synthesis •Test Vector Conversion
§ EDA/CAE SUPPORT
• Schematic Capture
§ Viewlogic (Synopsys): Viewdraw
§ EEA: Auklet (ECS)
• Synthesis
§ Synopsys: DesignCompiler
§ Exemplar Logic: Leonardo
• Simulation
§ Cadence: Verilog-XL
§ Synopsys: VSS (VHDL)
§ Avant!: Polaris (Purespeed)
§ Viewlogic (Synopsys): Viewsim
§ Modeltech: V-System (VHDL)
• DFT § Synopsys: TestCompiler+
§ Viewlogic (Synopsys): TestGen (Sunrise)
• Place & Route
§ Cadence: GateEnsemble
§ Avant!: Aquarius-GA (Apollo)
• Delay Calculation (Post-Route)
§ EEA: Peacock (EXDT)
11
DATA SHEET
ASIC
S1L60000 Series
May 2000
Epson Electronics America, Inc.
8
150 River Oaks Pkwy
8
San Jose, CA 95134
8
Tel: (408)922-0200
8
§ EDA/CAE SUPPORT (continued)
• Static Timing
§ Synopsys: PrimeTime (DesignTime)
§ Viewlogic (Synopsys): Motive
• Layout Verification
§ Cadence: Dracula/LVS
This page is intentionally left blank.
12 Epson Electronics America, Inc. 8150 River Oaks Pkwy 8San Jose, CA 95134 8Tel: (408)922-0200
ASIC
S1L60000 Series
DATA SHEET
NOTICE
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of EEA. EEA reserves
the right to make changes to this material without notice. EEA does not assume any liability of any kind arising out of any inaccuracies
contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is
applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is
granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free
from any patent or copyright infringement of a third party. This material or portions there of may contain technology or the subject relating to
strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from
the Ministry of International Trade and Industry or other approval from another government agency.
EPSON implies SEIKO EPSON CORPORATION and EPSON affiliated company.
EEA Systems Inc. 1998 All Rights Reserved, Rev. 0.1
Trademark & Company Name
XNF is registered trademark of Synopsys Inc. All other product names mentioned herein are trademarks and/or registered trademarks of their
respective owners.
For additional information about EEA ASIC products and services, or to discuss a solution tailored to your specific requirements, call your local
EEA sales office or contact the factory.
Corporate Headquarters Northeast Regional Southeast Regional Central Regional
Northwest Regional Sales Office Sales Office Sales Office
Sales Office & Design Center 301 Edgewater Place, Suite 120, 4300 Six Forks Road, Suite 430, 1450 E. American Lane, #1550
150 River Oaks Parkway Wakefield, MA 01880 Raleigh, NC 27609 Schaumburg, IL 60173
San Jose, CA 95134 Phone: (617)246-3600 Phone: (919)781-7667 Phone: (847)517-7667
Phone: (408)922-0200 Fax: (617)246-5443 Fax: (919)781-6778 Fax: (847)517-7601
Fax: (408)922-0238
http://www.eea.epson.com