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MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/
V540GM/B90543G(S)/547G(S)/548G(S)/F548GL(S)
CMOS F2MC-16LX MB90540G/545G
Series 16-bit Proprietary Microcontroller
Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600
Document Number: 002- 07696 Rev. *A Revised 2016 November 30
The MB90540G/545G series with FULL-CAN and Flash ROM is specially designed for automotive and industrial applications. Its
main features are on-board CAN Interfaces (MB90540G series: 2 channels, MB90545G series: 1 channel) , which conform to CAN
V2.0A and V2.0B specifications, sup porting very flexible messa ge buffer scheme and so offering more functions than a normal full
CAN approach. The instruction set by F2MC-16LX CPU core inherits an AT architecture of the F2MCfamily with additional instruction
sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipula-
tion instructions.The micro controller has a 32-bit accumulator for processing long word data.The MB90540G/545G series has
peripheral resources of 8/10-bit A/D converters, UART (SCI) , extended I/O serial interfaces, 8/16-bit timer, I/O timer (input capture
(ICU) , output compare (OCU) ) .
Features
Clock
Embedded PLL clock multiplication circuit
Operating clock (PLL clock) can be selected from : divided-
by-2 of oscillation or one to four times the oscil lation
Minimum instruction execution time : 62.5 ns (operation at
oscillation of 4 MHz, PLL four times multiplied :
machine clock 16 MHz and at operating VCC = 5.0 V)
Subsystem Clock : 32 kHz
Instruction set to optimize controller applications
Rich data types (bit, byte, word, long word)
Rich addressing mode (23 types)
Enhanced signed multiplication/division instruction and
RETI instruction functions
Enhanced precision calculation realized by the 32-bit
accumulator
Instruction set designed for high level language (C
language) and multi-task ope rations
Adoption of system stack pointer
Enhanced pointer indirect instructions
Barrel shift instructions
Program patch function (for two address pointers)
Enhanced execution speed : 4-byte Instruction queue
Enhanced interrupt function : 8 leve ls, 34 factors
Automatic data transmission function independent of CPU
operation
Extended intelligent I/O service function (EI2OS)
Embedded ROM size and types
MASK ROM : 256 Kbytes / 64 Kbytes / 128 Kbytes
Flash ROM : 128 Kbytes/256 Kbytes
Embedded RAM size : 2 Kbytes/4 Kbytes/6 Kbytes/8 Kbytes
(evaluation chip)
Flash ROM
Supports automatic programming, Embedded Algorithm
Write/Erase/Erase-Suspend/Resume commands
A flag indicati ng completion of the algorithm
Hard-wired reset vector available in order to point to a fixed
boot sector in Flash Memory
Erase can be performed on each block
Block protection with external programming voltage
Low-power consumption (stand-by) mode
Sleep mode (mode in which CPU operating clock is
stopped)
Stop mode (mode in which oscillation is stopped)
CPU intermittent operation mode
Watch mode
Hardware stand-by mode
Process
0.5 m CMOS technology
I/O port
General-purpose I/O ports : 81 ports
T imer
Watchdog timer : 1 channel
8/16-bit PPG timer : 8/16-bit 4 channels
16-bit reload timer : 2 channels
16-bit I/O timer
16-bit free-run timer : 1 channel
Input capture : 8 channels
Output compare : 4 channels
Extended I/O serial interface : 1 channel
UART0
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized (with start/stop
bit) transmission can be selectively used.
UART 1 (SCI)
With full-duplex double buffer (8-bit length)
Clock asynchronized or clock synchronized serial (extended
I/O serial) can be used.
External interrupt circuit (8 channels)
A modul e for star ting an extended intelligent I/O service
(EI2OS) and generating an external interrupt which is
triggered by an external input.
Delayed interrupt generation module
Generates an interrupt request for switching tasks.
8/10-bit A /D converter (8 channels)
8/10-bit resolution can be selectively used.
Document Number: 002- 07696 Rev. *A Page 2 of 70
MB90540G/545G Series
Starting by an external trigger input.
Conversion time : 26.3 s
FULL-CAN interfaces
MB90540G series : 2 channels
MB90545G series : 1 channel
Conforming to Versi on 2.0 Part A and Part B
Flexible message buffering (mailbox and FIFO buffering can
be mixed)
External bus interface : Maximum address space 16 Mbytes
Package: QFP-100, LQFP-100
Document Number: 002- 07696 Rev. *A Page 3 of 70
MB90540G/545G Series
Contents
Features..............................................................................1
Product Lineup..................................................................4
Pin Assignment .................................................................7
Pin Description..................................................................9
I/O Circuit Type................................................................14
Handling Devices.............................................................17
Block Diagram .................................................................21
Memory Map.......................... .............. .............. .............. .22
I/O Map..............................................................................23
CAN Controller................ .............. .............. .............. .......29
Interrupt Map....................................................................35
Electrical Characteristics............ .. ... .............. ... ... ...........37
Example Characteristics.......... .......................................61
Ordering Information.......................................................66
Package Dimensions.......................................................67
Major Changes.................................................................69
Document History....... .............. .............. .............. ...........69
Sales, Solutions, and Legal Information.......................70
Document Number: 002- 07696 Rev. *A Page 4 of 70
MB90540G/545G Series
1. Product Lineup
(Continued)
Features MB90F543G (S) /F548G (S)
MB90F549G (S) /F546G (S)
MB90F548GL(S)
MB90543G (S)
MB90547G (S)
MB90548G (S)
MB90549G (S) MB90V540G
CPU F2MC-16LX CPU
System cloc k On-chip PLL clock multiplier (1, 2, 3, 4, 1/2 when PLL stop)
Minimum instruction exection time : 62.5 ns (machine clock 16MHz, 4MHz osc. four times multiplied by PLL)
ROM
Flash memory
MB90F543G(S)/F548G(S) / F548GL(S)
: 128 Kbytes
MB90F549G(S)/F546G(S ) :
256 Kbytes
MASK ROM :
MB90547G(S): 64 Kbytes
MB90543G(S)/548G(S): 128
Kbytes
MB90549G(S): 256 Kbytes
External
RAM
MB90F548G(S)/F548GL(S):
4 Kbytes
MB90F543G (S) /F549G(S) :
6 Kbytes
MB90F546G(S) : 8 Kbytes
MB90547G(S): 2 Kbytes
MB90548G(S): 4 Kbytes
MB90543G(S)/549G(S):
6 Kbytes
8 Kbytes
Clocks
MB90F543G/F548G/F549G/F546G/
F548GL :
Two clocks system
MB90F543GS/F548GS/F549GS/
F546GS/F548GLS :
One clock system
MB90543G/547G/548G/549G :
Two clocks system
MB90543GS/547GS/548GS/
549GS :
One clock system
Two clocks system*1
Operating voltage range *3
Temperature range 40 C to 105 C
Package QFP100, LQFP100 PGA-256
Emulator-specify
power supply*2 None
UART0
Full duplex double buffer
Support asynchronous/synchronous (with start/stop bit) transfer
Baud rate : 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous)
500 K/1 M/2 Mbps (synchronous) at System clock 16 MHz
UART1
(SCI)
Full duplex double buffer
Asynchronous (start-stop synchronized) and CLK-synchronous communication
Baud rate : 1202/2404/4808/9615/19230/31250/38460/62500 bps (asynchronous)
62.5 K/125 K/250 K/500 K/1 M/2 Mbps (synchronous) at 6, 8, 10, 12, 16 MHz
Serial I/O
Transfer can be started from MSB or LSB
Supports internal clock synchronized transfer and external clock synchronized transfer
Supports positive-edge and nagative-edge clock synchronization
Baud rate : 31.25 K/62.5 K/125 K/500 K/1 Mbps at System clock 16 MHz
A/D Converter 10-bit or 8-bit resolution
8 input channels
Conversion time : 26.3 s (per one channel)
Document Number: 002- 07696 Rev. *A Page 5 of 70
MB90540G/545G Series
*1 : If the one clock system is used, equip X0A and X1A with clocks from the tool side.
Features MB90F543G (S) /F548G (S)
MB90F549G (S) /F546G (S)
MB90F548GL(S)
MB90543G (S)
MB90547G (S)
MB90548G (S)
MB90549G (S) MB90V540G
16-bit Reload Timer
(2 channels)
Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys System clock frequency)
Supports External Event Count function
Signals an interrupt when overflow
16-bit Free-run Timer Supports Timer Clear when a match with Output Compare (Channel 0)
Operation clock freq. : fsys/22, fsys/24, fsys/26, fsys/28 (fsys System clock freq.)
16-bit Output Compare
(4 channels)
Signals an interrupt when a match with 16-bit Free-run Timer
Four 16-bit compare registers
A pair of compare registers can be used to generate an output signal
16-bit Input Capture
(8 channels)
Rising edge, falling edge or rising & falling edge sensitive
Four 16-bit Capture registers
Signals an interrupt upon external event
8/16-bit
Programmable
Pulse Generator
(4 channels)
Supports 8-bit and 16-bit operation modes
Eight 8-bit reload counters
Eight 8-bit reload registers for L pulse width
Eight 8-bit reload registers for H pulse width
A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit
reload counter
4 output pins
Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc 4 MHz
(fsys System clock frequency, fosc Oscillation clock frequency)
CAN Interface
MB90540G series
: 2 channels
MB90545G series
: 1 channel
Conforms to CAN Specification Version 2.0 Part A and B
Automatic re-transmission in case of error
Automatic transmission responding to Remote Frame
Prioritized 16 massage buffers for data and ID’s supports multipe massages
Flexible configuration of acceptance filtering :
Full bit compare/Full bit mask/Two partial bit masks
Supports up to 1 Mbps
32 kHz Sub-clock Sub-clock for low power operation
External Interrupt
(8 channels) Can be programmed edge sensitive or level sensitive
External bus
interface External access using the selectable 8-bit or 16-bit bus is enabled
(external bus mode.)
I/O Ports
Virtually all external pins can be used as general purpose I/O
All push-pull outputs and schmitt trigger inputs
Bit-wise programmable as input/outpu t or peripheral signal
Sub-clock for 32 kHz Sub clock low power operation
Flash Memory
Supports automatic programming, Embeded Algorithm
Write/Erase/Erase-Suspend/Erase-Resume commands
A flag indicating completion of the algorithm
Number of erase cycles : 10,000 times
Data retention time : 10 years
Boot block configuration
Erase can be performed on each block
Block protection by externally programmed voltage
Document Number: 002- 07696 Rev. *A Page 6 of 70
MB90540G/545G Series
*2 : It is setting of DIP switch S2 when Emulation pod (MB2145-507) is used.Please refer to the MB2145-507 hardware manual (2.7
Emulator-specific Power Pin) abo ut details.
*3 : Operating V oltage Range
Products Operation guarantee range
MB90F543G(S)/F546G(S)/F548G(S)/
MB90549G(S)/F549G(S)/V540/V540G 4.5 V to 5.5 V
MB90F548GL(S)/543G(S)/547G(S)/548G(S) 3.5 V to 5.5 V
Document Number: 002- 07696 Rev. *A Page 7 of 70
MB90540G/545G Series
2. Pin Assignment
(TOP VIEW)
(FPT-100P-M06)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
X0A
X1A
PA0
RST
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
HST
MD2
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P20/A16
P21/A17
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL/WR
P33/WRH
P34/HRQ
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
VCC
P45/SOT1
P46/SOT2
P47/SCK2
C
P50/SIN2
P51/INT4
P52/INT5
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
P53/INT6
P54/INT7
P55/ADTG
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
Document Number: 002- 07696 Rev. *A Page 8 of 70
MB90540G/545G Series
(TOP VIEW)
(FPT-100P-M20)
P22/A18
P23/A19
P24/A20
P25/A21
P26/A22
P27/A23
P30/ALE
P31/RD
VSS
P32/WRL/WR
P34/HRQ
P33/WRH
P35/HAK
P36/RDY
P37/CLK
P40/SOT0
P41/SCK0
P42/SIN0
P43/SIN1
P44/SCK1
VCC
P45/SOT1
P46/SOT2
P47/SCK2
C
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P97/RX1
P96/TX1
P95/RX0
P94/TX0
P93/INT3
P92/INT2
P91/INT1
P90/INT0
P87/TOT1
P86/TIN1
P85/OUT1
P84/OUT0
P83/PPG3
P82/PPG2
P81/PPG1
P80/PPG0
P77/OUT3/IN7
P76/OUT2/IN6
P75/IN5
P74/IN4
P73/IN3
P72/IN2
P71/IN1
P70/IN0
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
P21/A17
P20/A16
P17/AD15
P16/AD14
P15/AD13
P14/AD12
P13/AD11
P12/AD10
P11/AD09
P10/AD08
P07/AD07
P06/AD06
P05/AD05
P04/AD04
P03/AD03
P02/AD02
P01/AD01
P00/AD00
VCC
X1
X0
VSS
X0A
X1A
PA0
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P50/SIN2
P51/INT4
P52/INT5
P53/INT6
P54/INT7
P55/ADTG
AVCC
AVRH
AVRL
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P56/TIN0
P57/TOT0
MD0
MD1
MD2
HST
Document Number: 002- 07696 Rev. *A Page 9 of 70
MB90540G/545G Series
3. Pin Description
(Continued)
Pin No. Pin name Circuit type Function
LQFP*2 QFP*1
80
81 82
83 X0
X1 A
(Oscillation) High speed crystal oscillator input pins
78 80 X0A A
(Oscillation)
Low speed crystal oscillator input pins. For the one clock system parts,
perfom external pull-down processing.
77 79 X1A Low speed crystal oscillator input pins. For the one clock system parts, leave
it open.
75 77 RST B External reset request input pin
50 52 HST C Hardware standby input pin
83 to 90 85 to 92 P00 to P07 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
AD00 to AD07 I/O pins for 8 lower bits of the external address/data bus. This function is
enabled when the external bus is enabled.
91 to 98 93 to 100 P10 to P17 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
AD08 to AD15 I/O pins for 8 higher bits of the external address/data bus. This function is
enabled when the external bus is enabled.
99 to 6 1 to 8
P20 to P27
I
General I/O port with programmable pullup. In external bus mode, this
function is valid when the corresponding bits in the external address output
control resister (HACR) are set to “1”.
A16 to A23 8-bit I/O pins for A16 to A23 at the external address/data bus. In external bus
mode, this function is valid when the corresponding bits in the external
address output control resister (HACR) are set to “0”.
79P30 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
ALE Address latch enable output pin. This function is enabled when the external
bus is enabled.
810
P31 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode.
RD Read strobe output pin for the data bus. This function is enabled when the
external bus is enabled.
10 12
P32
I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the WR/WRL pin output is disabled.
WRL Write strobe output pin for the data bus. This function is enabled when both
the external bus and the WR/WRL pin output are enabled. WRL is write-
strobe output pin for the lower 8 bits of the data bus in 16-bit access. WR is
write-strobe output pin for the 8 bits of the data bus in 8-bit access.
WR
Document Number: 002- 07696 Rev. *A Page 10 of 70
MB90540G/545G Series
(Continued)
Pin No. Pin name Circuit type Function
LQFP*2 QFP*1
11 13
P33
I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode, external bus 8-bit mode or when WRH pin output is disabled.
WRH Write strobe output pin for the 8 higher bits of the data bus. This function is
enabled when the external bus is enabled, when the external bus 16-bit mode
is selected, and when the WRH output pin is enabled.
12 14 P34 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the hold function is disabled.
HRQ Hold request input pin. This function is enabled when both the external bus
and the hold functions are enabled.
13 15 P35 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the hold function is disabled.
HAK Hold acknowledge output pin. This function is enabled when both the external
bus and the hold functions are enabled.
14 16 P36 I
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the external ready function is disabled.
RDY Ready input pin. This function is enabled when both the external bus and the
external ready functions are enabled.
15 17 P37 H
General I/O port with programmable pullup. This function is enabled in the
single-chip mode or when the CLK output is disabled.
CLK CLK output pin. This function is enabled when both the external bus and CLK
outputs are enabled.
16 18 P40 G
General I/O port. This function is enabled when UART0 disables the serial
data output.
SOT0 Serial data output pin for UART0. This function is enabled when UART0
enables the serial data output.
17 19 P41 G
General I/O port. This function is enabled when UART0 disables serial clock
output.
SCK0 Serial clock I/O pin for UART0. This function is enabled when UART0 enables
the serial clock output.
18 20 P42 GGeneral I/O port. This function is always enabled.
SIN0 Serial data input pin for UART0. Set the corresponding Port
Direction Register to input if this function is used.
19 21 P43 GGeneral I/O port. This function is always enabled.
SIN1 Serial data input pin for UART1. Set the corresponding Port
Direction Register to input if this function is used.
Document Number: 002- 07696 Rev. *A Page 11 of 70
MB90540G/545G Series
(Continued)
Pin No. Pin name Circuit type Function
LQFP*2 QFP*1
20 22 P44 G
General I/O port. This function is enabled when UART1 disables the clock
output.
SCK1 Serial clock pulse I/O pin for UART1. This function is enabled when UART1
enables the serial clock output.
22 24 P45 G
General I/O port. This function is enabled when UART1 disables the serial
data output.
SOT1 Serial data output pin for UART1. This function is enabled when UART1
enables the serial data output.
23 25 P46 G
General I/O port. This function is enabled when the Extended I/O serial
interface disables the serial data output.
SOT2 Serial data output pin for the Extended I/O serial interface. This function is
enabled when the Extended I/O serial interface enables the serial data output.
24 26
P47
G
General I/O port. This function is enabled when the Extended I/O serial
interface disables the clock output.
SCK2 Serial clock pulse I/O pin for the Extended I/O serial interface . This function is
enabled when the Extended I/O serial interface enables the Serial clock
output.
26 28 P50 DGeneral I/O port. This function is always enabled.
SIN2 Serial data input pin for the Extended I/O serial interface . Set the
corresponding Port Direction Register to input if this function is used.
27 to 30 29 to 32 P51 to P54 DGeneral I/O port. This function is always enabled.
INT4 to INT7 External interrupt request input pins for INT4 to INT7. Set the corresponding
Port Direction Register to input if this function is used.
31 33 P55 DGeneral I/O port. This function is always enabled.
ADTG Trigger input pin for the A/D converter. Set the corresponding Port Direction
Register to input if this function is used.
36 to 39 38 to 41 P60 to P63 E
General I/O port. This function is enabled when the analog input enable
register specifies a port.
AN0 to AN3 Analog input pins for the 8/10-bit A/D converter . This function is enabled when
the analog input enable register specifies A/D.
41 to 44 43 to 46 P64 to P67 E
General I/O port. The function is enabled when the analog input enable
register specifies a port.
AN4 to AN7 Analog input pins for the 8/10-bit A/D converter . This function is enabled when
the analog input enable register specifies A/D.
45 47 P56 DGeneral I/O port. This function is always enabled.
TIN0 Event input pin for the 16-bit reload timers 0. Set the corresponding Port
Direction Register to input if this function is used.
Document Number: 002- 07696 Rev. *A Page 12 of 70
MB90540G/545G Series
(Continued)
Pin No. Pin name Circuit type Function
LQFP*2 QFP*1
46 48 P57 D
General I/O port. This function is enabled when the 16-bit reload timers 0
disables the output.
TOT0 Output pin for the 16-bit reload timers 0. This function is enabled when the
16-bit reload timers 0 enables the output.
51 to 56 53 to 58
P70 to P75
D
General I/O ports. This function is always enabled.
IN0 to IN5 Trigger input pins for input captures ICU0 to ICU5. Set the corresponding
Port Direction Register to input if this
function is used.
57 , 58 59 , 60
P76 , P77
D
General I/O ports. This function is enabled when the OCU disables the
waveform output.
OUT2 , OUT3 Event output pins for output compares OCU2 and OCU3. This function is
enabled when the OCU enables the waveform output.
IN6 , IN7 Trigger input pins for input captures ICU6 and ICU7. Set the corresponding
Port Direction Register to input and disable the OCU waveform output if this
function is used.
59 to 62 61 to 64 P80 to P83 D
General I/O ports. This function is enabled when 8/16-bit PPG disables the
waveform output.
PPG0 to PPG3 Output pins for 8/16-bit PPGs. This function is enabled when 8/16-bit PPG
enables the waveform output.
63 , 64 65 , 66 P84 , P85 D
General I/O ports. This function is enabled when the OCU disables the
waveform output.
OUT0 , OUT1 W aveform output pins for output compares OCU0 and OCU1. This function is
enabled when the OCU enables the waveform output.
65 67 P86 DGeneral I/O port. This function is always enabled.
TIN1 Input pin for the 16-bit reload timers 1. Set the corresponding Port Direction
Register to input if this function is used.
66 68 P87 D
General I/O port. This function is enabled when the 16-bit reload timers 1
disables the output.
TOT1 Output pin for the 16-bit reload timers 1.This function is enabled when the 16-
bit reload timers 1 enables the output.
67 to 70 69 to 72 P90 to P93 DGeneral I/O port. This function is always enabled.
INT0 to INT3 External interrupt request input pins for INT0 to INT3. Set the corresponding
Port Direction Register to input if this function is used.
71 73 P94 DGeneral I/O port. This function is enabled when CAN0 disables the output.
TX0 TX output pin for CAN0. This function is enabled when CAN0 enables the
output.
Document Number: 002- 07696 Rev. *A Page 13 of 70
MB90540G/545G Series
(Continued)
*1 : FPT-100P-M06
*2 : FPT-100P-M20
Pin No. Pin name Circuit type Function
LQFP*2 QFP*1
72 74 P95 DGeneral I/O port. This function is always enabled.
RX0 RX input pin for CAN0 Interface. When the CAN function is used, output from
the other functions must be stopped.
73 75 P96 DGeneral I/O port. This function is enabled when CAN1 disables the output.
TX1 TX output pin for CAN1. This function is enabled when CAN1 enables the
output (only MB90540G series) .
74 76 P97 DGeneral I/O port. This function is always enabled.
RX1 RX input pin for CAN1 Interface. When the CAN function is used, output from
the other functions must be stopped (only MB90540G series) .
76 78 PA0 D General I/O port. This function is always enabled.
32 34 AVCC Power
supply Power supply pin for the A/D Converter . This power supply must be turned on
or off while a voltage higher than or equal to AVCC is applied to VCC.
35 37 AVSS Power
supply Power supply pin for the A/D Converter.
33 35 AVRH Power
supply
External reference voltage input pin for the A/D Converter. This power supply
must be turned on or off while a voltage higher than or equal to AVRH is
applied to AVCC.
34 36 AVRL Power
supply External reference voltage input pin for the A/D Converter.
47, 48 49, 50 MD0, MD1 C Input pins for specifying the operating mode. The pins must be directly
connected to VCC or VSS.
49 51 MD2 F Input pin for specifying the operating mode. The pin must be directly
connected to VCC or VSS.
25 27 C Power supply stabilization capacitor pin. It should be connected externally to
an 0.1 F ceramic capacitor.
21, 82 23, 84 VCC Power
supply Input pin for power supply (5.0 V) .
9, 40, 79 11, 42, 81 VSS Power
supply Input pin for power supply (0.0 V) .
Document Number: 002- 07696 Rev. *A Page 14 of 70
MB90540G/545G Series
4. I/O Circuit Type
(Continued)
Circuit type Diagram Remarks
A
High-speed oscillation feedback resistor :
1 M approx.
Low-speed oscillation feedback re sistor:
10 M approx.
B
CMOS Hysteresis input
Pull-up resistor : 50 k approx.
C
CMOS Hysteresis input
D
CMOS level output
CMOS Hysteresis input
Standby control signal
X1, X1A
X0, X0A
R
R (Pull-up) CMOS
Hysteresis input
RCMOS
Hysteresis input
R
P-ch
N-ch
CMOS
Hysteresis input
V
CC
Document Number: 002- 07696 Rev. *A Page 15 of 70
MB90540G/545G Series
(Continued)
Circuit type Diagram Remarks
E
CMOS level output
CMOS Hysteresis input
Analog input
F
CMOS Hysteresis input
Pull-down Resistor : 50 k approx.
(except Flash devices)
G
CMOS level output
CMOS Hysteresis input
TTL level input (Flash devices in
Flash writ er mode only)
R
VCC P-ch
N-ch
CMOS
Hysteresis input
Analog input
P-ch
N-ch
R
R (Pull-down)
CMOS
Hysteresis input
R
V
CC
P-ch
N-ch
RT
CMOS
Hysteresis inp
ut
TTL level inp
ut
Document Number: 002- 07696 Rev. *A Page 16 of 70
MB90540G/545G Series
(Continued)
Circuit type Diagram Remarks
H
CMOS level output
CMOS Hysteresis input
Programmable pu l l- up resi st or :
50 k approx.
I
CMOS level output
CMOS Hysteresis input
TTL level input (Flash devices in
Flash writ er mode only)
Programmable pullup resistor :
50 k approx.
VCC
P-chP-ch
N-ch
V
CC
CMOS
Hysteresis inp
ut
CNTL
R
R
VCC
P-ch
P-ch
N-ch
RT
VCC CNTL
CMOS
Hysteresis input
TTL level input
Document Number: 002- 07696 Rev. *A Page 17 of 70
MB90540G/545G Series
5. Handling Devices
(1) Preventing latch-up
CMOS IC chips may suffer latch-up under the following conditions :
A voltage higher than VCC or lower than VSS is applied to an input or output pin.
A voltage higher than the rated voltage is applied between VCC and VSS.
The AVcc power supply is applied before the VCC voltage.
Latch-up may increase the power supply current drastically, causi ng thermal damage to the device.
For the same reason, care mus t also be taken in not all owing the analog pow er-supply voltage (AVCC, AVRH) to exceed the digital
power-supply voltage.
(2) Handling unused pins
Leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. Therefor they
must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k.
Unused bi-di rectional pins shoul d be set to the output state and can be l eft open, or the input state w ith the above described
connection.
(3) Using external clock
To use external clock, drive X0 pin only and leave X1 pin unconnected.
Below is a diagram of how to use external clock.
(4) Use of the sub-clock
Use one clock system parts when the sub-clock is not used. In that case, pull-down the pin X0A and leave th e pin X1A open. When
using two clock system parts, a 32 kHz oscillator has to be connected to the X0A and X1A pins.
(5) Power supply pins (VCC/VSS)
In products with multiple VCC or VSS pins, the pins of a same potential are internally connected in the device to avoid abnormal
operations including latch-up. However you must connect the pins to an external power and a ground line to lower the electro-
magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the
total current rating.
Make sure to connect VCC and VSS pins via the lowest impedance to power lines.
It is recommended to provide a bypass capacitor of around 0.1 F between VCC and VSS pins near the device.
X0
X1
MB90540G/545G Series
Open
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
MB90540G/545G
Series
Document Number: 002- 07696 Rev. *A Page 18 of 70
MB90540G/545G Series
(6) Pull-up/down resistors
The MB90540G/545G Series does no t support internal pull-up /down resistors (except Port0 Port3 : pull-up resistors) . Use
external components where needed.
(7) Crystal Oscillator Circuit
Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via the
shortest distances from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort,
that lines of oscillation circuits do not cross the lines of other circuits.
It is highly recommended to provide a printed circuit board artwork surrounding X0 and X1 pins with a ground area for stabilizing the
operation.
(8) Turning-on Sequen ce of Power Supply to A/D Converter and Analog Inputs
Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN7) after turning-on the
digital power supply (VCC) .
Turn-off the digital power after turn ing off the A/D converter supp ly and an alog inputs. In this ca se, make sure that the voltage doe s
not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable) .
(9) Connection of Unused Pins of A/D Converter
Connect unused pins of A/D converter to AVCC VCC, AVSS AVRH VSS.
(10) N.C. Pin
The N.C. (internally connect ed) pin must be opened for use.
(11) Notes on Energization
To prevent the internal regulator circuit fro m malfunctioni ng, set the voltage rise time during energization at 50 s or more (0.2 V to
2.7 V) .
Document Number: 002- 07696 Rev. *A Page 19 of 70
MB90540G/545G Series
(12) Indeterminate outputs from ports 0 and 1 (MB90V540G only)
During oscillation setting time of step-down circuit (during a power-on reset) after the power is turned on, the outputs from ports 0
and 1 become following state.
If RST pin is “H”, the outputs become inde terminate.
If RST pin is “L”, the outputs become high-impedance.
Pay attention to the port output timing shown as follow.
Oscillation setting time*2
Power-on reset*1
Period of indeterminated
VCC (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal
*1 : Power-on reset time : “Period of clock frequency” 217 (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : “Period of clock frequency” 218 (Clock frequency of 16 MHz : 16.38 ms)
RST pin is “H”
Document Number: 002- 07696 Rev. *A Page 20 of 70
MB90540G/545G Series
(13) Initialization
In the device, there are internal registe rs which are ini tialized only by a power-o n reset. To initialize these regi sters, please turn on
the power again.
(14) Directions of “DIV A, Ri” and “DIVW A, RWi” instructions
In the Signed multiplication and divisio n instructions (“DIV A, Ri” and “DIVW A, RWi”) , the value of the corresponding ban k register
(DTB, ADB, USB, SSB) is set in “00H”.
If the values of the corresponding bank registers (DTB, ADB, USB, SSB) are set to other than “00H”, the remainder by the execution
result of the instruction is not stored in the register of the instruction operand.
(15) Using REALOS
The use of EI2OS is not possible with the REALOS real time operating system.
(16) Caution on Operations during PLL Clock Mode
If the PLL clock mode is selected, the microcontroller attempt to be working with the self-os cillating circuit even when there is no
external oscillator or external clock input is stopped. Performance of this operation, however, cannot be guaranteed.
Oscillation setting time*2
Power-on reset*1
VCC (Power-supply pin)
PONR (power-on reset) signal
RST (external asynchronous reset) signal
RST (internal reset) signal
Oscillation clock signal
KA (internal operation clock A) signal
KB (internal operation clock B) signal
PORT (port output) signal High-impedance
*1 : Power-on reset time : “Period of clock frequency” 217 (Clock frequency of 16 MHz : 8.19 ms)
*2 : Oscillation setting time : “Period of clock frequency” 218 (Clock frequency of 16 MHz : 16.38 ms)
RST pin is “L”
Document Number: 002- 07696 Rev. *A Page 21 of 70
MB90540G/545G Series
6. Block Diagram
X0, X1
SOT0
SCK0
SIN0
SOT1
SCK1
SIN1
SOT2
SCK2
SIN2
AVCC
AVSS
AN0 to AN7
AVRH
AVRL
ADTG
X0A, X1A
RST
HST
F2MC 16LX
CPU
FMC-16 Bus
IN0 to IN5
IN6/OUT2,
IN7/OUT3
OUT0, OUT1
TIN0, TIN1
AD00 to AD15
A16 to A23
ALE
RD
WRL
WRH
HRQ
HAK
RDY
CLK
INT0 to INT7
TOT0, TOT1
RX0, RX1 *
TX0, TX1 *
PPG0 to PPG3
Clock
Controller
RAM
2 K/4 K/6 K/8 K
ROM/Flash
128 K/256 K/
64K(ROM only)
Prescaler
UART0
UART1
(SCI)
Prescaler
Serial I/O
10-bit A/D
Converter
8 ch.
Prescaler
16-bit
Free-run
Timer
16-bit Input
Capture
8 ch.
16-bit Output
Compare
4 ch.
8/16-bit
PPG
4 ch.
CAN
Controller
16-bit Reload
Timer 2 ch.
External
Bus
Interface
External
Interrupt
8 ch.
* : Only the MB90540G series has two channels
Document Number: 002- 07696 Rev. *A Page 22 of 70
MB90540G/545G Series
7. Memory Map
The memory space of the MB90540G/545G Series is shown below.
Note : The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective .
Since the low-order 16 bits address are the same, the table in ROM can be referenced without using the “far” specification in
the pointer declaration.
For example, an attempt to access 00C000H accesses the value at FFC000H in ROM.The ROM are a in ba nk FF exce ed s 48
Kbytes, and its entire image cannot be shown in bank 00.The image between FF4000H and FFFFFFH is visible in bank 00,
while the image between FF0000H and FF3FFFH is visible only in bank FF.
MB90V540G/
F546G (S)
FFFFFF
H
FEFFFF
H
FF0000
H
FDFFFF
H
FE0000
H
FCFFFF
H
FD0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
0020FF
H
001FF5
H
001FF0
H
000100
H
0000BF
H
000000
H
FC0000
H
ROM
(FF bank)
ROM
(FE bank)
ROM
(FD bank)
ROM
(FC bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 8 K
External
Peripheral
ROM correction
MB90543G(S)
F543G(S)
FFFFFF
H
FEFFFF
H
FF0000
H
FE0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002000
H
0018FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 6 K
External
Peripheral
MB90548G(S)
MB90F548GL(S)
MB90F548G (S)
FFFFFF
H
FEFFFF
H
FF0000
H
FE0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002000
H
0010FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 4 K
External
Peripheral
MB90549G (S) /
F549G (S)
FDFFFF
H
FCFFFF
H
FD0000
H
FC0000
H
ROM
(FD bank)
ROM
(FC bank)
FFFFFF
H
FEFFFF
H
FF0000
H
FE0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002100
H
0018FF
H
000100
H
0000BF
H
000000
H
ROM
(FF bank)
ROM
(FE bank)
External
ROM
(Image of
FF bank)
Peripheral
External
RAM 6 K
External
Peripheral
FFFFFF
H
FF0000
H
00FFFF
H
004000
H
003FFF
H
003900
H
002000
H
0008FF
H
000100
H
0000BF
H
ROM
(FF bank)
ROM
(Image of
FF bank)
Peripheral
External
RAM 2 K
External
Peripheral
MB90547G (S)
000000
H
External
Document Number: 002- 07696 Rev. *A Page 23 of 70
MB90540G/545G Series
8. I/O Map
(Continued)
Address Register Abbreviation Access Resource name Initial value
00HPort 0 data register PDR0 R/W Port 0 XXXXXXXXB
01HPort 1 data register PDR1 R/W Port 1 XXXXXXXXB
02HPort 2 data register PDR2 R/W Port 2 XXXXXXXXB
03HPort 3 data register PDR3 R/W Port 3 XXXXXXXXB
04HPort 4 data register PDR4 R/W Port 4 XXXXXXXXB
05HPort 5 data register PDR5 R/W Port 5 XXXXXXXXB
06HPort 6 data register PDR6 R/W Port 6 XXXXXXXXB
07HPort 7 data register PDR7 R/W Port 7 XXXXXXXXB
08HPort 8 data register PDR8 R/W Port 8 XXXXXXXXB
09HPort 9 data register PDR9 R/W Port 9 XXXXXXXXB
0AHPort A data register PDRA R/W Port A _ _ _ _ _ _ _XB
0BH to 0FHReserved
10HPort 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B
11HPort 1 direction register DDR1 R/W Port 1 0 0 0 0 0 0 0 0B
12HPort 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 0 0B
13HPort 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B
14HPort 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
15HPort 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
16HPort 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
17HPort 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B
18HPort 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
19HPort 9 direction register DDR9 R/W Port 9 0 0 0 0 0 0 0 0B
1AHPort A direction register DDRA R/W Port A _ _ _ _ _ _ _0B
1BHAnalog Input Enable register ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B
1CHPort 0 Pullup control register PUCR0 R/W Port 0 0 0 0 0 0 0 0 0B
1DHPort 1 Pullup control register PUCR1 R/W Port 1 0 0 0 0 0 0 0 0B
1EHPort 2 Pullup control register PUCR2 R/W Port 2 0 0 0 0 0 0 0 0B
1FHPort 3 Pullup control register PUCR3 R/W Port 3 0 0 0 0 0 0 0 0B
20HSerial Mode Control Register 0 UMC0 R/W
UART0
0 0 0 0 0 1 0 0B
21HSerial Status Register 0 USR0 R/W 0 0 0 1 0 0 0 0B
22HSerial input data register 0/
Serial output data register 0 UIDR0/UODR0 R/W XXXXXXXXB
23HRate and data register 0 URD0 R/W 0 0 0 0 0 0 0XB
Document Number: 002- 07696 Rev. *A Page 24 of 70
MB90540G/545G Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
24HSerial mode register 1 SMR1 R/W
UART1
0 0 0 0 0 0 0 0B
25HSerial control register 1 SCR1 R/W 0 0 0 0 0 1 0 0B
26HSerial input data register 1/
Serial output data register 1 SIDR1/SODR1 R/W XXXXXXXXB
27HSerial status register 1 SSR1 R/W 0 0 0 0 1_0 0B
28HUART1 prescaler control register CDCR R/W 0_ _ _1 1 1 1B
29HSerial Edge select register SES1 R/W _ _ _ _ _ _ _0B
2AHProhibited
2BHSerial I/O prescaler SCDCR R/W
Extended I/O
Serial Interface
0_ _ _1 1 1 1B
2CHSerial mode control register SMCS R/W _ _ _ _0 0 0 0B
2DHSerial mode control register SMCS R/W 0 0 0 0 0 0 1 0B
2EHSerial data register SDR R/W XXXXXXXXB
2FHSerial Edge select register SES2 R/W _ _ _ _ _ _ _0B
30HExternal interrupt enable register ENIR R/W
External Interrupt
0 0 0 0 0 0 0 0B
31HExternal interrupt request register EIRR R/W XXXXXXXXB
32HExternal interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B
33HExternal interrupt level register ELVR R/W 0 0 0 0 0 0 0 0B
34HA/D control status register 0 ADCS0 R/W
A/D Converter
0 0 0 0 0 0 0 0B
35HA/D control status register 1 ADCS1 R/W 0 0 0 0 0 0 0 0B
36HA/D data register 0 ADCR0 R XXXXXXXXB
37HA/D data register 1 ADCR1 R/W 0 0 0 0 1 _ XXB
38HPPG0 operation mode control register PPGC0 R/W 16-bit Programmable
Pulse
Generator 0/1
0 _ 0 0 0 _ _ 1B
39HPPG1 operation mode control register PPGC1 R/W 0 _ 0 0 0 0 0 1B
3AHPPG0/1 clock selection register PPG01 R/W 0 0 0 0 0 0 _ _B
3BHProhibited
3CHPPG2 operation mode control register PPGC2 R/W 16-bit Programmable
Pulse
Generator 2/3
0 _ 0 0 0 _ _1B
3DHPPG3 operation mode control register PPGC3 R/W 0 _ 0 0 0 0 0 1B
3EHPPG2/3 Clock Selection Register PPG23 R/W 0 0 0 0 0 0 _ _B
3FHProhibited
40HPPG4 operation mode control register PPGC4 R/W 16-bit Programmable
Pulse
Generator 4/5
0 _ 0 0 0 _ _ 1B
41HPPG5 operation mode control register PPGC5 R/W 0 _ 0 0 0 0 0 1B
42HPPG4/5 clock selection register PPG45 R/W 0 0 0 0 0 0 _ _B
43HProhibited
44HPPG6 operation mode control register PPGC6 R/W 16-bit Programmable
Pulse
Generator 6/7
0 _ 0 0 0 _ _ 1B
45HPPG7 operation mode control register PPGC7 R/W 0 _ 0 0 0 0 0 1B
46HPPG6/7 clock selection register PPG67 R/W 0 0 0 0 0 0 _ _B
Document Number: 002- 07696 Rev. *A Page 25 of 70
MB90540G/545G Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
47H to 4BHProhibited
4CHInput capture control status register 0/1 ICS01 R/W Input Capture 0/1 0 0 0 0 0 0 0 0B
4DHInput capture control status register 2/3 ICS23 R/W Input Capture 2/3 0 0 0 0 0 0 0 0B
4EHInput capture control status register 4/5 ICS45 R/W Input Capture 4/5 0 0 0 0 0 0 0 0B
4FHInput capture control status register 6/7 ICS67 R/W Input Capture 6/7 0 0 0 0 0 0 0 0B
50HTimer control status register 0 TMCSR0 R/W
16-bit Reload Timer 0
0 0 0 0 0 0 0 0B
51HTimer control status register 0 TMCSR0 R/W _ _ _ _ 0 0 0 0B
52HTimer register 0/reload register 0 TMR0/TMRLR0 R/W XXXXXXXXB
53HTimer register 0/reload register 0 TMR0/TMRLR0 R/W XXXXXXXXB
54HTimer control status register 1 TMCSR1 R/W
16-bit Reload Timer 1
0 0 0 0 0 0 0 0B
55HTimer control status register 1 TMCSR1 R/W _ _ _ _ 0 0 0 0B
56HTimer register 1/reload register 1 TMR1/TMRLR1 R/W XXXXXXXXB
57HTimer register 1/reload register 1 TMR1/TMRLR1 R/W XXXXXXXXB
58HOutput compare control status register 0 OCS0 R/W Output Compare 0/1 0 0 0 0 _ _ 0 0B
59HOutput compare control status register 1 OCS1 R/W _ _ _0 0 0 0 0B
5AHOutput compare control status register 2 OCS2 R/W Output Compare 2/3 0 0 0 0 _ _ 0 0B
5BHOutput compare control status register 3 OCS3 R/W _ _ _ 0 0 0 0 0B
5CH to 6BHProhibited
6CHTimer Data register TCDT R/W
I/O T imer
0 0 0 0 0 0 0 0B
6DHTimer Data register TCDT R/W 0 0 0 0 0 0 0 0B
6EHTimer Control register TCCS R/W 0 0 0 0 0 0 0 0B
6FHROM mirror function
selection register ROMM R/W ROM Mirror _ _ _ _ _ _ _ 1B
70H to 7FHReserved for CAN 0 Interface.
80H to 8FHReserved for CAN 1 Interface.
90H to 9DHProhibited
9EHProgram address detection
control status register PACSR R/W Address Match
Detection
Function 0 0 0 0 0 0 0 0B
9FHDelayed interrupt/release register DIRR R/W Delayed Interrupt _ _ _ _ _ _ _ 0B
A0HLow-power mode control register LPMCR R/W Low Power
Controller 0 0 0 1 1 0 0 0B
A1HClock selection register CKSCR R/W Low Power
Controller 1 1 1 1 1 1 0 0B
Document Number: 002- 07696 Rev. *A Page 26 of 70
MB90540G/545G Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
A2H to A4HProhibited
A5HAutomatic ready function select register ARSR W External Memory
Access
0 0 1 1 _ _ 0 0B
A6HExternal address output control register HACR W 0 0 0 0 0 0 0 0B
A7HBus control signal selection register ECSR W 0 0 0 0 0 0 0 _B
A8HWatchdog Timer control register WDTC R/W Watchdog Timer XXXXX 1 1 1B
A9HTime Base Timer Control register TBTC R/W Time Base Timer 1 - - 0 0 1 0 0B
AAHWatch timer control register WTC R/W Watch Timer 1 X 0 0 0 0 0 0B
ABH to ADHProhibited
AEHFlash memory control status register
(Flash only, otherwise reserved) FMCS R/W Flash Memory 0 0 0 X 0 0 0 0B
AFHProhibited
B0HInterrupt control register 00 ICR00 R/W
Interrupt
controller
0 0 0 0 0 1 1 1B
B1HInterrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
B2HInterrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
B3HInterrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
B4HInterrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B
B5HInterrupt control register 05 ICR05 R/W 0 0 0 0 0 1 1 1B
B6HInterrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
B7HInterrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1B
B8HInterrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1B
B9HInterrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
BAHInterrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
BBHInterrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
BCHInterrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
BDHInterrupt control register 13 ICR13 R/W 0 0 0 0 0 1 1 1B
BEHInterrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B
BFHInterrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B
C0H to FFHExternal
Address Register Abbreviation Access Resource name Initial value
1FF0HProgram address detection register 0 PADR0 R/W
Address Match
Detection Function
XXXXXXXXB
1FF1HProgram address detection register 0 PADR0 R/W XXXXXXXXB
1FF2HProgram address detection register 0 PADR0 R/W XXXXXXXXB
1FF3HProgram address detection register 1 PADR1 R/W XXXXXXXXB
1FF4HProgram address detection register 1 PADR1 R/W XXXXXXXXB
1FF5HProgram address detection register 1 PADR1 R/W XXXXXXXXB
Document Number: 002- 07696 Rev. *A Page 27 of 70
MB90540G/545G Series
(Continued)
Address Register Abbreviation Access Resource name Initial value
3900HReload L PRLL0 R/W
16-bit Programmable Pulse
Generator 0/1
XXXXXXXXB
3901HReload H PRLH0 R/W XXXXXXXXB
3902HReload L PRLL1 R/W XXXXXXXXB
3903HReload H PRLH1 R/W XXXXXXXXB
3904HReload L PRLL2 R/W
16-bit Programmable Pulse
Generator 2/3
XXXXXXXXB
3905HReload H PRLH2 R/W XXXXXXXXB
3906HReload L PRLL3 R/W XXXXXXXXB
3907HReload H PRLH3 R/W XXXXXXXXB
3908HReload L PRLL4 R/W
16-bit Programmable Pulse
Generator 4/5
XXXXXXXXB
3909HReload H PRLH4 R/W XXXXXXXXB
390AHReload L PRLL5 R/W XXXXXXXXB
390BHReload H PRLH5 R/W XXXXXXXXB
390CHReload L PRLL6 R/W
16-bit Programmable Pulse
Generator 6/7
XXXXXXXXB
390DHReload H PRLH6 R/W XXXXXXXXB
390EHReload L PRLL7 R/W XXXXXXXXB
390FHReload H PRLH7 R/W XXXXXXXXB
3910H to 3917HReserved
3918HInput Capture Register 0 IPCP0 R
Input Capture 0/1
XXXXXXXXB
3919HInput Capture Register 0 IPCP0 R XXXXXXXXB
391AHInput Capture Register 1 IPCP1 R XXXXXXXXB
391BHInput Capture Register 1 IPCP1 R XXXXXXXXB
391CHInput Capture Register 2 IPCP2 R
Input Capture 2/3
XXXXXXXXB
391DHInput Capture Register 2 IPCP2 R XXXXXXXXB
391EHInput Capture Register 3 IPCP3 R XXXXXXXXB
391FHInput Capture Register 3 IPCP3 R XXXXXXXXB
3920HInput Capture Register 4 IPCP4 R
Input Capture 4/5
XXXXXXXXB
3921HInput Capture Register 4 IPCP4 R XXXXXXXXB
3922HInput Capture Register 5 IPCP5 R XXXXXXXXB
3923HInput Capture Register 5 IPCP5 R XXXXXXXXB
3924HInput Capture Register 6 IPCP6 R
Input Capture 6/7
XXXXXXXXB
3925HInput Capture Register 6 IPCP6 R XXXXXXXXB
3926HInput Capture Register 7 IPCP7 R XXXXXXXXB
3927HInput Capture Register 7 IPCP7 R XXXXXXXXB
Document Number: 002- 07696 Rev. *A Page 28 of 70
MB90540G/545G Series
(Continued)
Read/write notation
Initial value notation
Note: Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results
in reading “X”.
Address Register Abbreviation Access Resource name Initial value
3928HOutput Compare Register 0 OCCP0 R/W
Output Compare 0/1
XXXXXXXXB
3929HOutput Compare Register 0 OCCP0 R/W XXXXXXXXB
392AHOutput Compare Register 1 OCCP1 R/W XXXXXXXXB
392BHOutput Compare Register 1 OCCP1 R/W XXXXXXXXB
392CHOutput Compare Register 2 OCCP2 R/W
Output Compare 2/3
XXXXXXXXB
392DHOutput Compare Register 2 OCCP2 R/W XXXXXXXXB
392EHOutput Compare Register 3 OCCP3 R/W XXXXXXXXB
392FHOutput Compare Register 3 OCCP3 R/W XXXXXXXXB
3930H to 39FFHReserved
3A00H to 3AFFHReserved for CAN 0 Interface.
3B00H to 3BFFHReserved for CAN 0 Interface.
3C00H to 3CFFHReserved for CAN 1 Interface.
3D00H to 3DFFHReserved for CAN 1 Interface.
3E00H to 3FFFHReserved
R/W : Reading and writing permitted
R : Read-only
W : Write-only
0 : Initial value is “0”.
1 : Initial value is “1”.
X : Initial value is undefined.
_ : Initial value is unused.
Document Number: 002- 07696 Rev. *A Page 29 of 70
MB90540G/545G Series
9. CAN Controller
The MB90540G series contains two CAN controllers (CAN0 and CAN1) , the MB90545G series contains only one (CAN0) . The Evaluation Chip
MB90V540G also has two CAN controllers.
The CAN controller has the following features :
Conforms to CAN Specification Version 2.0 Part A and B
❐Supports transmission/reception in st andard frame and extended frame formats
Supports transmission of data frames by receiving remote frames
16 transmitting/receiving message buffers
❐29-bit ID and 8-byte data
❐Multi-level message buffer configuration
Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance regi ster 1 for each message buffer as ID
acceptance mask
❐Two acceptance mask registers in either standard frame format or extende d frame formats
Bit rate programmable from 10 Kbps to 1 Mbps (when input cl ock is at 16 MHz)
List of Control Registers
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
000070H000080HMessage buffer valid register BVALR R/W 00000000 00000000B
000071H000081H
000072H000082HTransmit request register TREQR R/W 00000000 00000000B
000073H000083H
000074H000084HTransmit cancel register TCANR W 00000000 00000000B
000075H000085H
000076H000086HTransmit complete register TCR R/W 00000000 00000000B
000077H000087H
000078H000088HReceive complete register RCR R/W 00000000 00000000B
000079H000089H
00007AH00008AHRemote request receiving register RRTRR R/W 00000000 00000000B
00007BH00008BH
00007CH00008CHReceive overrun register ROVRR R/W 00000000 00000000B
00007DH00008DH
00007EH00008EHReceive interrupt enable register RIER R/W 00000000 00000000B
00007FH00008FH
Document Number: 002- 07696 Rev. *A Page 30 of 70
MB90540G/545G Series
(Continued)
List of Message Buffers (ID Registers )
Address Register Abbreviation Access Initial Value
CAN0 CAN1
003B00H003D00HControl status register CSR R/W, R 00---000 0----0-1B
003B01H003D01H
003B02H003D02HLast event indicator register LEIR R/W -------- 000-0000B
003B03H003D03H
003B04H003D04HReceive/transmit error counter register RTEC R 00000000 00000000B
003B05H003D05H
003B06H003D06HBit timing register BTR R/W -1111111 11111111B
003B07H003D07H
003B08H003D08HIDE register IDER R/W XXXXXXXX XXXXXXXXB
003B09H003D09H
003B0AH003D0AHTransmit RTR register TRTRR R/W 00000000 00000000B
003B0BH003D0BH
003B0CH003D0CHRemote frame receive waiting register RFWTR R/W XXXXXXXX XXXXXXXXB
003B0DH003D0DH
003B0EH003D0EHTransmit request enable register TIER R/W 00000000 00000000B
003B0FH003D0FH
003B10H003D10H
Acceptance mask select register AMSR R/W
XXXXXXXX XXXXXXXXB
003B11H003D11H
003B12H003D12HXXXXXXXX XXXXXXXXB
003B13H003D13H
003B14H003D14H
Acceptance mask register 0 AMR0 R/W
XXXXXXXX XXXXXXXXB
003B15H003D15H
003B16H003D16HXXXXX--- XXXXXXXXB
003B17H003D17H
003B18H003D18H
Acceptance mask register 1 AMR1 R/W
XXXXXXXX XXXXXXXXB
003B19H003D19H
003B1AH003D1AHXXXXX--- XXXXXXXXB
003B1BH003D1BH
Address Register Abbreviation Access Initial Value
CAN0 CAN1
003A00H
to
003A1FH
003C00H
to
003C1FH
General-purpose RAM R/W XXXXXXXXB
to
XXXXXXXXB
003A20H003C20H
ID register 0 IDR0 R/W
XXXXXXXX XXXXXXXXB
003A21H003C21H
003A22H003C22HXXXXX--- XXXXXXXXB
003A23H003C23H
Document Number: 002- 07696 Rev. *A Page 31 of 70
MB90540G/545G Series
(Continued)
003A24H003C24H
ID register 1 IDR1 R/W
XXXXXXXX XXXXXXXXB
003A25H003C25H
003A26H003C26HXXXXX--- XXXXXXXXB
003A27H003C27H
003A28H003C28H
ID register 2 IDR2 R/W
XXXXXXXX XXXXXXXXB
003A29H003C29H
003A2AH003C2AHXXXXX--- XXXXXXXXB
003A2BH003C2BH
003A2CH003C2CH
ID register 3 IDR3 R/W
XXXXXXXX XXXXXXXXB
003A2DH003C2DH
003A2EH003C2EHXXXXX--- XXXXXXXXB
003A2FH003C2FH
003A30H003C30H
ID register 4 IDR4 R/W
XXXXXXXX XXXXXXXXB
003A31H003C31H
003A32H003C32HXXXXX--- XXXXXXXXB
003A33H003C33H
003A34H003C34H
ID register 5 IDR5 R/W
XXXXXXXX XXXXXXXXB
003A35H003C35H
003A36H003C36HXXXXX--- XXXXXXXXB
003A37H003C37H
003A38H003C38H
ID register 6 IDR6 R/W
XXXXXXXX XXXXXXXXB
003A39H003C39H
003A3AH003C3AHXXXXX--- XXXXXXXXB
003A3BH003C3BH
Address Register Abbreviation Access Initial Value
CAN0 CAN1
Document Number: 002- 07696 Rev. *A Page 32 of 70
MB90540G/545G Series
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
003A3CH003C3CH
ID register 7 IDR7 R/W
XXXXXXXX XXXXXXXXB
003A3DH003C3DH
003A3EH003C3EHXXXXX--- XXXXXXXXB
003A3FH003C3FH
003A40H003C40H
ID register 8 IDR8 R/W
XXXXXXXX XXXXXXXXB
003A41H003C41H
003A42H003C42HXXXXX--- XXXXXXXXB
003A43H003C43H
003A44H003C44H
ID register 9 IDR9 R/W
XXXXXXXX XXXXXXXXB
003A45H003C45H
003A46H003C46HXXXXX--- XXXXXXXXB
003A47H003C47H
003A48H003C48H
ID register 10 IDR10 R/W
XXXXXXXX XXXXXXXXB
003A49H003C49H
003A4AH003C4AHXXXXX--- XXXXXXXXB
003A4BH003C4BH
003A4CH003C4CH
ID register 11 IDR11 R/W
XXXXXXXX XXXXXXXXB
003A4DH003C4DH
003A4EH003C4EHXXXXX--- XXXXXXXXB
003A4FH003C4FH
003A50H003C50H
ID register 12 IDR12 R/W
XXXXXXXX XXXXXXXXB
003A51H003C51H
003A52H003C52HXXXXX--- XXXXXXXXB
003A53H003C53H
003A54H003C54H
ID register 13 IDR13 R/W
XXXXXXXX XXXXXXXXB
003A55H003C55H
003A56H003C56HXXXXX--- XXXXXXXXB
003A57H003C57H
003A58H003C58H
ID register 14 IDR14 R/W
XXXXXXXX XXXXXXXXB
003A59H003C59H
003A5AH003C5AHXXXXX--- XXXXXXXXB
003A5BH003C5BH
003A5CH003C5CH
ID register 15 IDR15 R/W
XXXXXXXX XXXXXXXXB
003A5DH003C5DH
003A5EH003C5EHXXXXX--- XXXXXXXXB
003A5FH003C5FH
Document Number: 002- 07696 Rev. *A Page 33 of 70
MB90540G/545G Series
List of Message Buffers (DLC Registers and Data Registers)
(Continued)
Address Register Abbreviation Access Initial Value
CAN0 CAN1
003A60H003C60HDLC register 0 DLCR0 R/W ----XXXXB
003A61H003C61H
003A62H003C62HDLC register 1 DLCR1 R/W ----XXXXB
003A63H003C63H
003A64H003C64HDLC register 2 DLCR2 R/W ----XXXXB
003A65H003C65H
003A66H003C66HDLC register 3 DLCR3 R/W ----XXXXB
003A67H003C67H
003A68H003C68HDLC register 4 DLCR4 R/W ----XXXXB
003A69H003C69H
003A6AH003C6AHDLC register 5 DLCR5 R/W ----XXXXB
003A6BH003C6BH
003A6CH003C6CHDLC register 6 DLCR6 R/W ----XXXXB
003A6DH003C6DH
003A6EH003C6EHDLC register 7 DLCR7 R/W ----XXXXB
003A6FH003C6FH
003A70H003C70HDLC register 8 DLCR8 R/W ----XXXX
003A71H003C71H
003A72H003C72HDLC register 9 DLCR9 R/W ----XXXXB
003A73H003C73H
003A74H003C74HDLC register 10 DLCR10 R/W ----XXXXB
003A75H003C75H
003A76H003C76HDLC register 11 DLCR11 R/W ----XXXXB
003A77H003C77H
003A78H003C78HDLC register 12 DLCR12 R/W ----XXXXB
003A79H003C79H
003A7AH003C7AHDLC register 13 DLCR13 R/W ----XXXXB
003A7BH003C7BH
003A7CH003C7CHDLC register 14 DLCR14 R/W ----XXXXB
003A7DH003C7DH
003A7EH003C7EHDLC register 15 DLCR15 R/W ----XXXXB
003A7FH003C7FH
003A80H
to
003A87H
003C80H
to
003C87H
Data register 0 (8 bytes) DTR0 R/W XXXXXXXXB
to
XXXXXXXXB
Document Number: 002- 07696 Rev. *A Page 34 of 70
MB90540G/545G Series
(Continued)
Address Register Abbreviation Access Initial Va lue
CAN0 CAN1
003A88H
to
003A8FH
003C88H
to
003C8FH
Data register 1 (8 bytes) DTR1 R/W XXXXXXXXB
to
XXXXXXXXB
003A90H
to
003A97H
003C90H
to
003C97H
Data register 2 (8 bytes) DTR2 R/W XXXXXXXXB
to
XXXXXXXXB
003A98H
to
003A9FH
003C98H
to
003C9FH
Data register 3 (8 bytes) DTR3 R/W XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
003AA7H
003CA0H
to
003CA7H
Data register 4 (8 bytes) DTR4 R/W XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
003AAFH
003CA8H
to
003CAFH
Data register 5 (8 bytes) DTR5 R/W XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
003AB7H
003CB0H
to
003CB7H
Data register 6 (8 bytes) DTR6 R/W XXXXXXXXB
to
XXXXXXXXB
003AB8H
to
003ABFH
003CB8H
to
003CBFH
Data register 7 (8 bytes) DTR7 R/W XXXXXXXXB
to
XXXXXXXXB
003AC0H
to
003AC7H
003CC0H
to
003CC7H
Data register 8 (8 bytes) DTR8 R/W XXXXXXXXB
to
XXXXXXXXB
003AC8H
to
003ACFH
003CC8H
to
003CCFH
Data register 9 (8 bytes) DTR9 R/W XXXXXXXXB
to
XXXXXXXXB
003AD0H
to
003AD7H
003CD0H
to
003CD7H
Data register 10 (8 bytes) DTR10 R/W XXXXXXXXB
to
XXXXXXXXB
003AD8H
to
003ADFH
003CD8H
to
003CDFH
Data register 11 (8 bytes) DTR11 R/W XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
003AE7H
003CE0H
to
003CE7H
Data register 12 (8 bytes) DTR12 R/W XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
003AEFH
003CE8H
to
003CEFH
Data register 13 (8 bytes) DTR13 R/W XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
003CF0H
to
003CF7H
Data register 14 (8 bytes) DTR14 R/W XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
003AFFH
003CF8H
to
003CFFH
Data register 15 (8 bytes) DTR15 R/W XXXXXXXXB
to
XXXXXXXXB
Document Number: 002- 07696 Rev. *A Page 35 of 70
MB90540G/545G Series
10. Interrupt Map
(Continued)
Interrupt cause EI2OS
clear Interrupt vector Interrupt control register
Number Address Number Address
Reset N/A #08 FFFFDCH
INT9 instruction N/A #09 FFFFD8H
Exception N/A #10 FFFFD4H
CAN 0 RX N/A #11 FFFFD0HICR00 0000B0H
CAN 0 TX/NS N/A #12 FFFFCCH
CAN 1 RX N/A #13 FFFFC8HICR01 0000B1H
CAN 1 TX/NS N/A #14 FFFFC4H
External Interrupt INT0/INT1 *1 #15 FFFFC0HICR02 0000B2H
Time Base Timer N/A #16 FFFFBCH
16-bit Reload Timer 0 *1 #17 FFFFB8HICR03 0000B3H
8/10-bit A /D Converter *1 #18 FFFFB4H
16-bit Free-run Timer N/A #19 FFFFB0HICR04 0000B4H
External Interrupt INT2/INT3 *1 #20 FFFFACH
Serial I/O *1 #21 FFFFA8HICR05 0000B5H
8/16-bit PPG 0/1 N/A #22 FFFFA4H
Input Capture 0 *1 #23 FFFFA0HICR06 0000B6H
External Interrupt INT4/INT5 *1 #24 FFFF9CH
Input Capture 1 *1 #25 FFFF98HICR07 0000B7H
8/16-bit PPG 2/3 N/A #26 FFFF94H
External Interrupt INT6/INT7 *1 #27 FFFF90HICR08 0000B8H
W atch Timer N/A #28 FFFF8CH
8/16-bit PPG 4/5 N/A #29 FFFF88HICR09 0000B9H
Input Capture 2/3 *1 #30 FFFF84H
8/16-bit PPG 6/7 N/A #31 FFFF80HICR10 0000BAH
Output Compare 0 *1 #32 FFFF7CH
Output Compare 1 *1 #33 FFFF78HICR11 0000BBH
Input Capture 4/5 *1 #34 FFFF74H
Output Compare 2/3 - Input Capture 6/7 *1 #35 FFFF70HICR12 0000BCH
16-bit Reload Timer 1 *1 #36 FFFF6CH
UART 0 RX *2 #37 FFFF68HICR13 0000BDH
UART 0 TX *1 #38 FFFF64H
UART 1 RX *2 #39 FFFF60HICR14 0000BEH
UART 1 TX *1 #40 FFFF5CH
Flash Memory N/A #41 FFFF58HICR15 0000BFH
Delayed interrupt N/A #42 FFFF54H
Document Number: 002- 07696 Rev. *A Page 36 of 70
MB90540G/545G Series
(Continued)
*1 : The interrupt request flag is cleared by the EI2OS interrupt clear signal.
*2 : The interrupt request flag is cleared by the EI2OS interrupt clear signal. A stop request is available.
Notes :
N/A : The interrupt request flag is not cleared by the EI2OS interrupt clear signal.
For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the
EI2OS interrupt clear signal.
At the end of EI2OS, the EI2OS clear signal will be asserted for all the interru pt flags assigned to the same interrupt number. If
one interrupt flag starts the EI2OS and in the meantime another interrupt flag is set by a hardware event, the later event is lost
because the flag is cleared by the EI2OS clear signal caused by the first event. So it is recommended not to use the EI2OS for
this interrupt number.
If EI2OS is enabled, EI2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is
asserted. This means that different interrupt sources share the same EI2OS Descriptor which should be unique for each interrupt
source. For this reason, when one interrupt source uses the EI2OS, the other interrup t shou ld be disabled.
Document Number: 002- 07696 Rev. *A Page 37 of 70
MB90540G/545G Series
11. Electrical Characteristics
11.1 Absolute Maximum Ratings (VSS AVSS 0.0 V)
*1 : AVCC, AVRH, AVRL should not exceed VCC. Also, A VRH, AVRL should not exceed A VCC, and AVRL does not exceed AVRH.
*2 : VI and VO should not exceed VCC 0.3 V. However if the maximum current to/from an input is limited by some means with
external components, the ICLAMP rating supercedes the VI rating.
*3 : The maximum output current is a peak value for a corresponding pin.
*4 : Average output current is an average current value observed for a 10 0 ms period for a corresponding pin.
*5 : Total average current is an average current value observed for a 100 ms period for all corresponding pins.
*6 :
❐Applicable to pins : P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80
to P87, P90 to P97, PA0
❐Use within recommended operating conditions.
❐Use at DC voltage (current) .
❐The B signal should always be applied with a limiting resistance placed between the B signal and the microcontroller.
❐The value of the limiting resistance should be set so that when the B signal is applied the input current to the microcontroller
pin does not exceed rated values, either instantaneously or for prolonged periods.
❐Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass
through the protective diode and in crease the potential at the VCC pin, and this may affect ot he r de vi ce s.
❐Note that if a B signal is input when the microcontroller current is off (not fixed at 0 V) , the power supply is provided from the
pins, so that incomplete operation may result.
❐Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting supply volt-
age may not be sufficient to operate the power-on result.
❐Care must be taken not to leave the B input pin open.
Parameter Symbol Value Units Remarks
Min Max
Power supply voltage
VCC VSS 0.3 VSS 6.0 V
AVCC VSS 0.3 VSS 6.0 V VCC AVCC *1
AVRH, AVRL VSS 0.3 VSS 6.0 V AVCC AVRH/AVRL, AVRH
AVRL *1
Input voltage VIVSS 0.3 VSS 6.0 V *2
Output voltage VOVSS 0.3 VSS 6.0 V *2
Maximum clamp current ICLAMP 2.0 2.0 mA *6
Total maximum clamp current | ICLAMP | 20 mA *6
“L” level max output current IOL 15 mA *3
“L” level avg. output current IOLAV 4mA *4
“L” level max overall output current IOL 100 mA
“L” level avg. overall output current IOLAV 50 mA *5
“H” level max output current IOH 15 mA *3
“H” level avg. output current IOHAV 4mA *4
“H” level max overall output current IOH 100 mA
“H” level avg. overall output current IOHAV 50 mA *5
Power consumption PD500 mW Flash device
400 mW MASK ROM
Operating temperature TA40 105 C
Storage temperature TSTG 55 150 C
Document Number: 002- 07696 Rev. *A Page 38 of 70
MB90540G/545G Series
❐Note that analog system input/output pins other than the A/D input pins (LCD drive pin s, comparator input pins, etc.) cannot
accept B signal input.
❐Sample recommended circuits :
WARNING: Semiconductor devices can be permanently damaged by a pplication of stress (voltage , current, temperature, e tc.) in
excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
V
CC
R
Input/Output Equivalent circuits
B input (0 V to 16 V)
Limiting
resistance
Protective diode
Document Number: 002- 07696 Rev. *A Page 39 of 70
MB90540G/545G Series
11.2 Recommended Conditions (VSS AVSS 0.0 V)
*: Use a ceramic capacitor or a capacitor of better 4. AC characteristics. The bypass capacitor should be greater than this
capacitor.
WARNING: The recommended operating conditions are required in order to ensure the normal operati on of the semiconductor
device. All of the device’s electrical characteristics are wa rranted when the device is operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation outside these
ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sh eet.
Users considering application outside the listed conditions are advised to contact their representatives beforehan d.
Parameter Symbol Value Units Remarks
Min Typ Max
Power supply voltage VCC, AVCC
4.5 5.0 5.5 V
Under normal operation : Other than
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
Under normal operation when A/D conveter is
used :
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
3.5 5.0 5.5 V Under normal operation when A/D conveter is
not used :
MB90F548GL(S)/543G(S)/547G(S)/548G(S)
3.0 5.5 V Maintain RAM data in stop mode
Smooth capacitor CS0.022 0.1 1.0 F*
Operating temperature TA40 105 C
C
C
S
C Pin Connection Diagram
Document Number: 002- 07696 Rev. *A Page 40 of 70
MB90540G/545G Series
11.3 DC Characteristics
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10%, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Continued)
Parameter Symbol Pin name Condition Value Units Remarks
Min Typ Max
Input H
voltage
VIHS
CMOS
hysteresis
input pin 0.8 VCC VCC 0.3 V
VIH TTL input pin 2.0 V
VIHM MD input pin VCC 0.3 VCC 0.3 V
Input L
voltage
VILS
CMOS
hysteresis
input pin VCC 0.3 0.2 VCC V
VIL TTL input pin 0.8 V
VILM MD input pin VSS 0.3 VSS 0.3 V
Output H
voltage VOH All output pins VCC 4.5 V,
IOH 4.0 mA VCC 0.5 V
Output L
voltage VOL All output pins VCC 4.5 V,
IOL 4.0 mA 0.4 V
Input leak
current IIL VCC 5.5 V,
VSS VI VCC 55A
Pull-up
resistance RUP
P00 to P07,
P10 to P17,
P20 to P27,
P30 to P37,
RST
25 50 100 k
Pull-down
resistance RDOWN MD2 25 50 100 kExcept
Flash
devices
Document Number: 002- 07696 Rev. *A Page 41 of 70
MB90540G/545G Series
(Continued) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
* : The power supply current testing conditions are when using the external clock.
Parameter Sym-
bol Pin name Condition Value Units Remarks
Min Typ Max
Power
supply
current*
ICC
VCC
Internal frequency : 16 MHz, At
normal operating 40 55 mA
Internal frequency : 16 MHz, At
Flash programming/erasing 50 70 mA Flash device
ICCS Internal frequency : 16 MHz, At
sleep mode 12 20 mA
ICTS
VCC 5.0 V 10,
Internal frequency : 2 MHz,
At pseudo timer mode
300 600 A
600 1100 A MB90F548GL (S) only
200 400 AMB90543G(S)/547G(S)/
548(S) only
ICCL Internal frequency : 8 kHz,
At sub operation, TA 25 C
400 750 A MB90F548GL only
50 100 A MASK ROM
150 300 A Flash device
ICCLS Internal frequency : 8 kHz,
At sub sleep, TA 25 C15 40 A
ICCT Internal frequency : 8 kHz,
At timer mode, TA 25 C725A
ICCH1 At stop, TA 25 C520A
ICCH2 At hardware standby mode,
TA 25 C50 100 A
Input
capacity CIN
Other than
AVCC, AVSS,
AVRH,
AVRL, C,
VCC, VSS
515pF
Document Number: 002- 07696 Rev. *A Page 42 of 70
MB90540G/545G Series
11.4 AC Characteristics
11.4.1 Clock Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Continued)
Parameter Symbol Pin name Value Units Remarks
Min Typ Max
Oscillation frequency fCX0, X1
316 MHz No multiplier
When using an oscillator circuit
VCC 5.0 V 10%
816 MHz PLL multiplied by 1
When using an oscillator circuit
VCC 5.0 V 10%
48MHz
PLL multiplied by 2
When using an oscillator circuit
VCC 5.0 V 10%
35.33 MHz PLL multiplied by 3
When using an oscillator circuit
VCC 5.0 V 10%
34MHz
PLL multiplied by 4
When using an oscillator circuit
VCC 5.0 V 10%
35MHz
When using an oscillator circuit
VCC < 4.5 V(MB90F548GL(S)/543G(S)/
547G(S)/548G(S))
316 MHz No multiplier
When using an external clock
816 MHz PLL multiplied by 1
When using an external clock
48MHz
PLL multiplied by 2
When using an external clock
35.33 MHz PLL multiplied by 3
When using an external clock
34MHz
PLL multiplied by 4
When using an external clock
fCL X0A, X1A 32.768 kHz
Document Number: 002- 07696 Rev. *A Page 43 of 70
MB90540G/545G Series
(Continued) (MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Parameter Symbol Pin name Value Units Remarks
Min Typ Max
Clock cycle time tCYL X0, X1
62.5 333 ns No multiplier
When using an oscillator circuit
VCC 5.0 V 10%
62.5 125 ns PLL multiplied by 1
When using an oscillator circuit
VCC 5.0 V 10%
125 250 ns PLL multiplied by 2
When using an oscillator circuit
VCC 5.0 V 10%
187.5 333 ns PLL multiplied by 3
When using an oscillator circuit
VCC 5.0 V 10%
250 333 ns PLL multiplied by 4
When using an oscillator circuit
VCC 5.0 V 10%
200 333 ns When using an oscillator circuit
VCC < 4.5 V(MB90F548GL(S)/543G(S)/
547G(S)/548G(S))
62.5 333 ns No multiplier
When using an external clock
62.5 125 ns PLL multiplied by 1
When using an external clock
125 250 ns PLL multiplied by 2
When using an external clock
187.5 333 ns PLL multiplied by 3
When using an external clock
250 333 ns PLL multiplied by 4
When using an external clock
tLCYL X0A, X1A 30.5 s
Input clock pulse width PWH, PWL X0 10 ns Duty ratio is about 30 to 70.
PWLH, PWLL X0A 15.2 s
Input clock rise and fall
time tCR, tCF X0 5 ns When using an external clock
Machine clock frequency fCP 1.5 16 MHz When using main clock
fLCP 8.192 kHz When using sub-clock
Machine clock cycle time tCP 62.5 666 ns When using main clock
tLCP 122.1 s When using sub-clock
Document Number: 002- 07696 Rev. *A Page 44 of 70
MB90540G/545G Series
X0
tCYL
tCF tCR
0.8 VCC
0.2 VCC
PWH PWL
X0A
tLCYL
tCF tCR
0.8 VCC
0.2 VCC
PWLH PWLL
Clock Timing
5.5
3.5
1.5 816
Guaranteed operation range
(MB90F548GL(S)/543G(S)/547G(S)/548G(S))
Guaranteed PLL operation range
(MB90F548GL(S)/543G(S)/547G(S)/548G(S))
4.5
Guaranteed operation range
(Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S))
Guaranteed PLL operation range
( Other than MB90F548GL(S)/543G(S)/547G(S)/548G(S))
Power supply voltage
VCC (V)
Machine clock fCP (MHz)
Guaranteed PLL operation range
Guaranteed A/D Converter
operation range
Document Number: 002- 07696 Rev. *A Page 45 of 70
MB90540G/545G Series
AC characteristics are set to the measured reference voltage values below.
16
12
8
9
4
34 8 16
×4×3×2×1
×1/2
(PLL off)
External clock frequency and Machin e clock frequency
Machine clock
fCP (MHz)
External clock fC (MHz)
0.8 V
CC
0.2 V
CC
2.4 V
0.8 V
2.0 V
0.8 V
Input signal waveform Output signal waveform
Hysteresis Input Pin
TTL Input Pin
Output Pin
Document Number: 002- 07696 Rev. *A Page 46 of 70
MB90540G/545G Series
11.4.2 Clock Outpu t Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
11.4.3 Reset and Hardware Standb y Inpu t Timing
(MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Note : “tcp” represents one cycle time of the machine clock.
Oscillation time of oscillator is time that amplitude reached the 90. In the crystal oscillator, the oscillation time is between
several ms to tens of ms. In ceramic oscillator, the oscillation time is between handreds of s to several ms. In the external
clock, the oscillation time is 0 ns.
Any reset can not fully initialize the Flash Memory if it is perfo rming the automatic algorithm.
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Cycle time tCYC CLK VCC 5 V 1062.5 ns
CLK CLKtCHCL 20 ns
Parameter Symbol Pin
name Value Units Remarks
Min Max
Reset input time tRSTL RST
4 tCP ns Under normal operat ion
Oscillation time of
oscillator 4 tCP ms In stop mode
100 sIn pseudo timer mode (MB90543G
(S) /547G (S) /548G (S) )
4 tCP ns In pseudo timer mode
(Other than MB90543G (S) /547G
(S) /548G (S) )
2 tLCP sIn sub-clock mode,
sub-sleep mode,
timer mode
Hardware standby input time tHSTL HST 4 tCP ns Under normal operat ion
CLK
t
CYC
2.4 V 2.4 V
0.8 V
t
CHCL
Document Number: 002- 07696 Rev. *A Page 47 of 70
MB90540G/545G Series
RST
HST 0.2 VCC
tRSTL, tHSTL
0.2 VCC
tRSTL
0.2 VCC 0.2 VCC
4 tCP
RST
X0
Internal operation clock
Internal reset
90% of
amplitude
Oscillation time of
oscillator Oscillation setting time
Instruction execution
In under normal operation, pseudo timer mode, sub-clock mode, sub-sleep mode, time r mode
In stop mode
Document Number: 002- 07696 Rev. *A Page 48 of 70
MB90540G/545G Series
11.4 .4 Power On Reset
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
* : VCC must be kept lower than 0.2 V before power-on.
Notes : The above values are used for creating a power-on reset.
Some registers in the device are initialized only upon a power-on reset. To initialize these register, turn on the power
supply using the above values.
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Power on rise time tRVCC 0.05 30 ms *
Power off time tOFF VCC 50 ms Waiting time until power-on
VCC
VCC
VSS
3.0 V
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
RAM data being held
It is recommended to keep the
rising speed of the supply voltage
at 50 mV/ms or slower.
Sudden changes in the power suppl y voltage may cause a power-on reset.
To change the power supply voltage while the device is in operation, it is recommended to
raise the voltage smoothly to suppress fluctuation s as show n belo w.
In this case, change the supply voltage with the PLL clock not used. If the voltage drop is
1 V or fewer per second, however, you can use the PLL clock.
Document Number: 002- 07696 Rev. *A Page 49 of 70
MB90540G/545G Series
11.4.5 Bus Timing (Read)
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
ALE pulse width tLHLL ALE
tCP/2 20 ns
Valid address ALE time tAVLL
ALE,
A16 to A23,
AD00 to AD15 tCP/2 20 ns
ALE Address valid time tLLAX ALE, AD00 to
AD15 tCP/2 15 ns
Valid address RD time tAVRL
A16 toA23,
AD00 to AD15,
RD tCP 15 ns
Valid address Valid data
input tAVDV A16 to A23,
AD00 to AD15 5 tCP/2 60 ns
RD pulse width tRLRH RD 3 tCP/2 20 ns
RD Valid data input tRLDV RD, AD00 to
AD15 3 tCP/2 60 ns
RD Data hold time tRHDX RD, AD00 to
AD15 0ns
RD ALE time tRHLH RD, ALE tCP/2 15 ns
RD Address valid time tRHAX RD, A16 to A23 tCP/2 10 ns
Valid address CLK time tAVCH
A16 to A23,
AD00 to AD15,
CLK tCP/2 20 ns
RD CLK time tRLCH RD, CLK tCP/2 20 ns
ALE RD time tLLRL ALE, RD tCP/2 15 ns
Document Number: 002- 07696 Rev. *A Page 50 of 70
MB90540G/545G Series
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.2 VCC
0.8 VCC
0.2 VCC
0.8 VCC
CLK
ALE
RD
A16 to A23
AD00 to AD15
2.4 V
tAVCH
tLHLL
tRHLH
tAVLL
tAVRL tRLDV
tRLRH
tRHAX
tRHDX
tLLAX
tLLRL
tRLCH
tAVDV
Address Read data
Bus Timing (Read)
Document Number: 002- 07696 Rev. *A Page 51 of 70
MB90540G/545G Series
11.4.6 Bus Timing (Write)
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Valid address WR time tAVWL A16 to A23 AD00
to AD15, WR
tCP 15 ns
WR pulse width tWLWH WR 3 tCP/2 20 ns
Valid data output WR time tDVWH AD00 to AD15,
WR 3 tCP/2 20 ns
WR Data hold time tWHDX AD00 to AD15,
WR 20 ns
WR Address valid time tWHAX A16 to A23, WR tCP/2 10 ns
WR ALE time tWHLH WR, ALE tCP/2 15 ns
WR CLK time tWLCH WR, CLK tCP/2 20 ns
0.8 V
0.8 V
2.4 V
2.4 V
2.4 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
2.4 V
CLK
ALE
WR (WRL, WRH)
A16 to A23
AD00 to AD15
tWHLH
tAVWL tWLWH
tWHAX
tWHDX
tWLCH
tDVWH
Address Write data
Bus Timing (Write)
Document Number: 002- 07696 Rev. *A Page 52 of 70
MB90540G/545G Series
11.4.7 Ready Input Timing
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Note : If the RDY setup time is insufficient, use the auto-ready function.
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
RDY setup time tRYHS RDY 45 ns
RDY hold time tRYHH RDY 0 ns
tRYHS tRYHH
2.4 V
0.8 VCC
0.2 VCC
0.8 VCC
CLK
ALE
RD/WR
RDY
no WAIT is used.
RDY
When WAIT is used
(1 cycle).
Ready Input Timing
Document Number: 002- 07696 Rev. *A Page 53 of 70
MB90540G/545G Series
11.4.8 Hold Timing
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Note : There is more than 1 cycle from the time HRQ is read to the time the HAK is changed.
11.4.9 UART0/1, Serial I/O Timing
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Notes :
■AC characteristic in CLK synchronized mode.
■CL is load capacity value of pins when testing.
■For tCP (Machine clock cycle time) , refer to “ (1) Clock Timing”.
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Pin floating HAK time tXHAL HAK 30 tCP ns
HAK time Pin valid time tHAHV HAK tCP 2 tCP ns
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Serial clock cycle time tSCYC SCK0 to SCK2
Internal clock operation
output pins are CL 80
pF 1 TTL.
8 tCP ns
SCK SOT delay time tSLOV SCK0 to SCK2,
SOT0 to SOT2 80 80 ns
Valid SIN SCKtIVSH SCK0 to SCK2,
SIN0 to SIN2 100 ns
SCK Valid SIN hold time tSHIX SCK0 to SCK2,
SIN0 to SIN2 60 ns
Serial clock “H” pulse width tSHSL SCK0 to SCK2
External clock operation
output pins are CL 80
pF 1 TTL.
4 tCP ns
Serial clock “L” pulse width tSLSH SCK0 to SCK2 4 tCP ns
SCK SOT delay time tSLOV SCK0 to SCK2,
SOT0 to SOT2 150 ns
Valid SIN SCKtIVSH SCK0 to SCK2,
SIN0 to SIN2 60 ns
SCK Valid SIN hold time tSHIX SCK0 to SCK2,
SIN0 to SIN2 60 ns
HAK
tXHAL tHAHV
2.4 V
0.8 V 2.4 V
2.4 V
0.8 V
0.8 V
Each pin
High impedance
Hold Timing
Document Number: 002- 07696 Rev. *A Page 54 of 70
MB90540G/545G Series
SCK
SOT
SIN
t
SCYC
t
SLOV
t
IVSH
t
SHIX
0.8 V0.8 V
2.4 V
2.4 V
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
Internal Shift Clock Mode
SCK
SOT
SIN
t
SLSH
t
SHSL
t
SLOV
t
IVSH
t
SHIX
0.2 V
CC
0.2 V
CC
0.8 V
CC
0.8 V
CC
2.4 V
0.8 V
0.8 V
CC
0.2 V
CC
0.8 V
CC
0.2 V
CC
External Shift Clock Mode
Document Number: 002- 07696 Rev. *A Page 55 of 70
MB90540G/545G Series
11.4.10 Timer Input Timing
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
11.4.11 Timer Output Timing
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Input pulse width tTIWH TIN0, TIN1 4 tCP ns
tTIWL IN0 to IN7
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
CLK TOUT change time tTO TOT0 , TOT1,
PPG0 to PPG3 30 ns
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTIWH tTIWL
Timer Input Timing
CLK
TOUT
2.4 V
t
TO
2.4 V
0.8 V
Timer Output Timing
Document Number: 002- 07696 Rev. *A Page 56 of 70
MB90540G/545G Series
11.4 .12 Trigg er Input Timing
(MB90543G(S)/547G(S)/548G(S)/F5 48GL(S): VCC 3.5 V to 5.5 V, VSS AVSS 0.0 V, TA 40 C to 105 C)
(Other than MB90543G(S)/547G(S)/548G(S)/F548GL(S): VCC 5.0 V 10, VSS AVSS 0.0 V, TA 40 C to 105 C)
Parameter Symbol Pin name Condition Value Units Remarks
Min Max
Input pulse width tTRGH
tTRGL
INT0 to INT7,
ADTG 5 tCP ns Under nomal operation
1s In stop mode
0.8 VCC 0.8 VCC
0.2 VCC 0.2 VCC
tTRGH tTRGL
Trig ger Input Timing
Document Number: 002- 07696 Rev. *A Page 57 of 70
MB90540G/545G Series
11.5 A/D Converter
11.5.1 Electrical Characteristics
(VCC AVCC 5.0 V10, VSS AVSS 0.0 V, 3.0 V AVRH AVRL, TA 40 C to 105 C)
* : When not using an A/D converter, this is the current (VCC AVCC AVRH 5.0 V) when the CPU is stopped.
Note: The functionality of the A/D converter is only guaranteed for VCC 5.0 V 10 (also for MB90543G(S)/547G(S)/548G(S)/
F548G(S)/F548GL(S)).
Parameter Symbol Pin name Value Units Remarks
Min Typ Max
Resolution 10 bit
Conversion error 5.0 LSB
Nonlinearity error 2.5 LSB
Differential nonlinearity
error 1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVRL 3.5
LSB AVRL 0.5
LSB AVRL 4.5
LSB V
Full scale transition voltage VFST AN0 to AN7 AVRH 6.5
LSB AVRH 1.5
LSB AVRH 1.5
LSB V
Compare time 352 tCP ns Internal
frequency :
16 MHz
Sampling time 64 tCP ns Internal
frequency :
16 MHz
Analog port input current IAIN AN0 to AN7 11AVCC AVCC
5.0 V 1
Analog input voltage range VAIN AN0 to AN7 AVRL AVRH V
Reference voltage range AVRH AVRL 2.7 AVCC V
AVRL 0 AVRH 2.7 V
Power supply current IAAVCC 5mA
IAH AVCC 5A*
Reference voltage supply curre nt IRAVRH 400 600 A Flash device
140 260 A MASK ROM
IRH AVRH 5A*
Offset between input
channels AN0 to AN7 4LSB
Document Number: 002- 07696 Rev. *A Page 58 of 70
MB90540G/545G Series
11.5.2 A/D Converter Glos sary
Resolution : Analog changes that are identifiable with the A/D converter
Linearity error : The deviation of the straight line connecting the zero transition point (“00 0000 0000” “00 0000
0001”) with the full-scale transition point (“11 1111 1110” “11 1111 1111”) from actual convers ion
characteristics
Differential linearity error : The deviation of input voltage needed to cha nge the output code by 1 LSB from the theore tical value
Total error : The total error is defined as a difference between the actual value and the theoretical value, which
includes zero-transition error/full-scale transition error and linearity error.
(Continued)
3FF
3FE
3FD
004
003
002
001
AVRL AVRH
V
NT
0.5 LSB
0.5 LSB
{1 LSB × (N − 1) + 0.5 LSB}
Analog input
Digital output
Total error
Actual conversion
Value
Actual conversion
characteristics
(measured value)
Theoretical
characteristics
[V]
AVRH AVRL
1024
1 LSB (Theoretical value)
VOT (Theoretical value) AVRL 0.5 LSB [V]
VFST (Theoretical value ) AVRH 1.5 LSB [V]
Total error for digital output N [LSB]
VNT {1 LSB (N 1) 0.5 LSB}
1 LSB
VNT : Voltage at a transition of digital outp ut from (N 1) to N
Document Number: 002- 07696 Rev. *A Page 59 of 70
MB90540G/545G Series
(Continued)
11.5.3 Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions, :
Output impedance values of the external circuit of 15 k or lower are recommended.
When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is
recommended to minimized the effect of voltage distribu tion between the external cap acitor and internal capacitor.
Note : When the output impedan ce of the external circuit is too high, the sampli ng period for analog voltages may not be sufficient
(sampling period 4.00 s @machine clock of 16 MHz) .
11.5.4 Error
The smaller the | AVRH AVRL |, the greater the error would become relatively.
3FF
3FE
3FD
004
003
002
001
AVRL AVRH AVRL AVRH
N + 1
N
N − 1
N − 2
VNT
VNT
V (N + 1) T
VOT
VFST
{1 LSB × (N − 1) + VOT }
Digital output
Digital output
Linearity error Differential linearity error
Analog input Analog input
Actual conversion
value
(measured value)
Actual conversion
characteristics
Theoretical
characteristics
(measured value)
Theorential characteristics
Actual conversion value
(measured value)
(measured value)
Acturel conversion
value
Linearity erro r of
digital output N [LSB]
VNT {1 LSB (N 1) VOT}
1 LSB
[V]
VFST VOT
1022
1 LSB
1 LSB [LSB]
V (N 1) T VNT
1 LSB
Differential linearity error
of digital N
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
3.2 kΩ Max
30 pF Max
Analog input Comparator
Equipment of analog input circuit model
Document Number: 002- 07696 Rev. *A Page 60 of 70
MB90540G/545G Series
11.6 Flash Memory Program/Erase Characteristics
Parameter Condition Value Units Remarks
Min Typ Max
Sector erase time
TA 25 C
VCC 5.0 V
1 15 s Excludes 00H programming prior erasure
Chip erase time 5sMB90F543G (S) /F548G (S)
/F548GL (S) Excludes 00H
programming
prior erasure
7s MB90F549G (S) /F546G (S)
Word (16 bit width)
programming time 16 3,600 s Excludes system-level overhead
Erase/Program cycle 10,000 cycle
Document Number: 002- 07696 Rev. *A Page 61 of 70
MB90540G/545G Series
12. Example Characteristics
5
4.5
4
3.5
3
2.5
2
1.5
1
0.5
00 -10-8-6-4-2
IOH [mA]
VOH [V]
VOH – IOH
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
00108642
IOL [mA]
VOL [V]
VOL – IOL
(VCC = 4.5 V, Ta = +25˚C) (VCC = 4.5 V,Ta = +25˚C)
5
4
3
2
1
03 5.554.543.5
Vin [V]
Vin – Vcc
6 6.5
VIH
VIL
(Ta = +25˚C)
“H” level output voltage
“H” level input voltage/ “L” level input voltage
(Hysterisis inpiut)
“L” level output voltage
Document Number: 002- 07696 Rev. *A Page 62 of 70
MB90540G/545G Series
Power supply current (MB90549G)
40
35
30
25
20
15
10
5
0276543
Vcc [V]
Icc [mA]
Icc – Vcc
fcp = 12 MHz
fcp = 16 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
12
10
8
6
4
2
0
276543 Vcc [V]
Icc [mA]
Iccs – Vcc
fcp = 12 MHz
fcp = 16 MHz
fcp = 10 MHz
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
600
500
400
300
200
100
0276543
Vcc [V]
ICTS [μA]
ICTS – VCC
fcp = 2 MHz
60
50
40
30
20
10
0276543
Vcc [V]
ICCL [μA]
ICCL – VCC
fcp = 8 kHz
70
80
90
100
(Ta = +25˚C) (Ta = +25˚C)
(Ta = +25˚C) (Ta = +25˚C)
Document Number: 002- 07696 Rev. *A Page 63 of 70
MB90540G/545G Series
40
35
30
25
20
15
10
5
0
Vcc [V]
ICCLS [μA]
ICCLS – VCC
fcp = 8 kHz
25
20
15
10
5
027
6543
Vcc [V]
ICCT [μA]
ICCT – VCC
fcp = 8 kHz
27
6543
(Ta = +25˚C) (Ta = +25˚C)
23456
ICCH1 – VCC
VCC [V] 7
20
18
16
14
12
10
8
6
4
0
ICCH1 [μA]
2
(STOP, Ta = +25 ˚C)
100
90
85
70
60
50
40
30
20
0
23456
ICCH2 – VCC
ICCH2 [μA]
VCC [V] 7
10
(hardware standby, Ta = +25 ˚C)
Document Number: 002- 07696 Rev. *A Page 64 of 70
MB90540G/545G Series
Power supply current (MB90F549G)
45
40
35
30
25
20
15
10
5
023456
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
fcp = 16 MHz
fcp = 12 MHz
fcp = 10 MHz
Icc – Vcc
ICC [mA]
VCC [V]
14
12
10
8
6
4
2
023456
fcp = 8 MHz
fcp = 4 MHz
fcp = 2 MHz
fcp = 16 MHz
fcp = 12 MHz
fcp = 10 MHz
Iccs – Vcc
ICC [mA]
VCC [V]
600
500
400
300
200
100
023456
fcp = 2 MHz
ICTS – VCC
ICTS [μA]
VCC [V]
300
250
200
150
100
50
023456
fcp = 8 kHz
ICCL – VCC
ICCL [μA]
VCC [V]
77
77
(Ta = +25 ˚C) (Ta = +25 ˚C)
(Ta = +25 ˚C) (Ta = +25 ˚C)
Document Number: 002- 07696 Rev. *A Page 65 of 70
MB90540G/545G Series
45
40
35
30
25
20
15
10
5
023456
fcp = 8 MHz
ICCLS – VCC
ICCLS [μA]
VCC [V] 7
25
20
15
10
5
023456
fcp = 8 MHz
ICCT – VCC
ICCT [μA]
VCC [V] 7
100
90
85
70
60
50
40
30
20
0
23456
ICCH2 – VCC
ICCH2 [μA]
VCC [V] 7
10
(hardware standby, Ta = +25 ˚C)
(Ta = +25 ˚C)
(Ta = +25 ˚C)
23456
ICCH1 – VCC
VCC [V] 7
20
18
16
14
12
10
8
6
4
0
ICCH1 [μA]
2
(STOP, Ta = +25 ˚C)
Document Number: 002- 07696 Rev. *A Page 66 of 70
MB90540G/545G Series
13. Ordering Information
Part number Package Remarks
MB90F543GPF
MB90F543GSPF
MB90F546GPF
MB90F546GSPF
MB90F548GPF
MB90F548GSPF
MB90F548GLPF
MB90F548GLSPF
MB90F549GPF
MB90F549GSPF
MB90543GPF
MB90543GSPF
MB90547GPF
MB90547GSPF
MB90548GPF
MB90548GSPF
MB90549GPF
MB90549GSPF
100-pinPlastic QFP
(FPT-100P-M06)
MB90F543GPMC
MB90F543GSPMC
MB90F546GPMC
MB90F546GSPMC
MB90F548GPMC
MB90F548GSPMC
MB90F548GLPMC
MB90F548GLSPMC
MB90F549GPMC
MB90F549GSPMC
MB90543GPMC
MB90543GSPMC
MB90547GPMC
MB90547GSPMC
MB90548GPMC
MB90548GSPMC
MB90549GPMC
MB90549GSPMC
100-pinPlastic LQFP
(FPT-100P-M20)
Document Number: 002- 07696 Rev. *A Page 67 of 70
MB90540G/545G Series
14. Package Dimensions
(Continued)
100-pin plastic QFP Lead pitch 0.65 mm
Package width ×
package length 14.00 × 20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference) P-QFP100-14×20-0.65
100-pin plastic QFP
(FPT-100P-M06)
(
FPT-100P-M06
)
C
2002 FUJITSU LIMITED F100008S-c-5-5
1 30
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002)
M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00
+0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
0~8˚
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
©2002-2008 FUJITSU MICROELECTRONICS LIMITED F100008S-c-5-6
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Document Number: 002- 07696 Rev. *A Page 68 of 70
MB90540G/545G Series
(Continued)
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.0 mm × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm Max
Weight 0.65 g
Code
(Reference) P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M20)
(FPT-100P-M20)
C
2005 FUJITSU LIMITED F100031S-c-2-1
14.00
±
0.10(.551
±
.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020)
0.20±
0.05
(.008
±
.002) M
0.08(.003) 0.145
±
0.055
(.0057
±
.0022)
0.08(.003)
"A"
INDEX .059
–.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0
˚
~8
˚
(0.50(.020))
(.024
±
.006)
0.60
±
0.15
0.25(.010)
0.10
±
0.10
(.004
±
.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values
©2005-2008 FUJITSU MICROELECTRONICS LIMITED F100031S-c-2-2
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
Document Number: 002- 07696 Rev. *A Page 69 of 70
MB90540G/545G Series
15. Major Changes
Spansion Publication Number: DS07-13703 -7E
NOTE: Please see “Document History” about later revised information.
Document History
Section Change Results
■ PRODUCT LINEUP Changed the name in peripheral resource.
16-bit I/O Timer 16-bit Free-run Timer
■ I/O CIRCUIT TYPE Changed the name of input typ.
Hysteresis CMOS Hysteresis
HYS CMOS Hysteresis
■ BLOCK DIAGRAM Changed the arrow direction of SOT1 signal at UART1(SCI).
“ ” (input/output) “” (output)
■ I/O MAP Changed the text of “Note”.
■ INTERRUPT MAP Changed the name of peripheral re source of the pin number: #19.
I/O T imer 16-bit Free-run Timer
■ ELECTRICAL CHARACTERISTICS
2. Recommended Conditions Changed the remarks of “parameter: Power supply voltage”.
3. DC Characteristics Changed the maximum value of symbol : VILM of parameter: Input voltage.
VCC + 0.3 VSS + 0.3
Added the following remarks for parameter : Pull-down resistance.
Except Flash device
4. AC Characteristics
(1) Clock Timing Added the value when using an external clock in Oscillation frequency and
Clock cycle time on (1) Clock Timing for parameter.
Added the item of A/D converter operation range in figure of “ Guaranteed
PLL operation range”
(3) Reset and Hardware Standby Input Timing Changed the following item.
(3) Reset and Hardware Standby Input Timing Remarks:
In sub-clock mode, sub-sleep mode, timer mode
2tCP 2tLCP
(4) Power On Reset Changed as follows;
Due to repetitive operation Waiting time until power-on
5. A/D Converter Changed the unit of Zero transition voltage and Full scale transition voltage.
mV V
■ ORDERING INFORMATION Added the MB90F548GLPMC in Part Numbers.
Document Title: MB90F543G(S)/546G(S)/548G(S)/549G(S)/549G(S)/V540G/MB90543G(S)/547G(S)/548G(S)/F548GL(S)
CMOS F2MC-16LX MB90540G/545G Series 16-bit Proprietary Microcontro l ler
Document Number: 002-07696
Revision ECN Orig. of
Change Submission
Date Description of Change
** AKIH 11/13/2008 Migrated to Cypress and assigned document number 002-07696.
No change to document contents or format.
*A 5537115 AKIH 11/30/2016 Updated to Cypress template
Document Number: 002-07696 Rev. *A Revised November 30, 2016 Page 70 of 70
MB90540G/545G Series
© Cypress Semiconductor Corporation, 2002-2016. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including an y so ftw ar e or fi rmw ar e incl u ded o r r efe r ence d i n thi s docu m ent ("Softwar e" ), is o w ned b y C yp re ss u nd er th e i nte l lectua l p ro pe rt y l aws an d treaties o f t he U ni te d Sta t es an d other countrie s
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