PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1992, Texas Instruments Incorporated
1
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•Choice of Operating Speeds
High-Speed, A Devices . . . 25 MHz Min
Half-Power, A-2 Devices . . . 16 MHz Min
•Choice of Input/Output Configuration
•Package Options Include Both Ceramic DIP
and Chip Carrier in Addition to Ceramic
Flat Package
DEVICE I
INPUTS 3-STATE
O OUTPUTS REGISTERED
Q OUTPUTS
I/O
PORT
S
PAL16L8 10 2 0 6
PAL16R4 8 0 4 (3-state buffers) 4
PAL16R6 8 0 6 (3-state buffers) 2
PAL16R8 8 0 8 (3-state buffers) 0
description
These programmable array logic devices feature
high speed and a choice of either standard or
half-power devices. They combine Advanced
Low-Power Schottky technology with proven
titanium-tungsten fuses. These devices will
provide reliable, high-performance substitutes for
conventional TTL logic. Their easy
programmability allow for quick design of ”custom”
functions and typically results in a more compact
circuit board. In addition, chip carriers are
available for further reduction in board space.
The Half-Power versions offer a choice of
operating frequency, switching speeds, and
power dissipation. In many cases, these
Half-Power devices can result in significant power
reduction from an overall system level.
The PAL16’ M series is characterized for
operation over the full military temperature range
of –55°C to 125°C.
PAL is a registered trademark of Advanced Micro Devices Inc.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
I
I
I
I
I
I
I
I
I
GND
VCC
O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
PAL16L8’
J OR W PACKAGE
(TOP VIEW)
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I
PAL16L8’
FK PACKAGE
(TOP VIEW)
I
I
I
O
I/O O
I
GND
IVCC
PAL16R4AM, PAL16R4A-2M, PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
I/O
Q
Q
Q
Q
I/O
I/O
OE
(TOP VIEW)
PAL16R4’
J OR W PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
I/O
Q
Q
Q
Q
Q
Q
I/O
OE
(TOP VIEW)
PAL16R6’
J OR W PACKAGE
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
CLK
I
I
I
I
I
I
I
I
GND
VCC
Q
Q
Q
Q
Q
Q
Q
Q
OE
(TOP VIEW)
PAL16R8’
J OR W PACKAGE
I
I
CLK
I/O
I/O I/O
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
I/O
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
PAL16R4’
FK PACKAGE
I
I
CLK
I/O
QI/O
I
GND
VCC
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
OE
PAL16R6’
FK PACKAGE
I
I
CLK
Q
QQ
I
GND
VCC
OE
3 2 1 20 19
910111213
4
5
6
7
8
18
17
16
15
14
Q
Q
Q
Q
Q
I
I
I
I
I
(TOP VIEW)
PAL16R8’
FK PACKAGE
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3
functional block diagrams (positive logic)
denotes fused inputs
PAL16L8AM
PAL16L8A-2M
PAL16R4AM
PAL16R4A-2M
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I
EN ≥1
&
32 X 64
10 16
166
7
7
7
7
7
7
7
7
6
16 x
Q
I/O
I/O
I/O
I/O
I
EN
816
164
7
7
7
8
8
8
7
4
16 x
≥1
&
32 X 64 ≥1
8
Q
Q
Q
4
1D
I = 0 2
CLK C1
EN 2
OE
4
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
4
functional block diagrams (positive logic)
denotes fused inputs
PAL16R6AM
PAL16R6A-2M
PAL16R8AM
PAL16R8A-2M
Q
I/O
I/O
I
EN
816
162
7
8
8
8
7
2
16 x
≥1
&
32 X 64 ≥1
8
Q
Q
Q
6
1D
I = 0 2
CLK C1
EN 2
OE
6
8Q
8Q
Q
I816
168
8
8
8
8
16 x
8
Q
Q
Q
1D
I = 0 2
CLK C1
EN 2
8Q
8Q
&
32 X 64 ≥1
OE
8Q
8Q
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
O
12
I
11
Increment
I1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
PAL16L8AM, PAL16L8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5
logic diagram (positive logic)
04812 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
I/O
18
Q
17
Q
16
Q
15
Q
14
I/O
13
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
PAL16R4AM, PAL16R4A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
6
logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
I/O
19
Q
17
Q
16
Q
15
Q
14
I/O
12
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
PAL16R6AM, PAL16R6A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7
logic diagram (positive logic)
0 4 8 12 16 20 24 28 31
I2
I3
I4
I5
I6
I7
I8
I9
Q
17
Q
16
Q
15
Q
14
11
Increment
CLK 1
Fuse number = First fuse number + Increment
0
32
64
96
128
160
192
224
256
288
320
352
384
416
448
480
512
544
576
608
640
672
704
736
768
800
832
864
896
928
960
992
1024
1056
1088
1120
1152
1184
1216
1248
1280
1312
1344
1376
1408
1440
1472
1504
1536
1568
1600
1632
1664
1696
1728
1760
1792
1824
1856
1888
1920
1952
1984
2016
First
Fuse
Numbers
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
C1
1D
I = 0
OE
Q
18
C1
1D
I = 0
Q
13
C1
1D
I = 0
Q
19
C1
1D
I = 0
Q
12
C1
1D
I = 0
PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
8
logic diagram (positive logic)
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9
programming information
Texas Instruments programmable logic devices can be programmed using widely available software and
inexpensive device programmers.
Complete programming specifications, algorithms, and the latest information on hardware, software, and
firmware are available upon request. Information on programmers capable of programming Texas Instruments
programmable logic is also available, upon request, from the nearest TI field sales office, local authorized TI
distributor, or by calling Texas Instruments at (214) 997-5666.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage applied to disabled output (see Note 1) 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NOTE 1: These ratings apply except for programming pins during a programming cycle.
recommended operating conditions
MIN NOM MAX UNIT
VCC Supply voltage 4.5 5 5.5 V
VIH High-level input voltage 2 5.5 V
VIL Low-level input voltage 0.8 V
IOH High-level output current –2 mA
IOL Low-level output current 12 mA
TAOperating free-air temperature –55 25 125 °C
µA
µA
µA
mA
VCC = 5.5 V, VO = 2.7 V
VCC = 5.5 V, VO = 0.4 V
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 0.4 V
IOZH
IOZL
IIH
IIL
ns
Pulse duration (see Note 2)
tw
PAL16L8AM, PAL16R4AM, PAL16R6AM, PAL16R8AM
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
10
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = –18 mA –1.5 V
VOH VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.25 0.4 V
Outputs 20
I/O ports 100
Outputs –20
I/O ports –100
IIVCC = 5.5 V, VI = 5.5 V 0.2 mA
I/O Ports 100
All others 25
OE input –0.2
All others –0.1
IOS‡VCC = 5.5 V, VO = 0.5 V –30 –250 mA
ICC VCC = 5.5 V, VI = 0, Outputs open 75 180 mA
timing requirements
MIN MAX UNIT
fclock Clock Frequency 0 25 MHz
Clock high 15
Clock low 20
tsu Setup time, input or feedback before CLK↑25 ns
thHold time, input or feedback after CLK↑0 ns
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency , fclock. The minimum pulse durations specified are
only for clock high or low, but not for both simultaneously.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
fmax 25 45 MHz
tpd I, I/O O, I/O 15 30 ns
tpd CLK↑QR1 = 390 Ω, 10 20 ns
ten OE↓QR2 = 750 Ω, 15 25 ns
tdis OE↑QSee Figure 1 10 25 ns
ten I, I/O O, I/O 14 30 ns
tdis I, I/O O, I/O 13 30 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
µA
µA
µA
mA
VCC = 5.5 V, VO = 2.7 V
VCC = 5.5 V, VO = 0.4 V
VCC = 5.5 V, VI = 2.7 V
VCC = 5.5 V, VI = 0.4 V
IOZH
IOZL
IIH
IIL
ns
Pulse duration (see Note 2)
tw
PAL16L8A-2M, PAL16R4A-2M, PAL16R6A-2M, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11
electrical characteristics over recommended operating free-air temperature range
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK VCC = 4.5 V, II = –18 mA –1.5 V
VOH VCC = 4.5 V, IOH = –2 mA 2.4 3.2 V
VOL VCC = 4.5 V, IOL = 12 mA 0.25 0.4 V
Outputs 20
I/O ports 100
Outputs –20
I/O ports –100
IIVCC = 5.5 V, VI = 5.5 V 0.2 mA
I/O Ports 100
All others 25
OE input –0.2
All others –0.1
IOS‡VCC = 5.5 V, VO = 0.5 V –30 –250 mA
ICC VCC = 5.5 V, VI = 0, Outputs open 75 90 mA
timing requirements
MIN MAX UNIT
fclock Clock Frequency 0 16 MHz
Clock high 25
Clock low 25
tsu Setup time, input or feedback before CLK↑35 ns
thHold time, input or feedback after CLK↑0 ns
NOTE 2: The total clock period of clock high and clock low must not exceed clock frequency, fclock. The minimum pulse durations specified are
only for clock high or low, but not for both simultaneously.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITION MIN TYP†MAX UNIT
fmax 16 25 MHz
tpd I, I/O O, I/O 25 40 ns
tpd CLK↑QR1 = 390 Ω, 11 25 ns
ten OE↓QR2 = 750 Ω, 20 25 ns
tdis OE↑QSee Figure 1 11 25 ns
ten I, I/O O, I/O 25 40 ns
tdis I, I/O O, I/O 25 35 ns
†All typical values are at VCC = 5 V, TA = 25°C.
‡Not more than one output should be shorted at a time and the duration of the short circuit should not exceed one second. Set VO at 0.5 V to avoid
test equipment degradation.
PAL16L8AM, PAL16L8A-2M, PAL16R4AM, PAL16R4A-2M
PAL16R6AM, PAL16R6A-2M, PAL16R8AM, PAL16R8A-2M
STANDARD HIGH-SPEED PAL CIRCUITS
SRPS016 – D2705, FEBRUAR Y 1984 – REVISED MARCH 1992
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
12 SRPS016
PARAMETER MEASUREMENT INFORMATION
tsu
S1
From Output
Under Test Test
Point
R2
CL
(see Note A)
LOAD CIRCUIT FOR
3-STATE OUTPUTS
3 V
0
1.5 V
1.5 V
th
1.5 V
Timing
Input
Data
Input
Input
In-Phase
Output
Out-of-Phase
Output
(see Note D)
tpd
tpd
tpd
tpd
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOH
VOH
VOL
VOL
3 V
0
3 V
0
1.5 V 1.5 V
1.5 V 1.5 V
tw
High-Level
Pulse
Low-Level
Pulse
Output
Control
(low-level
enabling)
W aveform 1
S1 Closed
(see Note B)
W aveform 2
S1 Open
(see Note B)
1.5 V 1.5 V
3 V
0
≈ 3.3 V
VOL
VOH
VOH – 0.5 V
≈ 0 V
ten
ten
tdis
tdis
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.5 V 1.5 V
1.5 V
1.5 V 1.5 V
1.5 V
1.5 V
1.5 V
R1
3 V
3 V
0
0
VOL + 0.5 V
5 V
NOTES: A. CL includes probe and jig capacitance and is 50 pF for tpd and ten, 5 pF for tdis.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2
is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses have the following characteristics: PRR ≤ 10 MHz, tr and tf ≤ 2 ns, duty cycle = 50%
D. When measuring propagation delay times of 3-state outputs, switch S1 is closed.
E. Equivalent loads may be used for testing.
Figure 1. Load Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
81036072A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103607RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103607SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036082A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103608RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103608SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036092A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103609RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103609SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036102A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103610RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103610SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036112A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103611RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103611SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036122A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103612RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103612SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036132A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103613RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103613SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
81036142A ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
8103614RA ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
8103614SA ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16L8A-2MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16L8A-2MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16L8A-2MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16L8A-2MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16L8AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16L8AMJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16L8AMJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16L8AMWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16R4A-2MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16R4A-2MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R4A-2MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R4A-2MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16R4AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16R4AMJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R4AMJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R4AMWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16R6A-2MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16R6A-2MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
PAL16R6A-2MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R6A-2MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16R6AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16R6AMJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R6AMJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R6AMWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16R8A-2MFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16R8A-2MJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R8A-2MJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R8A-2MWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
PAL16R8AMFKB ACTIVE LCCC FK 20 1 TBD POST-PLATE N / A for Pkg Type
PAL16R8AMJ ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R8AMJB ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type
PAL16R8AMWB ACTIVE CFP W 20 1 TBD Call TI N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF PAL16L8A-2M, PAL16L8AM, PAL16R4A-2M, PAL16R4AM, PAL16R6A-2M, PAL16R6AM, PAL16R8A-2M,
PAL16R8AM :
•Catalog: PAL16L8A-2,PAL16L8A,PAL16R4A-2,PAL16R4A,PAL16R6A-2,PAL16R6A,PAL16R8A-2,PAL16R8A
NOTE: Qualified Version Definitions:
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 3
MECHANICAL DATA
MLCC006B – OCTOBER 1996
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FK (S-CQCC-N**) LEADLESS CERAMIC CHIP CARRIER
4040140/D 10/96
28 TERMINAL SHOWN
B
0.358
(9,09)
MAX
(11,63)
0.560
(14,22)
0.560
0.458
0.858
(21,8)
1.063
(27,0)
(14,22)
A
NO. OF
MINMAX
0.358
0.660
0.761
0.458
0.342
(8,69)
MIN
(11,23)
(16,26)
0.640
0.739
0.442
(9,09)
(11,63)
(16,76)
0.962
1.165
(23,83)
0.938
(28,99)
1.141
(24,43)
(29,59)
(19,32)(18,78)
**
20
28
52
44
68
84
0.020 (0,51)
TERMINALS
0.080 (2,03)
0.064 (1,63)
(7,80)
0.307
(10,31)
0.406
(12,58)
0.495
(12,58)
0.495
(21,6)
0.850
(26,6)
1.047
0.045 (1,14)
0.045 (1,14)
0.035 (0,89)
0.035 (0,89)
0.010 (0,25)
12
1314151618 17
11
10
8
9
7
5
432
0.020 (0,51)
0.010 (0,25)
6
12826 27
19
21
B SQ
A SQ 22
23
24
25
20
0.055 (1,40)
0.045 (1,14)
0.028 (0,71)
0.022 (0,54)
0.050 (1,27)
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a metal lid.
D. The terminals are gold plated.
E. Falls within JEDEC MS-004
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