SG1525A/SG2525A/SG3525A SG1527A/SG2527A/SG3527A REGULATING PULSE WIDTH MODULATOR DESCRIPTION FEATURES The SG1525A/1527A series of pulse width modulator integrated circuits are designed to offer improved performance and lower external parts count when used to implement all types of switching power supplies. The on-chip +5.1 volt reference is trimmed to 1% initial accuracy and the input common-mode range of the error amplifier includes the reference voltage, eliminating external potentiometers and divider resistors. A Sync input to the oscillator allows multiple units to be slaved together, or a single unit to be synchronized to an external system clock. A single resistor between the CT pin and the Discharge pin provides a wide range of deadtime adjustment. These devices also feature built-in soft-start circuitry with only a timing capacitor required externally. A Shutdown pin controls both the soft-start circuitry and the output stages, providing instantaneous turn-off with soft-start recycle for slow turn-on. These functions are also controlled by an undervoltage lockout which keeps the outputs off and the soft-start capacitor discharged for input voltages less than that required for normal operation. Another unique feature of these PWM circuits is a latch following the comparator. Once a PWM pulse has been terminated for any reason, the outputs will remain off for the duration of the period. The latch is reset with each clock pulse. The output stages are totem-pole designs capable of sourcing or sinking in excess of 200mA. The SG1525A output stage features NOR logic, giving a LOW output for an OFF state. The SG1527A utilizes OR logic which results in a HIGH output level when OFF. * * * * * * * * 8V to 35V operation 5.1V reference trimmed to 1% 100Hz to 500KHz oscillator range Separate oscillator sync terminal Adjustable deadtime control Internal soft-start Input undervoltage lockout Latching P.W.M. to prevent multiple pulses * Dual source/sink output drivers HIGH RELIABILITY FEATURES - SG1525A, SG1527A Available to MIL-STD-883B MIL-M38510/12602BEA - JAN1525AJ MIL-M38510/12604BEA - JAN1527AJ Radiation data available LMI level "S" processing available BLOCK DIAGRAM Rev 1.4a 3/19/2005 Copyright 1996 Microsemi Inc. 1 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570 ABSOLUTE MAXIMUM RATINGS (Note 1) Supply Voltage (+VIN) ....................................................... 40V Collector Supply Voltage (VC) ........................................... 40V Logic Inputs ....................................................... -0.3V to 5.5V Analog Inputs ....................................................... -0.3V to V IN Output Current, Source or Sink ................................... 500mA Reference Load Current ............................................... 50mA Oscillator Charging Current ............................................ Operating Junction Temperature Range Hermetic (J, L Packages) ..................................... Plastic (N, DW Packages ) ....................................... Storage Temperature Range .......................... -65C to Lead Temperature (Soldering, 10 seconds) ................. Note 1. Values beyond which damage may occur. RoHS Peak Package Solder Reflow Temp. (40 sec. max. exp.)...... 260C(+0, -5) 5mA 150C 150C 150C 300C THERMAL DATA Note A. Junction Temperature Calculation: TJ = TA + (PD x JA). Note B. The above numbers for JC are maximums for the limiting J Package: Thermal Resistance-Junction to Case, JC .................. 30C/W Thermal Resistance-Junction to Ambient, JA .............. 80C/W DW Package: Thermal Resistance-Junction to Case, JC .................. 40C/W Thermal Resistance-Junction to Ambient, JA ............. 95C/W L Package: Thermal Resistance-Junction to Case, JC .................. 35C/W Thermal Resistance-Junction to Ambient, JA ........... 120C/W N Package: Thermal Resistance-Junction to Case, JC ................... 40C/W Thermal Resistance-Junction to Ambient, JA ............. 65C/W thermal resistance of the package in a standard mounting configuration. The JA numbers are meant to be guidelines for the thermal performance of the device/pcboard system. All of the above assume no ambient airflow. RECOMMENDED OPERATING CONDITIONS (Note 2) Deadtime Resistor Range (RD) ............................. 0 to 500 Maximum Shutdown Source Impedance ......................... 5K Oscillator Timing Capacitor (CT) ................... 0.001F to 0.1F Operating Ambient Temperature Range SG1525A/SG1527A .................................... -55C to 125C SG2525A/SG2527A ...................................... -25C to 85C SG3525A/SG3527A ......................................... 0C to 70C Input Voltage (+VIN) ................................................ 8V to 35V Collector Voltage (VC) .......................................... 4.5V to 35V Sink/Source Load Current (steady state) ............. 0 to 100mA Sink/Source Load Current (peak) ......................... 0 to 400mA Reference Load Current ........................................ 0 to 20mA Oscillator Frequency Range ....................... 100Hz to 350KHz Oscillator Timing Resistor (RT) ........................ 2K to 150K Note 2: Range over which the device is functional. ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over the operating ambient temperatures for SG1525A/SG1527A with -55C TA 125C, SG2525A/SG2527A with -25C TA 85C, SG3525A/SG3527A with 0C TA 70C, and +VIN = 20V. Low duty cycle pulse testing techniques are used which maintains junction and case temperatures equal to the ambient temperature.) Parameter Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability (Note 3) Total Output Voltage Range (Note 3) Short Circuit Current Output Noise Voltage (Note 3) Long Term Stability (Note 3) Test Conditions TJ = 25C VIN = 8V to 35V IL = 0 to 20mA Over Operating Temperature Range Over Line, Load and Temperature VREF = 0V, TJ = 25C 10Hz f 10KHz, TJ = 25C TJ = 125C SG1525A/2525A SG3525A Units SG1527A/2527A SG3527A Min. Typ. Max. Min. Typ. Max. 5.05 5.10 10 20 20 5.00 80 40 20 V 5.15 5.00 5.10 5.20 mV 30 10 30 mV 50 20 50 mV 50 20 50 V 5.25 5.20 4.95 mA 80 100 100 40 200 Vrms 200 50 mV/khr 20 50 Note 3. These parameters, although guaranteed over the recommended operating conditions, are not 100% tested in production. Note 4. FOSC = 40KHz (RT = 3.6K, CT = 0.01F, RD = 0) Note 5. Applies to SG1525A/2525A/3525A only, due to polarity of output pulses. Rev 1.4a Copyright 1996 2 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570 ELECTRICAL CHARACTERISTICS Parameter (continued) Test Conditions Oscillator Section (Note 4) Initial Accuracy TJ = 25C Voltage Stability VIN = 8V to 35V Temperature Stability (Note 3) MIN TJ MAX RT = 150K, CT = 0.1F Minimum Frequency (Note 3) Maximum Frequency (Note 3) RT = 2K, CT = 1nF IRT = 2mA Current Mirror Clock Amplitude Clock Width TJ = 25C Sync Threshold Sync Voltage = 3.5V Sync Input Current Error Amplifier Section (VCM = 5.1V) Input Offset Voltage Input Bias Current Input Offset Current DC Open Loop Gain RL 10M, TJ = 25C Gain-Bandwidth Product (Note 3) AV = 0dB, TJ = 25C Output Low Level Output High Level VCM = 1.5V to 5.2V Common Mode Rejection VIN = 8V to 35V Supply Voltage Rejection P.W.M. Comparator Section (Note 4) VCOMP = 0.6V Minimum Duty Cycle Maximum Duty Cycle VCOMP = 3.6V Input Threshold (Note 4) Zero Duty Cycle Maximum Duty Cycle Input Bias Current Soft-Start Section Soft Start Current VSHUTDOWN = 0V Soft Start Voltage VSHUTDOWN = 2V VSHUTDOWN = 2.5V Shutdown Input Current Output Drivers Section (each transistor, V C = 20V) Output High Level ISOURCE = 20mA ISOURCE = 100mA Output Low Level ISINK = 20mA ISINK = 100mA VCOMP and V SS = High Undervoltage Lockout Collector Leakage (Note 5) VC = 35V Rise Time CL = 1nF, TJ = 25C Fall Time CL = 1nF, TJ = 25C Shutdown Delay (Note 3) VSD = 3V, CS = 0, TJ = 25C Total Standby Current Standby Current VIN = 35V Rev 1.4a Copyright 1996 3 SG1525A/2525A SG3525A SG1527A/2527A SG3527A Units Min. Typ. Max. Min. Typ. Max. 37.6 40 42.4 37.6 0.3 1 6 3 150 350 350 1.7 2.0 2.2 1.7 3.0 3.5 3.0 0.3 0.5 1.0 0.3 1.2 2.0 2.8 1.2 1.0 2.5 0.5 1 60 1 3.8 60 50 75 2 0.2 5.6 75 60 5 10 1 60 1 0.5 3.8 60 50 40 1 3 42.4 2 6 150 2.0 3.5 0.5 2.0 1.0 2.2 2 1 10 10 1 75 2 0.2 5.6 75 60 49 0.9 3.3 .05 3.6 2.0 25 50 0.4 0.4 80 0.6 1.0 18 17 19 18 0.2 1.0 7 3.6 2.0 % % V V A 25 50 0.4 0.4 80 0.6 1.0 A V mA 18 17 19 18 0.2 1.0 7 100 50 0.2 0.4 2.2 8 200 600 300 0.5 V V V V V A ns ns s 6 14 20 mA 0 45 0.6 100 50 0.2 0.4 2.2 8 200 600 300 0.5 14 20 0.5 mV A A dB MHz V V dB dB 49 0.9 3.3 .05 0 45 0.6 1.0 2.8 2.5 KHz % % Hz KHz mA V s V mA 6 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570 OSCILLATOR SECTION FIGURE 1 - OSCILLATOR SCHEMATIC FIGURE 3 - OSCILLATOR DISCHARGE TIME VS. R D AND CT FIGURE 2 - OSCILLATOR CHARGE TIME VS. RT AND CT ERROR AMPLIFIER SECTION FIGURE 4 - ERROR AMPLIFIER FIGURE 5 - ERROR AMPLIFIER OPEN-LOOP FREQUENCY RESPONSE Rev 1.4a Copyright 1996 4 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570 OUTPUT SECTION FIGURE 6 -OUTPUT CIRCUIT (1/2 Circuit Shown) FIGURE 7 - OUTPUT SATURATION CHARACTERISTICS APPLICATION INFORMATION For single-ended supplies, the driver outputs are grounded. The VC terminal is switched to ground by the totem-pole source transistors on alternate oscillator cycles. In conventional push-pull bipolar designs, forward base drive is controlled by R1 - R3 . Rapid turn-off times for the power devices are achieved with speed-up capacitors C1 and C2 . The low source impedance of the output drivers provides rapid charging of power FET input capacitance while minimizing external components. Low power transformers can be driven directly by the SG1525A. Automatic reset occurs during deadtime, when both ends of the primary winding are switched to ground. Rev 1.4a Copyright 1996 5 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570 APPLICATION INFORMATION (continued) SHUTDOWN OPTIONS 1. Use an external transistor or open-collector comparator to pull down on the Comp terminal. This will set the PWM latch turning off both outputs. If the shutdown signal is momentary, pulseby-pulse protection can be accomplished as the PWM latch will be reset with each clock pulse. 3. Apply a positive-going signal to the Shutdown terminal. This will provide most rapid shutdown of the outputs but will not immediately set the PWM latch if there is a Soft-Start capacitor. This capacitor will discharge but with a current of approximately twice the charging current. 2. The same results can be accomplished by pulling down on the Soft-Start terminal with the difference that on this pin, shutdown will not affect the amplifier compensation network but must discharge any Soft-Start capacitor. 4. The shutdown terminal can be used to set the PWM latch on a pulse-by-pulse basis if there is no external capacitance on Soft-Start terminal. Slow turn-on may still be accomplished by applying an external capacitor, blocking diode, and charging resistor to the comp terminal. (See SG1524 Application Note). SG1525A/1527A LAB TEST FIXTURE Rev 1.4a Copyright 1996 6 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570 CONNECTION DIAGRAMS & ORDERING INFORMATION Package 16-PIN CERAMIC DIP J - PACKAGE 16-PIN PLASTIC DIP N - PACKAGE 16-PIN WIDE BODY PLASTIC S.O.I.C. DW - PACKAGE Part No. (See Notes Below) Ambient Temperature Range SG1525AJ/883B JAN1525AJ SG1525AJ/DESC SG1525AJ SG2525AJ SG3525AJ SG1527AJ/883B JAN1527AJ SG1527AJ/DESC SG1527AJ SG2527AJ SG3527AJ -55C to 125C -55C to 125C -55C to 125C -55C to 125C -25C to 85C 0C to 70C -55C to 125C -55C to 125C -55C to 125C -55C to 125C -25C to 85C 0C to 70C SG2525AN SG3525AN SG2527AN SG3527AN -25C to 85C 0C to 70C -25C to 85C 0C to 70C SG2525ADW SG3525ADW SG2527ADW SG3527ADW -25C to 85C 0C to 70C -25C to 85C 0C to 70C Connection Diagram INV. INPUT N.I. INPUT 1 16 2 15 SYNC OSC. OUTPUT CT RT 3 14 4 13 5 12 6 11 DISCHARGE SOFT-START 7 10 8 9 VREF +VIN OUTPUT B VC GROUND OUTPUT A SHUTDOWN COMPENSATION N Package: RoHS Compliant / Pb-free Transition DC: 0503 N Package: RoHS / Pb-free 100% Matte Tin Lead Finish INV. INPUT N.I. INPUT SYNC OSC. OUTPUT 1 16 2 15 3 14 4 13 CT RT DISCHARGE 5 12 6 11 7 10 SOFT-START 8 9 VREF +VIN OUTPUT B VC GROUND OUTPUT A SHUTDOWN COMPENSATION DW Package: RoHS Compliant / Pb-free Transition DC: 0516 DW Package: RoHS / Pb-free 100% Matte Tin Lead Finish 20-PIN CERAMIC LEADLESS CHIP CARRIER L- PACKAGE SG1525AL/883B SG1525AL SG1527AL/883B SG1527AL -55C to 125C -55C to 125C -55C to 125C -55C to 125C 1. N.C. 2. INV. INPUT 3. N.I. INPUT 4. SYNC 5. OSC. OUTPUT 6. N.C. 7. CT 8. RT 9. DISCHARGE 10. SOFT-START 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 11. N.C. 12. COMP. 13. SHUTDOWN 14. OUTPUT A 15. GROUND 16. N.C. 17. VC 18. OUTPUT B 19. +VIN 20. VREF Note 1. Contact factory for JAN and DESC product availablity. 2. All packages are viewed from the top. Rev 1.4a Copyright 1996 7 11861 Western Avenue Garden Grove, CA 92841 (714) 898-8121 FAX: (714) 893-2570