Filterless High Efficiency
Class-D Stereo Audio Amplifier
SSM2302
Rev. 0
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2006 Analog Devices, Inc. All rights reserved.
FEATURES
Filterless Class-D amplifier with built-in output stage
1.4 W into 8 Ω at 5.0 V supply with less than 1% THD
85% efficiency at 5.0 V, 1.4 W into 8 Ω speaker
Better than 98 dB SNR (signal-to-noise ratio)
Single-supply operation from 2.5 V to 5.0 V
20 nA ultralow shutdown current
Short-circuit and thermal protection
Available in 16-lead, 3 mm × 3 mm LFCSP
Pop-and-click suppression
Built-in resistors reduce board component count
Fixed and user-adjustable gain configurations
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
GENERAL DESCRIPTION
The SSM2302 is a fully integrated, high efficiency, Class-D stereo
audio amplifier. It is designed to maximize performance for
mobile phone applications. The application circuit requires a
minimum of external components and operates from a single
2.5 V to 5.0 V supply. It is capable of delivering 1.4 W of con-
tinuous output power with less than 1% THD + N driving an
8 Ω load from a 5.0 V supply.
The SSM2302 features a high efficiency, low noise modulation
scheme. It operates with 85% efficiency at 1.4 W into 8 Ω from a
5.0 V supply and has a signal-to-noise ratio (SNR) that is better
than 98 dB. PDM modulation is used to provide lower EMI-
radiated emissions compared with other Class-D architectures.
The SSM2302 has a micropower shutdown mode with a typical
shutdown current of 20 nA. Shutdown is enabled by applying a
logic low to the SD pin.
The architecture of the device allows it to achieve a very low level
of pop and click. This minimizes voltage glitches at the output
during turn-on and turn-off, thus reducing audible noise on
activation and deactivation.
The fully differential input of the SSM2302 provides excellent
rejection of common-mode noise on the input. Input coupling
capacitors can be omitted if the dc input common-mode voltage
is approximately VDD/2.
The SSM2302 also has excellent rejection of power supply noise,
including noise caused by GSM transmission bursts and RF
rectification. PSRR is typically 63 dB at 217 Hz.
The gain can be set to 6 dB or 12 dB utilizing the gain control
select pin connected respectively to ground or VDD. Gain can
also be adjusted externally by using an external resistor.
The SSM2302 is specified over the commercial temperature range
(−40°C to +85°C). It has built-in thermal shutdown and output
short-circuit protection. It is available in a 16-lead, 3 mm × 3 mm
lead-frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
GAIN
CONTROL FET
DRIVER
MODULATOR
0.1µF
VDDVDD
GNDGND
INTERNAL
OSCILLATOR
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
VBATT
2.5V TO 5.0V
INR–
GAIN
SD
GAIN
SHUTDOWN
INL+
INL–
10µF
0.01µF
1
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
0.01µF
1
0.01µF
1
0.01µF
1
LEFT IN+
LEFT IN–
RIGHT IN–
RIGHT IN+
SSM2302
06051-001
Figure 1.
SSM2302
Rev. 0 | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Typical Application Circuits............................................................ 9
Application Notes ........................................................................... 12
Overview...................................................................................... 12
Gain Selection ............................................................................. 12
Pop-and-Click Suppression ...................................................... 12
EMI Noise.................................................................................... 12
Layout .......................................................................................... 13
Input Capacitor Selection.......................................................... 13
Proper Power Supply Decoupling ............................................ 13
Evaluation Board Information...................................................... 14
Introduction................................................................................ 14
Operation .................................................................................... 14
SSM2302 Application Board Schematic.................................. 15
SSM2302 Stereo Class-D Amplifier Evaluation Module
Component List.......................................................................... 16
SSM2302 Application Board Layout........................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
REVISION HISTORY
6/06—Revision 0: Initial Version
SSM2302
Rev. 0 | Page 3 of 20
SPECIFICATIONS
VDD = 5.0 V, TA = 25oC, RL = 8 Ω, unless otherwise noted
Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DEVICE CHARACTERISTICS
Output Power PO RL = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.4 W
R
L = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.615 W
R
L = 8 Ω, THD = 1%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.275 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 5.0 V 1.53 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 3.6 V 0.77 W
R
L = 8 Ω, THD = 10%, f = 1 kHz, 20 kHz BW, VDD = 2.5 V 0.35 W
Efficiency η POUT =1.4 W, 8 Ω, VDD = 5.0 V 85 %
Total Harmonic Distortion + Noise THD + N PO = 1 W into 8 Ω each channel, f = 1 kHz, VDD = 5.0 V 0.1 %
P
O = 0.5 W into 8 Ω each channel, f = 1 kHz, VDD = 3.6 V 0.04 %
Input Common-Mode Voltage Range VCM 1.0 VDD − 1 V
Common-Mode Rejection Ratio CMRRGSM VCM = 2.5 V ± 100 mV at 217 Hz 55 dB
Channel Separation XTA LK PO = 100 mW , f = 1 kHz 98 dB
Average Switching Frequency fSW 1.8 MHz
Differential Output Offset Voltage VOOS G = 6 dB; G = 12 dB 2.0 mV
POWER SUPPLY
Supply Voltage Range VDD Guaranteed from PSRR test 2.5 5.0 V
Power Supply Rejection Ratio PSRR VDD = 2.5 V to 5.0 V, 50 Hz, input floating/ground 70 85 dB
PSRRGSM VRIPPLE = 100 mV at 217 Hz, inputs ac GND,
CIN = 0.01 μF, input referred
63 dB
Supply Current ISY VIN = 0 V, no load, VDD = 5.0 V 8.0 mA
V
IN = 0 V, no load, VDD = 3.6 V 6.6 mA
V
IN = 0 V, no load, VDD = 2.5 V 5.3 mA
Shutdown Current ISD SD = GND 20 nA
GAIN CONTROL
Closed-Loop Gain Av0 GAIN pin = 0 V 6 dB
Av1 GAIN pin = VDD 12 dB
Differential Input Impedance ZIN SD = VDD, 150 KΩ
SD = GND 210 KΩ
SHUTDOWN CONTROL
Input Voltage High VIH ISY ≥ 1 mA 1.2 V
Input Voltage Low VIL ISY ≤ 300 nA 0.5 V
Turn-On Time tWU SD rising edge from GND to VDD 30 ms
Turn-Off Time tSD SD falling edge from VDD to GND 5 μs
Output Impedance ZOUT SD = GND >100 KΩ
NOISE PERFORMANCE
Output Voltage Noise en VDD = 2.5 V to 5.0 V, f = 20 Hz to 20 kHz, inputs are
ac grounded, sine wave, AV = 6 dB, A weighting
35 μV
Signal-to-Noise Ratio SNR POUT = 1.4 W, RL = 8 Ω 98 dB
SSM2302
Rev. 0 | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Absolute maximum ratings apply at 25°C, unless otherwise noted.
Table 2.
Parameter Rating
Supply Voltage 6 V
Input Voltage VDD
Common-Mode Input Voltage VDD
Storage Temperature Range −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Junction Temperature Range −65°C to +165°C
Lead Temperature Range
(Soldering, 60 sec)
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 3. Thermal Resistance
Package Type θJA θ
JC Unit
16-lead, 3 mm × 3 mm LFCSP 44 31.5 °C/W
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
SSM2302
Rev. 0 | Page 5 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
NC = NO CONNECT
1OUTL+
2OUTL–
3SD
4INL+
11 OUTR–
12 OUTR+
10 GAIN
9 INR+
5
INL–
6
NC
7
NC
8
INR–
15 VDD
16 GND
14 VDD
13 GND
TOP VIEW
(Not to Scale)
SSM2302
06051-002
Figure 2. SSM2302 LFCSP Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Description
1 OUTL+ Inverting Output for Left Channel.
2 OUTL− Noninverting Output for Left Channel.
3 SD Shutdown Input. Active low digital input.
4 INL+ Noninverting Input for Left Channel.
5 INL− Inverting Input for Left Channel.
6 NC No Connect.
7 NC No Connect.
8 INR− Inverting Input for Right Channel.
9 INR+ Noninverting Input for Right Channel.
10 GAIN Gain Selection. Digital input.
11 OUTR− Noninverting Output for Right Channel.
12 OUTR+ Inverting Output for Right Channel.
13 GND Ground for Output Amplifiers.
14 VDD Power Supply for Output Amplifiers.
15 VDD Power Supply for Output Amplifiers.
16 GND Ground for Output Amplifiers.
SSM2302
Rev. 0 | Page 6 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
100
0.01
0.000001 0.00010.00001 10
OUTPUT POWER (W)
THD + N (%)
10
1
0.1
0.001 0.01 0.1 1
R
L
= 8Ω, 33µH
GAIN = 12dB
V
DD
= 2.5V
V
DD
= 3.6V
V
DD
= 5V
06051-003
Figure 3. THD + N vs. Output Power into 8 Ω, AV = 12 dB
100
0.01
0.0000001
0.000001 0.0001
0.00001 10
OUTPUT POWER (W)
THD + N (%)
10
1
0.1
0.001
0.01
0.1
1
RL = 8Ω, 33µH
GAIN = 6dB
VDD = 2.5V
VDD = 3.6V
VDD = 5V
06051-004
Figure 4. THD + N vs. Output Power into 8 Ω, AV = 6 dB
100
0.0001
10 100k
FREQUENCY (Hz)
THD + N (%)
V
DD
= 5V
R
L
= 8Ω, 33µH
0.5W 0.25W
1W
10
1
0.1
0.01
0.001
100 1k 10k
06051-005
Figure 5. THD + N vs. Frequency, VDD = 5.0 V
100
0.0001
10 100k
FREQUENCY (Hz)
THD + N (%)
V
DD
= 3.6V
R
L
= 8Ω, 33µH
250mW 125mW
500mW
10
1
0.1
0.01
0.001
100 1k 10k
06051-006
Figure 6. THD + N vs. Frequency, VDD = 3.6 V
100
0.0001
10 100k
FREQUENCY (Hz)
THD + N (%)
VDD = 2.5V
RL = 8Ω, 33µH
125mW 75mW
250mW
10
1
0.1
0.01
0.001
100 1k 10k
06051-007
Figure 7. THD + N vs. Frequency, VDD = 2.5 V
9
0
2.5 5.5
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
8
7
6
5
4
3
2
1
3.0 3.5 4.0 4.5 5.0
06051-008
Figure 8. Supply Current vs. Supply Voltage, No Load
SSM2302
Rev. 0 | Page 7 of 20
SHUTDOWN VOLTAGE (V)
SHUTDOWN CURRENT (µA)
12
0
00
.8
10
8
6
4
2
1.0
0
00.8
OUTPUT POWER (W)
POWER DISSIPATION (W)
V
DD
= 3.6V
R
L
= 8Ω, 33µH
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.1 0.2 0.3 0.4 0.5 0.6 0.7
V
DD
= 5V
V
DD
= 2.5V
V
DD
= 3.6V
0.1 0.2 0.3 0.4 0.5 0.6 0.7
06051-009
06051-012
Figure 9. Supply Current vs. Shutdown Voltage
1.6
0
2.5 5.0
SUPPLY VOLTAGE (V)
OUTPUT POWER (W)
10%
1%
1.4
1.2
1.0
0.8
0.6
0.4
0.2
3.0 3.5 4.0 4.5
f
= 1kHz
GAIN = 2
RL = 8Ω, 33µH
06051-010
Figure 10. Maximum Output Power vs. Supply Voltage
100
0
01
.4
OUTPUT POWER (W)
EFFICIENCY (%)
RL = 8Ω, 33µH
90
80
70
60
50
40
30
20
10
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3
VDD = 2.5V VDD = 3.6V
VDD = 5V
06051-011
Figure 11. Efficiency vs. Output Power into 8 Ω
Figure 12. Power Dissipation vs. Output Power at VDD = 3.6 V
1.8
0
01
OUTPUT POWER (W)
POWER DISSIPATION (W)
.3
VDD = 5V
RL = 8Ω, 33µH
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2
06051-013
Figure 13. Power Dissipation vs. Output Power at VDD = 5.0 V
400
0
01.6
OUTPUT POWER (W)
SUPPLY CURRENT (mA)
RL = 8Ω, 33µH
VDD = 3.6V
VDD = 2.5V
VDD = 5V
350
300
250
200
150
100
50
0.2 0.4 0.6 0.8 1.0 1.2 1.4
06051-014
Figure 14. Output Power vs. Supply Current, One Channel
SSM2302
Rev. 0 | Page 8 of 20
7
–2
–10 90
TIME (ms)
VOLTAGE
6
5
4
3
2
1
0
–1
–5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85
SD INPUT
OUTPUT
06051-018
0
–100
10 100k
FREQUENCY (Hz)
PSRR (dB)
–10
–20
–30
–40
–50
–60
–70
–80
–90
100 1k 10k
06051-015
Figure 15. Power Supply Rejection Ratio vs. Frequency Figure 18. Turn-On Response
0
–80
10 100k
FREQUENCY (Hz)
CMRR (dB)
100 1k 10k
–10
–20
–30
–40
–50
–60
–70
06051-016
R
L
= 8Ω, 33µH
GAIN = 6dB
7
–2
–20 180
TIME (ms)
VOLTAGE
6
5
4
3
2
1
0
–1
0 20 40 60 80 100 120 140 160
SD INPUT
OUTPUT
06051-019
Figure 16. Common-Mode Rejection Ratio vs. Frequency Figure 19. Turn-Off Response
0
–140
10 100k
FREQUENCY (Hz)
CROSSTALK (dB)
100 1k 10k
–20
–40
–60
–80
–100
–120
V
DD
= 3.6V
V
RIPPLE
= 1V rms
R
L
= 8Ω, 33µH
06051-017
Figure 17. Crosstalk vs. Frequency
SSM2302
Rev. 0 | Page 9 of 20
TYPICAL APPLICATION CIRCUITS
GAIN
CONTROL FET
DRIVER
MODULATOR
VDDVDD
GNDGND
V
DD
INTERNAL
OSCILLATOR
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
INR–
GAIN
SD
GAIN
SHUTDOWN
INL+
INL–
0.01µF
1
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
0.01µF
1
0.01µF
1
0.01µF
1
LEFT IN+
LEFT IN–
RIGHT IN–
RIGHT IN+
SSM2302
06051-030
0.1µF VBATT
2.5V TO 5.0V
10µF
Figure 20. Stereo Differential Input Configuration, Gain = 12 dB
GAIN
CONTROL FET
DRIVER
MODULATOR
VDDVDD
GNDGND
INTERNAL
OSCILLATOR
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
INR–
SD
SHUTDOWN
INL+
INL–
0.01µF
0.01µF
0.01µF
0.01µF
LEFT IN
RIGHT IN
SSM2302
0
6051-031
GAIN
GAIN
0.1µF VBATT
2.5V TO 5.0V
10µF
Figure 21. Stereo Single-Ended Input Configuration, Gain = 6 dB
SSM2302
Rev. 0 | Page 10 of 20
GAIN
CONTROL FET
DRIVER
MODULATOR
VDDVDD
GNDGND
V
DD
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
INR–
GAIN
SD
GAIN
SHUTDOWN
INL+
INL–
0.01µF
1
1
INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY V
DD
/2.
0.01µF
1
0.01µF
1
R
R
0.01µF
1
LEFT IN+
LEFT IN–
RIGHT IN–
RIGHT IN+
SSM2302
06051-036
R
R
EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)] 0.1µF VBATT
2.5V TO 5.0V
10µF
Figure 22. Stereo Differential Input Configuration, User-Adjustable Gain
GAIN
CONTROL FET
DRIVER
MODULATOR
VDDVDD
GNDGND
INTERNAL
OSCILLATOR
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
1INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
EXTERNAL GAIN SETTINGS = 20 log[4/(1 + R/150kΩ)]
INR–
GAIN
SD
SHUTDOWN
INL+
INL–
0.01µF1
0.01µF1
0.01µF1
0.01µF1
LEFT IN
RIGHT IN
POP/CLICK
SUPPRESSION
R
R
R
R
SSM2302
06051-037
VDD GAIN
0.1µF VBATT
2.5V TO 5.0V
10µF
Figure 23. Stereo Single-Ended Input Configuration, User-Adjustable Gain
SSM2302
Rev. 0 | Page 11 of 20
GAIN
CONTROL FET
DRIVER
MODULATOR
VDDVDD
GNDGND
INTERNAL
OSCILLATOR
POP/CLICK
SUPPRESSION
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
INR–
GAIN
SD
SHUTDOWN
INL+
INL–
0.01µF1
1INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
0.01µF1
0.01µF1
R
R
0.01µF1
LEFT IN+
LEFT IN–
RIGHT IN–
RIGHT IN+
SSM2302
06051-038
GAIN
R
R
EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)] 0.1µF VBATT
2.5V TO 5.0V
10µF
Figure 24. Stereo Differential Input Configuration, User-Adjustable Gain
GAIN
CONTROL FET
DRIVER
MODULATOR
VDDVDD
GNDGND
INTERNAL
OSCILLATOR
OUTR+
OUTR–
OUTL+
OUTL–
GAIN
CONTROL
BIAS
FET
DRIVER
MODULATOR
INR+
1INPUT CAPS ARE OPTIONAL IF INPUT DC COMMON-MODE
VOLTAGE IS APPROXIMATELY VDD/2.
EXTERNAL GAIN SETTINGS = 20 log[2/(1 + R/150kΩ)]
INR–
SD
SHUTDOWN
INL+
INL–
0.01µF1
0.01µF1
0.01µF1
0.01µF1
LEFT IN
RIGHT IN
POP/CLICK
SUPPRESSION
R
R
R
R
SSM2302
06051-039
GAIN
GAIN
0.1µF VBATT
2.5V TO 5.0V
10µF
Figure 25. Stereo Single-Ended Input Configuration, User-Adjustable Gain
SSM2302
Rev. 0 | Page 12 of 20
APPLICATION NOTES
OVERVIEW
The SSM2302 stereo Class-D audio amplifier features a filterless
modulation scheme that greatly reduces the external components
count, conserving board space and thus reducing systems cost.
The SSM2302 does not require an output filter, but instead relies
on the inherent inductance of the speaker coil and the natural
filtering of the speaker and human ear to fully recover the audio
component of the square-wave output. While most Class-D ampli-
fiers use some variation of pulse-width modulation (PWM), the
SSM2302 uses a Σ-Δ modulation to determine the switching
pattern of the output devices. This provides a number of important
benefits. Σ-Δ modulators do not produces a sharp peak with
many harmonics in the AM frequency band, as pulse-width
modulators often do. Σ-Δ modulation provides the benefits of
reducing the amplitude of spectral components at high frequencies;
that is, reducing EMI emission that might otherwise be radiated
by speakers and long cable traces. The SSM2302 also offers
protection circuits for overcurrent and temperature protection.
GAIN SELECTION
Pulling the GAIN pin high of the SSM2302 sets the gain of the
speaker amplifier to 12 dB; pulling it low sets the gain of the
speaker amplifier to 6 dB.
It is possible to adjust the SSM2302 gain by using external resistors
at the input. To set a gain lower than 12 dB refer to Figure 22 for
differential input configuration and Figure 23 for single-ended
configuration. For external gain configuration from a fixed 12 dB
gain, please use the following formula:
External Gain Settings = 20 log[4/(1 + R/150 kΩ)]
To set a gain lower than 6 dB refer to Figure 24 for differential
input configuration and Figure 25 for single-ended configuration.
For external gain configuration from a fixed 6 dB gain, use the
following formula:
External Gain Settings = 20 log[2/(1 + R/150 kΩ)]
POP-AND-CLICK SUPPRESSION
Voltage transients at the output of audio amplifiers can occur when
shutdown is activated or deactivated. Voltage transients as low
as 10 mV can be heard as an audio pop in the speaker. Clicks
and pops can also be classified as undesirable audible transients
generated by the amplifier system, therefore as not coming from
the system input signal. Such transients can be generated when
the amplifier system changes its operating mode. For example, the
following can be sources of audible transients: system power-up/
power-down, mute/unmute, input source change, and sample rate
change. The SSM2302 has a pop-and-click suppression architecture
that reduces this output transients, resulting in noiseless activation
and deactivation.
EMI NOISE
The SSM2302 uses a proprietary modulation and spread-
spectrum technology to minimize EMI emissions from the
device. Figure 26 shows SSM2302 EMI emission starting from
100 kHz to 30 MHz. Figure 27 shows SSM2302 EMI emission
from 30 kHz to 2 GHz. These figures clearly describe the SSM2302
EMI behavior as being well below the FCC regulation values,
starting from 100 kHz and passing beyond 1 GHz of frequency.
Although the overall EMI noise floor is slightly higher, frequency
spurs from the SSM2302 are greatly reduced.
06051-032
70
0
0.1 100
FREQUENCY (MHz)
LEVEL (dB(µV/m))
60
50
40
30
20
10
110
= HORIZONTAL
= VERTICAL
= REGULATION VALUE
Figure 26. EMI Emissions from SSM2302
06051-033
70
0
10 10k
FREQUENCY (MHz)
LEVEL (dB(µV/m))
60
50
40
30
20
10
100 1k
= HORIZONTAL
= VERTICAL
= REGULATION VALUE
Figure 27. EMI Emissions from SSM2302
The measurements for Figure 26 and Figure 27 were taken with
a 1 kHz input signal, producing 0.5 W output power into an 8 Ω
load from a 3.6 V supply. Cable length was approximately 5 cm.
The EMI was detected using a magnetic probe touching the 2”
output trace to the load.
SSM2302
Rev. 0 | Page 13 of 20
LAYOUT
As output power continues to increase, care needs to be taken to
lay out PCB traces and wires properly between the amplifier,
load, and power supply. A good practice is to use short, wide
PCB tracks to decrease voltage drops and minimize inductance.
Make track widths at least 200 mil for every inch of track length
for lowest DCR, and use 1 oz or 2 oz of copper PCB traces to
further reduce IR drops and inductance. A poor layout
increases voltage drops, consequently affecting efficiency. Use
large traces for the power supply inputs and amplifier outputs to
minimize losses due to parasitic trace resistance. Proper
grounding guidelines helps to improve audio performance,
minimize crosstalk between channels, and prevent switching
noise from coupling into the audio signal. To maintain high
output swing and high peak output power, the PCB traces that
connect the output pins to the load and supply pins should be as
wide as possible to maintain the minimum trace resistances. It
is also recommended to use a large-area ground plane for
minimum impedances. Good PCB layouts also isolate critical
analog paths from sources of high interference. High frequency
circuits (analog and digital) should be separated from low
frequency ones. Properly designed multilayer printed circuit
boards can reduce EMI emission and increase immunity to RF
field by a factor of 10 or more compared with double-sided
boards. A multilayer board allows a complete layer to be used
for ground plane, whereas the ground plane side of a double-
side board is often disrupted with signal crossover. If the system
has separate analog and digital ground and power planes, the
analog ground plane should be underneath the analog power
plane, and, similarly, the digital ground plane should be
underneath the digital power plane. There should be no overlap
between analog and digital ground planes nor analog and
digital power planes.
INPUT CAPACITOR SELECTION
The SSM2302 will not require input coupling capacitors if the
input signal is biased from 1.0 V to VDD − 1.0 V. Input
capacitors are required if the input signal is not biased within
this recommended input dc common-mode voltage range, if
high-pass filtering is needed (Figure 20), or if using a single-
ended source (Figure 21). If high-pass filtering is needed at the
input, the input capacitor along with the input resistor of the
SSM2302 will form a high-pass filter whose corner frequency is
determined by the following equation:
fC = 1/(2π × RIN × CIN)
Input capacitor can have very important effects on the circuit
performance. Not using input capacitors degrades the output
offset of the amplifier as well as the PSRR performance.
PROPER POWER SUPPLY DECOUPLING
To ensure high efficiency, low total harmonic distortion (THD),
and high PSRR, proper power supply decoupling is necessary.
Noise transients on the power supply lines are short-duration
voltage spikes. Although the actual switching frequency can
range from 10 kHz to 100 kHz, these spikes can contain
frequency components that extend into the hundreds of
megahertz. The power supply input needs to be decoupled with
a good quality low ESL and low ESR capacitor—usually around
4.7 μF. This capacitor bypasses low frequency noises to the
ground plane. For high frequency transients noises, use a 0.1 μF
capacitor as close as possible to the VDD pin of the device.
Placing the decoupling capacitor as close as possible to the
SSM2302 helps maintain efficiency performance.
SSM2302
Rev. 0 | Page 14 of 20
EVALUATION BOARD INFORMATION
INTRODUCTION
The SSM2302 audio power amplifier is a complete low power,
Class-D, stereo audio amplifier capable of delivering 1.4 W/channel
into 8 Ω load. In addition to the minimal parts required for the
application circuit, measurement filters are provided on the
evaluation board so that conventional audio measurements can
be made without additional components.
This section provides an overview of Analog Devices SSM2302
evaluation board. It includes a brief description of the board as
well as a list of the board specifications.
Table 5. SSM2302 Evaluation Board Specifications
Parameter Specification
Supply Voltage Range, VDD 2.5 V to 5.0 V
Power Supply Current Rating 1.5 A
Continuous Output Power, PO
(RL = 8 Ω, f = 1 kHz, 22 kHz BW)
1.4 W
Minimum Load Impedance 8 Ω
OPERATION
Use the following steps when operating the SSM2302
evaluation board.
Power and Ground
1. Set the power supply voltage between 2.5 V and 5.0 V. When
connecting the power supply to the SSM2302 evaluation
board, make sure to attach the ground connection to the
GND header pin first and then connect the positive supply
to the VDD header pin.
Inputs and Outputs
1. Ensure that the audio source is set to the minimum level.
2. Connect the audio source to Inputs INL± and INR±.
3. Connect the speakers to Outputs OUTL± and OUTR±.
Gain Control
The gain select header controls the gain setting of the SSM2302.
1. Select jumper to LG for 6 dB gain.
2. Select jumper to HG for 12 dB gain.
External Gain Settings
It is possible to adjust the SSM2302 gain using external resistors
at the input. To set a gain lower than 12 dB refer to Figure 22
and Figure 23 on the product data sheet for proper circuit con-
figuration. For external gain configuration from a fixed 12 dB
gain, use the following formula:
External Gain Settings = 20 log[4/(1 + R/150 kΩ)]
To set a gain lower than 6 dB refer to Figure 24 and Figure 25
on the product data sheet for proper circuit configuration. For
external gain configuration from a fixed 6 dB gain, use the
following formula:
External Gain Settings = 20 log[2/(1 + R/150 kΩ)]
Shutdown Control
The shutdown select header controls the shutdown function of
the SSM2302. The shutdown pin on the SSM2302 is active low,
meaning that a low voltage (GND) on this pin places the SSM2302
into shutdown mode.
1. Select jumper to 1-2 position. Shutdown pulled to VDD.
2. Select jumper to 2-3 position. Shutdown pulled to GND.
Input Configurations
1. For differential input configuration with input capacitors
do not place a jumper on JP8, JP9, JP10, and JP11.
2. For differential input configuration without input capacitors
place a jumper on JP8, JP9, JP10, and JP11.
SSM2302
Rev. 0 | Page 15 of 20
SSM2302 APPLICATION BOARD SCHEMATIC
NC
NC
U1
SSM2302
INR–
INR+
GAIN
OUTR+
OUTR–
4
3
2
1
INL+
SD
OUTL+
OUTL–
INL–
15
14
13
16
GAIN
C4
1nF
C3
1nF
1
2
2
C10
0.01µF
C7
0.1µF
C6
0.1µF
C5
10µF
C11
0.01µF
R3
100kΩ
RIGHT IN
RIN+
RIN–
JP11
HEADER 2
JP10
HEADER 2
1
1
2
3
12
9
10
11
12
VDD
VDD V
DD
GND
GND
6
7
8
5
GAIN SD
L1
FERRITE BEAD
L2
FERRITE BEAD
L1
FERRITE BEAD
OUT RIGHT
OUT LEFT
L2
FERRITE BEAD
SD C2
1nF
C1
1nF
1
2
V
DD
V
DD
V
DD
HEADER 13C
JP12
6
4
2
5
3
1
2
C8
0.01µF
C9
0.01µF
LEFT IN
JP1
JP3
LIN+
INL+
LIN–
JP9
HEADER 2
JP8
HEADER 2
1
1
2
3
12
JP2
POWER
12
R4
100kΩ
06051-034
Figure 28. SSM2302 Application Board Schematic
SSM2302
Rev. 0 | Page 16 of 20
SSM2302 STEREO CLASS-D AMPLIFIER EVALUATION MODULE COMPONENT LIST
Table 6.
Reference Description Footprint Quantity Manufacturer/Part Number
C8, C9, C10, C11 Capacitors, 0.01 μF 0402 4 Murata Manufacturing Co., Ltd./GRM15
C6, C7 Capacitor, 0.1 μF 0603 2 Murata Manufacturing Co., Ltd./GRM18
C5 Capacitor, 10 μF 0805 1 Murata Manufacturing Co., Ltd./GRM21
C1, C2, C3, C4 Capacitor, 1 nF 0402 4 Murata Manufacturing Co., Ltd./GRM15
R3, R4 Resistor, 100 kΩ 0603 2 Vishay/CRCW06031003F
L1, L2, L3, L4 Ferrite bead 0402 4 Murata Manufacturing Co., Ltd./BLM15EG121
U1 IC, SSM2302 3.0 mm × 3.0 mm 1 SSM2302CSPZ
EVAL BOARD PCB evaluation board 1
SSM2302
Rev. 0 | Page 17 of 20
SSM2302 APPLICATION BOARD LAYOUT
06051-035
Figure 29. SSM2302 Application Board Layout
SSM2302
Rev. 0 | Page 18 of 20
OUTLINE DIMENSIONS
1
0.50
BSC
0.60 MAX
PIN 1
INDICATO
R
1.50 REF
0.50
0.40
0.30
0.25 MIN
0.45
2.75
BSC SQ
TOP
VIEW
12° MAX 0.80 MAX
0.65 TYP
SEATING
PLANE
PIN 1
INDICATO
R
0.90
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.20 REF
3.00
BSC SQ
*1.65
1.50 SQ
1.35
16
5
13
8
9
12
4
EXPOSED
PAD
(BOTTOM VIEW)
*COMPLIANT
TO
JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 30. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model Temperature Range Package Description Package Option Branding
SSM2302CPZ-R21−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 A15
SSM2302CPZ-REEL1−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 A15
SSM2302CPZ-REEL71−40°C to +85°C 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ] CP-16-3 A15
1 Z = Pb-free part.
SSM2302
Rev. 0 | Page 19 of 20
NOTES
SSM2302
Rev. 0 | Page 20 of 20
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06051-0-6/06(0)
