R07DS0511EJ0300 Rev.3.00 Page 1 of 6
Jul 27, 2011
Preliminary Datasheet
2SK2788
Silicon N Channel MOS FET
High Speed Power Switching
Features
Low on-resistance
RDS(on) = 0.12 typ (VGS = 10 V, ID = 1 A)
Low drive current
High speed switching
4 V gate drive devices .
Outline
RENESAS Package code: PLZZ0004CA-A
(Package name: UPAK)
1. Gate
2. Drain
3. Source
4. Drain
4
321D
G
S
Note: Marking is “VY”
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 60 V
Gate to source voltage VGSS 20 V
Drain current ID 2 A
Drain peak current ID(pulse)*1 4 A
Body to drain diode reverse drain current IDR 2 A
Channel dissipation Pch*2 1 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW 100 s, duty cycle 10 %
2. When using the alumina ceramic board (12.5 x 2 0 x 0.7 mm)
R07DS0511EJ0300
(Previous: REJ03G1033-0200)
Rev.3.00
Jul 27, 2011
2SK2788 Preliminary
R07DS0511EJ0300 Rev.3.00 Page 2 of 6
Jul 27, 2011
Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 60 V ID = 10 mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS 20 — V IG = 100 A, VDS = 0
Zero gate voltage drain current IDSS10 A VDS = 60 V, VGS = 0
Gate to source leak current IGSS10 A VGS = 16 V, VDS = 0
Gate to source cutoff voltage VGS(off) 1.0 — 2.0 V ID = 1 mA, VDS = 10 V
RDS(on) 0.12 0.16 I
D = 1 A, VGS = 10 V*3
Static drain to source on state
resistance RDS(on) 0.16 0.25 I
D = 1 A, VGS = 4 V*3
Forward transfer admittance |yfs| 1.6 2.8 S ID = 1 A, VDS = 10 V*3
Input capacitance Ciss 180 pF
Output capacitance Coss — 90 — pF
Reverse transfer capacitance Crss 30 pF
VDS = 10 V, VGS = 0,
f = 1 MHz
Turn-on delay time td(on) 9 ns
Rise time tr — 15 — ns
Turn-off delay time td(off) — 40 — ns
Fall time tf — 35 — ns
VGS = 10 V, ID = 1 A,
RL = 30
Body to drain diode forward voltage VDF — 0.9 — V ID = 2 A, VGS = 0
Body to drain diode reverse
recovery time trr — 35 — ns
IF = 2 A, VGS = 0
diF/ dt = 50A/s
Notes: 3. Pulse test
2SK2788 Preliminary
R07DS0511EJ0300 Rev.3.00 Page 3 of 6
Jul 27, 2011
Main Characteristics
Power vs. Temperature Derating
Channel Dissipation Pch (W)
Ambient Temperature Ta (°C)
Maximum Safe Operation Area
Drain to Source Voltage V
DS
(V)
Drain Current I
D
(A)
Typical Output Characteristics
Drain Current I
D
(A)
Drain to Source Voltage V
DS
(V)
Typical Transfer Characteristics
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
Gate to Source Voltage V
GS
(V)
Drain to Source Saturation Voltage
vs. Gate to Source Voltage
Drain to Source Saturation Voltage
V
DS (on)
(V)
Drain Current I
D
(A)
Static Drain to Source on State
Resistance vs. Drain Current
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
0.1 0.3 1 310 30 10
0
5
4
3
2
1
0246810
5
4
3
2
1
0246810
6 V
2.0
1.5
1.0
0.5
050 100 150 200
10
3
1
0.3
0.1
0.03
0.01 Ta = 25°C
1 ms
PW = 10 ms (1shot)
DC Operation (Tc = 25°C)
100 μs
3.5 V
4 V
5 V
V
GS
= 2 V
2.5 V
3 V Tc = 75°C
25°C
–25°C
Pulse Test
V
DS = 10 V
Pulse Test
Operation in
this area is
limited by RDS(on)
Test condition :
When using the alumina ceramic
board (12.5 x 20 x 0.7 mm)
10 V
2.0
1.6
1.2
0.8
0.4
02468 10 0.1 3 1000.3 30
5
2
1
0.2
0.5
0.1
0.05 101
ID = 2 A
1 A
V
GS
= 4 V
10 V
Pulse Test Pulse Test
2SK2788 Preliminary
R07DS0511EJ0300 Rev.3.00 Page 4 of 6
Jul 27, 2011
Case Temperature T
C
(°C)
Static Drain to Source on State
Resistance vs. Temperature
Static Drain to Source on State Resistance
R
DS (on)
(Ω)
Forward Transfer Admittance
vs. Drain Current
Drain Current I
D
(A)
Forward Transfer Admittance yfs (S)
Body to Drain Diode Reverse
Recovery Time
Reverse Drain Current I
DR
(A)
Reverse Recovery Time trr (ns)
Typical Capacitance
vs. Drain to Source Voltage
Drain to Source Voltage V
DS
(V)
Capacitance C (pF)
Dynamic Input Characteristics
Gate Charge Qg (nc)
Drain to Source Voltage V
DS
(V)
Gate to Source Voltage V
GS
(V)
Switching Characteristics
Switching Time t (ns)
Drain Current I
D
(A)
0.5
0.4
0.3
0.2
0.1
–40 0 40 80 120 160
00.1 0.2 0.5 1 2 5 10
10
5
1
2
0.2
0.5
0.1
V
GS
= 4 V
10 V
1, 2 A
1 A
2 A 25°C
Tc = –25°C
75°C
Pulse Test
V
DS
= 10 V
Pulse Test
0.1 0.2 0.5 1 2 5 10 0102030405
0
1000
200
500
100
10
20
50
100
80
60
40
20
0
20
16
12
8
4
246810
0
100
50
10
20
2
5
1
500
200
50
100
10
20
5
di / dt = 50 A / μs
V
GS
= 0, Ta = 25°C
V
GS
= 0
f = 1 MHz
Ciss
Coss
Crss
I
D
= 2 A
V
GS
V
DS
V
DD
= 50 V
25 V
10 V
V
DD
= 10 V
25 V
50 V
0.1 0.2 0.5 1 2 5 10
V
GS
= 10 V,
V
DD
= 30 V
PW = 5 μs, duty < 1 %
tftr
td(on)
td(off)
2SK2788 Preliminary
R07DS0511EJ0300 Rev.3.00 Page 5 of 6
Jul 27, 2011
10
8
6
4
2
00.4 0.8 1.2 1.6 2.0
V
GS
= 0, –5 V
10 V 5 V
Vin Monitor
D.U.T.
Vin
10 V
R
L
V
DD
= 30 V
tr
td(on)
Vin
90% 90%
10%
10%
Vout
td(off)
Vout
Monitor
50 Ω
90%
10%
tf
Source to Drain Voltage V
SD
(V)
Reverse Drain Current I
DR
(A)
Reverse Drain Current vs.
Source to Drain Voltage
Pulse Test
Switching Time Test Circuit Waveform
2SK2788 Preliminary
R07DS0511EJ0300 Rev.3.00 Page 6 of 6
Jul 27, 2011
Package Dimensions
4.5 ± 0.1
1.8 Max 1.5 ± 0.1
0.44 Max
0.44 Max
0.48 Max
0.53 Max
1.51.5
3.0
2.5 ± 0.1
4.25 Max
0.8 Min
φ1
0.4
(1.5)
(2.5)
(0.4)
(0.2)
Previous Code
PLZZ0004CA-AUPAK / UPAKVMASS[Typ.]
0.050gSC-62 RENESAS CodeJEITA Package Code
Unit: mm
Package Name
UPAK
Ordering Information
Orderable Part Number Quantity Shipping Container
2SK2788VYTL-E 1000 pcs Taping
2SK2788VYTR-E 1000 pcs Taping
Note: For some grad es, production may be terminated. Please contact the Renesas sales office to check the state of
production before ordering the product.
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