ISL23415TFUZ-T - Intersil Corporation

Single, Low Voltage Digitally Controlled Potentiometer

(XDCP™)

ISL23415

The ISL23415 is a volatile, low voltage, low noise, low power,

SPI™ bus, 256 taps, single digitally controlled potentiometer

(DCP), which integrates DCP core, wiper switches and control

logic on a monolithic CMOS integrated circuit.

The digitally controlled potentiometer is implemented with a

combination of resistor elements and CMOS switches. The

position of the wipers are controlled by the user through the

SPI bus interface. The potentiometer has an associated

volatile Wiper Register (WR) that can be directly written to and

read by the user. The contents of the WR controls the position

of the wiper. When powered on, the ISL23415’s wiper will

always commence at mid-scale (128 tap position).

The low voltage, low power consumption, and small package

of the ISL23415 make it an ideal choice for use in battery

operated equipment. In addition, the ISL23415 has a VLOGIC

pin allowing down to 1.2V bus operation, independent from the

VCC value. This allows for low logic levels to be connected

directly to the ISL23415 without passing through a voltage

level shifter.

The DCP can be used as a three-terminal potentiometer or as a

two-terminal variable resistor in a wide variety of applications

including control, parameter adjustments, and signal

processing.

Features

• 256 resistor taps

• SPI serial interface

- No additional level translator for low bus supply

- Daisy Chaining of multiple DCP

•Power supply

-V

CC = 1.7V to 5.5V analog power supply

-V

LOGIC = 1.2V to 5.5V SPI bus/logic power supply

• Wiper resistance: 70Ω typical @ VCC = 3.3V

• Shutdown Mode - forces the DCP into an end-to-end open

circuit and RW is shorted to RL internally

• Power-on preset to mid-scale (128 tap position)

• Shutdown and standby current <2.8µA max

• DCP terminal voltage from 0V to VCC

•10kΩ, 50kΩ or 100kΩ total resistance

• Extended industrial temperature range: -40°C to +125°C

• 10 Ld MSOP or 10 Ld µTQFN packages

• Pb-free (RoHS compliant)

Applications

• Power supply margining

• RF power amplifier bias compensation

•LCD bias compensation

• Gain adjustment in battery powered instruments

• Portable medical equipment calibration

FIGURE 1. FORWARD AND BACKWARD RESISTANCE vs TAP

POSITION, 10k

FIGURE 2. VREF ADJUSTMENT

2000

4000

6000

8000

10000

0 50 100 150 200 250

TAP POSITION (DECIMAL)

RESISTANCE (Ω)

August 16, 2011

FN7780.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) and XDCP are trademarks owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

ISL23415

2FN7780.1

August 16, 2011

Block Diagram

LEVEL

SHIFTER

VCC

GND

SCK

SDI

SDO

POWER-UP

INTERFACE,

CONTROL

AND

STATUS

LOGIC

VOLATILE

AND

WIPER

CONTROL

CIRCUITRY

VLOGIC

I/O BLOCK

Pin Configurations

ISL23415

(10 LD MSOP)

TOP VIEW

ISL23415

(10 LD µTQFN)

TOP VIEW

SDO

VLOGIC

SDI

GND

SCK

VCC

GNDSCK

SDI

510

SDO

VLOGIC

Pin Descriptions

MSOP µTQFN SYMBOL DESCRIPTION

110V

LOGIC SPI bus/logic supply.

Range 1.2V to 5.5V

2 1 SCK Logic Pin - Serial bus clock input

3 2 SDO Logic Pin - Serial bus data output

(configurable)

4 3 SDI Logic Pin - Serial bus data input

5 4 CS Logic Pin - Active low Chip Select

65 RLDCP “low” terminal

76 RWDCP wiper terminal

8 7 RH DCP “high” terminal

98 V

CC Analog power supply.

Range 1.7V to 5.5V

10 9 GND Ground pin

ISL23415

3FN7780.1

August 16, 2011

Ordering Information

PART NUMBER

(Note 5)

PART

MARKING

RESISTANCE

OPTION

(kΩ)

TEMP. RANGE

(°C)

PACKAGE

(Pb-free)

PKG.

DWG. #

ISL23415TFUZ (Notes 1, 3) 3415T 100 -40 to +125 10 Ld MSOP M10.118

ISL23415UFUZ (Notes 1, 3) 3415U 50 -40 to +125 10 Ld MSOP M10.118

ISL23415WFUZ (Notes 1, 3) 3415W 10 -40 to +125 10 Ld MSOP M10.118

ISL23415TFRUZ-T7A (Notes 2, 4) HE 100 -40 to +125 10 Ld µTQFN 2.1x1.6 L10.2.1x1.6A

ISL23415TFRUZ-TK (Notes 2, 4) HE 100 -40 to +125 10 Ld µTQFN 2.1x1.6 L10.2.1x1.6A

ISL23415UFRUZ-T7A (Notes 2, 4) HD 50 -40 to +125 10 Ld µTQFN 2.1x1.6 L10.2.1x1.6A

ISL23415UFRUZ-TK (Notes 2, 4) HD 50 -40 to +125 10 Ld µTQFN 2.1x1.6 L10.2.1x1.6A

ISL23415WFRUZ-T7A (Notes 2, 4) HC 10 -40 to +125 10 Ld µTQFN 2.1x1.6 L10.2.1x1.6A

ISL23415WFRUZ-TK (Notes 2, 4) HC 10 -40 to +125 10 Ld µTQFN 2.1x1.6 L10.2.1x1.6A

NOTES:

1. Add “-TK” or “-T7A” suffix for Tape and Reel option. Please refer to TB347 for details on reel specifications.

2. Please refer to TB347 for details on reel specifications.

3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu

plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are

MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

5. For Moisture Sensitivity Level (MSL), please see device information page for ISL23415. For more information on MSL please see techbrief TB363.

ISL23415

4FN7780.1

August 16, 2011

Absolute Maximum Ratings Thermal Information

Supply Voltage Range

VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

VLOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on any DCP Terminal Pin . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Voltage on any Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6.0V

Wiper Current IW (10s). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±6mA

ESD Rating

Human Body Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . .6.5kV

CDM Model (Tested per JESD22-A114E) . . . . . . . . . . . . . . . . . . . . . . . 1kV

Machine Model (Tested per JESD22-A115-A) . . . . . . . . . . . . . . . . . . 200V

Latch Up

(Tested per JESD-78B; Class 2, Level A) . . . . . . . . . . 100mA @ +125°C

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

10 Ld MSOP Package (Note 6, 7). . . . . . . . 170 70

10 Ld µTQFN Package (Note 6, 7) . . . . . . . 145 90

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C

VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7V to 5.5V

VLOGIC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2V to 5.5V

DCP Terminal Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0 to VCC

Max Wiper Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±3mA

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

6. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.

7. For θJC, the “case temp” location is the center top of the package.

Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

Boldface limits apply over the operating temperature range, -40°C to +125°C.

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

RTOTAL RH to RL Resistance W option 10 kΩ

U option 50 kΩ

T option 100 kΩ

RH to RL Resistance Tolerance -20 ±2 +20 %

End-to-End Temperature Coefficient W option 175 ppm/°C

U option 85 ppm/°C

T option 70 ppm/°C

VRH, VRL DCP Terminal Voltage VRH or VRL to GND 0V

CC V

RWWiper Resistance RH - floating, VRL = 0V, force IW current

to the wiper, IW = (VCC - VRL)/RTOTAL,

VCC = 2.7V to 5.5V

70 200 Ω

VCC = 1.7V 580 Ω

CH/CL/CWTerminal Capacitance See “DCP Macro Model” on page 8. 32 pF

ILkgDCP Leakage on DCP Pins Voltage at pin from GND to VCC -0.4 <0.1 0.4 µA

Noise Resistor Noise Density Wiper at middle point, W option 16 nV/√Hz

Wiper at middle point, U option 49 nV/√Hz

Wiper at middle point, T option 61 nV/√Hz

Feed Thru Digital Feedthrough from Bus to Wiper Wiper at middle point -65 dB

PSRR Power Supply Reject Ratio Wiper output change if VCC change

±10%; wiper at middle point

-75 dB

ISL23415

5FN7780.1

August 16, 2011

VOLTAGE DIVIDER MODE (0V @ RL; VCC @ RH; measured at RW, unloaded)

INL

(Note 13)

Integral Non-linearity, Guaranteed

Monotonic

W option -1.0 ±0.5 +1.0 LSB

(Note 9)

U, T option -0.5 ±0.15 +0.5 LSB

(Note 9)

DNL

(Note 12)

Differential Non-linearity, Guaranteed

Monotonic

W option -1 ±0.4 +1 LSB

(Note 9)

U, T option -0.4 ±0.1 +0.4 LSB

(Note 9)

FSerror

(Note 11)

Full-scale Error W option -3.5 -2 0LSB

(Note 9)

U, T option -2 -0.5 0LSB

(Note 9)

ZSerror

(Note 10)

Zero-scale Error W option 023.5 LSB

(Note 9)

U, T option 00.4 2LSB

(Note 9)

TCV

(Note 14)

Ratiometric Temperature Coefficient W option, Wiper Register set to 80 hex 8 ppm/°C

U option, Wiper Register set to 80 hex 4 ppm/°C

T option, Wiper Register set to 80 hex 2.3 ppm/°C

Large Signal Wiper Settling Time From code 0 to FF hex 300 ns

fcutoff -3dB Cutoff Frequency Wiper at middle point W option 1200 kHz

Wiper at middle point U option 250 kHz

Wiper at middle point T option 120 kHz

RHEOSTAT MODE (Measurements between RW and RL pins with RH not connected, or between RW and RH with RL not connected)

RINL

(Note 18)

Integral Non-linearity, Guaranteed

Monotonic

W option; VCC = 2.7V to 5.5V -2.0 ±1 +2.0 MI

(Note 15)

W option; VCC = 1.7V 10.5 MI

(Note 15)

U, T option; VCC = 2.7V to 5.5V -1.0 ±0.3 +1.0 MI

(Note 15)

U, T option; VCC = 1.7V 2.1 MI

(Note 15)

RDNL

(Note 17)

Differential Non-linearity, Guaranteed

Monotonic

W option; VCC = 2.7V to 5.5V -1 ±0.4 +1 MI

(Note 15)

W option; VCC = 1.7V ±0.6 MI

(Note 15)

U, T option; VCC = 2.7V to 5.5V -0.5 ±0.15 +0.5 MI

(Note 15)

U, T option; VCC = 1.7V ±0.35 MI

(Note 15)

Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

ISL23415

6FN7780.1

August 16, 2011

Roffset

(Note 16)

Offset, Wiper at 0 Position W option; VCC = 2.7V to 5.5V 035.5 MI

(Note 15)

W option; VCC = 1.7V 6.3 MI

(Note 15)

U, T option; VCC = 2.7V to 5.5V 00.5 2MI

(Note 15)

U, T option; VCC = 1.7V 1.1 MI

(Note 15)

TCR

(Note 19)

Resistance Temperature Coefficient W option; Wiper register set between

32 hex and FF hex

220 ppm/°C

U option; Wiper register set between

32 hex and FF hex

100 ppm/°C

T option; Wiper register set between 32

hex and FF hex

75 ppm/°C

Analog Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

Boldface limits apply over the operating temperature range, -40°C to +125°C.

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

ILOGIC VLOGIC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V,

fSCK = 5MHz (for SPI active read and write)

1.5 mA

VLOGIC = 1.2V, VCC = 1.7V,

fSCK = 1MHz (for SPI active read and write)

30 µA

ICC VCC Supply Current (Write/Read) VLOGIC = 5.5V, VCC = 5.5V 100 µA

VLOGIC = 1.2V, VCC = 1.7V 10 µA

ILOGIC SB VLOGIC Standby Current VLOGIC = 5.5V, VCC = 5.5V,

SPI interface in standby

1.3 µA

VLOGIC = 1.2V, VCC = 1.7V,

SPI interface in standby

0.4 µA

ICC SB VCC Standby Current VLOGIC = 5.5V, VCC = 5.5V,

SPI interface in standby

1.5 µA

VLOGIC = 1.2V, VCC = 1.7V,

SPI interface in standby

1µA

ILOGIC SHDN VLOGIC Shutdown Current VLOGIC = 5.5V, VCC = 5.5V,

SPI interface in standby

1.3 µA

VLOGIC = 1.2V, VCC = 1.7V,

SPI interface in standby

0.4 µA

ICC SHDN VCC Shutdown Current VLOGIC = VCC = 5.5V,

SPI interface in standby

1.5 µA

VLOGIC = 1.2V, VCC = 1.7V,

SPI interface in standby

1µA

ILkgDig Leakage Current, at Pins CS, SDO, SDI, SCK Voltage at pin from GND to VLOGIC -0.4 <0.1 0.4 µA

ISL23415

7FN7780.1

August 16, 2011

tDCP Wiper Response Time W option; CS rising edge to wiper new position,

from 10% to 90% of final value.

0.4 µs

U option; CS rising edge to wiper new position,

from 10% to 90% of final value.

1.5 µs

T option; CS rising edge to wiper new position,

from 10% to 90% of final value.

3.5 µs

tShdnRec DCP Recall Time From Shutdown Mode CS rising edge to wiper recalled position and

RH connection

1.5 µs

VCC, VLOGIC

Ramp

VCC, VLOGIC Ramp Rate Ramp monotonic at any level 0.01 50 V/ms

Operating Specifications VCC = 2.7V to 5.5V, VLOGIC = 1.2V to 5.5V over recommended operating conditions unless otherwise stated.

Boldface limits apply over the operating temperature range, -40°C to +125°C. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted.

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

VIL Input LOW Voltage -0.3 0.3 x VLOGIC V

VIH Input HIGH Voltage 0.7 x VLOGIC VLOGIC+ 0.3 V

Hysteresis SDI and SCK Input Buffer Hysteresis VLOGIC > 2V 0.05 x VLOGIC V

VLOGIC < 2V 0.1 x VLOGIC

VOL SDO Output Buffer LOW Voltage IOL = 3mA, VLOGIC > 2V 0 0.4 V

IOL = 1.5mA, VLOGIC < 2V 0.2 x VLOGIC V

Rpu

(Note 19)

SDO Pull-up Resistor Off-chip Maximum is determined by tRO and tFO with

maximum bus load Cb = 30pF, fSCK =5MHz

1.5 kΩ

Cpin SCK, SDO, SDI, CS Pin Capacitance 10 pF

fSCK SCK Frequency VLOGIC = 1.7V to 5.5V 5 MHz

VLOGIC = 1.2V to 1.6V 1 MHz

tCYC SPI Clock Cycle Time VLOGIC ≥ 1.7V 200 ns

tWH SPI Clock High Time VLOGIC ≥ 1.7V 100 ns

tWL SPI Clock Low Time VLOGIC ≥ 1.7V 100 ns

tLEAD Lead Time VLOGIC ≥ 1.7V 250 ns

tLAG Lag Time VLOGIC ≥ 1.7V 250 ns

tSU SDI, SCK and CS Input Setup Time VLOGIC ≥ 1.7V 50 ns

tHSDI, SCK and CS Input Hold Time VLOGIC ≥ 1.7V 50 ns

tRI SDI, SCK and CS Input Rise Time VLOGIC ≥ 1.7V 10 ns

tFI SDI, SCK and CS Input Fall Time VLOGIC ≥ 1.7V 10 20 ns

tDIS SDO Output Disable Time VLOGIC ≥ 1.7V 0 100 ns

tSO SDO Output Setup Time VLOGIC ≥ 1.7V 50 ns

tVSDO Output Valid Time VLOGIC ≥ 1.7V 150 ns

tHO SDO Output Hold Time VLOGIC ≥ 1.7V 0 ns

tRO SDO Output Rise Time Rpu = 1.5k, Cbus = 30pF 60 ns

tFO SDO Output Fall Time Rpu = 1.5k, Cbus = 30pF 60 ns

ISL23415

8FN7780.1

August 16, 2011

DCP Macro Model

tCS CS Deselect Time 2 µs

NOTES:

8. Typical values are for TA = +25°C and 3.3V supply voltages.

9. LSB = [V(RW)255 – V(RW)0]/255. V(RW)255 and V(RW)0 are V(RW) for the DCP register set to FF hex and 00 hex respectively. LSB is the incremental

voltage when changing from one tap to an adjacent tap.

10. ZS error = V(RW)0/LSB.

11. FS error = [V(RW)255 – VCC]/LSB.

12. DNL = [V(RW)i – V(RW)i-1]/LSB-1, for i = 1 to 255. i is the DCP register setting.

13. INL = [V(RW)i – i • LSB – V(RW)0]/LSB for i = 1 to 255

14. for i = 16 to 255 decimal, T = -40°C to +125°C. Max( ) is the maximum value of the wiper voltage

and Min( ) is the minimum value of the wiper voltage over the temperature range.

15. MI = |RW255 – RW0|/255. MI is a minimum increment. RW255 and RW0 are the measured resistances for the DCP register set to FF hex and 00

hex respectively.

16. Roffset = RW0/MI, when measuring between RW and RL.

Roffset = RW255/MI, when measuring between RW and RH.

17. RDNL = (RWi – RWi-1)/MI -1, for i = 16 to 255.

18. RINL = [RWi – (MI • i) – RW0]/MI, for i = 16 to 255.

19. for i = 16 to 255, T = -40°C to +125°C. Max( ) is the maximum value of the resistance and Min( ) is the

minimum value of the resistance over the temperature range.

20. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

Serial Interface Specification For SCK, SDI, SDO, CS Unless Otherwise Noted. (Continued)

SYMBOL PARAMETER TEST CONDITIONS

MIN

(Note 20)

TYP

(Note 8)

MAX

(Note 20) UNITS

Max V RW()

()Min V RW()

()–

VRWi+25°C()()

------------------------------------------------------------------------------106

+165°C

---------------------

×=

Max Ri()Min Ri()–[]

Ri +25°C()

-------------------------------------------------------10

+165°C

---------------------

×=

32pF

RTOTAL

32pF

Timing Diagrams

Input Timing

...

SCK

SDI

SDO

MSB LSB

tLEAD

tSU tFI

tCS

tLAG

tCYC

tWL

...

tRI

tWH

ISL23415

9FN7780.1

August 16, 2011

Output Timing

XDCP™ Timing (for All Load Instructions)

Timing Diagrams (Continued)

...

SCK

SDO

SDI ADDR

MSB LSB

tDIS

tHO

...

tSO

...

SCK

SDI MSB LSB

tDCP

...

SDO

*When CS is HIGH

SDO at Z or Hi-Z state

Typical Performance Curves

FIGURE 3. 10k DNL vs TAP POSITION, VCC = 5V FIGURE 4. 50k DNL vs TAP POSITION, VCC = 5V

-0.4

-0.2

0.2

0.4

0 50 100 150 200 250

DNL (LSB)

TAP POSITION (DECIMAL)

-0.30

-0.15

0.15

0.30

0 50 100 150 200 250

DNL (LSB)

TAP POSITION (DECIMAL)

ISL23415

10 FN7780.1

August 16, 2011

FIGURE 5. 10k INL vs TAP POSITION, VCC = 5V FIGURE 6. 50k INL vs TAP POSITION, VCC = 5V

FIGURE 7. 10k RDNL vs TAP POSITION, VCC = 5V FIGURE 8. 50k RDNL vs TAP POSITION, VCC = 5V

FIGURE 9. 10k RINL vs TAP POSITION, VCC = 5V FIGURE 10. 50k RINL vs TAP POSITION, VCC = 5V

Typical Performance Curves (Continued)

-0.4

-0.2

0.2

0.4

0 50 100 150 200 250

INL (LSB)

TAP POSITION (DECIMAL)

-0.30

-0.15

0.15

0.30

0 50 100 150 200 250

INL (LSB)

TAP POSITION (DECIMAL)

-0.4

-0.2

0.2

0.4

0 50 100 150 200 250

RDNL (MI)

TAP POSITION (DECIMAL)

-0.30

-0.15

0.15

0.30

0 50 100 150 200 250

RDNL (MI)

TAP POSITION (DECIMAL)

-0.6

-0.4

-0.2

0.2

0.4

0.6

0 50 100 150 200 250

RINL (MI)

TAP POSITION (DECIMAL)

-0.30

-0.15

0.15

0.30

0 50 100 150 200 250

RINL (MI)

TAP POSITION (DECIMAL)

ISL23415

11 FN7780.1

August 16, 2011

FIGURE 11. 10k WIPER RESISTANCE vs TAP POSITION, VCC = 5V FIGURE 12. 50k WIPER RESISTANCE vs TAP POSITION, VCC = 5V

FIGURE 13. 10k TCv vs TAP POSITION FIGURE 14. 50k TCv vs TAP POSITION

FIGURE 15. 10k TCr vs TAP POSITION FIGURE 16. 50k TCr vs TAP POSITION

Typical Performance Curves (Continued)

0 50 100 150 200 250

WIPER RESISTANCE (Ω)

TAP POSITION (DECIMAL)

+125°C

-40°C

+25°C

0 50 100 150 200 250

TAP POSITION (DECIMAL)

WIPER RESISTANCE (Ω)

+125°C

-40°C

+25°C

100

150

200

250

300

15 65 115 165 215

TCv (ppm/°C)

TAP POSITION (DECIMAL)

15 65 115 165 215

TCv (ppm/°C)

TAP POSITION (DECIMAL)

100

200

300

400

500

600

15 65 115 165 215

TCr (ppm/°C)

TAP POSITION (DECIMAL)

100

150

200

15 65 115 165 215

TCr (ppm/°C)

TAP POSITION (DECIMAL)

ISL23415

12 FN7780.1

August 16, 2011

FIGURE 17. 100k TCv vs TAP POSITION FIGURE 18. 100k TCr vs TAP POSITION

FIGURE 19. WIPER DIGITAL FEEDTHROUGH FIGURE 20. WIPER TRANSITION GLITCH

FIGURE 21. WIPER LARGE SIGNAL SETTLING TIME FIGURE 22. POWER-ON START-UP IN VOLTAGE DIVIDER MODE

Typical Performance Curves (Continued)

15 65 115 165 215

TCv (ppm/°C)

TAP POSITION (DECIMAL)

120

15 65 115 165 215

TCr (ppm/°C)

TAP POSITION (DECIMAL)

10mV/DIV

1µs/DIV

RW PIN

SCK CLOCK

20mV/DIV

5µs/DIV

1V/DIV

1µs/DIV

CS RISING EDGE

VRW

1V/DIV

0.1s/DIV

ISL23415

13 FN7780.1

August 16, 2011

Functional Pin Description

Potentiometers Pins

RH AND RL

The high (RH) and low (RL) terminals of the ISL23415 are

equivalent to the fixed terminals of a mechanical potentiometer.

The RH and RL are referenced to the relative position of the wiper

and not the voltage potential on the terminals. With the WR

with the WR register set to 0, the wiper is closest to RL.

The RW is the wiper terminal, and it is equivalent to the

moveable terminal of a mechanical potentiometer. The position

of the wiper within the array is determined by the WR register.

Power Pins

VCC

Power terminal for the potentiometer section analog power

source. Can be any value needed to support voltage range of DCP

pins, from 1.7V to 5.5V, independent of the VLOGIC voltage.

Bus Interface Pins

SERIAL CLOCK (SCL)

This input is the serial clock of the SPI serial interface.

SERIAL DATA INPUT (SDI)

The SDI is a serial data input pin for SPI interface. It receives

operation code, wiper address and data from the SPI remote

host device. The data bits are shifted in at the rising edge of the

serial clock SCK, while the CS input is low.

SERIAL DATA OUTPUT (SDO)

The SDO is a serial data output pin. During a read cycle, the data

bits are shifted out on the falling edge of the serial clock SCK and

will be available to the master on the following rising edge of SCK.

The output type is configured through ACR[1] bit for Push-Pull or

Open Drain operation. Default setting for this pin is Push-Pull. An

external pull-up resistor is required for Open Drain output

operation. When CS is HIGH, the SDO pin is in tri-state (Z) or

high-tri-state (Hi-Z) depends on the selected configuration.

CHIP SELECT (CS)

CS LOW enables the ISL23415, placing it in the active power

mode. A HIGH to LOW transition on CS is required prior to the

start of any operation after power-up. When CS is HIGH, the

ISL23415 is deselected and the SDO pin is at high impedance,

and the device will be in the standby state.

VLOGIC

Digital power source for the logic control section. It supplies an

internal level translator for 1.2V to 5.5V serial bus operation. Use

the same supply as the I2C logic source.

Principles of Operation

The ISL23415 is an integrated circuit incorporating one DCP with

its associated registers and an SPI serial interface providing

direct communication between a host and the potentiometer.

The resistor array is comprised of individual resistors connected

in series. At either end of the array and between each resistor is

an electronic switch that transfers the potential at that point to

the wiper.

The electronic switches on the device operate in a “make before

break” mode when the wiper changes tap positions.

Voltage at any DCP pins, RH, RL or RW, should not exceed VCC

level at any conditions during power-up and normal operation.

The VLOGIC pin needs to be connected to the SPI bus supply

which allows reliable communication with the wide range of

microcontrollers and independent of the VCC level. This is

extremely important in systems where the digital supply has

lower levels than the analog supply.

FIGURE 23. 10k -3dB CUT OFF FREQUENCY FIGURE 24. STANDBY CURRENT vs TEMPERATURE

Typical Performance Curves (Continued)

RTOTAL = 10k

-3dB FREQUENCY = 1.4MHz AT MIDDLE TAP

CH1: 0.5V/DIV, 0.2µs/DIV RH PIN

CH2: 0.2V/DIV, 0.2µs/DIV RW PIN

0.2

0.4

0.6

0.8

1.0

1.2

-40 -15 10 35 60 85 110

STANDBY CURRENT I

(µA)

TEMPERATURE (°C)

VCC = 5.5V, VLOGIC = 5.5V

VCC = 1.7V, VLOGIC = 1.2V

ISL23415

14 FN7780.1

August 16, 2011

DCP Description

Each DCP is implemented with a combination of resistor

elements and CMOS switches. The physical ends of DCP are

equivalent to the fixed terminals of a mechanical potentiometer

(RH and RL pins). The RW pin of the DCP is connected to

intermediate nodes, and is equivalent to the wiper terminal of a

mechanical potentiometer. The position of the wiper terminal

within the DCP is controlled by the 8-bit volatile Wiper Register

(WR). When the WR of a DCP contains all zeroes (WR[7:0] = 00h),

its wiper terminal (RW) is closest to its “Low” terminal (RL). When

the WR register of a DCP contains all ones (WR[7:0] = FFh), its

wiper terminal (RW) is closest to its “High” terminal (RH). As the

value of the WR increases from all zeroes (0) to all ones (255

decimal), the wiper moves monotonically from the position

closest to RL to the position closest to RH. At the same time, the

resistance between RW and RL increases monotonically, while

the resistance between RH and RW decreases monotonically.

While the ISL23415 is being powered up, the WR is reset to 80h

(128 decimal), which locates RW roughly at the center between

RL and RH.

The WR can be read or written to directly using the SPI serial

interface as described in the following sections.

Memory Description

The ISL23415 contains two volatile 8-bit registers: the Wiper

of ISL23415 is in Table 1. The Wiper Register WR at address 0

contains current wiper position of the DCP. The Access Control

bits described in Table 2.

The SDO bit (ACR[1]) configures type of SDO output pin. The

default value of SDO bit is 0 for Push-Pull output. The SDO pin

can be configured as Open Drain output for some applications. In

this case, an external pull-up resistor is required, reference the

“Serial Interface Specification” on page 7.

Shutdown Function

The SHDN bit (ACR[6]) disables or enables shutdown mode for all

DCP channels simultaneously. When this bit is 0, i.e., each DCP is

forced to end-to-end open circuit and each RW shorted to RL

through a 2kΩ serial resistor, as shown in Figure 25. Default value

of the SHDN bit is 1.

When the device enters shutdown, all current DCP WR settings are

maintained. When the device exits shutdown, the wipers will

return to the previous WR settings after a short settling time

(see Figure 26).

SPI Serial Interface

The ISL23415 supports an SPI serial protocol, mode 0. The

device is accessed via the SDI input and SDO output with data

clocked in on the rising edge of SCK, and clocked out on the

falling edge of SCK. CS must be LOW during communication with

the ISL23415. The SCK and CS lines are controlled by the host or

master. The ISL23415 operates only as a slave device.

All communication over the SPI interface is conducted by

sending the MSB of each byte of data first.

Protocol Conventions

The SPI protocol contains Instruction Byte followed by one or more

Data Bytes. A valid Instruction Byte contains instruction as the three

MSBs, with the following five register address bits (see Table 3).

The next byte sent to the ISL23415 is the Data Byte.

Table 4 contains a valid instruction set for ISL23415.

If the [R4:R0] bits are zero or one, then the read or write is to the

WRi register. If the [R4:R0] are 10000, then the operation is to

the ACR.

TABLE 1. MEMORY MAP

ADDRESS

(hex) VOLATILE

DEFAULT SETTING

(hex)

10 ACR 40

0WR 80

TABLE 2. ACCESS CONTROL REGISTER (ACR)

BIT # 76543210

NAME 0SHDN

00 0 0SDO0

FIGURE 25. DCP CONNECTION IN SHUTDOWN MODE

FIGURE 26. SHUTDOWN MODE WIPER RESPONSE

TABLE 3. INSTRUCTION BY TE FORMAT

BIT #76543210

I2 I1 I0 R4 R3 R2 R1 R0

2kΩ

POWER-UP

USER PROGRAMMED

MID SCALE = 80H

SHDN ACTIVATED SHDN RELEASED

AFTER SHDN

WIPER VOLTAGE, VRW (V)

SHDN MODE

TIME (s)

WIPER RESTORE TO

THE ORIGINAL POSITION

ISL23415

15 FN7780.1

August 16, 2011

Write Operation

A write operation to the ISL23415 is a two or more bytes

operation. It requires first, the CS transition from HIGH-to-LOW.

Then the host sends a valid Instruction Byte, followed by one or

more Data Bytes to the SDI pin. The host terminates the write

operation by pulling the CS pin from LOW-to-HIGH. Instruction is

executed on the rising edge of CS (see Figure 27).

Read Operation

A Read operation to the ISL23415 is a four byte operation. It

requires first, the CS transition from HIGH-to-LOW. Then the host

sends a valid Instruction Byte, followed by a “dummy” Data Byte,

NOP Instruction Byte and another “dummy” Data Byte to SDI pin.

The SPI host receives the Instruction Byte (instruction code +

rising edge of SCK during third and fourth bytes, respectively. The

host terminates the read by pulling the CS pin from LOW-to-HIGH

(see Figure 28).

TABLE 4. INSTRUCTION SET

INSTRUCTION SET

OPERATIONI2 I1 I0 R4 R3 R2 R1 R0

000XXXXXNOP

001XXXXXACR READ

011XXXXXACR WRTE

1 0 0 R4R3R2R1R0WRi or ACR READ

1 1 0 R4R3R2R1R0WRi or ACR WRTE

Where X means “do not care”.

FIGURE 27. TWO BYTE WRITE SEQUENCE

SCK

SDI

SDO

WR INSTRUCTION

DATA BYTE

1 3 4 5 7 8 9 1011121314151626

ADDR

FIGURE 28. FOUR BYTE READ SEQUENCE

SCK

SDI

SDO

RD ADDR

NOP

RD ADDR READ DATA

1 8 16 24 32

ISL23415

16 FN7780.1

August 16, 2011

Applications Information

Communicating with ISL23415

Communication with ISL23415 proceeds using SPI interface

through the ACR (address 10000b) and WR (addresses 00000b)

registers.

The wiper of the potentiometer is controlled by the WR register.

Writes and reads can be made directly to these register to control

and monitor the wiper position.

Daisy Chain Configuration

When application needs more than one ISL23415, it can

communicate with all of them without additional CS lines by

daisy chaining the DCPs as shown on Figure 29. In Daisy Chain

configuration, the SDO pin of the previous chip is connected to

the SDI pin of the following chip, and each CS and SCK pins are

connected to the corresponding microcontroller pins in parallel,

like regular SPI interface implementation. The Daisy Chain

configuration can also be used for simultaneous setting of

multiple DCPs. Note, the number of daisy chained DCPs is

limited only by the driving capabilities of SCK and CS pins of

microcontroller; for larger number of SPI devices buffering of

SCK and CS lines is required.

Daisy Chain Write Operation

The write operation starts by HIGH-to-LOW transition on CS line,

followed by N number of two bytes write instructions on SDI line

with reversed chain access sequence: the instruction byte + data

byte for the last DCP in chain is going first, as shown in Figure 30,

where N is a number of DCPs in chain. The serial data is going

through DCPs from DCP0 to DCP(N-1) as follow: DCP0 --> DCP1 -->

DCP2 --> ... --> DCP(N-1). The write instruction is executed on the

rising edge of CS for all N DCPs simultaneously.

Daisy Chain Read Operation

The read operation consists of two parts: first, send the read

instructions (N two bytes operation) with valid address; second,

read the requested data while sending NOP instructions (N two

bytes operation) as shown in Figures 31 and 32.

The first part starts by HIGH-to-LOW transition on CS line,

followed by N two bytes read instruction on SDI line with reversed

chain access sequence: the instruction byte + dummy data byte

for the last DCP in chain is going first, followed by LOW-to-HIGH

transition on CS line. The read instructions are executed during

second part of read sequence. It also starts by HIGH-to-LOW

transition on CS line, followed by N number of two bytes NOP

instructions on SDI line and LOW-to-HIGH transition of CS. The

data is read on every even byte during second part of read

sequence while every odd byte contains code 111b followed by

address from which the data is being read.

Wiper Transition

When stepping up through each tap in voltage divider mode,

some tap transition points can result in noticeable voltage

transients, or overshoot/undershoot, resulting from the sudden

transition from a very low impedance “make” to a much higher

impedance “break within a short period of time (<1µs). There are

several code transitions such as 0Fh to 10h, 1Fh to 20h,..., EFh to

FFh, which have higher transient glitch. Note, that all switching

transients will settle well within the settling time as stated in the

datasheet. A small capacitor can be added externally to reduce

the amplitude of these voltage transients, but that will also

reduce the useful bandwidth of the circuit, thus may not be a

good solution for some applications. It may be a good idea, in

that case, to use fast amplifiers in a signal chain for fast

recovery.

VLOGIC Requirements

It is recommended to keep VLOGIC powered all the time during

normal operation. In a case where turning VLOGIC OFF is

necessary, it is recommended to ground the VLOGIC pin of the

ISL23415. Grounding the VLOGIC pin or both VLOGIC and VCC does

not affect other devices on the same bus. It is good practice to put

a 1µF capacitor in parallel with 0.1µF decoupling capacitor close to

the VLOGIC pin.

VCC Requirements and Placement

It is recommended to put a 1µF capacitor in parallel with 0.1µF

decoupling capacitor close to the VCC pin.

SCK

MOSI

MISO CS

SCK

SDI SDO

SCK

SDI SDO

SCK

SDI SDO

SCK

SDI SDO

µC

DCP0 DCP1 DCP2 DCP(N-1)

FIGURE 29. DAISY CHAIN CONFIGURATION

N DCP IN A CHAIN

ISL23415

17 FN7780.1

August 16, 2011

SCK

SDI

SDO 0

WR D C P2

WR D C P1 WR D C P0

WR D C P1

SDO 1 WR D C P2

SDO 2

WR D C P2

FIGURE 30. DAISY CHAIN WRITE SEQUENCE OF N = 3 DCP

16 CLKLS 16 CLKS 16 CLKS

FIGURE 31. TWO BYTE READ INSTRUCTION

SCK

SDI

SDO

INSTRUCTION ADDR

DATA IN

DATA OUT

1 2 10 11 12 13 14 15 16345 67 8 9

SCK

SDI

SDO

RD DCP1 RD DCP0 NOP

NOP NOP

DCP2 OUT DCP1 OUT DCP0 OUT

RD DCP2

16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS 16 CLKS

FIGURE 32. DAISY CHAIN READ SEQUENCE OF N = 3 DCP

ISL23415

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7780.1

August 16, 2011

For additional products, see www.intersil.com/product_tree

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make

sure you have the latest Rev.

Products

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For a complete listing of Applications, Related Documentation and Related Parts, please see the respective device information page on

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FITs are available from our website at http://rel.intersil.com/reports/search.php

DATE REVISION CHANGE

12/15/10 FN7780.0 Initial Release.

7/28/11 FN7780.1 Added “Shutdown Function” section and revised “VLOGIC Standby Current”and “VCC Shutdown Current” limits on

page 6.

On page 7, split “Wiper Response Time” up into 3 separate conditions for each option (W, U, T).

ISL23415

19 FN7780.1

August 16, 2011

Mini Small Outline Plastic Packages (MSOP)

NOTES:

1. These package dimensions are within allowable dimensions of

JEDEC MO-187BA.

2. Dimensioning and tolerancing per ANSI Y14.5M-1994.

3. Dimension “D” does not include mold flash, protrusions or gate

burrs and are measured at Datum Plane. Mold flash, protrusion

and gate burrs shall not exceed 0.15mm (0.006 inch) per side.

4. Dimension “E1” does not include interlead flash or protrusions

and are measured at Datum Plane. Interlead flash and

protrusions shall not exceed 0.15mm (0.006 inch) per side.

5. Formed leads shall be planar with respect to one another within

0.10mm (.004) at seating Plane.

6. “L” is the length of terminal for soldering to a substrate.

7. “N” is the number of terminal positions.

8. Terminal numbers are shown for reference only.

9. Dimension “b” does not include dambar protrusion. Allowable

dambar protrusion shall be 0.08mm (0.003 inch) total in excess

of “b” dimension at maximum material condition. Minimum space

between protrusion and adjacent lead is 0.07mm (0.0027 inch).

10. Datums and to be determined at Datum plane

11. Controlling dimension: MILLIMETER. Converted inch dimen-

sions are for reference only

0.25

(0.010)

4X θ

GAUGE

PLANE

SEATING

PLANE

EE1

TOP VIEW

INDEX

AREA

-C-

-B-

0.20 (0.008) ABC

SEATING

PLANE

0.20 (0.008) C

0.10 (0.004) C

-A-

-H-

SIDE VIEW

-B-

END VIEW

0.20 (0.008) CD

- H -

-A - - B -

- H -

M10.118 (JEDEC MO-187BA)

10 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE

SYMBOL

INCHES MILLIMETERS

NOTESMIN MAX MIN MAX

A 0.037 0.043 0.94 1.10 -

A1 0.002 0.006 0.05 0.15 -

A2 0.030 0.037 0.75 0.95 -

b 0.007 0.011 0.18 0.27 9

c 0.004 0.008 0.09 0.20 -

D 0.116 0.120 2.95 3.05 3

E1 0.116 0.120 2.95 3.05 4

e 0.020 BSC 0.50 BSC -

E 0.187 0.199 4.75 5.05 -

L 0.016 0.028 0.40 0.70 6

L1 0.037 REF 0.95 REF -

N10 107

R 0.003 - 0.07 - -

R1 0.003 - 0.07 - -

5o15o5o15o-

α0o6o0o6o-

Rev. 0 12/02

ISL23415

20 FN7780.1

August 16, 2011

Package Outline Drawing

L10.2.1x1.6A

10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 5, 3/10

BOTTOM VIEW

DETAIL "X"

SIDE VIEW

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

0.10

1.60

2.10

INDEX AREA

PIN 1

(6X 0.50 )

(10 X 0.20)

(0.10 MIN.)

(0.05 MIN)

(10X 0.60)

PACKAGE

(2.00) (0.80)

(1.30)

(2.50)

0.08

SEATING PLANE

0.10 C

SEE DETAIL "X"

MAX. 0.55

0 . 125 REF

0-0.05

6X 0.50

10 X 0.20 4

0.10

MAB

0.80

PIN #1 ID

0.10 MIN.

0.05 MIN.

4X 0.20 MIN.

10X 0.40

OUTLINE

Lead width dimension applies to the metallized terminal and is measured

The configuration of the pin #1 identifier is optional, but must be located within

the zone indicated. The pin #1 identifier may be either a mold or mark feature.

Dimensioning and tolerancing conform to ASME Y14.5M-1994.

Unless otherwise specified, tolerance : Decimal ± 0.05

All Dimensions are in millimeters. Angles are in degrees.

Dimensions in ( ) for Reference Only.

between 0.15mm and 0.30mm from the terminal tip.

Maximum package warpage is 0.05mm.

NOTES:

Maximum allowable burrs is 0.076mm in all directions.6.

Same as JEDEC MO-255UABD except:7.

No lead-pull-back, MIN. Package thickness = 0.45 not 0.50mm

Lead Length dim. = 0.45mm max. not 0.42mm.