7-1083
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
CD4094BMS
CMOS 8-Stage Shift-and-Store
Bus Register
Pinout
CD4094BMS
TOP VIEW
Functional Diagram
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
STROBE
DATA
CLOCK
Q1
Q2
Q3
VSS
Q4
VDD
Q5
Q6
Q7
Q8
Q’S
QS
OUTPUT ENABLE
8-STAGE
SHIFT
REGISTER
8-BIT
STORAGE
REGISTER
3-STATE
OUTPUTS
SERIAL
OUTPUTS
10
9
Q’S
QS
VDD = 16
VSS = 8
DATA 2
CLOCK 3
STROBE 1
OUTPUT
ENABLE 15
PARALLEL OUTPUTS Q1 - Q8
(TERMINALS 4, 5, 6, 7, 14, 13, 12, 11, RESPECTIVELY)
Features
• High Voltage Type (20V Rating)
• 3-State Parallel Outputs for Connection to Common
Bus
• Separate Serial Outputs Synchronous to Both Positive
and Negative Clock Edges for Cascading
• Medium Speed Operation - 5MHz at 10V (typ)
• Standardized Symmetrical Output Characteristics
• 100% Tested for Quiescent Current at 20V
• Maximum Input Current of 1µA at 18V Over Full Pack-
age Temperature Range; 100nA at 18V and +25oC
• Noise Margin (Over Full Package/Temperature Range)
- 1V at VDD = 5V
- 2V at VDD = 10V
- 2.5V at VDD = 15V
• 5V, 10V and 15V Parametric Ratings
• Meets All Requirements of JEDEC Tentative Standard
No. 13B, “Standard Specifications for Description of
‘B’ Series CMOS Devices”
Applications
• Serial-to-Parallel Data Conversion
• Remote Control Holding Register
• Dual-Rank Shift, Hold, and Bus Applications
Description
CD4094BMS is a 8-stage serial shift register having a storage
latch associated with each stage for strobing data from the serial
input to parallel buffered 3-state outputs. The parallel outputs
may be connected directly to common bus lines. Data is shifted
on positive clock transitions. The data in each shift register stage
is transferred to the storage register when the STROBE input is
high. Data in the storage register appears at the outputs when-
ever the OUTPUT -ENABLE signal is high.
Two serial outputs are available for cascading a number of
CD4094BMS devices. Data is available at the QS serial output
terminal on positive clock edges to allow for high-speed opera-
tion in cascaded systems in which the clock rise time is fast. The
same serial information, available at the Q’S terminal on the next
negative clock edge, provides a means for cascading
CD4094BMS devices when the clock rise time is slow .
The CD4094BMS is supplied in these 16 lead outline packages:
Braze Seal DIP H4X
Frit Seal DIP H1F
Ceramic Flatpack H6W
December 1992
File Number 3194
7-1084
Specifications CD4094BMS
Absolute Maximum Ratings Reliability Information
DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V
(Voltage Referenced to VSS Terminals)
Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V
DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Package Types D, F, K, H
Storage Temperature Range (TSTG). . . . . . . . . . . -65oC to +150oC
Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC
At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for
10s Maximum
Thermal Resistance . . . . . . . . . . . . . . . . θja θjc
Ceramic DIP and FRIT Package. . . . . 80oC/W 20oC/W
Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W
Maximum Package Power Dissipation (PD) at +125oC
For TA = -55oC to +100oC (Package Type D, F, K). . . . . . 500mW
For TA = +100oC to +125oC (Package Type D, F, K) . . . . .Derate
Linearity at 12mW/oC to 200mW
Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW
For TA = Full Package Temperature Range (All Package Types)
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
TABLE 1. DC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS (NOTE 1) GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1 +25oC-10µA
2 +125oC - 1000 µA
VDD = 18V, VIN = VDD or GND 3 -55oC-10µA
Input Leakage Current IIL VIN = VDD or GND VDD = 20 1 +25oC -100 - nA
2 +125oC -1000 - nA
VDD = 18V 3 -55oC -100 - nA
Input Leakage Current IIH VIN = VDD or GND VDD = 20 1 +25oC - 100 nA
2 +125oC - 1000 nA
VDD = 18V 3 -55oC - 100 nA
Output Voltage VOL15 VDD = 15V, No Load 1, 2, 3 +25oC, +125oC, -55oC - 50 mV
Output Voltage VOH15 VDD = 15V, No Load (Note 3) 1, 2, 3 +25oC, +125oC, -55oC 14.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1 +25oC 0.53 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1 +25oC 1.4 - mA
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1 +25oC 3.5 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1 +25oC - -0.53 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1 +25oC - -1.8 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1 +25oC - -1.4 mA
Output Current (Source) IOH15 VDD = 15V, VOUT = 13.5V 1 +25oC - -3.5 mA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1 +25oC -2.8 -0.7 V
P Threshold Voltage VPTH VSS = 0V, IDD = 10µA 1 +25oC 0.7 2.8 V
Functional F VDD = 2.8V, VIN = VDD or GND 7 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 20V, VIN = VDD or GND 7 +25oC
VDD = 18V, VIN = VDD or GND 8A +125oC
VDD = 3V, VIN = VDD or GND 8B -55oC
Input Voltage Low
(Note 2) VIL VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC - 1.5 V
Input Voltage High
(Note 2) VIH VDD = 5V, VOH > 4.5V, VOL < 0.5V 1, 2, 3 +25oC, +125oC, -55oC 3.5 - V
Input Voltage Low
(Note 2) VIL VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC- 4 V
Input Voltage High
(Note 2) VIH VDD = 15V, VOH > 13.5V,
VOL < 1.5V 1, 2, 3 +25oC, +125oC, -55oC11 - V
Tri-State Output
Leakage IOZL VIN = VDD or GND
VOUT = 0V VDD = 20V 1 +25oC -0.4 - µA
2 +125oC -12 - µA
VDD = 18V 3 -55oC -0.4 - µA
Tri-State Output
Leakage IOZH VIN = VDD or GND
VOUT = VDD VDD = 20V 1 +25oC - 0.4 µA
2 +125oC-12µA
VDD = 18V 3 -55oC - 0.4 µA
NOTES: 1. All voltages referenced to device GND, 100% testing being
implemented.
2. Go/No Go test with limits applied to inputs.
3. For accuracy, voltage is measured differentially to VDD. Limit
is 0.050V max.
7-1085
Specifications CD4094BMS
TABLE 2. AC ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITSMIN MAX
Propagation Delay
Clock to Serial Output QS TPHL1
TPLH1 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 600 ns
10, 11 +125oC, -55oC - 810 ns
Propagation Delay
Clock to Serial Output
Q’S
TPHL2
TPLH2 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 460 ns
10, 11 +125oC, -55oC - 621 ns
Propagation Delay
Clock to Parallel Output TPHL3
TPLH3 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 840 ns
10, 11 +125oC, -55oC - 1134 ns
Propagation Delay
Strobe to Parallel Output TPHL4
TPLH4 VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 580 ns
10, 11 +125oC, -55oC - 783 ns
Propagation Delay
Output Enable to Parallel
Output
TPHZ
TPZH VDD = 5V, VIN = VDD or GND
(Note 2, 3) 9 +25oC - 280 ns
10, 11 +125oC, -55oC - 378 ns
Propagation Delay
Output Enable to Parallel
Output
TPLZ
TPZL VDD = 5V, VIN = VDD or GND
(Note 2, 3) 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
Transition Time TTHL
TTLH VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC - 200 ns
10, 11 +125oC, -55oC - 270 ns
Maximum Clock Input
Frequency FCL VDD = 5V, VIN = VDD or GND
(Note 1, 2) 9 +25oC 1.25 - MHz
10, 11 +125oC, -55oC .93 - MHz
NOTES:
1. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
2. -55oC and +125oC limits guaranteed, 100% testing being implemented.
3. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 5V, VIN = VDD or GND 1, 2 -55oC, +25oC- 5 µA
+125oC - 150 µA
VDD = 10V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 300 µA
VDD = 15V, VIN = VDD or GND 1, 2 -55oC, +25oC- 10µA
+125oC - 600 µA
Output Voltage VOL VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOL VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC-50mV
Output Voltage VOH VDD = 5V, No Load 1, 2 +25oC, +125oC,
-55oC4.95 - V
Output Voltage VOH VDD = 10V, No Load 1, 2 +25oC, +125oC,
-55oC9.95 - V
Output Current (Sink) IOL5 VDD = 5V, VOUT = 0.4V 1, 2 +125oC 0.36 - mA
-55oC 0.64 - mA
Output Current (Sink) IOL10 VDD = 10V, VOUT = 0.5V 1, 2 +125oC 0.9 - mA
-55oC 1.6 - mA
7-1086
Specifications CD4094BMS
Output Current (Sink) IOL15 VDD = 15V, VOUT = 1.5V 1, 2 +125oC 2.4 - mA
-55oC 4.2 - mA
Output Current (Source) IOH5A VDD = 5V, VOUT = 4.6V 1, 2 +125oC - -0.36 mA
-55oC - -0.64 mA
Output Current (Source) IOH5B VDD = 5V, VOUT = 2.5V 1, 2 +125oC - -1.1 mA
-55oC - -2.0 mA
Output Current (Source) IOH10 VDD = 10V, VOUT = 9.5V 1, 2 +125oC - -0.9 mA
-55oC - -2.6 mA
Output Current (Source) IOH15 VDD =15V, VOUT = 13.5V 1, 2 +125oC - -2.4 mA
-55oC--mA
Input Voltage Low VIL VDD = 10V, VOH > 9V, VOL < 1V 1, 2 +25oC, +125oC,
-55oC-3V
Input Voltage High VIH VDD = 10V, VOH > 9V , VOL < 1V 1, 2 +25oC, +125oC,
-55oC7-V
Propagation Delay
Clock to Serial Output Qs TPHL1
TPLH1 VDD = 10V 1, 2, 3 +25oC - 250 ns
VDD = 15V 1, 2, 3 +25oC - 190 ns
Propagation Delay
Clock to Serial Output Q’s TPHL2
TPLH2 VDD = 10V 1, 2, 3 +25oC - 220 ns
VDD = 15V 1, 2, 3 +25oC - 150 ns
Propagation Delay
Clock to Parallel Output TPHL3
TPLH3 VDD = 10V 1, 2, 3 +25oC - 390 ns
VDD = 15V 1, 2, 3 +25oC - 270 ns
Propagation Delay
Strobe to Parallel Output TPHL4
TPLH4 VDD = 10V 1, 2, 3 +25oC - 290 ns
VDD = 15V 1, 2, 3 +25oC - 200 ns
Propagation Delay
Output Enable to Parallel
Output
TPHZ
TPZH VDD = 10V 1, 2, 4 +25oC - 120 ns
VDD = 15V 1, 2, 4 +25oC - 90 ns
Propagation Delay
Output Enable to Parallel
Output
TPLZ
TPZL VDD = 10V 1, 2, 4 +25oC - 100 ns
VDD = 15V 1, 2, 4 +25oC - 80 ns
Transition Time TTLH
TTHL VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 80 ns
Maximum Clock Input
Frequency FCL VDD = 10V 1, 2, 3 +25oC 2.5 - MHz
VDD = 15V 1, 2, 3 +25oC 3 - MHz
Minimum Data Setup
Time TS VDD = 5V 1, 2, 3 +25oC - 125 ns
VDD = 10V 1, 2, 3 +25oC - 55 ns
VDD = 15V 1, 2, 3 +25oC - 35 ns
Maximum Clock Input
Rise and Fall Time TRCL
TFCL VDD = 5V 1, 2, 3, 5 +25oC-15µs
VDD = 10V 1, 2, 3, 5 +25oC-5µs
VDD = 15V 1, 2, 3, 5 +25oC-5µs
Minimum Clock Pulse
Width TW VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 100 ns
VDD = 15V 1, 2, 3 +25oC - 83 ns
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-1087
Specifications CD4094BMS
Minimum Strobe Pulse
Width TW VDD = 5V 1, 2, 3 +25oC - 200 ns
VDD = 10V 1, 2, 3 +25oC - 80 ns
VDD = 15V 1, 2, 3 +25oC - 70 ns
Input Capacitance CIN Any Input 1, 2 +25oC - 7.5 pF
NOTES:
1. All voltages referenced to device GND.
2. The parameters listed on Table 3 are controlled via design or process and are not directly tested. These parameters are characterized
on initial design release and upon design changes which would affect these characteristics.
3. CL = 50pF, RL = 200K, Input TR, TF < 20ns.
4. CL = 50pF, RL = 1K, Input TR, TF < 20ns.
5. If more than one unit is cascaded, TRCL should be made less than or equal to the sumof the transition time and the fixed propagation
delay of the output of the driving stage for the estimated capacitive load.
TABLE 4. POST IRRADIATION ELECTRICAL PERFORMANCE CHARACTERISTICS
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
Supply Current IDD VDD = 20V, VIN = VDD or GND 1, 4 +25oC-25µA
N Threshold Voltage VNTH VDD = 10V, ISS = -10µA 1, 4 +25oC -2.8 -0.2 V
N Threshold Voltage
Delta ∆VTN VDD = 10V, ISS = -10µA 1, 4 +25oC-±1V
P Threshold Voltage VTP VSS = 0V, IDD = 10µA 1, 4 +25oC 0.2 2.8 V
P Threshold Voltage
Delta ∆VTP VSS = 0V, IDD = 10µA 1, 4 +25oC-±1V
Functional F VDD = 18V, VIN = VDD or GND 1 +25oC VOH >
VDD/2 VOL <
VDD/2 V
VDD = 3V, VIN = VDD or GND
Propagation Delay Time TPHL
TPLH VDD = 5V 1, 2, 3, 4 +25oC - 1.35 x
+25oC
Limit
ns
NOTES: 1. All voltages referenced to device GND.
2. CL = 50pF, RL = 200K, Input TR, TF < 20ns. 3. See Table 2 for +25oC limit.
4. Read and Record
TABLE 5. BURN-IN AND LIFE TEST DELTA PARAMETERS +25oC
PARAMETER SYMBOL DELTA LIMIT
Supply Current - MSI-2 IDD ± 1.0µA
Output Current (Sink) IOL5 ± 20% x Pre-Test Reading
Output Current (Source) IOH5A ± 20% x Pre-Test Reading
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
Initial Test (Pre Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
TABLE 3. ELECTRICAL PERFORMANCE CHARACTERISTICS (Continued)
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
LIMITS
UNITSMIN MAX
7-1088
Specifications CD4094BMS
Interim Test 1 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
Interim Test 2 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Interim Test 3 (Post Burn-In) 100% 5004 1, 7, 9 IDD, IOL5, IOH5A
PDA (Note 1) 100% 5004 1, 7, 9, Deltas
Final Test 100% 5004 2, 3, 8A, 8B, 10, 11
Group A Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group B Subgroup B-5 Sample 5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11, Deltas Subgroups 1, 2, 3, 9, 10, 11
Subgroup B-6 Sample 5005 1, 7, 9
Group D Sample 5005 1, 2, 3, 8A, 8B, 9 Subgroups 1, 2 3
NOTE: 1. 5% Parameteric, 3% Functional; Cumulative for Static 1 and 2.
TABLE 7. TOTAL DOSE IRRADIATION
CONFORMANCE GROUPS MIL-STD-883
METHOD
TEST READ AND RECORD
PRE-IRRAD POST-IRRAD PRE-IRRAD POST-IRRAD
Group E Subgroup 2 5005 1, 7, 9 Table 4 1, 9 Table 4
TABLE 8. BURN-IN AND IRRADIATION TEST CONNECTIONS
FUNCTION OPEN GROUND VDD 9V ± -0.5V
OSCILLATOR
50kHz 25kHz
Static Burn-In 1
(Note 1) 4 - 7, 9 - 14 1 - 3, 8, 15 16
Static Burn-In 2
(Note 1) 4 - 7, 9 - 14 8 1 - 3, 15, 16
Dynamic Burn-
In (Note 1) - 8 1, 15, 16 4 - 7, 9 - 14 3 2
Irradiation
(Note 2) 4 - 7, 9 - 14 8 1 - 3, 15, 16
NOTES:
1. Each pin except VDD and GND will have a series resistor of 10K ± 5%, VDD = 18V ± 0.5V
2. Each pin except VDD and GND will have a series resistor of 47K ±5%; Group E, Subgroup 2, sample size is 4 dice/wafer, 0 failures, VDD
= 10V ± 0.5V
TABLE 6. APPLICABLE SUBGROUPS
CONFORMANCE GROUP MIL-STD-883
METHOD GROUP A SUBGROUPS READ AND RECORD
7-1089
CD4094BMS
FIGURE 1. LOGIC DIAGRAM
TRUTH TABLE
CL∆OUTPUT
ENABLE STROBE DATA
PARALLEL OUTPUTS SERIAL OUTPUTS
Q1 QN QS* Q’S
0XXOCOCQ7NC
0XXOCOCNCQ7
1 0 X NCNCQ7NC
1100QN-1 Q7 NC
1111QN-1 Q7 NC
1 1 1 NC NC NC Q7
∆ = Level Change Logic 1 = High
X = Don’t Care Logic 0 = Low
NC = No Change
OC = Open Circuit
* At the positive clock edge information in the 7th shift register stage is transferred to the 8th register stage
and the QS output
DQ
Q
8
CL
CL
TR
TR LATCH
8
3 -
STATE
8
TR
TR LATCH
2
3 -
STATE
2
DQ
1
CL
CL
TR
TR
TRTR
p
n
pn
TR
TR
CL
CL
5
2
3
1
15
DQ
2
CL
CL
CL
CL
p
n
CL
CL
p
n
11
STAGES
3 - 7
6 7 14 13 124
SERIAL
OUT
Q’S10
SERIAL
OUT
QS
9
VDD
VSS
* ALL INPUTS
PROTECTED BY
CMOS PROTECTION
NETWORK
*
*
*
*
SERIAL
IN
CLOCK
STROBE
OUTPUT
ENABLE LATCH
1
3-STATE
1
VDD VSS
pn
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8
*
7-1090
CD4094BMS
Typical Performance Characteristics
FIGURE 2. TYPICAL OUTPUT LOW (SINK) CURRENT
TRANSFER CHARACTERISTICS FIGURE 3. MINIMUM OUTPUT LOW (SINK) CURRENT
CHARACTERISTICS
FIGURE 4. TYPICAL OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS FIGURE 5. MINIMUM OUTPUT HIGH (SOURCE) CURRENT
CHARACTERISTICS
FIGURE 6. CLOCK-TO-SERIAL OUTPUT QS PROPAGATION
DELAY vs CL FIGURE 7. CLOCK-TO-SERIAL OUTPUT Q’S PROPAGATION
DELAY vs CL
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
15
10
5
20
25
30
DRAIN-TO-SOURCE VOLT AGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
10V
5V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = 15V
0 5 10 15
7.5
5.0
2.5
10.0
12.5
15.0
DRAIN-TO-SOURCE VOLT AGE (VDS) (V)
OUTPUT LOW (SINK) CURRENT (IOL) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
0
-5
-10
-15
DRAIN-TO-SOURCE VOLT AGE (VDS) (V)
-20
-25
-30
0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
-10V
-15V
AMBIENT TEMPERATURE (T A) = +25oC0
-5
-10
-15
DRAIN-TO-SOURCE VOLT AGE (VDS) (V) 0-5-10-15
OUTPUT HIGH (SOURCE) CURRENT (IOH) (mA)
GATE-TO-SOURCE VOLT AGE (VGS) = -5V
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
100
SUPPLY VOL TAGE (VDD) = 5V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
10V
20 40 60 80 100
15V
200
300
400
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
50
SUPPLY VOL TAGE (VDD) = 5V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
10V
20 40 60 80 100
15V
100
150
200
250
300
7-1091
CD4094BMS
FIGURE 8. CLOCK-TO-PARALLEL OUTPUT PROPAGATION
DELAY vs CL FIGURE 9. STROBE-TO-PARALLEL OUTPUT PROPAGATION
DELAY vs CL
FIGURE 10. OUTPUT ENABLE-TO-PARALLEL OUTPUT
PROPAGATION DELAY vs CL FIGURE 11. TYPICAL TRANSITION TIME vs LOAD
CAPACITANCE
FIGURE 12. TYPICAL MAXIMUM-CLOCK-FREQUENCY vs
SUPPLY VOLTAGE FIGURE 13. DYNAMIC POWER DISSIPATION vs INPUT CLOCK
FREQUENCY
Typical Performance Characteristics (Continued)
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
100
SUPPLY VOL TAGE (VDD) = 5V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
10V
20 40 60 80 100
15V
200
300
400
500
600 AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
100
SUPPLY VOL TAGE (VDD) = 5V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
10V
20 40 60 80 100
15V
200
300
400
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0
50
SUPPLY VOL TAGE (VDD) = 5V
PROPAGATION DELAY TIME (tPHL, tPLH) (ns)
10V
20 40 60 80 100
15V
100
150
200
250
300
15V
10V
5V
tPHL
tPLH
AMBIENT TEMPERATURE (T A) = +25oC
LOAD CAPACITANCE (CL) (pF)
0 40 60 80 10020
0
50
100
150
200
SUPPLY VOL TAGE (VDD) = 5V
10V
5V
TRANSITION TIME (tTHL, tTLH) (ns)
MAXIMUM CLOCK FREQUENCY (fCL MAX) (MHz)
15
10
5
0 5 10 15 20
SUPPLY VOLTAGE (VDD) (V)
AMBIENT TEMPERATURE (TA) = +25oC
LOAD CAPACITANCE (CL) = 50PF
CL = 15pF
CL = 50pF
AMBIENT TEMPERATURE (TA) = +25oC
SUPPLY VOLTAGE (VDD) = 15V
10V
5V 10V
INPUT FREQUENCY (fI) (kHz)
11010
2103104
104
103
102
10
105
POWER DISSIPATION /PACKAGE (PD) (µW)
106
105
ALTERNATING 0 AND 1 PATTERN
OUTPUT ENABLE HIGH
STROBE HIGH EVERY 8 CLOCK PULSES
7-1092
CD4094BMS
FIGURE 14. TIMING DIAGRAM
FIGURE 15. REMOTE CONTROL HOLDING REGISTER
3 - STATE
3 - STATE
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
INTERNAL Q1
OUTPUT Q1
INTERNAL Q7
OUTPUT Q7
SERIAL QS
OUTPUT
SERIAL Q’S
OUTPUT
3
STATE
3
STATE
DIGITALLY CONTROLLED
EQUIPMENT
(REQUIRES CONTINUOUS
DIGITAL CONTROL)
CD4094BMS
STROBE CLOCK
DIGITALLY CONTROLLED
EQUIPMENT
CD4094BMS
STROBE CLOCK
DIGITALLY CONTROLLED
EQUIPMENT
CD4094BMS
STROBE CLOCK
CONTROL
AND
SYNC
CIRCUITRY
DATA CLOCK
FROM REMOTE
CONTROL PANEL
DQ’S DQSD
1093
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
Sales Office Headquarters
NORTH AMERICA
Intersil Corporation
P. O. Box 883, Mail Stop 53-204
Melbourne, FL 32902
TEL: (321) 724-7000
FAX: (321) 724-7240
EUROPE
Intersil SA
Mercure Center
100, Rue de la Fusee
1130 Brussels, Belgium
TEL: (32) 2.724.2111
FAX: (32) 2.724.22.05
ASIA
Intersil (Taiwan) Ltd.
Taiwan Limited
7F-6, No. 101 Fu Hsing North Road
Taipei, Taiwan
Republic of China
TEL: (886) 2 2716 9310
FAX: (886) 2 2715 3029
CD4094BMS
METALLIZATION: Thickness: 11kÅ−14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 inches
Chip Dimensions and Pad Layout
Dimensions in parenthesis are in millimeters and are
derived from the basic inch dimensions as indicated.
Grid graduations are in mils (10-3 inch).
