JESD204B Clock Generator with 14 LVDS/HSTL Outputs AD9528 Data Sheet FEATURES FUNCTIONAL BLOCK DIAGRAM APPLICATIONS High performance wireless transceivers LTE and multicarrier GSM base stations Wireless and broadband infrastructure Medical instrumentation Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs; supports JESD204B Low jitter, low phase noise clock distribution ATE and high performance instrumentation Rev. C VXCO_IN REFA REFB PLL2 / O OUT0/ OUT0 SYSREF JESD204B / O OUT13/ OUT13 PLL1 REF_SEL SYSREF_REQ CONTROL INTERFACE (SPI AND I2C) AD9528 CLOCK DISTRIBUTION 14 OUTPUTS 12380-001 14 outputs configurable for HSTL or LVDS Maximum output frequency 2 outputs up to 1.25 GHz 12 outputs up to 1 GHz Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy (start-up frequency accuracy: <100 ppm) Dedicated 8-bit dividers on each output Coarse delay: 63 steps at 1/2 the period of the RF VCO divider output frequency with no jitter impact Fine delay: 15 steps of 31 ps resolution Typical output to output skew: 20 ps Duty cycle correction for odd divider settings Output 12 and Output 13, VCXO output at power up Absolute output jitter: <160 fs at 122.88 MHz, 12 kHz to 20 MHz integration range Digital frequency lock detect SPI- and I2C-compatible serial control port Dual PLL architecture PLL1 Provides reference input clock cleanup with external VCXO Phase detector rate up to 110 MHz Redundant reference inputs Automatic and manual reference switchover modes Revertive and nonrevertive switching Loss of reference detection with holdover mode Low noise LVDS/HSTL outputs from VCXO used for radio frequency/intermediate frequency (RF/IF) synthesizers PLL2 Phase detector rate of up to 275 MHz Integrated low noise VCO Figure 1. GENERAL DESCRIPTION The AD9528 is a two-stage PLL with an integrated JESD204B SYSREF generator for multiple device synchronization. The first stage phase-locked loop (PLL) (PLL1) provides input reference conditioning by reducing the jitter present on a system clock. The second stage PLL (PLL2) provides high frequency clocks that achieve low integrated jitter as well as low broadband noise from the clock output drivers. The external VCXO provides the low noise reference required by PLL2 to achieve the restrictive phase noise and jitter requirements necessary to achieve acceptable performance. The on-chip VCO tunes from 3.450 GHz to 4.025 GHz. The integrated SYSREF generator outputs single shot, N-shot, or continuous signals synchronous to the PLL1 and PLL2 outputs to time align multiple devices. The AD9528 generates two outputs (Output 1 and Output 2) with a maximum frequency of 1.25 GHz, and 12 outputs up to 1 GHz. Each output can be configured to output directly from PLL1, PLL2, or the internal SYSREF generator. Each of the 14 output channels contains a divider with coarse digital phase adjustment and an analog fine phase delay block that allows complete flexibility in timing alignment across all 14 outputs. The AD9528 can also be used as a dual input flexible buffer to distribute 14 device clock and/or SYSREF signals. At power-up, the AD9528 sends the VCXO signal directly to Output 12 and Output 13 to serve as the power-up ready clocks. Note that, throughout this data sheet, the dual function pin names are referenced by the relevant function where applicable. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 (c)2014-2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9528 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Theory of Operation ...................................................................... 25 Applications ....................................................................................... 1 Detailed Block Diagram ............................................................ 25 Functional Block Diagram .............................................................. 1 Overview ..................................................................................... 25 General Description ......................................................................... 1 Component Blocks--PLL1 ....................................................... 25 Revision History ............................................................................... 3 Component Blocks-- PLL2 ...................................................... 27 Specifications..................................................................................... 4 Clock Distribution ..................................................................... 29 Conditions ..................................................................................... 4 SYSREF Operation ......................................................................... 32 Supply Current .............................................................................. 4 SYSREF Signal Path.................................................................... 32 Power Dissipation ......................................................................... 5 SYSREF Generator ..................................................................... 34 Input Characteristics--REFA, REFA, REFB, REFB, VCXO_IN, VCXO_IN, SYSREF_IN, and SYSREF_IN ........... 6 Serial Control Port ......................................................................... 35 PLL1 Characteristics .................................................................... 6 SPI Serial Port Operation .......................................................... 35 VCXO_VT Output Characteristics ............................................ 7 I2C Serial Port Operation .......................................................... 38 PLL2 Characteristics .................................................................... 7 Device Initialization and Calibration Flowcharts ...................... 41 Clock Distribution Output Characteristics............................... 7 Power Dissipation and Thermal Considerations ....................... 46 Output Timing Alignment Characteristics ............................... 8 Clock Speed and Driver Mode ................................................. 46 SYSREF_IN, SYSREF_IN, VCXO_IN, and VCXO_IN Timing Characteristics .............................................................................. 8 Evaluation of Operating Conditions........................................ 46 Clock Output Absolute Phase Noise--Dual Loop Mode ........ 8 Clock Output Absolute Phase Noise--Single Loop Mode...... 9 Clock Output Absolute Time Jitter .......................................... 10 SPI/I2C Port Selection ................................................................ 35 Thermally Enhanced Package Mounting Guidelines ............ 47 Control Register Map ..................................................................... 48 Control Register Map Bit Descriptions ....................................... 52 Clock Output Additive Time Jitter (Buffer Mode) ................ 12 Serial Control Port Configuration (Register 0x0000 to Register 0x0001) ......................................................................... 52 Logic Input Pins--RESET, REF_SEL, and SYSREF_REQ .... 12 Clock Part Family ID (Register 0x0003 to Register 0x0006) ...... 53 Status Output Pins--STATUS0 and STATUS1....................... 12 SPI Version (Register 0x000B) .................................................. 53 Serial Control Port--Serial Port Interface (SPI) Mode ......... 13 Vendor ID (Register 0x000C to Register 0x000D) ................ 53 2 Serial Control Port--I C Mode ................................................ 14 IO_UPDATE (Register 0x000F) ............................................... 53 Absolute Maximum Ratings .......................................................... 15 PLL1 Control (Register 0x0100 to Register 0x010B) ............. 54 Thermal Resistance .................................................................... 15 PLL2 (Register 0x0200 to Register 0x0209) ............................ 56 ESD Caution ................................................................................ 15 Clock Distribution (Register 0x300 to Register 0x0329) ...... 59 Pin Configuration and Function Descriptions ........................... 16 Power-Down Control (Register 0x0500 to Register 0x0504) ..... 63 Typical Performance Characteristics ........................................... 19 Status Control (Register 0x0505 to Register 0x0509) ............ 65 Input/Output Termination Recommendations .......................... 22 Outline Dimensions ....................................................................... 67 Typical Application Circuit ........................................................... 23 Ordering Guide .......................................................................... 67 Terminology .................................................................................... 24 Rev. C | Page 2 of 67 Data Sheet AD9528 REVISION HISTORY 7/15--Rev. B to Rev.C Changes to Differential Input Voltage, Sensitivity Frequency < 250 MHz Parameter and Differential Input Voltage, Sensitivity Frequency > 250 MHz Parameter, Table 4 ....................................... 6 Changes to Figure 12 Caption, Figure 13 Caption, and Figure 14 Caption .............................................................................................20 Changes to Figure 15 Caption, Figure 16 Caption, Figure 17 Caption, and Figure 18 Caption ....................................................21 Changes to Figure 27 ......................................................................25 Changes to Implementation Specific Details Section.................35 Changes to I2C Serial Port Operation Section .............................38 4/15--Rev. A to Rev. B Changes to Serial Control Port Section and Table 24 ................35 3/15--Rev. 0 to Rev. A Moved Revision History................................................................... 3 Changes to Table 8 ............................................................................ 7 Changes to Voltage Parameter, Table 15 ...................................... 12 Changes to Figure 2 ........................................................................ 16 Added Figure 13, Renumbered Sequentially ............................... 20 Deleted Figure 17 ............................................................................ 21 Added Figure 15 .............................................................................. 21 Changes to Figure 16 Caption ....................................................... 21 Changes to Figure 27 ...................................................................... 25 Changes to SYSREF Generator Section........................................ 34 Changes to Serial Control Port Section and Implementation Specific Details Section .................................................................. 35 Changes to Table 36 ........................................................................ 48 Changes to Table 37 ........................................................................ 52 10/14--Revision 0: Initial Version Rev. C | Page 3 of 67 AD9528 Data Sheet SPECIFICATIONS The AD9528 is configured for dual loop mode. The REFA differential input is enabled at 122.88 MHz, fVCXO = 122.88 MHz and singleended, fVCO = 3686.4 MHz, VCO divider = 3. Doubler and analog delay are off, SYSREF generation is on, unless otherwise noted. Typical is given for VDDx = 3.3 V 5%, and TA = 25C, unless otherwise noted. Minimum and maximum values are given over the full VDDx and TA (-40C to +85C) variation, as listed in Table 1. CONDITIONS Table 1. Parameter SUPPLY VOLTAGE VDDx1 TEMPERATURE Ambient Temperature Range, TA Junction Temperature, TJ 1 Min Typ Max Unit Test Conditions/Comments 3.135 3.3 3.465 V 3.3 V 5% -40 +25 +85 C +115 C Refer to the Power Dissipation and Thermal Considerations section to calculate the junction temperature VDDx includes the VDD pins (Pin 1, Pin 10, Pin 16, Pin 20, and Pin 72) and the VDD13 pin through the VDD0 pin, unless otherwise noted. See the Pin Configuration and Function Descriptions for details. SUPPLY CURRENT Table 2. Parameter SUPPLY CURRENT Dual Loop Mode VDD (Pin 1, Pin 72) VDD (Pin 10) VDD (Pin 16) VDD ( Pin 20) Single Loop Mode VDD (Pin 1, Pin 72) VDD (Pin 10) VDD (Pin 16) VDD (Pin 20) Buffer Mode VDD (Pin 1, Pin 72) VDD (Pin 10) VDD (Pin 16) VDD (Pin 20) Chip Power-Down Mode VDD (Pin 1, Pin 10, Pin 16, Pin 20, and Pin 72) Min Typ Max Unit 19 29 34 64 21 32 37 71 mA mA mA mA 7 29 34 64 9 32 37 71 mA mA mA mA Test Conditions/Comments Excludes clock distribution section; clock distribution outputs running as follows: 7 HSTL device clocks at 122.88 MHz, 7 LVDS SYSREF clocks (3.5 mA) at 960 kHz PLL1 and PLL2 enabled PLL1 off and REFA and REFB inputs off 122.88 MHz reference source applied to the VCXO inputs (input to PLL2) PLL1 and PLL2 off, REFA and REFB inputs disabled; 122.88 MHz reference source applied to VCXO differential inputs to drive 7 of 14 outputs, internal SYSREF generator off, 960 kHz input source applied to SYSREF differential inputs to drive the other 7 outputs, dividers in clock distribution path bypassed in clock distribution channel 17 23 2 15 15 19 25 3 19 mA mA mA mA mA Chip power-down bit enabled (Register 0x0500, Bit 0 = 1) Rev. C | Page 4 of 67 Data Sheet AD9528 Parameter SUPPLY CURRENT FOR EACH CLOCK DISTRIBUTION CHANNEL LVDS Mode, 3.5 mA Min Typ Max Unit Test Conditions/Comments Each clock output channel has a dedicated VDD pin. The current draw for each VDD pin includes the divider, fine delay, and output driver, fine delay is off; see the Pin Configuration and Function Descriptions section for pin assignment 21 24 28 23 26 30 mA mA mA Output = 122.88 MHz, channel divider = 10 Output = 409.6 MHz, channel divider = 3 Output = 737.28 MHz, channel divider = 1, VCO divider = 5, LVDS boost mode of 4.5 mA recommended 22 25 29 24 27 31 mA mA mA Output = 122.88 MHz, channel divider =10 Output = 409.6 MHz, channel divider = 3 Output = 737.28 MHz, channel divider = 1, VCO divider = 5 25 26 29 37 27 28 31 41 mA mA mA mA 2.5 4 mA Output = 122.88 MHz, channel divider =10 Output = 409.6 MHz, channel divider = 3 Output = 983.04 MHz, channel divider = 1, VCO divider = 5, VCO = 3932.16 MHz Output = 1228.8 MHz, channel divider = 1, only output channels OUT1 and OUT2 support output frequencies greater than ~1 GHz For each channel VDD pin, chip power-down bit enabled (Register 0x0500, Bit 0 = 1) Typ Max Unit Test Conditions/Comments Does not include power dissipated in termination resistors 1675 1780 mW 1635 1810 mW Differential REFA input at 122.88 MHz; fVCXO = 122.88 MHz, fVCO = 3686.4 MHz, VCO divider at 3 clock distribution outputs running as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz PLL1 off, differential VCXO input at 122.88 MHz, clock distribution outputs running as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz 1030 1200 mW LVDS Boost Mode, 4.5 mA HSTL Mode, 9 mA Chip Power-Down Mode POWER DISSIPATION Table 3. Parameter TOTAL POWER DISSIPATION Typical Dual Loop Mode Configuration Typical Single Loop Mode Configuration Typical Buffer Mode Chip Power-Down Mode RESET Enabled INCREMENTAL POWER DISSIPATION Low Power Base Configuration PLL1 OFF Output Distribution LVDS Mode, 3.5 mA LVDS Mode, 4.5 mA Min 65 1015 1200 mW PLL1 and PLL2 off, differential VCXO input at 122.88 MHz. SYSREF generator off, differential SYSREF input at 960 kHz; clock distribution outputs running as follows: 7 HSTL at 122.88 MHz, 7 LVDS (3.5 mA) at 960 kHz Chip power-down bit enabled (Register 0x0500, Bit 0 = 1) mW RESET pin low Does not include power dissipated in termination resistors 590 mW 0 mW 70 78 92 73 81 95 mW mW mW mW mW mW Dual loop mode, SYSREF generation and fine delay off; total power with 1 LVDS output running at 122.88 MHz, single-ended REFA at 122.88 MHz; REFB off, VCXO = 122.88 MHz, VCO = 3686.4 MHz Define settings to power off PLL1 Incremental power increase for each additional enable output Single 3.5 mA LVDS output at 122.88 MHz, channel divider = 10 Single 3.5 mA LVDS output at 409.6 MHz, channel divider = 3 Single 3.5 mA LVDS output at 737.28 MHz, VCO divider = 5, channel divider = 1 Single 4.5 mA LVDS output at 122.88 MHz, channel divider = 10 Single 4.5 mA LVDS output at 409.6 MHz, channel divider = 3 Single 4.5 mA LVDS output at 737.28 MHz, VCO divider = 5 Rev. C | Page 5 of 67 AD9528 Parameter HSTL Mode, 9 mA Data Sheet Min REFA Differential On Single-Ended SYSREF Generator Enabled Fine Delay On Typ 80 85 95 125 Max Unit mW mW mW mW Test Conditions/Comments Single 9 mA HSTL output at 122.88 MHz, channel divider = 10 Single 9 mA HSTL output at 409.6 MHz, channel divider = 3 Single 9 mA HSTL output at 983.04 MHz, VCO divider = 5, channel divider = 1 Single 9 mA HSTL output at 1228.8 MHz, channel divider = 1 72 72 5 mW mW mW REFA and REFB running at 122.88 MHz, REF_SEL = REFB REFA and REFB running at 122.88 MHz, REF_SEL = REFB Single 3.5 mA LVDS output at 960 kHz 1 mW Maximum delay setting INPUT CHARACTERISTICS--REFA, REFA, REFB, REFB, VCXO_IN, VCXO_IN, SYSREF_IN, AND SYSREF_IN Table 4. Parameter DIFFERENTIAL MODE Input Frequency Range Input Frequency Range (VCXO_IN) Input Slew Rate (VCXO_IN) Common-Mode Internally Generated Input Voltage Input Common-Mode Range Differential Input Voltage, Sensitivity Frequency < 250 MHz Differential Input Voltage, Sensitivity Frequency > 250 MHz Differential Input Resistance Differential Input Capacitance Duty Cycle Pulse Width Low Pulse Width High CMOS MODE, SINGLE-ENDED INPUT Input Frequency Range Input High Voltage Input Low Voltage Input Capacitance Duty Cycle Pulse Width Low Pulse Width High Min 500 0.6 Typ 0.7 0.4 200 Max Unit Test Conditions/Comments 400 1250 MHz MHz For buffer mode V/s V Minimum limit imposed for jitter performance 0.8 V mV p-p DC-coupled LVDS mode and HSTL mode supported Can accommodate single-ended inputs via ac grounding of unused inputs; instantaneous voltage on either pin must not exceed 1.8 V dc mV p-p Can accommodate single-ended inputs via ac grounding of unused inputs; instantaneous voltage on either pin must not exceed 1.8 V dc 1.4 250 4.8 4 k pF Duty cycle limits are set by pulse width high and pulse width low 1 1 ns ns 250 1.4 0.65 2 MHz V V pF Duty cycle limits are set by pulse width high and pulse width low 1.6 1.6 ns ns PLL1 CHARACTERISTICS Table 5. Parameter PFD FREQUENCY Charge Pump Current LSB Size Reference Frequency Detector Threshold Min Typ 0.5 950 Max 110 Unit MHz A kHz Test Conditions/Comments 7-bit resolution Do not use automatic holdover if the reference frequency is less than the minimum value Rev. C | Page 6 of 67 Data Sheet AD9528 VCXO_VT OUTPUT CHARACTERISTICS Table 6. Parameter OUTPUT VOLTAGE High Low Min Typ Max Unit Test Conditions/Comments V mV RLOAD > 20 k 150 Max Unit Test Conditions/Comments 4025 MHz MHz/V dBc/Hz MHz VDD - 0.15 PLL2 CHARACTERISTICS Table 7. Parameter VCO (ON CHIP) Frequency Range Gain PLL2 FIGURE OF MERIT (FOM) MAXIMUM PFD FREQUENCY Min Typ 3450 48 -226 275 CLOCK DISTRIBUTION OUTPUT CHARACTERISTICS Table 8. Parameter HSTL MODE Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle f < 500 MHz f = 500 MHz to 800 MHz f = 800 MHz to 1.25 GHz f = 800 MHz to 1.25 GHz Differential Output Voltage Swing Common-Mode Output Voltage LVDS MODE, 3.5 mA Output Frequency Rise Time/Fall Time (20% to 80%) Duty Cycle f < 500 MHz f = 500 MHz to 800 MHz f = 800 MHz to 1.25 GHz Balanced, Differential Output Swing (VOD) Min Typ Max Unit Test Conditions/Comments 60 1000 1250 160 MHz MHz ps All outputs Outputs OUT1 and OUT2 only 100 termination across output pair % % % % mV 48 46 44 50 900 1000 53 54 62 57 1100 0.88 0.9 0.94 V 50 1000 1250 216 MHz GHz ps 53 54 58 390 % % % mV 3 mV 1.35 1.2 V mV 19 mA 47 46 48 345 50 51 50 50 51 54 Unbalanced, VOD Common-Mode Output Voltage Common-Mode Difference Short-Circuit Output Current 1.15 15 Rev. C | Page 7 of 67 If using PLL2 VOH - VOL for each leg of a differential pair for default amplitude setting with the driver not toggling; the peak-topeak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2x these values (see Figure 5 for variation over frequency) 3.5 mA All outputs Outputs OUT1 and OUT2 only 100 termination across output pair Voltage swing between output pins; output driver static (see Figure 6 for variation over frequency) Absolute difference between voltage swing of normal pin and inverted pin; output driver static Voltage difference between output pins; output driver static Output driver static AD9528 Data Sheet OUTPUT TIMING ALIGNMENT CHARACTERISTICS Table 9. Parameter OUTPUT TIMING SKEW PLL1 Outputs PLL1 to PLL1 PLL1 to SYSREF PLL1 to SYSREF PLL1 to SYSREF PLL1 to PLL2 PLL2 Outputs PLL2 to PLL2 PLL2 to SYSREF PLL2 to SYSREF PLL2 to SYSREF PLL2 to PLL1 OUTPUT DELAY ADJUST Coarse Adjustable Delay Fine Adjustable Delay Resolution Step Insertion Delay Min Typ Max Unit Test Conditions/Comments Delay off on all outputs, maximum deviation between rising edges of outputs; all outputs are on and in HSTL mode, unless otherwise noted 17 17 361 253 257 100 100 510 1150 1000 ps ps ps ps ps PLL1 clock to PLL1 clock SYSREF retimed by PLL1 clock SYSREF not retimed by any clock SYSREF retimed by PLL2 clock PLL1 clock to PLL2 clock 20 20 620 253 257 165 165 750 1150 1000 ps ps ps ps ps PLL2 clock to PLL2 clock SYSREF retimed by PLL2 clock SYSREF not retimed by any clock SYSREF retimed by PLL1 clock PLL2 clock to PLL1 clock Enables digital and analog delay capability 32 Steps Resolution step is the period of VCO RF divider (M1) output/2 15 Steps Resolution step 31 425 ps ps Analog delay enabled and delay setting equal to zero SYSREF_IN, SYSREF_IN, VCXO_IN, AND VCXO_IN TIMING CHARACTERISTICS Table 10. Parameter PROPAGATION LATENCY OF VCXO PATH PROPAGATION LATENCY OF SYSREF PATH RETIMED WITH DEVICE CLOCK Setup Time of External SYSREF Relative to Device Clock Output Hold Time of External SYSREF Relative to Device Clock Output RETIMED WITH VCXO Setup Time of External SYSREF Relative to VCXO Input Hold Time of External SYSREF Relative to VCXO Min Unit ns ns Test Conditions/Comments VCXO input to device clock output, not retimed SYSREF input to SYSREF output, not retimed -1.13 ns Given a SYSREF input clock rate equal to 122.88 MHz 0.7 ns -0.21 0.09 ns ns 1.92 1.83 Typ 2.3 2.2 Max 2.7 2.6 CLOCK OUTPUT ABSOLUTE PHASE NOISE--DUAL LOOP MODE Application examples are based on a typical setups (see Table 2) using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.88 MHz; channel divider = 10 or 1; PLL2 loop bandwidth (LBW) = 450 kHz. Table 11. Parameter HSTL OUTPUT fOUT = 122.88 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset Min Typ Max -87 -106 -126 -135 -139 Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. C | Page 8 of 67 Test Conditions/Comments Data Sheet AD9528 Parameter 800 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset fOUT = 1228.8 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset LVDS OUTPUT fOUT = 122.88 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset fOUT = 1228.8 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset Min Typ -147 -149 -161 -162 Max Unit dBc/Hz dBc/Hz dBc/Hz dBc/Hz Test Conditions/Comments OUT1 and OUT2 only, channel divider = 1 -62 -85 -106 -115 -119 -127 -129 -147 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -86 -106 -126 -135 -139 -147 -148 -157 -158 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -66 -86 -106 -115 -119 -127 -129 -147 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz OUT1 and OUT2 only, channel divider = 1 CLOCK OUTPUT ABSOLUTE PHASE NOISE--SINGLE LOOP MODE Single loop mode is based on the typical setup (see Table 2) using an external 122.88 MHz reference (SMA100A generator); reference = 122.88 MHz; channel divider = 10; PLL2 LBW = 450 kHz. Table 12. Parameter HSTL OUTPUT fOUT = 122.88 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset Min Typ -104 -113 -123 -135 -140 -147 -149 -161 -162 Max Unit Test Conditions/Comments dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz Rev. C | Page 9 of 67 AD9528 Parameter fOUT = 1228.8 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset LVDS OUTPUT fOUT = 122.88 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 40 MHz Offset fOUT = 1228.8 MHz 10 Hz Offset 100 Hz Offset 1 kHz Offset 10 kHz Offset 100 kHz Offset 800 kHz Offset 1 MHz Offset 10 MHz Offset 100 MHz Offset Data Sheet Min Typ Max Unit Test Conditions/Comments OUT1 and OUT2 only, channel divider = 1 -85 -95 -103 -114 -120 -126 -128 -147 -153 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -111 -113 -123 -135 -140 -147 -148 -157 -157 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz -85 -95 -103 -114 -120 -126 -128 -146 -152 dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz dBc/Hz OUT1 and OUT2 only, channel divider = 1 CLOCK OUTPUT ABSOLUTE TIME JITTER Table 13. Parameter OUTPUT ABSOLUTE RMS TIME JITTER Dual Loop Mode HSTL Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 Min Typ Max Unit Test Conditions/Comments Application examples are based on typical setups (see Table 2) using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.88 MHz; channel divider = 10 or 1; PLL2 LBW = 450 kHz 117 123 159 172 177 109 114 fs fs fs fs fs fs fs Integrated BW = 200 kHz to 5 MHz Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 40 MHz Integrated BW = 1 kHz to 40 MHz Integrated BW = 1 MHz to 40 MHz Integrated BW = 200 kHz to 5 MHz 116 147 154 160 74 fs fs fs fs fs Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 100 MHz Integrated BW = 1 kHz to 100 MHz Integrated BW = 1 MHz to 100 MHz Rev. C | Page 10 of 67 Data Sheet Parameter LVDS Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 Single Loop Mode HSTL Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 LVDS Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 AD9528 Min Typ 124 136 179 209 213 160 116 Max Unit fs fs fs fs fs fs fs Test Conditions/Comments Integrated BW = 200 kHz to 5 MHz Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 40 MHz Integrated BW = 1 kHz to 40 MHz Integrated BW = 1 MHz to 40 MHz Integrated BW = 200 kHz to 5 MHz 118 150 157 163 76 fs fs fs fs fs Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 100 MHz Integrated BW = 1 kHz to 100 MHz Integrated BW = 1 MHz to 100 MHz 115 122 156 171 179 110 116 fs fs fs fs fs fs fs Integrated BW = 200 kHz to 5 MHz Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 40 MHz Integrated BW = 1 kHz to 40 MHz Integrated BW = 1 MHz to 40 MHz Integrated BW = 200 kHz to 5 MHz 118 146 153 163 81 123 135 177 207 214 160 117 fs fs fs fs fs fs fs fs fs fs fs fs Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 100 MHz Integrated BW = 1 kHz to 100 MHz Integrated BW = 1 MHz to 100 MHz Integrated BW = 200 kHz to 5 MHz Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 40 MHz Integrated BW = 1 kHz to 40 MHz Integrated BW = 1 MHz to 40 MHz Integrated BW = 200 kHz to 5 MHz 119 147 155 164 83 fs fs fs fs fs Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 100 MHz Integrated BW = 1 kHz to 100 MHz Integrated BW = 1 MHz to 100 MHz Rev. C | Page 11 of 67 AD9528 Data Sheet CLOCK OUTPUT ADDITIVE TIME JITTER (BUFFER MODE) Table 14. Parameter OUTPUT ADDITIVE RMS TIME JITTER Min Typ Buffer Mode HSTL Output fOUT = 122.88 MHz Max 66 81 112 145 146 132 79 101 140 187 189 176 LVDS Output fOUT = 122.88 MHz Unit Test Conditions/Comments Application examples are based on typical performance (see Table 2) using an external 122.88 MHz source driving VCXO inputs (distribution section only, does not include PLL and VCO) fs fs fs fs fs fs fs fs fs fs fs fs Integrated BW = 200 kHz to 5 MHz Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 40 MHz Integrated BW = 1 kHz to 40 MHz Integrated BW = 1 MHz to 40 MHz Integrated BW = 200 kHz to 5 MHz Integrated BW = 200 kHz to 10 MHz Integrated BW = 12 kHz to 20 MHz Integrated BW = 10 kHz to 40 MHz Integrated BW = 1 kHz to 40 MHz Integrated BW = 1 MHz to 40 MHz LOGIC INPUT PINS--RESET, REF_SEL, AND SYSREF_REQ Table 15. Parameter VOLTAGE Input High Input Low INPUT LOW CURRENT CAPACITANCE RESET TIMING Pulse Width Low Inactive to Start of Register Programming Min Typ Max Unit 0.6 14 V V A pF 1.3 13 4 1.0 2.5 Test Conditions/Comments ns ns STATUS OUTPUT PINS--STATUS0 AND STATUS1 Table 16. Parameter OUTPUT VOLTAGE High Low Min Typ Max Unit 0.02 V V 3 Rev. C | Page 12 of 67 Test Conditions/Comments Data Sheet AD9528 SERIAL CONTROL PORT--SERIAL PORT INTERFACE (SPI) MODE Table 17. Parameter CS (INPUT) Voltage Input Logic 1 Input Logic 0 Current Input Logic 1 Input Logic 0 Input Capacitance SCLK (INPUT) IN SPI MODE Voltage Input Logic 1 Input Logic 0 Current Input Logic 1 Input Logic 0 Input Capacitance SDIO Voltage Input Logic 1 Input Logic 0 Current Input Logic 1 Input Logic 0 Input Capacitance SDIO, SDO (OUTPUTS) Voltage Output Logic 1 Output Logic 0 TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High Pulse Width Low SDIO to SCLK Setup SCLK to SDIO Hold SCLK to Valid SDIO and SDO CS to SCLK Setup CS to SCLK Hold CS Minimum Pulse Width High Symbol Min Typ Max Unit 1.37 1.33 V V -52 -82 2 A A pF Test Conditions/Comments CS has an internal 40 k pull-up resistor SCLK has an internal 40 k pull-down resistor in SPI mode but not in I2C mode 1.76 1.22 V V 0.0037 0.0012 2 A A pF Input is in bidirectional mode 1.76 1.22 V V 0.0037 0.0012 3.5 A A pF 3.11 0.0018 50 tHIGH tLOW tDS tDH tDV tS tC tPWH 4 2 2.2 -0.9 6 1.25 0 0.9 Rev. C | Page 13 of 67 V V MHz ns ns ns ns ns ns ns ns AD9528 Data Sheet SERIAL CONTROL PORT--I2C MODE Table 18. Parameter SDA, SCL VOLTAGE Input Logic 1 Input Logic 0 Input Current Symbol -10 Max Unit 0.3 x VDD +10 V V A 0.015 x VDD SDA Output Logic 0 Voltage at 3 mA Sink Current Output Fall Time from VIHMIN to VILMAX TIMING 1 Typ 0.7 x VDD Hysteresis of Schmitt Trigger Inputs Clock Rate (SCL, fI2C) Bus Free Time Between a Stop and Start Condition Setup Time for a Repeated Start Condition Hold Time (Repeated) Start Condition Setup Time for a Stop Condition Low Period of the SCL Clock High Period of the SCL Clock SCL, SDA Rise Time SCL, SDA Fall Time Data Setup Time Data Hold Time Capacitive Load for Each Bus Line Min Test Conditions/Comments When inputting data Input voltage between 0.1 x VDD and 0.9 x VDD V When outputting data 20 + 0.1 CB1 0.2 V 250 ns Bus capacitance from 10 pF to 400 pF All I2C timing values are referred to VIHMIN (0.3 x VDD) and VILMAX levels (0.7 x VDD) tIDLE 1.3 400 kHz s tSET; STR 0.6 s tHLD; STR 0.6 s tSET; STP tLOW tHIGH tRISE tFALL tSET; DAT tHLD; DAT C B1 0.6 1.3 0.6 20 + 0.1 CB1 20 + 0.1 CB1 100 0 s s s ns ns ns ns pF 300 300 400 CB is the capacitance of one bus line in picofarads (pF). Rev. C | Page 14 of 67 After this period, the first clock pulse is generated Data Sheet AD9528 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 19. Parameter VDD REFA, REFA, REFB, REFB, VCXO_IN, VCXO_IN, SYSREF_IN, SYSREF_IN, SYSREF_REQ to GND SCLK/SCL, SDIO/SDA, SDO, CS to GND RESET, REF_SEL, SYSREF_REQ to GND STATUS0/SP0, STATUS1/SP1 to GND Junction Temperature Storage Temperature Range Lead Temperature (10 sec) Rating -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V -0.3 V to +3.6 V 125C -65C to +150C 300C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. JA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 20. Thermal Resistance Package Type 72-Lead LFCSP, 10 mm x 10 mm Airflow Velocity (m/sec) 0 1.0 2.5 JA1, 2 21.3 20.1 18.1 JC1, 3 1.7 JB1, 4 12.6 JT1, 2 0.1 0.2 0.3 Unit C/W C/W C/W 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). 2 Additional power dissipation information can be found in the Power Dissipation and Thermal Considerations section. ESD CAUTION Rev. C | Page 15 of 67 AD9528 Data Sheet 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 VDD SYSREF_IN SYSREF_IN VDD0 OUT0 OUT0 VDD1 OUT1 OUT1 VDD2 OUT2 OUT2 VDD3 OUT3 OUT3 SYSREF_REQ STATUS1/SP1 STATUS0/SP0 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 AD9528 TOP VIEW (Not to Scale) 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 VDD4 OUT4 OUT4 VDD5 OUT5 OUT5 VDD6 OUT6 OUT6 VDD7 OUT7 OUT7 VDD8 OUT8 OUT8 VDD9 OUT9 OUT9 NOTES 1. NIC = NO INTERNAL CONNECTION. THIS PIN CAN BE LEFT FLOATING. 2. THE EXPOSED PAD IS THE GROUND CONNECTION ON THE CHIP. IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL STRENGTH BENEFITS. 12380-002 RESET VDD CS SCLK/SCL SDIO/SDA SDO OUT13 OUT13 VDD13 OUT12 OUT12 VDD12 OUT11 OUT11 VDD11 OUT10 OUT10 VDD10 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 VDD REFA REFA REF_SEL REFB REFB LF1 VCXO_VT NIC VDD VCXO_IN VCXO_IN NIC LF2_CAP LDO_VCO VDD NIC NIC Figure 2. Pin Configuration Table 21. Pin Function Descriptions Pin No. 1 2 Mnemonic VDD REFA Type1 P I 3 REFA I 4 REF_SEL I 5 REFB I 6 REFB I 7 8 9 10 11 LF1 VCXO_VT NIC VDD VCXO_IN O O NIC P I 12 VCXO_IN I 13 14 NIC LF2_CAP NIC O Description 3.3 V Supply for the PLL1 Input Section. Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. Reference Input Select. The reference input selection function defaults to software control via internal Register 0x010A, Bits[2:0]. When the REF_SEL pin is active, a logic low selects REFA and logic high selects REFB. Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. PLL1 External Loop Filter. VCXO Control Voltage. Connect this pin to the voltage control pin of the external VCXO. No Internal Connection. The pin can be left floating. 3.3 V Supply for the PLL2 Section. PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. Complementary PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. No Internal Connection. The pin can be left floating. PLL2 External Loop Filter Capacitor Connection. Connect capacitor between this pin and the LDO_VCO pin. Rev. C | Page 16 of 67 Data Sheet AD9528 Pin No. 15 Mnemonic LDO_VCO Type1 P/O 16 17 18 19 20 21 22 23 24 VDD NIC NIC RESET VDD CS SCLK/SCL SDIO/SDA SDO P NIC NIC I P 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 OUT13 OUT13 VDD13 OUT12 OUT12 VDD12 OUT11 OUT11 VDD11 OUT10 OUT10 VDD10 OUT9 OUT9 VDD9 OUT8 OUT8 VDD8 OUT7 OUT7 VDD7 OUT6 OUT6 VDD6 OUT5 OUT5 VDD5 OUT4 OUT4 VDD4 STATUS0/SP0 STATUS1/SP1 SYSREF_REQ OUT3 OUT3 VDD3 OUT2 OUT2 VDD2 O O P O O P O O P O O P O O P O O P O O P O O P O O P O O P I/O I/O I O O P O O P I I/O O Description 2.5 V LDO Internal Regulator Decoupling for the VCO. Connect a 0.47 F decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 3.3 V Supply for the PLL2 Internal Regulator. No Internal Connection. The pin can be left floating. No Internal Connection. The pin can be left floating. Digital Input, Active Low. Resets internal logic to default states. 3.3 V Supply for the PLL2 Internal Regulator. Serial Control Port Chip Select, Active Low. This pin has an internal 30 k pull-up resistor. Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming. Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I2C Mode (SDA). Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up or pull-down resistor on this pin. Square Wave Clocking Output 13. Complementary Square Wave Clocking Output 13. 3.3 V Supply for the Output 13 Clock Driver. Square Wave Clocking Output 12. Complementary Square Wave Clocking Output 12. 3.3 V Supply for the Output 12 Clock Divider. Square Wave Clocking Output 11. Complementary Square Wave Clocking Output 11. 3.3 V Supply for the Output 11 Clock Driver. Square Wave Clocking Output 10. Complementary Square Wave Clocking Output 10. 3.3 V Supply for the Output 10 Clock Divider. Square Wave Clocking Output 9. Complementary Square Wave Clocking Output 9. 3.3 V Supply for the Output 9 Clock Driver. Square Wave Clocking Output 8. Complementary Square Wave Clocking Output 8. 3.3 V Supply for the Output 8 Clock Divider. Square Wave Clocking Output 7. Complementary Square Wave Clocking Output 7. 3.3 V Supply for the Output 7 Clock Driver. Square Wave Clocking Output 6. Complementary Square Wave Clocking Output 6. 3.3 V Supply for the Output 6 Clock Divider. Square Wave Clocking Output 5. Complementary Square Wave Clocking Output 5. 3.3 V Supply for the Output 5 Clock Driver. Square Wave Clocking Output 4. Complementary Square Wave Clocking Output 4. 3.3 V Supply for the Output 4 Clock Divider. Lock Detect and Other Status Signals/I2C Address. This pin has an internal 30 k pull-down resistor. Lock Detect and Other Status Signals/I2C Address. This pin has an internal 30 k pull-down resistor. SYSREF Request Input Logic Control. Square Wave Clocking Output 3. Complementary Square Wave Clocking Output 3. 3.3 V Supply for the Output 3 Clock Driver. Square Wave Clocking Output 2. High speed output up to 1.25 GHz. Complementary Square Wave Clocking Output 2. High speed output up to 1.25 GHz. 3.3 V Supply for the Output 2 Clock Divider. Rev. C | Page 17 of 67 AD9528 Data Sheet Pin No. 64 65 66 67 68 69 70 Mnemonic OUT1 OUT1 VDD1 OUT0 OUT0 VDD0 SYSREF_IN Type1 O O P O O P I 71 SYSREF_IN I 72 EP VDD EP, GND P GND 1 Description Square Wave Clocking Output 1. High speed output up to 1.25 GHz. Complementary Square Wave Clocking Output 1. High speed output up to 1.25 GHz. 3.3 V Supply for the Output 1 Clock Driver. Square Wave Clocking Output 0. Complementary Square Wave Clocking Output 0. 3.3 V Supply for the Output 0 Clock Divider. External SYSREF Input Clock. Along with SYSREF_IN, this pin is the differential input for an external SYSREF signal. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. Complementary External SYSREF Input Clock. Along with SYSREF_IN, this pin is the differential input for an external SYSREF signal. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 3.3 V Supply for the PLL1 Input Section. Exposed Pad. The exposed pad is the ground connection on the chip. It must be soldered to the analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. P means power, I means input, O means output, I/O means input/output, P/O means power/output, and GND means ground. Rev. C | Page 18 of 67 Data Sheet AD9528 TYPICAL PERFORMANCE CHARACTERISTICS fVCXO = 122.88 MHz, REFA differential at 122.88 MHz, fVCO = 3686.4 MHz, and doubler is off, unless otherwise noted. External PLL1 loop filter component values are as follows: RZERO = 10 k, CZERO = 1 F, CPOLE = 200 pF. External PLL2 external capacitor CZERO = 1 nF. PLL1 charge pump = 5 A and PLL2 charge pump = 805 A. 40 1.2 CURRENT (mA) 30 25 20 15 10 0 50 250 450 650 850 1050 1250 OUTPUT FREQUENCY (MHz) 1.0 0.8 0.6 0.4 0.2 12380-003 5 LVDS BOOST LVDS 0 0 200 400 600 800 1000 1200 1400 OUTPUT FREQUENCY (MHz) 12380-006 DIFFERENTIAL VOLTAGE SWING (V p-p) 35 Figure 6. Differential Voltage Swing vs. Output Frequency, LVDS Mode and LVDS Boost Mode Figure 3. VDDx Current (Typical) vs. Output Frequency, HSTL Mode 60 35 58 30 56 54 DUTY CYCLE (%) CURRENT (mA) 25 20 LVDS BOOST LVDS 15 HSTL LVDS LVDS BOOST 52 50 48 46 10 44 5 250 450 650 850 1050 1250 OUTPUT FREQUENCY (MHz) 40 12380-004 0 50 Figure 4. VDDx Current (Typical) vs. Output Frequency, LVDS Mode and LVDS Boost Mode 0 200 400 600 800 1000 OUTPUT FREQUENCY (MHz) 1200 1400 Figure 7. Positive Duty Cycle vs. Output Frequency, HSTL, LVDS, and LVDS Boost Modes 2.0 1.5 1 1.0 0 200 400 600 800 1000 OUTPUT FREQUENCY (MHz) 1200 1400 Figure 5. Differential Voltage Swing vs. Output Frequency, HSTL Mode Rev. C | Page 19 of 67 12380-008 0.5 12380-005 DIFFERENTIAL VOLTAGE SWING (V p-p) 2.5 0 12380-007 42 CH1 500mV M1.25ns 20.0GS/s A CH1 80.0mV Figure 8. Output Waveform (Differential), HSTL at 122.88 MHz Data Sheet 1 M200ps 20.0GS/s A CH1 -80 -90 -100 -110 -120 -130 -140 1: 2: 3: 4: 5: 6: 7: x: 80.0mV 100Hz -105.7178dBc/Hz 1kHz -134.3390dBc/Hz 10kHz -145.1476dBc/Hz 100kHz -152.6346dBc/Hz 1MHz -157.9614dBc/Hz 10MHz -161.1440dBc/Hz 40MHz -161.1443dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -87.3785dBc/19.69MHz RMS NOISE: 60.4767rad 3.46506mdeg RMS JITTER: 78.33fsec RESIDUAL FM: 619.186Hz 1 2 -150 -160 -170 -180 100 12380-010 CH1 500mV -20 -30 -40 -50 -60 -70 7 3 4 5 1k 10k 100k 1M 12380-012 PHASE NOISE (dBc/Hz) AD9528 6 10M FREQUENCY (Hz) Figure 9. Output Waveform (Differential), HSTL at 1228.8 MHz R1 A CH1 80.0mV 1 2 3 7 4 5 1k 10k 100k 1M 6 10M A CH1 80.0mV -20 -30 -40 -50 -60 -70 -80 -90 -100 1: 2: 3: 4: 5: 6: 7: x: 100Hz -105.5794dBc/Hz 1kHz -125.9783dBc/Hz 10kHz -135.4507dBc/Hz 100kHz -139.4561dBc/Hz 1MHz -148.5800dBc/Hz 10MHz -161.0299dBc/Hz 40MHz -161.7150dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -81.2870dBc/19.69MHz RMS NOISE: 121.946rad 6.98697mdeg RMS JITTER: 157.945fsec RESIDUAL FM: 619.939Hz 1 -110 -120 -130 -140 -150 -160 -170 -180 100 2 3 4 7 5 6 1k 10k 100k 1M 12380-013 PHASE NOISE (dBc/Hz) Figure 13. Phase Noise, Output = 122.88 MHz, HSTL Mode, PLL1 Output Sent Directly to Clock Distribution, PLL2 Off (VCXO = 122.88 MHz, TAITEN VCXO (A0145-0-011-3) 12380-011 R1 M200ps 20.0GS/s 100Hz -97.1175dBc/Hz 1kHz -124.9178dBc/Hz 10kHz -137.7096dBc/Hz 100kHz -149.2171dBc/Hz 1MHz -154.9158dBc/Hz 10MHz -157.3075dBc/Hz 40MHz -157.7049dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -83.6685dBc/19.69MHz RMS NOISE: 92.7025rad 5.31146mdeg RMS JITTER: 120.069fsec RESIDUAL FM: 954.322Hz FREQUENCY (Hz) Figure 10. Output Waveform (Differential), LVDS and LVDS Boost Mode at 122.88 MHz CH1 200mV REF1 200mV 200ps -80 -90 -100 -110 -120 -130 -140 1: 2: 3: 4: 5: 6: 7: x: -150 -160 -170 -180 100 12380-009 CH1 200mV M1.25ns 20.0GS/s REF1 200mV 1.25ns -20 -30 -40 -50 -60 -70 12380-113 PHASE NOISE (dBc/Hz) Figure 12. Phase Noise, Output = 122.88 MHz, HSTL Mode, PLL1 Output Sent Directly to Clock Distribution, PLL2 Off (VCXO = 122.88 MHz, Crystek VCXO CVHD-950) 10M FREQUENCY (Hz) Figure 11. Output Waveform (Differential), LVDS and LVDS Boost Mode at 1228.8 MHz Figure 14. Phase Noise, Output = 122.88 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3686.4 MHz) Rev. C | Page 20 of 67 100Hz -96.5498dBc/Hz 1kHz -121.6777dBc/Hz 10kHz -132.7333dBc/Hz 100kHz -138.8233dBc/Hz 1MHz -148.6796dBc/Hz 10MHz -161.2569dBc/Hz 40MHz -161.8592dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -80.8845dBc/19.69MHz RMS NOISE: 127.73rad 7.31838mdeg RMS JITTER: 165.436fsec RESIDUAL FM: 606.124Hz 3 4 7 5 6 1k 10k 100k 1M 10M 1: 2: 3: 4: 5: 6: 7: x: 2 3 7 6 1k RMS JITTER (fs) 4 100k 1M 1k 7 100k 1M 10M 12380-015 PHASE NOISE (dBc/Hz) 4 10k 250 0 0.25 0.50 0.75 SLEW RATE (V/ns) 1.00 1.25 Figure 19. RMS Jitter in Buffer Mode with Both PLL1 and PLL2 Off vs. Slew Rate; Input Applied to the VCXO Input and Output Taken from Clock Distribution, Phase Noise Integration Range from 12 kHz to 20 MHz to Derive Jitter Number 100Hz -87.8362dBc/Hz 1kHz -107.4063dBc/Hz 10kHz -116.9100dBc/Hz 100kHz -120.3499dBc/Hz 1MHz -130.0948dBc/Hz 10MHz -148.6848dBc/Hz 40MHz -153.0204dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -63.1118dBc/19.69MHz RMS NOISE: 988.38rad 56.63mdeg RMS JITTER: 160.02fsec RESIDUAL FM: 2.52821kHz 6 300 100 10M 5 350 150 1: 2: 3: 4: 5: 6: 7: x: 3 400 200 7 12380-014 PHASE NOISE (dBc/Hz) 450 Figure 16. Phase Noise, Output = 245.76 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3686.4 MHz) 2 100M 500 FREQUENCY (Hz) -20 -30 -40 -50 -60 -70 -80 1 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100 10M 550 6 10k 1M 600 100Hz -100.4578dBc/Hz 1kHz -119.6740dBc/Hz 10kHz -128.8210dBc/Hz 100kHz -133.1106dBc/Hz 1MHz -142.2744dBc/Hz 10MHz -157.2191dBc/Hz 40MHz -158.8503dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -75.3030dBc/19.69MHz RMS NOISE: 242.865rad 13.9152mdeg RMS JITTER: 157.28fsec RESIDUAL FM: 955.126Hz 5 1k 100k Figure 18. Phase Noise, Output = 1228.8 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3686.4 MHz) 1: 2: 3: 4: 5: 6: 7: x: 3 10k FREQUENCY (Hz) Figure 15. Phase Noise, Output = 122.88 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, TAITEN VCXO (A0145-0-011-3), VCO = 3686.4 MHz) 2 4 5 FREQUENCY (Hz) -20 -30 -40 -50 -60 -70 -80 -90 1 -100 -110 -120 -130 -140 -150 -160 -170 -180 100 100Hz -84.5874dBc/Hz -105.8475dBc/Hz 1kHz 10kHz -115.4067dBc/Hz 100kHz -119.7711dBc/Hz 1MHz -128.8223dBc/Hz 10MHz -147.3225dBc/Hz 40MHz -152.6352dBc/Hz START 12kHz STOP 20kHz CENTER 10.006MHz SPAN 19.988MHz NOISE ANALYSIS RANGE X: BAND MARKER ANALYSIS RANGE Y: BAND MARKER INTG NOISE: -62.2776dBc/19.69MHz RMS NOISE: 1.08802rad 62.3389mdeg RMS JITTER: 140.921fsec RESIDUAL FM: 2.94672kHz 12380-018 2 -20 -30 -40 -50 -60 -70 -80 1 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 100 12380-016 1: 2: 3: 4: 5: 6: 7: x: PHASE NOISE (dBc/Hz) -20 -30 -40 -50 -60 -70 -80 -90 1 -100 -110 -120 -130 -140 -150 -160 -170 -180 100 AD9528 12380-115 PHASE NOISE (dBc/Hz) Data Sheet 100M FREQUENCY (Hz) Figure 17. Phase Noise, Output = 983.04 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3932.16 MHz) Rev. C | Page 21 of 67 AD9528 Data Sheet INPUT/OUTPUT TERMINATION RECOMMENDATIONS HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT 100 Figure 20. AC-Coupled LVDS Output Driver Figure 23. DC-Coupled HSTL Output Driver 0.1F AD9528 100 HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT AD9528 SELF-BIASED REF, VCXO INPUTS 100 (OPTIONAL1) 12380-020 LVDS OUTPUT HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT 12380-022 0.1F HSTL OUTPUT 0.1F 1RESISTOR VALUE DEPENDS UPON REQUIRED TERMINATION OF SOURCE. Figure 24. REFx, VCXO Input Differential Mode Receiver Figure 21. DC-Coupled LVDS Output Driver AD9528 0.1F 100 0.1F AD9528 3.3V CMOS DRIVER HIGH IMPEDANCE DOWNSTREAM DEVICE INPUT 12380-021 HSTL OUTPUT 12380-023 100 12380-019 LVDS OUTPUT AD9528 0.1F 0.1F Figure 22. AC-Coupled HSTL Output Driver 12380-123 AD9528 Figure 25. REFx, VCXO Input, Single-Ended Mode Receiver Rev. C | Page 22 of 67 Data Sheet AD9528 TYPICAL APPLICATION CIRCUIT The AD9528 is capable of synchronizing multiple devices designed to the JESD204B JEDEC standard. Figure 26 illustrates the AD9528 synchronizing to the system reference clock. The AD9528 first jitter cleans the system reference clock and TO NETWORK PROCESSOR SYSTEM REFERENCE CLOCK BASEBAND PROCESSOR DEVICE CLOCK multiples up to a higher frequency in dual loop mode. The clock distribution of the AD9528 is used to clock and synchronize all the surrounding JESD204B devices together in the system. CONTROL AND DATA INTERFACES TRANSCEIVER DEVICE CLOCK SYSREF SYSREF AD9528 TIMING AND CLOCK GENERATION VCXO ADP150 ULTRA LOW NOISE LDO ADP5054 ADP5052 OPTIONAL DEVICE CLOCK AND SYSREF PAIRS FOR OTHER TRANSCEIVERS OR LOGIC DEVICES 12380-124 CLOCK CLEANUP DC-TO-DC CONVERTER (SWITCHER) Figure 26. Synchronizing Multiple JESD204B Devices Rev. C | Page 23 of 67 AD9528 Data Sheet TERMINOLOGY Phase Jitter An ideal sine wave has a continuous and even progression of phase with time from 0 to 360 for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. Phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values with the units dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. In some applications, it is meaningful to integrate only the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase Noise Phase noise has a detrimental effect on the performance of analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and radio frequency (RF) mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev. C | Page 24 of 67 Data Sheet AD9528 THEORY OF OPERATION DETAILED BLOCK DIAGRAM VCXO LF1 VCXO_VT VCXO_IN LDO_VCO LF2_CAP VCXO_IN PLL1 REFA RA REFA 10-BIT DIVIDER REF_SEL REFB REFB D Q LOCK DETECT SWITCHOVER CONTROL 10-BIT DIVIDER N1 RB 10-BIT DIVIDER LOOP FILTER P F D FINE DELAY 8-BIT DIVIDER WITH COARSE DELAY PLL 2 M1 CHARGE PUMP 5-BIT DIVIDER x2 P F D CHARGE PUMP LOOP FILTER VCO DIVIDER /3, /4, /5 R1 N2 8-BIT DIVIDER OUT0 OUT0 SYNC D Q FINE DELAY 8-BIT DIVIDER WITH COARSE DELAY OUT1 OUT1 OUT2 TO OUT11 OUT2 TO OUT11 SYNC PLL2 FEEDBACK DIVIDER = N2 (N3) SYNC D Q FINE DELAY 8-BIT DIVIDER WITH COARSE DELAY SYSREF_IN SYSREF_IN SYNC D Q D Q D Q 8-BIT DIVIDER WITH COARSE DELAY LOCK DETECT CONTROL INTERFACE (SDI AND I2C) STATUS1/SP1 STATUS MONITOR LOCK DETECT/ SERIAL PORT ADDRESS OUT13 OUT13 SYNC SYSREF GENERATION TRIGGER D Q SPI_SYS_REF REQUEST STATUS0/SP0 FINE DELAY SYSREF GENERATION AD9528 SYSREF_REQ 12380-024 SDO SDIO/SDA SCLK/SCL CS RESET OUT12 OUT12 Figure 27. Top Level Diagram OVERVIEW The AD9528 is a clock generator that employs integer-N based phase-locked loops (PLL). The device architecture consists of two cascaded PLL stages. PLL1 consists of an integer division PLL that uses an external voltage controlled crystal oscillator (VCXO). PLL1 has a narrow loop bandwidth that provides initial jitter cleanup of the input reference signal for the input stage of PLL2. Conversely, the output of PLL1 is also routable to any clock distribution output, if desired. PLL2 is a frequency multiplying PLL that translates the first PLL stage output frequency to a range of 3.450 GHz to 4.025 GHz. PLL2 incorporates an integer based feedback divider that enables integer frequency multiplication. An RF VCO divider (3, 4, or 5) divides the VCO output of PLL2 before being routed to the input of the clock distribution section. Programmable integer dividers (1 to 256) in the clock distribution follow the RF VCO divider, establishing a final output frequency up to 1 GHz or less for the 12 available outputs. The OUT1 and OUT2 outputs can run up to 1.25 GHz. All of the divider settings in the clock distribution section are configurable via the serial programming port, enabling a wide range of input/output frequency ratios under program control. The dividers also include a programmable coarse delay to adjust timing of the output signals, if required. In addition, a fine delay adjust is available in the clock distribution path. The outputs are compatible with LVDS and HSTL logic levels. The AD9528 can produce a JESD204B SYSREF signal. This signal can be routed to any of the 14 outputs. The AD9528 can also receive an externally generated SYSREF signal and buffer to the outputs, with or without retiming. The AD9528 operates over the extended industrial temperature range of -40C to +85C. The AD9528 includes reference monitoring and automatic/manual switchover and holdover. A reference select pin is available to manually select which input reference is active. The accuracy of the holdover is dependent on the external VCXO frequency stability. All power supply pins on the AD9528 operate on a 3.3 V 5% supply domain. However, each power supply pin has a dedicated internal LDO regulator that provides approximately 1.8 V for standard operation of the device. These independent regulators provide extra supply rejection and help with output to output coupling, since none of the output drivers or dividers share a supply. COMPONENT BLOCKS--PLL1 PLL1 General Description PLL1 consists of a phase/frequency detector (PFD), a charge pump, an external VCXO, and a partially external loop filter operating in a closed loop. Rev. C | Page 25 of 67 AD9528 Data Sheet PLL1 Loop Filter PLL1 has the flexibility to operate with a narrow loop bandwidth. This relatively narrow loop bandwidth gives the AD9528 the ability to suppress jitter that appears on the input references (REFA and REFB). The low phase noise output of PLL1 acts as the reference to PLL2 and can be routed to the clock distribution section. The PLL1 loop filter is mostly external from LF1 (Pin 7) to ground. The value of the external components depend on the external VCXO and the configuration parameters, such as input clock rate and desired PLL1 loop bandwidth. LF1EXT_CAP PLL1 Reference Clock Inputs The AD9528 features two separate reference clock inputs, REFA and REFB. These inputs can be configured to accept differential or single-ended signals. REFA and REFB are self biased in differential mode and high impedance in single ended CMOS mode. If REFA or REFB is driven single-ended, decouple the unused side (REFA, REFB) via a suitable capacitor to a quiet ground. These inputs may be dc-coupled, but set the dc operation point as specified in the Specifications section. CEXT_POLE REXT_ZERO LF1 AD9528 CHARGE PUMP The differential reference input receiver is powered down when the differential reference input is not selected, or when the PLL1 is powered down. The single-ended buffers power down when the PLL1 is powered down, when their respective individual power-down registers are set, or when the differential receiver is selected. RPOLE2 165k BUFFER An external RC low-pass filter is recommended at the VCXO_VT output for the best noise performance at 1 kHz offset. The pole of this filter must be sufficiently high enough in frequency to avoid stability problems with the PLL loop bandwidth. LF1 RA VCXO_VT VCXO_IN VCXO_IN LOOP LOCK DETECT FILTER 10-BIT DIVIDER SWITCHOVER CONTROL 10-BIT DIVIDER RB P F D CHARGE PUMP 10-BIT DIVIDER N1 12380-026 REFB REFB 1k Figure 28. PLL1 Loop Filter PLL 1 REF_SEL TO EXTERNAL VCXO VCXO_VT 0.47F VCXO REFA REFA OPTIONAL FILTER 12380-025 CPOLE2 72pF AD9528 Figure 29. Input PLL (PLL1) Block Diagram Rev. C | Page 26 of 67 Data Sheet AD9528 PLL1 Input Dividers PLL1 Holdover Each reference input has a dedicated reference divider block. The input dividers provide division of the reference frequency in integer steps from 1 to 1023. In the absence of both input references, the device enters holdover mode. When the device switches to holdover mode, the charge pump tristates, allowing VCXO_VT to maintain its existing value for a period of time. Optionally, the charge pump can be programmed to force VCXO_VT to VDD/2. The device continues operating in this mode until a reference signal becomes available. Then the device exits holdover mode, and PLL1 resynchronizes with the active reference. Automatic holdover mode can be disabled with a register bit. PLL2 remains locked to the VCXO signal even when PLL1 is in holdover. PLL1 Reference Switchover The reference monitor verifies the presence or absence of the REFA and REFB signals. The status of the reference monitor guides the activity of the switchover control logic. The AD9528 supports automatic and manual PLL reference clock switching between REFA (the REFA and REFA pins) and REFB (the REFB and REFB pins). There are several configurable modes of reference switchover. The manual switchover is achieved either via programming a register setting or by using the REF_SEL pin. If manually selecting REFB, REFB must be present prior to when the switchover to REFB occurs. The automatic switchover occurs when REFA disappears and a reference is on REFB. PLL1 operates with REFA as the primary reference input; this is relevant to the switchover operation of the device. The reference automatic switchover can be set to work as follows: * Nonrevertive. Stay on REFB. Switch from REFA to REFB when REFA disappears, but do not switch back to REFA if it reappears. If REFB disappears, then go back to REFA. * Revert to REFA. Switch from REFA to REFB when REFA disappears. Return to REFA from REFB when REFA returns. If a switchover event occurs in nonrevertive mode and the missing input to REFA is reestablished, the return of the missing reference does not reset the nonrevertive switchover logic. The result of this setup is that, if REFB is selected during nonrevertive switchover mode and nonrevertive switchover is disabled and reenabled, REFB is still the active reference, regardless if REFA is present. The switchover logic can be reset by issuing a device reset. PLL1 Lock Time The typical PLL1 lock time occurs within 5x the period of the loop bandwidth, assuming a third-order loop filter with a phase margin of 55. It may take up to 10x the period of the loop bandwidth for the PLL1 lock detector circuit to show locked status. Calculate PLL1_TO in Figure 52 as PLL1_TO = 10/LBWPLL1 where: PLL1_TO is the PLL1 timeout. LBWPLL1 is the loop bandwidth of PLL1. COMPONENT BLOCKS--PLL2 PLL2 General Description PLL2 consists of an optional input reference 2x multiplier, reference divider, a PFD, a mostly integrated analog loop filter, an integrated voltage controlled oscillator (VCO), and a feedback divider. The VCO produces a nominal 3.8 GHz signal with an output divider that is capable of division ratios of 3, 4, and 5. PLL2 has a VCO with multiple bands spanning a range of 3.450 GHz to 4.025 GHz. The device automatically selects the appropriate band as part of its calibration process. Rev. C | Page 27 of 67 AD9528 Data Sheet LF2_CAP VDD LDO_VCO LDO LDO RZERO PLL_1.8V CPOLE1 x2 R1 DIVIDE-BY1, 2, 3...31 PFD CPOLE2 CHARGE PUMP 8 BITS, 3.5A LSB RPOLE2 RF VCO DIVIDER /3, /4, /5 TO DIST/ RESYNC VCO CAL DIVIDER A/B COUNTERS AD9528 DIVIDE-BY-4 PRESCALER N2 12380-027 N = 1 TO 256 Figure 30. PLL2 Block Diagram PLL2 Input 2x Frequency Multiplier PLL2 Feedback Dividers The 2x frequency multiplier provides the option to double the frequency at the PLL2 reference input. A higher frequency at the input to the PLL2 (PFD) allows reduced in-band phase noise and greater separation between the frequency generated by the PLL and the modulation spur associated with the PFD. Note that, as the input duty cycle deviates from 50%, harmonic distortion may increase. As such, beneficial use of the frequency multiplier is application specific. Typically, a VCXO with proper interfacing has a duty cycle that is approximately 50% at the VCXO_IN inputs. Note that the maximum output frequency of the 2x frequency multipliers must not exceed the maximum PFD rate specified in Table 7. PLL2 has two feedback paths as shown in Figure 30. In normal PLL2 operation mode, the PLL2 feedback path consists of N2 (an 8-bit divider) and M1 (a VCO RF divider). The product of N2 and M1 establishes the total PLL multiplication value for PLL2. If the 2x frequency multiplier is used, a fixed phase offset can occur from power-up to power-up between the input to the 2x frequency multiplier and the PLL2 PFD reference input. This presents the possibility for a fixed phase offset between the VCXO_IN frequency and PLL2 output of 1/2 the period of the signal applied to the VCXO_IN and VCXO_IN pins. If the internal SYSREF generator is used, choose the PLL2 feedback path as the input signal of the SYSREF generator to ensure fixed phase alignment of the SYSREF generator from power-up to power-up. PLL2 Input Reference Divider The input reference divider (R1) provides division in integer steps from 1 to 31 with a maximum input frequency of 275 MHz. The divider provides an option to prescale the PFD rate of PLL2 for output frequency planning and to accommodate more flexibility for setting the desired loop bandwidth for PLL2. If the R1 divider is used along with the SYSREF generator, choose the PLL2 feedback path as the input signal of the SYSREF generator to ensure fixed phase alignment of the SYSREF generator from power-up to power-up. The second feedback path for PLL2 uses the VCO CAL divider (see Figure 30). The VCO CAL divider is exclusively used to calibrate the internal VCO of PLL2. Register 0x0201, Register 0x0204, Register 0x0207, and Register 0x0208 program the PLL multiplication values for both PLL2 feedback paths. The total PLL multiplication in both feedback paths must equal one another for proper VCO calibration. After each VCO calibration, the VCO CAL divider feedback path automatically disables and reverts back to the feedback path with N2 and M1 dividers for normal operation. The VCO CAL divider is not available outside of VCO calibration. The VCO CAL divider consists of a prescaler (P) divider and two counters, A and B. The total divider value is VCO CAL divider = (P x B) + A where P = 4. The VCO CAL feedback divider has a dual modulus prescaler architecture with a nonprogrammable P that is equal to 4. The value of the B counter can be from 3 to 63, and the value of the A counter can be from 0 to 3. 16 is the minimum supported divide value. The VCO RF divider (M1) provides frequency division between the internal VCO and the clock distribution. The VCO RF divider can be set to divide by 3, 4, or 5. The VCO RF divider is part of the total PLL2 feedback path value for normal operation. PLL2 Loop Filter The PLL2 loop filter requires the connection of an external capacitor from LF2_CAP (Pin 14) to LDO_VCO (Pin 15). The Rev. C | Page 28 of 67 Data Sheet AD9528 value of the external capacitor depends on the operating mode and the desired phase noise performance. For example, a loop bandwidth of approximately 500 kHz produces the lowest integrated jitter. A lower bandwidth produces lower phase noise at 1 MHz but increases the total integrated jitter LF2_CAP LDO_VCO LDO CPOLE1 During power-up or reset, channels driven by the RF VCO driver are automatically held in sync until the first VCO calibration is finished. Therefore, none of those channel outputs can occur until VCO calibration is complete. CPOLE2 CHARGE PUMP VTUNE RPOLE2 12380-028 RZERO Figure 31. PLL2 Loop Filter Initiate a VCO calibration under the following conditions: * Table 22. PLL2 Loop Filter Programmable Values (Register 0x0205) RZERO () 3250 3000 2750 2500 2250 2100 2000 1850 1 2 CPOLE1 (pF) 48 40 32 24 16 8 0 RPOLE2 () 900 450 300 225 N/A1 N/A1 N/A1 N/A1 CPOLE2 (pF) Fixed at 16 N/A1 N/A1 N/A1 N/A1 N/A1 N/A1 N/A1 setup before executing the IO_UPDATE bit (Register 0x000F, Bit 0 = 1). A readback bit, VCO calibration in progress (Register 0x0509, Bit 0), indicates when a VCO calibration is in progress by returning a logic true (that is, Bit 0 = 1), however this bit is automatically cleared after the calibration is finished, so it tells if the calibration started but did not finish. After calibration, initiate a sync (see the Clock Distribution Synchronization section). A sync occurs automatically after calibration. See Figure 53 for the detailed procedure. LF2_CAP2 (pF) Typical at 1000 N/A1 N/A1 N/A1 N/A1 N/A1 N/A1 N/A1 N/A means not applicable. External loop filter capacitor. VCO The VCO is tunable from 3.450 GHz to 4.025 GHz. The VCO operates off the VCO LDO supply. This LDO requires an external compensation cap of 0.47 F to ground. The VCO requires calibration prior to use. VCO Calibration The AD9528 on-chip VCO must be manually calibrated to ensure proper PLL2 operation over process, supply, and temperature. VCO calibration requires a valid VCXO input clock and applicable preprogrammed PLL1 and PLL2 register values prior to issuing the VCO calibration to ensure a PLL2 phase lock condition. In addition, the value of the VCO CAL feedback divider (see Figure 30) must equal the combined divider values of both the 8-bit N2 divider and RF VCO divider (M1). For example, if the N2 divide value is 10 and the M1 divide value is 3, the total PLL2 multiplication value is 30 in normal operation, so the VCO CAL divider value must be set to 30 prior to initiating a VCO calibration. See the PLL2 Feedback Dividers section for more details. When total PLL2 feedback divider value is 15, see Figure 53 for the detailed procedure. VCO calibration is initiated by transitioning the calibrate VCO bit (Bit 0 of Register 0x0203) from 0 to 1 (this bit is not self clearing). The setting can be performed as part of the initial * After changing the PLL2 N2 or M1 divider settings or after a change in the PLL2 reference clock frequency. This means that a VCO calibration must be initiated any time that a PLL2 register or reference clock changes such that a different VCO frequency is the result. Whenever system calibration is desired. The VCO is designed to operate properly over temperature extremes, even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time. To calibrate using the 2x multiplier, the total feedback divide must be >16. If the application requires the use of a feedback divide value <16, see the following example: For fVCXO = 122.88 MHz, fVCO = 3686.4 MHz, M1 = 3, N2 = 5, and with the 2x multiplier enabled, the total feedback divider value of 15 is less than the supported minimum for the calibration divider. To calibrate, the 2x multiplier must be disabled, and the calibration divider must be set to 30. After the calibration is complete, the 2x multiplier is enabled and the PLL acquires lock. PLL2 Lock Time/VCO Calibration Time The typical PLL2 lock time occurs within 5x the period of the loop bandwidth, assuming a phase margin of 55. It can take up to 10x the period of the loop bandwidth for the PLL2 lock detector circuit to show locked status. The typical PLL2 VCO calibration time is 400,000 periods of the PLL2 PFD rate. Calculate PLL2_TO in Figure 52 as PLL2_TO = 10/LBWPLL2 + 400,000/fPFD_PLL2 where fPFD_PLL2 is the frequency of the PLL2 phase detector. CLOCK DISTRIBUTION The clock distribution consists of 14 individual channels (OUT0 to OUT13). The input frequency source for each channel output is selectable as either the PLL1 output, PLL2 output, or SYSREF. Each of the output channels also includes a dedicated 8-bit divider, two dedicated phase delay elements and an output driver, as shown in Figure 32. Rev. C | Page 29 of 67 AD9528 Data Sheet another 496 ps of additional delay. The average fine delay resolution step is approximately 31 ps. CLOCK DISTRIBUTION OUTx SYNC Figure 32. Clock Distribution Paths for PLL1, PLL2, and SYSREF Frequency Sources The following are various channel limitations, depending on the channel configuration: * * * Analog fine delay is supported for all channels, regardless of the input frequency source selected. Digital coarse delay is only supported when the channel divider is used. When SYSREF is used as the frequency source, the signal must be retimed by the output of the channel divider to use the digital coarse delay. Output channel synchronization is performed by synchronously resetting the 8-bit channel divider via the sync outputs bit in Register 0x032A, Bit 0. Therefore, the 8-bit divider path must be used to support synchronization. If SYSREF is the frequency source to an output, the SYSREF signal must be resampled by the output of the channel divider for a SYNC to occur. Each output channel has independent power-down control via Register 0x0501 and Register 0x0502. The total device power is reduced with each channel powered down, keeping the output static until the user is ready to disable the channel power-down control. In addition, Register 0x0503 and Register 0x0504 offer additional power savings via LDO power-down control for each channel output. Output Drivers Each channel and corresponding output driver has a dedicated internal LDO to power both the channel and output driver. The equivalent output driver circuits are shown in Figure 33 and Figure 34. The output driver design supports a common external 100 differential resistor for both HSTL and LVDS driver modes. In LVDS mode, a current of 3.5 mA causes a 350 mV peak voltage across the 100 load resistor. In LVDS boost mode, a current of 4.5 mA causes a 450 mV peak voltage across the 100 load resistor. Similarly, in HSTL mode, a current of 9 mA causes a 900 mV peak voltage across the 100 load resistor. Clock Dividers LVDS COMMON MODE CIRCUIT VREG = 1.8V 1.25V LVDS The output clock distribution dividers are referred to as D0 to D13, corresponding to output channels OUT0 through OUT13, respectively. Each divider is programmable with 8 bits of precision equal to any number from 1 through 256. Dividers have duty cycle correction set to provide nominal 50% duty cycle, even for odd divides. Note that a sync output command must be issued after changing the divide value to ensure the intended divide ratio occurs at the channel output(s). CM P OUT OUT + N 100 - LOAD P 3.5mA/4.5mA Digital Coarse Delay The AD9528 supports programmable phase offsets from 0 to 63 steps (6 bits) in half period increments of the RF VCO divider output frequency. Note that a sync output command must be issued after the new phase offset(s) are programmed to ensure the intended phase offset occurs at the channel output(s). This is accomplished by programming the new phase offset and then issuing a sync command via Register 0x032A, Bit 0. All outputs are disabled temporarily while the sync is active, unless the channel is programmed to ignore the sync command. The ignore sync command for each channel is controlled via Register 0x032B and Register 0x032C. N CM 12380-131 SYSREF Output Channel Power-Down OUTx FINE DELAY 12380-130 PLL2 8-BIT DIVIDER WITH COARSE DELAY Figure 33. LVDS Output Driver VREG = 1.8V 50 N P OUT + 100 - LOAD N OUT P 50 Analog Fine Delay Each channel includes a 4-bit fine analog delay block intended to provide substantially smaller delay steps compared to the half cycle of the RF VCO divider output. The fine analog delay enable bit in each channel activates the fine delay path; when the enable bit is asserted with the four delay bits = 0000, the minimum insertion delay is nominally 425 ps. Full-scale delay = 1111 adds Rev. C | Page 30 of 67 Figure 34. HSTL Output Driver 12380-132 D Q PLL1 Data Sheet AD9528 Clock Distribution Synchronization When using the sync output bit to synchronize outputs, first set and then clear the bit. The synchronization event is the clearing operation (that is, the Logic 1 to Logic 0 transition of the bit). The channel dividers are automatically synchronized to each other when PLL2 is ready. A block diagram of the clock distribution synchronization functionality is shown in Figure 35. The synchronization feature edge aligns all outputs together or to forces a desired phase offset between output edges. An automatic synchronization of the channel dividers is initiated the first time the PLL2 locks after a power-up or reset event. Subsequent lock and unlock events do not initiate a resynchronization unless preceded by a powerdown or reset of the device. In normal operation, the phase offsets are already programmed through the SPI/I2C port before the AD9528 starts to provide outputs. Although the digital coarse phase offsets cannot be adjusted while the dividers are operating, it is possible to adjust the phase of all outputs relative to each other without powering down PLL1 and PLL2. This is accomplished by programming the new phase offset using Bits[5:0] in the clock distribution registers, and then issuing an output sync by using the sync outputs bit (Register 0x032A, Bit 0). All outputs are disabled temporarily while the sync output bit in Register 0x032A, Bit 0 is active, unless the channel is programmed to ignore the sync output command. The ignore sync command for each channel is controlled via Register 0x032B and Register 0x032C. OUTx DIVIDE PHASE DIVIDER OUT SYNC DRIVER OUTx VCO RF DIVIDER 12380-030 FAN OUT SYNC OUTPUT BIT Figure 35. Clock Distribution Synchronization Block Diagram SYNC OUTPUTS VCO DIVIDER OUTPUT CLOCK DIVIDE = 2, PHASE = 0 6 x 0.5 PERIODS Figure 36. Clock Output Synchronization Timing Diagram Rev. C | Page 31 of 67 12380-031 DIVIDE = 2, PHASE = 6 AD9528 Data Sheet SYSREF OPERATION specify an internally generated pulse pattern. There are three modes of operation associated with the two sources as defined by Register 0x0403, Bits[7:6]. The AD9528 supports the JESD204B standard for synchronizing high speed converters and logic devices such as FPGAs by providing paired device clock and SYSREF clock signals. The SYSREF clock or device clock can be distributed to any one or more of the 14 outputs via the clock distribution section within the AD9528. After the SYSREF clock reaches the clock distribution section, programmable digital coarse delay and/or analog fine delay is available to adjust timing between the SYSREF clock with respect to the device clock. The delay establishes proper setup and hold timing downstream between device clock and SYSREF clock at the inputs of the converter(s) or logic device(s). * * * SYSREF Mode 1: External Figure 37 shows the SYSREF clock path with Mode 1 selected. Apply an external SYSREF clock signal to the SYSREF_IN and/or SYSREF_IN pin(s). A single-ended signal may be applied to either pin separately or a differential signal may be applied across both pins. Note that the SYSREF_REQ pin and Bit 0 of Register 0x0403 (SPI SYSREF Request) are unused in Mode 1. SYSREF SIGNAL PATH The AD9528 provides two sources for the purpose of generating a SYSREF signal. The first source is a user provided external SYSREF clock signal applied to SYSREF_IN and SYSREF_IN (Pin 70 and Pin 71, respectively). The second source is an internal SYSREF generation circuit that enables the user to 00 = Mode 1 (external SYSREF) 01 = Mode 2 (external SYSREF resampled by the VCXO or PLL2 feedback divider) 1x = Mode 3 (internally generated SYSREF). VCXO_IN PLL2 DIVIDER AD9528 SYSREF_IN SYSREF_IN D Q CONTROL INTERFACE (SPI AND I2C) LOCK DETECT D Q SYSREF GENERATION TRIGGER SPI SYSREF REQUEST D Q TO CLOCK DISTRIBUTION SYSREF_REQ Figure 37. Mode 1, Routes the External SYSREF Directly to the Clock Distribution Output(s) Rev. C | Page 32 of 67 12380-032 SYSREF GENERATION Data Sheet AD9528 SYSREF Mode 2: External with Retiming SYSREF Mode 3: Internal Figure 38 shows the SYSREF clock path with Mode 2 selected. Apply a differential or single-ended SYSREF clock signal to the SYSREF_IN and SYSREF_IN pins (see Mode 1). Figure 39 shows the SYSREF clock path with Mode 3 selected. Mode 3 uses the internal SYSREF pattern generator and the SYSREF request feature to produce a user defined SYSREF signal. A SYSREF request can be made via hardware (the SYSREF_REQ pin) or software (Register 0x0403, Bit 0, the SPI SYSREF request bit). In internal SYSREF mode, the PLLs must be locked before the SYSREF request signal is used. Unlike Mode 1, Mode 2 retimes the external SYSREF signal either with the signal originating at the VCXO_IN and VCXO_IN pins (Pin 11 and Pin 12, respectively), or with the signal at the feedback node of PLL2. Register 0x0402, Bit 4 selects the source that retimes the external SYSREF signal. Note that the SYSREF_REQ pin and Bit 0 of Register 0x0403 (SPI SYSREF Request) are unused in Mode 2. VCXO_IN PLL2 DIVIDER AD9528 SYSREF_IN SYSREF_IN D Q CONTROL INTERFACE (SPI AND I2C) LOCK DETECT D Q SYSREF GENERATION TRIGGER SPI SYSREF REQUEST D Q TO CLOCK DISTRIBUTION 12380-033 SYSREF GENERATION SYSREF_REQ Figure 38. Mode 2, Retimes the External SYSREF to the Internal VCXO or PLL2 Input Divider Output and then Routes to the Clock Distribution Output(s) VCXO_IN PLL2 DIVIDER AD9528 SYSREF_IN SYSREF_IN D Q CONTROL INTERFACE (SDI AND I2C) LOCK DETECT D Q SYSREF GENERATION TRIGGER SPI SYSREF REQUEST D Q TO CLOCK DISTRIBUTION SYSREF_REQ Figure 39. Mode 3, SYSREF Generated Internally and Routed to the Clock Distribution Rev. C | Page 33 of 67 12380-034 SYSREF GENERATION AD9528 Data Sheet SYSREF GENERATOR Pin Control--Level Trigger Mode The SYSREF pattern generator produces a user defined SYSREF signal (see Table 23). The input clock to the pattern generator is provided by the signal originating at the VCXO_IN and VCXO_IN pins, or with the signal at the feedback node of PLL2. The pattern generator contains a fixed divide by 2 followed by a programmable 16-bit K divider (set by Register 0x0401 and Register 0x0400) to program the pulse width of the SYSREF. The value of K ranges from 0 to 65535. For example, if the pattern generator input clock is 122.88 MHz, the maximum SYSREF period is 131,070/122,880,000 seconds (1066 s). The pattern generator acts as a timer that only issues pulses synchronous to all other outputs, regardless of when an asynchronous SYSREF request is issued. In level trigger mode (Register 0x0402, Bit 6 = 0), the SYSREF pattern generator is controlled by the SYSREF_REQ pin. If Nshot mode is enabled, force the SYSREF_REQ pin to 1 from 0 to start the SYSREF pattern sequence. After the sequence is complete and N pulses are output, force the SYSREF_REQ pin to 0. The pattern generator then waits for the next SYSREF request. SYSREF Request The SYSREF request signal starts or stops the internal SYSREF pattern generator. The signal is controlled by software or via pin control. The SYSREF request method is controlled by Register 0x0402, Bit 7. Software Control In software control mode, the SYSREF pattern generator is always level trigger sensitive to the SYSREF pattern generator trigger control bits (Register 0x402, Bits[6:5]). With Bit 6 = 0 for level trigger mode, Bit 5 is used as the trigger. If N-shot mode is enabled, set Bit 5 = 1 from 0 to start the SYSREF pattern sequence. After the sequence is complete and N pulses are output, the SYSREF pattern generator automatically clears Bit 5 and waits for the next SYSREF request. In continuous mode, force the SYSREF_REQ pin to 1 from 0 to start the SYSREF pattern sequence. Force the SYSREF_REQ pin to 0 to stop the sequence. The pattern generator then waits for next SYSREF request. Pin Control--Edge Trigger Mode In edge trigger mode, the SYSREF pattern generator is controlled by the rising edge or falling edge on the SYSREF_REQ pin. The rising or falling active edge is determined by Register 0x0402, Bits[6:5]. With Bit 6 = 1, Bit 5 controls the active trigger edge. If N-shot mode is enabled, the SYSREF_REQ pin active edge starts the SYSREF pattern sequence. After the sequence is complete and N pulses are output, the pattern generator waits for the next SYSREF request. If SYSREF_REQ is set to 0 before N pulse(s) are done, the current pattern sequence is not affected. Therefore, if the new SYSREF_REQ active edge arrives before the pattern sequence is complete, the new request is missed. In continuous mode, the SYSREF_REQ active edge starts the SYSREF pattern sequence. After the sequence, the pattern generator waits for the next SYSREF request. In continuous mode, the pattern sequence continues if Bit 5 = 1. Clear Bit 5 to stop the sequence and wait for the next SYSREF request. Table 23. On-Chip SYSREF Generation Modes SYSREF Pattern Generator Mode (Register 0x0403, Bits[5:4]) 00 01 Generation Output Mode N-shot mode (Register 0x0403, Bits[3:1]) N-shot mode[2:0] = 001 = 1 pulse out N-shot mode[2:0] = 010 = 2 pulses out N-shot mode[2:0] = 011 = 4 pulses out N-shot mode[2:0] = 100 = 6 pulses out N-shot mode[2:0] = 101 = 8 pulses out N-shot mode[2:0] = 110 or greater = 1 pulse out Continuous mode 10 11 PRBS Stop Description The SYSREF outputs N pulses after the SYSREF request is initiated and then the SYSREF output goes logic low until the next SYSREF request. N can be programmed as 1, 2, 4, 6, or 8. The SYSREF output continuously outputs a 101010...pulse train and behaves like a clock with a frequency of fIN/(2 x K) after the SYSREF request is initiated. Not applicable. In stop mode, the SYSREF output is static low. Rev. C | Page 34 of 67 Data Sheet AD9528 SERIAL CONTROL PORT The AD9528 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9528 serial control port is compatible with most synchronous transfer formats, including I2C, Motorola SPI, and Intel SSR protocols. The serial control port allows read/write access to the AD9528 register map. Table 24. Serial Port Mode Selection The AD9528 uses the Analog Devices unified SPI protocol. The unified SPI protocol guarantees that all new Analog Devices products using the unified protocol have consistent serial port characteristics. The SPI port configuration is programmable via Register 0x0000. This register is a part of the SPI control logic rather than in the register map and is distinct from the I2C Register 0x0000. Pin Descriptions Unified SPI differs from the SPI port found on older products like the AD9523 and AD9524 in the following ways: * * * Unified SPI does not have byte counts. A transfer is terminated when the CS pin goes high. The W1 and W0 bits in the traditional SPI become the A12 and A13 bits of the register address. This is similar to streaming mode in the traditional SPI. The address ascension bit (Register 0x0000, Bit 2 and Bit 5) controls whether register addresses are automatically incremented or decremented regardless of the LSB/MSB first setting. In traditional SPI, LSB first dictated autoincrements and MSB first dictated autodecrements of the register address. Devices that adhere to the unified serial port have a consistent structure of the first 16 register addresses. Although the AD9528 supports both the SPI and I2C serial port protocols, only one is active following power-up (as determined by the STATUS0/SP0 and STATUS1/SP1 multifunction pins during the start-up sequence). The only way to change the serial port protocol is to reset (or power cycle) the device. SPI/I2C PORT SELECTION The AD9528 has two serial interfaces, SPI and I2C. Users can select either the SPI or I2C depending on the states (logic high, logic low) of the two logic level input pins (STATUS0/SP0 and STATUS1/SP1), when initial power is applied or after a RESET. When both STATUS/SP1 and STATUS0/SP0 are low, the SPI interface is active. Otherwise, I2C is active with three different I2C slave address settings (seven bits wide), as shown in Table 24. The five most significant bits (MSBs) of the slave address are hardware coded as 10101, and the two LSBs are determined by the logic levels of the STATUS1/SP1and STATUS0/SP0 pins. STATUS1/SP1 Low Low High STATUS0/SP0 Low High Low Address SPI I2C = 1010100 I2C = 1010101 SPI SERIAL PORT OPERATION The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 50 MHz. The SPI port supports both 3-wire (bidirectional) and 4-wire (unidirectional) hardware configurations and both MSB-first and LSB-first data formats. Both the hardware configuration and data format features are programmable. The 3-wire mode uses the SDIO (serial data input/output) pin for transferring data in both directions. The 4-wire mode uses the SDIO pin for transferring data to the AD9528, and the SDO pin for transferring data from the AD9528. The CS (chip select) pin is an active low control that gates read and write operations. Assertion (active low) of the CS pin initiates a write or read operation to the AD9528 SPI port. Any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented based on the setting of the address ascension bits (Register 0x0000, Bit 2 and Bit 5). CS must be deasserted at the end of the last byte transferred, thereby ending the stream mode. This pin is internally connected to a 10 k pull-up resistor. When CS is high, the SDIO and SDO pins go into a high impedance state. Implementation Specific Details The following product specific items are defined in the unified SPI protocol: * * * * * * * Rev. C | Page 35 of 67 Analog Devices unified SPI protocol Revision: 1.0 Chip type: 0x5 Clock serial ID: 0x00F Physical layer: 3-and 4-wire supported Optional single-byte instruction mode: not supported Data link not used Control not used AD9528 Data Sheet Communication Cycle--Instruction Plus Data A readback operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0x0001, Bit 5. The unified SPI protocol consists of a two-part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9528 serial control port with information regarding the payload. The instruction word includes the R/W bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the starting register address of the first payload byte. SPI Instruction Word (16 Bits) The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next 15 bits are the register address (A14 to A0), which indicates the starting register address of the read/write operation (see Table 26). Note that A14 and A13 are ignored and treated as zeros in the AD9528 because there are no registers that require more than 13 address bits. Write If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9528. Data bits are registered on the rising edge of SCLK. Generally, it does not matter what data is written to blank registers; however, it is customary to use 0s. Note that there may be reserved registers with default values not equal to 0x00; however, every effort was made to avoid this. SPI MSB-/LSB-First Transfers The AD9528 instruction word and payload can be MSB first or LSB first. The default for the AD9528 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x0000, Bit 1 and Bit 6. Immediately after the LSB first bit is set, subsequent serial control port operations are LSB first. Most of the serial port registers are buffered and data written into these buffered registers does not take effect immediately. An additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. This transfer is accomplished with an IO_UPDATE operation, which is performed in one of two ways. One method is to write a Logic 1 to Register 0x000F, Bit 0 (this bit is an autoclearing bit). The user can change as many register bits as desired before executing an IO_UPDATE. The IO_UPDATE operation transfers the buffer register contents to their active register counterparts. Address Ascension If the address ascension bits (Register 0x0000, Bit 2 and Bit 5) are zero, the serial control port register address decrements from the specified starting address toward Address 0x0000. If the address ascension bits (Register 0x0000, Bit 2 and Bit 5) are one, the serial control port register address increments from the starting address toward Address 0x1FFF. Reserved addresses are not skipped during multibyte input/output operations; therefore, write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. Read If the instruction word indicates a read operation, the next N x 8 SCLK cycles clock out the data starting from the address specified in the instruction word. N is the number of data bytes read. The readback data is driven to the pin on the falling edge and must be latched on the rising edge of SCLK. Blank registers are not skipped over during readback. Table 25. Streaming Mode (No Addresses Skipped) Address Ascension Increment Decrement Stop Sequence 0x0000...0x1FFF 0x1FFF...0x0000 Table 26. Serial Control Port, 16-Bit Instruction Word MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 CS SCLK DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 16-BIT INSTRUCTION HEADER A1 A0 D7 D6 D5 D4 D3 D2 D1 REGISTER (N) DATA D0 D7 D6 D5 Figure 40. Serial Control Port Write--MSB First, Address Decrement, Two Bytes of Data Rev. C | Page 36 of 67 D4 D3 D2 D1 D0 REGISTER (N - 1) DATA DON'T CARE 12380-036 SDIO DON'T CARE DON'T CARE Data Sheet AD9528 CS SCLK DON'T CARE DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 SDO DON'T CARE D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 REGISTER (N) DATA 16-BIT INSTRUCTION HEADER REGISTER (N - 1) DATA REGISTER (N - 2) DATA REGISTER (N - 3) DATA DON'T CARE 12380-037 SDIO Figure 41. Serial Control Port Read--MSB First, Address Decrement, Four Bytes of Data tDS tS tDH CS DON'T CARE SDIO DON'T CARE tC tCLK tLOW DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 12380-038 SCLK tHIGH Figure 42. Timing Diagram for Serial Control Port Write--MSB First CS SCLK DATA BIT N 12380-039 tDV SDIO SDO DATA BIT N - 1 Figure 43. Timing Diagram for Serial Control Port Register Read--MSB First CS SCLK DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 16-BIT INSTRUCTION HEADER D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D3 D4 D5 D6 D7 REGISTER (N + 1) DATA Figure 44. Serial Control Port Write--LSB First, Address Increment, Two Bytes of Data CS tS tC tCLK tHIGH tLOW tDS SCLK BIT N BIT N + 1 Figure 45. Serial Control Port Timing--Write Table 27. Serial Control Port Timing Parameter tDS tDH tCLK tS tC tHIGH tLOW tDV Description Setup time between data and the rising edge of SCLK Hold time between data and the rising edge of SCLK Period of the clock Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle) Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) Minimum period that SCLK is in a logic high state Minimum period that SCLK is in a logic low state SCLK to valid SDIO (see Figure 43) Rev. C | Page 37 of 67 12380-041 tDH SDIO DON'T CARE 12380-040 SDIO DON'T CARE DON'T CARE AD9528 Data Sheet Start/stop functionality is shown in Figure 47. The start condition is characterized by a high to low transition on the SDA line while SCL is high. The master always generates the start condition to initialize a data transfer. The stop condition is characterized by a low to high transition on the SDA line while SCL is high. The master always generates the stop condition to terminate a data transfer. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit; bytes are sent MSB first. I2C SERIAL PORT OPERATION The I2C interface is popular because it requires only two pins and easily supports multiple devices on the same bus. Its main disadvantage is programming speed, which is 400 kbps (maximum). The AD9528 I2C port design uses the I2C fast mode; however, it supports both the 100 kHz standard mode and 400 kHz fast mode. The AD9528 does not strictly adhere to every requirement in the original I2C specification. In particular, specifications such as slew rate limiting and glitch filtering are not implemented. Therefore, the AD9528 is I2C compatible, but may not be fully I2C compliant. The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. The AD9528 I2C port consists of a serial data line (SDA) and a serial clock line (SCL). In an I2C bus system, the AD9528 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device; that is, no clock is generated by the AD9528. The AD9528 uses direct 16-bit memory addressing instead of more common 8-bit memory addressing. The no acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. A no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte. After issuing a no acknowledge bit, the AD9528 I2C state machine goes into an idle state. The AD9528 allows up to three unique slave devices to occupy the I2C bus. These are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. Table 24 lists the supported device slave addresses. Data Transfer Process The master initiates data transfer by asserting a start condition, which indicates that a data stream follows. All I2C slave devices connected to the serial bus respond to the start condition. I2C Bus Characteristics A summary of the various I2C abbreviations appears in Table 28. The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write and 1 = read). 2 Table 28. I C Bus Abbreviation Definitions Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge No acknowledge Write Read The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1, the master (receiver) reads from the slave device (transmitter). The transfer of data is shown in Figure 46. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The format for these commands is described in the Data Transfer Format section. SDA DATA LINE STABLE; DATA VALID CHANGE OF DATA ALLOWED Figure 46. Valid Bit Transfer 12380-042 SCL Data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. This addressing scheme gives a memory address of up to 216 - 1 = 65,535. The data bytes after these two memory address bytes are register data written to the control registers. In read mode, the data bytes after the slave address byte are register data written to or read from the control registers. Rev. C | Page 38 of 67 Data Sheet AD9528 no acknowledge bit, the slave device knows that the data transfer is finished and enters idle mode. The master then pulls the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. When all the data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull SDA low during the ninth clock pulse. This is known as a no acknowledge bit. By receiving the A start condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. SDA SCL S START CONDITION 12380-043 P STOP CONDITION Figure 47. Start and Stop Conditions MSB ACK FROM SLAVE RECEIVER SCL 1 S 2 3 TO 7 8 ACK FROM SLAVE RECEIVER 9 1 2 3 TO 7 8 9 10 P 12380-044 SDA Figure 48. Acknowledge Bit MSB ACK FROM SLAVE RECEIVER SCL 1 2 3 TO 7 8 9 ACK FROM SLAVE RECEIVER 1 2 3 TO 7 8 9 S 10 P 12380-045 SDA Figure 49. Data Transfer Process (Master Write Mode, 2-Byte Transfer) SDA ACK FROM MASTER RECEIVER S 1 2 3 TO 7 8 9 1 2 3 TO 7 8 9 10 P Figure 50. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First ACK From Slave Rev. C | Page 39 of 67 12380-046 SCL NONACK FROM MASTER RECEIVER AD9528 Data Sheet Data Transfer Format The write byte format is used to write a register address to the RAM starting from the specified RAM address (see Table 29). Table 29. Data Transfer Format, Write Byte Format S Slave address A W RAM address high byte A RAM address low byte A RAM Data 0 A RAM Data 1 A RAM Data 2 A P The send byte format is used to set up the register address for subsequent reads (see Table 30). Table 30. Data Transfer Format, Send Byte Format S Slave address W A RAM address high byte A RAM address low byte A P A P The receive byte format is used to read the data byte(s) from RAM starting from the current address (see Table 31). Table 31. Data Transfer Format, Receive Byte Format S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 The read byte format is the combined format of the send byte and the receive byte (see Table 32). Table 32. Data Transfer Format, Read Byte Format S Slave address W A RAM address high byte A RAM address low byte A Sr Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 A I2C Serial Port Timing SDA tLOW tF tSU; DAT tR tHD; STA tF tSP tBUF tR tHD; STA S tHD; DAT tHIGH tSU; STO tSU; STA Sr 2 Figure 51. I C Serial Port Timing Table 33. I2C Timing Definitions Parameter fSCL tBUF tHD; STA tSU; STA tSU; STO tHD; DAT tSU; DAT tLOW tHIGH tR tF tSP Description Serial clock Bus free time between stop and start conditions Repeated hold time start condition Repeated start condition setup time Stop condition setup time Data hold time Data setup time SCL clock low period SCL clock high period Minimum/maximum receive SCL and SDA rise time Minimum/maximum receive SCL and SDA fall time Pulse width of voltage spikes that must be suppressed by the input filter Rev. C | Page 40 of 67 P S 12380-047 SCL P Data Sheet AD9528 DEVICE INITIALIZATION AND CALIBRATION FLOWCHARTS The flowcharts in this section show a typical AD9528 initialization routine using an evaluation software generated setup file (.stp), and calibration routines designed for robust system startup. Figure 52, Figure 53, Figure 54, and Figure 55 assume the following: dual loop configuration, VCXO with a 100 ppm pull range, and a valid frequency translation from a .stp file. These flowcharts are provided as recommendations. The count variable for the chip level reset loop (RST_COUNT) and the count variable for the PLL2 recalibration loop (CAL_COUNT) are count variables used to establish a count limit to a loop, such that it is not an infinite loop. These variables only apply to initialization. Rev. C | Page 41 of 67 AD9528 Data Sheet START USER POWER SUPPLIES INITIALIZATION AND POWER-ON RESET WAIT APPLY VDD (ALL DOMAINS) VDD SETTLED? NO YES POR: WAIT 60ms APPLY REFERENCE INPUT (s) CHIP LEVEL RESET LOOP RST_COUNT = RST_COUNT + 1 RST_COUNT = 0 ISSUE A PIN LEVEL RESET SUB-PROCESS: WRITE REGISTERS FROM SETUP FILE WRITE: REGISTER 0x00F = 0x01 PLL2 RECALIBRATION LOOP CAL_COUNT = 0 SUB-PROCESS: ISSUE VCO CALIBRATION NO NO CAL_COUNT > 1 CAL_COUNT = CAL_COUNT + 1 START TIMEOUT CLOCK: TIME = 0 YES RST_COUNT > 0 YES RAISE FLAG FOR DEBUGGING! READ: R0x508 -R0x509 PLL2 LOCK DETECT POLLING LOOP NO REGISTER 0x508[1] = 1 NO YES TIMEOUT CLOCK: TIME > PLL_TO1 YES START TIMEOUT CLOCK: TIME = 0 PLL1 LOCK DETECT POLLING LOOP NO REGISTER 0x508[1] = 1 NO TIMEOUT CLOCK: YES TIME > PLL_TO2 YES 1PLL1_TO 2PLL2_TO IS A CALCULATED VALUE TIME OUT VALUE. PLEASE SEE THEORY OF OPERATION-COMPONENT BLOCKS-PLL1 FOR ITS FORMULA. IS A CALCULATED VALUE TIME OUT VALUE. PLEASE SEE THEORY OF OPERATION-COMPONENT BLOCKS-PLL2 FOR ITS FORMULA. Figure 52. Main Process, Initialization Rev. C | Page 42 of 67 12380-150 END Data Sheet AD9528 M1 x N2 [15] START ISSUE VCO CALIBRATION WRITE: COMMAND REGISTER 0x203[0] = 0 WRITE: REGISTER 0x0F = 0x01 WRITE: REGISTER 0x203[0] = 1 WRITE: REGISTER 0x0F = 0x01 NOTES 1. THIS ROUTINE ASSUMES THAT THE CALIBRATION DIVIDER VALUE IS SET TO A VALUE THAT IS EQUAL TO TWICE THE PRODUCT OF THE M1 AND N2 DIVIDE VALUES. THIS IS DONE AUTOMATICALLY BY THE AD9528 EVALUATION SOFTWARE WHEN THE PRODUCT OF M1 x N2 15. Figure 53. Subprocess, Issue VCO Calibration (M1 x N2 15) Rev. C | Page 43 of 67 12380-151 END AD9528 Data Sheet M1 x N2 [15] START CREATE LOCAL VARIABLES TO RESTORE NORMAL OPERATING STATE AFTER CALIBRATION READ: PTH_EN = REGISTER 0x202[5] READ: R_DIV = REGISTER 0x207 R_DIV = 0X00 NO HALVE PLL2 PFD RATE YES WRITE: REGISTER 0x207 = 0x02 WRITE: REGISTER 0x207 = R_DIV x 2 WRITE: REGISTER 0x202[5] = 1 WRITE: REGISTER 0x0F = 0x01 ISSUE VCO CALIBRATION WRITE: COMMAND REGISTER 0x203[0] = 0 WRITE: REGISTER 0x0F = 0x01 WRITE: REGISTER 0x203[0] = 1 WRITE: REGISTER 0x0F = 0x01 PLL2 CALIBRATION COMPLETE POLLING LOOP START TIMEOUT CLOCK: TIME = 0 NO REGISTER 0x509[0] = 0 NO TIMEOUT CLOCK: TIME > 100ms YES RAISE FLAG FOR DEBUGGING YES WRITE: REGISTER 0x207 = R_DIV USE LOCAL VARIABLES TO RESTORE PLL2 NORMAL OPERATING PFD RATE WRITE: REGISTER 0x202[5] = PTH_EN WRITE: REGISTER 0x0F = 0x01 NOTES 1. THIS ROUTINE ASSUMES THAT THE CALIBRATION DIVIDER VALUE IS SET TO A VALUE THAT IS EQUAL TO TWICE THE PRODUCT OF THE M1 AND N2 DIVIDE VALUES. THIS IS DONE AUTOMATICALLY BY THE AD9528 EVALUATION SOFTWARE WHEN THE PRODUCT OF M1 x N2 = 15. Figure 54. Subprocess, Issue VCO Calibration (M1 x N2 = 15) Rev. C | Page 44 of 67 12380-251 END Data Sheet AD9528 SOFTWARE GENERATED AD9528 SETUP FILE START WRITE: REGISTER 0x000 TO REGISTER 0x001 WRITE: REGISTER 0x100 TO REGISTER 0x10C WRITE: REGISTER 0x200 TO REGISTER 0x209 WRITE: REGISTER 0x300 TO REGISTER 0x32E WRITE: REGISTER 0x400 TO REGISTER 0x404 END Figure 55. Subprocess, Write Registers from the Setup File Rev. C | Page 45 of 67 12380-152 WRITE: REGISTER 0x500 TO REGISTER 0x504 AD9528 Data Sheet POWER DISSIPATION AND THERMAL CONSIDERATIONS The AD9528 is a multifunctional, high speed device that targets a wide variety of clock applications. The numerous innovative features contained in the device each consume incremental power. If all outputs are enabled in the maximum frequency and mode that have the highest power, the safe thermal operating conditions of the device may be exceeded. Careful analysis and consideration of power dissipation and thermal management are critical elements in the successful application of the AD9528. The AD9528 is specified to operate within the industrial temperature range of -40C to +85C. This specification is conditional, such that the absolute maximum junction temperature is not exceeded (as specified in Table 19). At high operating temperatures, extreme care must be taken when operating the device to avoid exceeding the junction temperature and potentially damaging the device. PLOAD = Differential Output Voltage Swing 2 100 The first step in evaluating the operating conditions is to determine the maximum power consumption (PD) internal to the AD9528. The maximum PD excludes power dissipated in the load resistors of the drivers because such power is external to the device. Use the power dissipation specifications listed in Table 3 to calculate the total power dissipated for the desired configuration. Selected driver mode of operation Output clock speed Supply voltage Ambient temperature The combination of these variables determines the junction temperature within the AD9528 for a given set of operating conditions. The AD9528 is specified for an ambient temperature (TA). To ensure that TA is not exceeded, use an airflow source. Use the following equation to determine the junction temperature on the application PCB: TJ = TCASE + (JT x PD) where: TJ is the junction temperature (C). TCASE is the case temperature (C) measured at the top center of the package. JT is the value from Table 20. PD is the power dissipation of the AD9528. Values of JA are provided for package comparison and PCB design considerations. JA can be used for a first order approximation of TJ by the equation Table 34 and Table 35 summarize the incremental power dissipation from the base power configuration for two different examples. Table 34. Temperature Gradient Examples, Example 1 Description Base Typical Configuration Output Driver Output Driver Output Driver Total Power 1 Mode N/A1 Frequency (MHz) N/A1 Maximum Power (mW) 590 6 x HSTL 3 x LVDS 1 x LVDS 122.88 122.88 409.6 480 210 78 1358 N/A means not applicable. Table 35. Temperature Gradient Examples, Example 2 TJ = TA + (JA x PD) where TA is the ambient temperature (C). Values of JC are provided for package comparison and PCB design considerations when an external heat sink is required. Values of JB are provided for package comparison and PCB design considerations. Clock speed directly and linearly influences the total power dissipation of the device and, therefore, the junction temperature. Two operating frequencies are listed under the incremental power dissipation parameter in Table 3. Using linear interpretation is a sufficient approximation for frequency not listed in the table. When calculating power dissipation for thermal consideration, remove the amount of power dissipated in the 100 resistor. If using the data in Table 3, this power is already removed. If using the current vs. frequency graphs provided in the Typical Performance Characteristics section, the power into the load must be subtracted, using the following equation: EVALUATION OF OPERATING CONDITIONS Many variables contribute to the operating junction temperature within the device, including * * * * CLOCK SPEED AND DRIVER MODE Description Base Typical Configuration Output Driver Total Power 1 Mode N/A1 Frequency (MHz) N/A1 Maximum Power (mW) 590 13 x HSTL 122.88 1040 1630 N/A means not applicable. Rev. C | Page 46 of 67 Data Sheet AD9528 The second step in evaluating the operating conditions is to multiply the power dissipated by the thermal impedance to determine the maximum power gradient. For this example, a thermal impedance of JA = 21.1C/W was used. Example 1 THERMALLY ENHANCED PACKAGE MOUNTING GUIDELINES See the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), for more information about mounting devices with an exposed paddle. (1358 mW x 21.1C/W) = 29C With an ambient temperature of 85C, the junction temperature is TJ = 85C + 29C = 114C This junction temperature is below the maximum allowable. Example 2 (1630 mW x 21.1C/W) = 34C With an ambient temperature of 85C, the junction temperature is TJ = 85C + 34C = 119C This junction temperature is greater than the maximum allowable. The ambient temperature must be lowered by 4C to operate in the condition of Example 2. Rev. C | Page 47 of 67 AD9528 Data Sheet CONTROL REGISTER MAP Table 36. Register Summary Addr (Hex) Register Name Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) Soft reset1 LSB first (SPI only)2 Address ascension (SPI only)3 SDO active (SPI only)4 SDO active (SPI only)4 Address ascension (SPI only)3 LSB first (SPI only)2 Soft reset1 0x00 Serial Port Configuration 0x0000 SPI Configuration A 0x0001 SPI Configuration B 0x0002 Reserved Reserved Read buffer register Reserved Reset sans regmap Reserved Reserved 0x00 0x00 Clock Part Family ID 0x0003 Chip type Reserved Chip type, Bits[3:0] 0x05 0x0004 Product ID Clock part serial ID, Bits[3:0] Reserved 0xFF 0x0005 Clock part serial ID, Bits[11:4] 0x00 0x0006 Revision Part versions, Bits[7:0] 0x03 0x0007 Reserved Reserved 0x00 0x0008 Reserved Reserved 0x00 0x0009 Reserved Reserved 0x00 0x000A Reserved Reserved 0x00 0x000B SPI version SPI version, Bits[7:0] 0x00 0x000C Vendor ID Vendor ID, Bits[7:0] 0x56 0x000D 0x000E Reserved 0x000F IO_UPDATE Vendor ID, Bits[15:8] 0x04 Reserved 0x00 Reserved IO_UPDATE 0x00 PLL1 Control 0x0100 PLL1 REFA (RA) divider 10-bit REFA (RA) divider, Bits[7:0] 0x0101 0x0102 PLL1 REFB (RB) divider 0x0105 0x0106 0x0107 0x0108 PLL1 feedback divider (N1) Force holdover PLL1 input receiver control Frequency detector power-down enable 0x00 10 bit N1 divider, Bits[9:8] 0x00 0x00 PLL1 charge pump current (A), Bits[6:0] Reserved REFB differential receiver enable Reserved 0x010A Disable holdover Reserved REFA differential receiver enable REFB input REFA input receiver enable receiver enable N1 feedback divider reset REFB divider (RB) reset Reserved PLL1 fast lock 10-bit REFB (RB) divider, Bits[9:8] 10-bit N1 divider [7:0] Reserved PLL1 charge pump control Fast lock enable REFA divider (RA) reset Holdover mode 0x0C Charge pump mode, Bits[1:0] 0x00 VCXO receiver VCXO singlepower-down ended negative pin enable enable CMOS mode VCXO differential receiver enable PLL1 feedback REFB singledivider source ended negative pin enable (CMOS mode) REFA single- 0x00 ended negative pin enable (CMOS mode) Reference selection mode, Bits[2:0] Fast lock charge pump current (A), Bits[6:0] Rev. C | Page 48 of 67 0x00 0x00 Reserved 0x0109 0x010B 10-bit REFA (RA) divider, Bits[9:8] 10-bit REFB (RB) divider, Bits[7:0] 0x0103 0x0104 0x00 Reserved 0x00 0x00 0x00 Data Sheet Addr (Hex) Register Name AD9528 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB) Default Value (Hex) PLL2 Control 0x0200 PLL2 charge pump control 0x0201 PLL2 VCO CAL feedback dividers 0x0202 PLL2 control 0x0203 PLL2 VCO control 0x0204 PLL2 RF VCO divider (M1) 0x0205 PLL2 loop filter control 0x0206 0x0207 PLL2 input divider (R1) 0x0208 PLL2 feedback divider (N2) 0x0209 PLL2 CP current (A), Bits[7:0] A divider, Bits[1:0] Lock detect power-down enable Reserved B divider, Bits[5:0] Frequency doubler enable Reserved Reserved 0x00 Reserved Doubler and R1 Reset VCO divider path calibration enable dividers PFD reference PFD feedback edge select edge select RPOLE2 (), Bits[1:0] 0x04 PLL2 charge pump mode, Bits[1:0] Treat reference as valid RF VCO divider (M1) power-down Force VCO to midpoint frequency 0x00 CPOLE1 (pF), Bits[1:0] 0x00 RZERO (), Bits[1:0] Bypass internal 0x00 RZERO resistor Reserved 5-bit R1 divider, Bits[4:0] 8-bit N2 divider, Bits[7:0] N2 divider power-down Manual VCO 0x00 calibrate (not autoclearing) RF VCO divider (M1), Bits[2:0] Reserved Reserved 0x03 0x00 0x00 N2 phase, Bits[5:0] 0x00 Clock Distribution Control 0x0300 Channel Output 0 0x0301 Channel control, Bits[2:0] Output format, Bits[1:0] 0x0302 0x0303 Channel Output 1 Channel control, Bits[2:0] Channel Output 2 Channel Control, Bits[2:0] Channel Output 3 Channel control, Bits[2:0] Channel control, Bits[2:0] Fine analog delay, Bits[3:0] Coarse digital delay, Bits[5:0] Fine analog delay enable Output format, Bits[1:0] 0x030E 0x0310 Channel control, Bits[2:0] Coarse digital delay, Bits[5:0] Fine analog delay enable Output format, Bits[1:0] 0x0311 Channel control, Bits[2:0] Fine analog delay, Bits[3:0] Coarse digital delay, Bits[5:0] Fine analog delay enable Output format, Bits[1:0] Coarse digital delay, Bits[5:0] Rev. C | Page 49 of 67 0x00 0x40 0x00 0x00 0x00 0x40 0x00 0x00 Fine analog delay, Bits[3:0] Divide ratio, Bits[7:0] 0x00 0x04 Divide ratio, Bits[7:0] Channel Output 6 0x00 0x00 Fine analog delay, Bits[3:0] Divide ratio, Bits[7:0] Channel Output 5 0x40 0x04 Divide ratio [7:0] Channel Output 4 0x030D 0x0314 Coarse digital delay [5:0] Output format, Bits[1:0] 0x030B 0x0313 Fine analog delay, Bits[3:0] Fine analog delay enable 0x00 0x00 Divide ratio [7:0] 0x030A 0x0312 Fine analog delay enable 0x00 0x04 Fine analog delay, Bits[3:0] Coarse digital delay, Bits[5:0] Output format, Bits[1:0] 0x0308 0x030F Fine analog delay enable Divide ratio, Bits[7:0] 0x0307 0x030C Coarse digital delay, Bits[5:0] Output format, Bits[1:0] 0x0305 0x0309 Fine analog delay, Bits[3:0] Divide ratio, Bits[7:0] 0x0304 0x0306 Fine analog delay enable 0x00 0x00 0x04 AD9528 Addr (Hex) Register Name 0x0315 Channel Output 7 0x0316 Data Sheet Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Channel control, Bits[2:0] Output format, Bits[1:0] Channel Output 8 Channel control, Bits[2:0] Output format, Bits[1:0] Channel Output 9 Channel control, Bits[2:0] Fine analog delay, Bits[3:0] 0x00 0x00 0x04 Fine analog delay enable Output format, Bits[1:0] Fine analog delay, Bits[3:0] 0x40 Coarse digital delay, Bits[5:0] 0x00 Divide ratio, Bits[7:0] Channel Output 10 0x031F Channel control, Bits[2:0] 0x00 Fine analog delay enable Output format, Bits[1:0] Fine analog delay, Bits[3:0] 0x00 Coarse digital delay, Bits[5:0] 0x0320 0x00 Divide ratio, Bits[7:0] Channel Output 11 0x0322 Channel control, Bits[2:0] 0x04 Fine analog delay enable Output format, Bits[1:0] Fine analog delay, Bits[3:0] 0x40 Coarse digital delay, Bits[5:0] 0x0323 0x00 Divide ratio [7:0] Channel Output 12 0x0325 Channel control, Bits[2:0] 0x00 Fine analog delay enable Output format, Bits[1:0] Fine analog delay, Bits[3:0] 0x20 Coarse digital delay, Bits[5:0] 0x0326 0x0327 0x00 Coarse digital delay, Bits[5:0] 0x031D 0x0324 0x40 Divide ratio, Bits[7:0] 0x031C 0x0321 Bit 0 (LSB) 0x00 Fine analog delay enable 0x031A 0x031E Bit 1 Fine analog delay, Bits[3:0] Divide ratio, Bits[7:0] 0x0319 0x031B Bit 2 Coarse digital delay, Bits[5:0] 0x0317 0x0318 Bit 3 Fine analog delay enable 0x00 Divide ratio, Bits[7:0] Channel Output 13 0x0328 Channel control, Bits[2:0] 0x00 Fine analog delay enable Output format, Bits[1:0] Fine analog delay, Bits[3:0] 0x20 Coarse digital delay, Bits[5:0] 0x0329 Default Value (Hex) 0x00 Divide ratio, Bits[7:0] 0x00 Sync Control 0x032A Distribution sync 0x032B Ignore sync enable 0x032C 0x032D SYSREF Bypass resample control 0x032E Reserved Sync outputs 0x00 Channel 7 ignore sync Channel 6 ignore sync Channel 5 ignore sync Channel 4 ignore sync Channel 3 ignore sync Channel 2 ignore sync Channel 1 ignore sync Channel 0 ignore sync 0x00 Reserved PLL2 feedback Channel 13 N2 divider ignore sync ignore sync Channel 12 ignore sync Channel 11 ignore sync Channel 10 ignore sync Channel 9 ignore sync Channel 8 ignore sync 0x00 Channel 6 Channel 5 Channel 4 Channel 3 Channel 2 Channel 1 Channel 0 Enable VCXO 0x00 bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF receiver path resample resample resample resample resample resample resample to distribution Reserved Channel 13 Channel 12 Channel 11 Channel 10 Channel 9 Channel 8 Channel 7 0x00 bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF bypass SYSREF resample resample resample resample resample resample resample SYSREF Control 0x0400 0x0401 0x0402 SYSREF pattern generator K divider SYSREF control 0x0403 0x0404 K divider, Bits[7:0] K divider, Bits[15:8] SYSREF request method SYSREF pattern generator trigger control, Bits[1:0] SYSREF source, Bits[1:0] SYSREF_IN receiver control 0x00 0x00 SYSREF pattern Resample generator clock source for external clock source SYSREF SYSREF pattern generator mode, Bits[1:0] Reserved Rev. C | Page 50 of 67 SYSREF test mode, Bits[1:0] N-shot mode, Bits[2:0] SYSREF IN receiver power-down Single-ended source negative input (CMOS mode) SYSREF reset 0x00 SPI SYSREF request 0x00 SYSREF differential receiver enable 0x04 Data Sheet Addr (Hex) Register Name AD9528 Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Default Value (Hex) Bit 2 Bit 1 Bit 0 (LSB) Bias generation PLL2 powerpower-down down enable disable or power-down PLL1 powerdown enable Clock distribution power-down enable Chip powerdown enable 0x10 Channel 5 power-down Channel 4 power-down Channel 3 power-down Channel 2 power-down Channel 1 power-down Channel 0 power-down 0x00 Channel 13 power-down Channel 12 power-down Channel 11 power-down Channel 10 power-down Channel 9 power-down Channel 8 power-down 0x00 Channel 6 LDO enable Channel 5 LDO enable Channel 4 LDO Channel 3 enable LDO enable Channel 2 LDO enable Channel 1 LDO enable Channel 0 LDO enable 0xFF PLL1 LDO enable Channel 13 LDO enable Channel 12 LDO enable Channel 10 LDO enable Channel 9 LDO enable Channel 8 LDO enable 0xFF Power-Down Control 0x0500 Power-down control enable 0x0501 Output channel power down enable Reserved Channel 7 power-down 0x0502 0x0503 Channel 6 power-down Reserved LDO regulator enable Channel 7 LDO enable 0x0504 PLL2 LDO enable Channel 11 LDO enable Status and Status Readback5 0x0505 Status control signals 0x0506 0x0507 Status pin enable and status divider enable 0x0508 Status Readback 0 0x0509 Status Readback 1 Status Monitor 0 Control, Bits[7:0] 0x00 Status Monitor 1 Control, Bits[7:0] 0x00 Reserved STATUS1 pin STATUS0 pin STATUS0 STATUS1 0x00 output enable output enable divider enable divider enable PLL2 feedback PLL1 feedback VCXO status status status Both REFA/REFB missing Reserved 1 REFB status REFA status PLL2 locked status PLL1 locked status 0x00 Holdover active status Selected reference Fast lock in progress VCO calibration busy status 0x00 The soft reset bits (Bit 0 and Bit 7) are logically AND gated internally; therefore, set or clear both bits together. The LSB first bits (Bit 1 and Bit 6) are logically AND gated internally; therefore, set or clear both bits together. 3 The address ascension bits (Bit 2 and Bit 5) are logically AND gated internally; therefore, set or clear both bits together. 4 The SDO active bits (Bit 3 and Bit 4) are logically AND gated internally; therefore, set or clear both bits together. 5 Register 0x0505, Register 0x0506, and Register 0x0507 are control status pins as notated by bit names 0x0505 (Status 0) and 0x0506 (Status 1). Register 0x0508 and Register 0x0509 are for readback via SPI/I2C. 2 Rev. C | Page 51 of 67 AD9528 Data Sheet CONTROL REGISTER MAP BIT DESCRIPTIONS SERIAL CONTROL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0001) Table 37. SPI Configuration A (Register 0x0000) Bits 7 6 Bit Name Soft reset (SPI only) LSB first (SPI only) 5 Address ascension (SPI only) 4 SDO active (SPI only) [3:0] Description Device reset. Bit order for SPI port. This bit has no effect in I2C mode. 1 = least significant bit first. 0 (default) = most significant bit first. This bit controls whether the register address is automatically incremented during a multibyte transfer. This bit has no effect in I2C mode. 1 = register addresses are automatically incremented in multibyte transfers. 0 (default) = register addresses are automatically decremented in multibyte transfers. Enables SPI port SDO pin. This bit has no effect in I2C mode. 1 = 4-wire mode (SDO pin enabled). 0 (default) = 3-wire mode. These bits are mirrors of Bits[7:4] of this register. However, each pair of the following corresponding bits are logically AND gated internally; therefore, set the bits to Logic 1 or Logic 0 together. Bit 3 corresponds to Bit 4. Bit 2 corresponds to Bit 5. Bit 1 corresponds to Bit 6. Bit 0 corresponds to Bit 7. Table 38. SPI Configuration B (Register 0x0001) Bits [7:6] 5 Bit Name Reserved Read buffer register [4:3] 2 Reserved Reset sans regmap [1:0] Reserved Description Reserved. For buffered registers, this bit controls whether the value read from the serial port is from the actual (active) registers or the buffered copy. 1 = reads buffered values that take effect on the next assertion of IO_UPDATE. 0 (default) = reads values currently applied to the internal logic of the device. Reserved. This bit resets the device while maintaining the current register settings. 1 = resets the device. 0 (default) = no action. Reserved. Rev. C | Page 52 of 67 Data Sheet AD9528 CLOCK PART FAMILY ID (REGISTER 0x0003 TO REGISTER 0x0006) Table 39. Clock Part Family ID Address 0x0003 Bits [7:4] [3:0] Bit Name Reserved Chip type, Bits[3:0] 0x0004 [7:4] Clock part serial ID, Bits[3:0] 0x0005 [3:0] [7:0] Reserved Clock part serial ID, Bits[11:4] 0x0006 [7:0] Part versions, Bits[7:0] Description Reserved. The Analog Devices unified SPI protocol reserves this read only register location for identifying the type of device. The default value of 0x05 identifies the AD9528 as a clock IC. The Analog Devices unified SPI protocol reserves this read only register location as the lower four bits of the clock part serial ID that, along with Register 0x0005, uniquely identifies the AD9528 within the Analog Devices clock chip family. No other Analog Devices chip that adheres to the Analog Devices unified SPI has these values for Register 0x0003, Register 0x0004, and Register 0x0005. The clock part serial ID is 0x00F; for these four bits it is 0xF. Default = 0xF. The Analog Devices unified SPI protocol reserves this read only register location as the upper eight bits of the clock part serial ID that, along with Register 0x0004, uniquely identifies the AD9528 within the Analog Devices clock chip family. No other Analog Devices chip that adheres to the Analog Devices unified SPI has these values for Register 0x0003, Register 0x0004, and Register 0x0005. Default: 0x00. The Analog Devices unified SPI protocol reserves this read only register location for identifying the die revision. Default = 0x03. SPI VERSION (REGISTER 0x000B) Table 40. SPI Version Bits [7:0] Bit Name SPI version, Bits[7:0] Description The Analog Devices unified SPI protocol reserves this read only register location for identifying the version of the unified SPI protocol. Default = 0x00. VENDOR ID (REGISTER 0x000C TO REGISTER 0x000D) Table 41. Vendor ID Address 0x000C Bits [7:0] Bit Name Vendor ID, Bits[7:0] 0x000D [7:0] Vendor ID, Bits[15:8] Description The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this device. All Analog Devices devices adhering to the unified serial port specification have the same value in this register. Default = 0x56. The Analog Devices unified SPI protocol reserves this read only register location for identifying Analog Devices as the chip vendor of this device. All Analog Devices devices adhering to the unified serial port specification have the same value in this register. Default = 0x04. IO_UPDATE (REGISTER 0x000F) Table 42. IO_UPDATE Bits [7:1] 0 Bit Name Reserved IO_UPDATE Description Reserved. Default = 0000000b. Writing a 1 to this bit transfers the data in the serial input/output buffer registers to the internal control registers of the device. This is an autoclearing bit. Rev. C | Page 53 of 67 AD9528 Data Sheet PLL1 CONTROL (REGISTER 0x0100 TO REGISTER 0x010B) Table 43. PLL1 REFA Divider (RA) and REFB Divider (RB) Control Address 0x0100 Bits [7:0] Bit Name 10-bit REFA (RA) divider 0x0101 0x0102 [1:0] [7:0] 10-bit REFB (RB) divider 0x0103 [1:0] Description 10-bit REFA divider, Bits[7:0] (LSB). Divide by 1 to divide by 1023. 0000000000, 0000000001 = divide by 1. 10-bit REFA divider, Bits[9:8] (MSB). 10-bit REFB divider, Bits[7:0] (LSB). Divide by 1 to divide by 1023. 0000000000, 0000000001 = divide by 1. 10-bit REFB divider, Bits[9:8] (MSB). Table 44. PLL1 Feedback Divider (N1) Address 0x0104 Bits [7:0] 0x0105 [1:0] Bit Name 10-bit N1 divider Description 10-bit feedback divider, Bits[7:0] (LSB). Divide by 1 to divide by 1023. 0000000000, 0000000001 = divide by 1. 10-bit feedback divider, Bits[9:8] (MSB). Table 45. PLL1 Charge Pump Control Address 0x0106 0x0107 Bits 7 Bit Name Force holdover [6:0] [7:6] 5 PLL1 charge pump current (A), Bits[6:0] Reserved Disable holdover [4:2] [1:0] Reserved Charge pump mode, Bits[1:0] Description Tristates the PLL1 charge pump. 0 = normal operation. 1 = forces holdover. These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 A with a full-scale magnitude of ~63.5 A. Reserved. Disable automatic holdover. 0 = automatic holdover enabled. 1 = automatic holdover disabled. Reserved. Controls the mode of the PLL1 charge pump. 00 = tristate (default). 01 = pump down. 10 = pump up. 11 = normal. Rev. C | Page 54 of 67 Data Sheet AD9528 Table 46. PLL1 Input Receiver Control Address 0x0108 0x0109 Bits 7 Bit Name Frequency detector power-down enable 6 REFB differential receiver enable 5 REFA differential receiver enable 4 REFB input receiver enable 3 REFA input receiver enable 2 VCXO receiver power-down enable 1 VCXO single-ended receiver mode enable CMOS mode 0 VCXO differential receiver enable [7:6] 5 Reserved N1 feedback divider reset 4 REFB divider (RB) reset 3 REFA divider (RA) reset 2 PLL1 Feedback Divider Source 1 REFB single-ended negative pin enable (CMOS mode) 0 REFA single-ended negative pin mode enable (CMOS mode) Description 1 = enabled. 0 = disabled (default). 1 = differential receiver mode. 0 = single-ended receiver mode (also depends on Register 0x0109, Bit 1) (default). 1 = differential receiver mode. 0 = single-ended receiver mode (also depends on Register 0x0109, Bit 0) (default). REFB receiver power-down control mode. 1 = enable REFB receiver. 0 = power-down (default). REFA receiver power-down control mode. 1 = enable REFA receiver. 0 = power-down (default). Enables control over power-down of the VCXO receivers. 1 = power-down control enabled. 0 = both receivers enabled (default). Selects which single-ended input pin is enabled when in the single-ended receiver mode (Register 0x0108, Bit 0 = 0). 1 = negative receiver from VCXO input (VCXO_IN pin) selected. 0 = positive receiver from VCXO input (VCXO_IN pin) selected (default). 1 = differential receiver mode. 0 = single-ended receiver mode (default). Reserved. Puts divider in reset. 1 = Divider held in reset. 0 = divider normal operation. Puts divider in reset. 1 = Divider held in reset. 0 = divider normal operation. Puts divider in reset. 1 = Divider held in reset. 0 = divider normal operation. Selects the input source to the PLL1 feedback divider. 1 = selects VCXO as the input to the PLL1 feedback divider. 0 = selects the PLL2 feedback divider output as the input to the PLL1 feedback divider. Selects which single-ended input pin is enabled when in single-ended receiver mode (also depends on Register 0x0108, Bit 6 = 0). 1 = REFB pin enabled. 0 = REFB pin enabled. Selects which single-ended input pin is enabled when in single-ended receiver mode (also depends on Register 0x0108, Bit 5 = 0). 1 = REFA pin enabled. 0 = REFA pin enabled. Rev. C | Page 55 of 67 AD9528 Address 0x010A Bits [7:4] 3 [2:0] 1 Data Sheet Bit Name Reserved Holdover mode Description Reserved. High permits the VCXO_CTRL control voltage to be forced to midsupply when the feedback or input clocks fail. Low tristates the charge pump output. 1 = VCXO_CTRL control voltage goes to VCC/2. Reference selection mode, Bits[2:0] 0 = VCXO_CTRL control voltage tracks the tristated (high impedance) charge pump (through the buffer). Programs the REFA, REFB mode selection (default = 000). REF_SEL Pin Bit 2 Bit 1 Bit 0 Description X1 0 0 0 Nonrevertive: stay on REFB. X1 0 0 1 Revert to REFA. X1 0 1 0 Select REFA. X1 0 1 1 Select REFB. 0 1 X1 X1 REF_SEL pin = 0 (low): REFA. 1 1 1 1 X X REF_SEL pin = 1 (high): REFB. X means don't care. Table 47. PLL Fast Lock (Register 0x010B) Bits 7 [6:0] Bit Name PLL1 fast lock enable Fast lock charge pump current (A), Bits[6:0] Description Enables PLL1 fast lock operation. These bits set the magnitude of the PLL1 charge pump current. Granularity is ~0.5 A with a full-scale magnitude of ~63.5 A. PLL2 (REGISTER 0x0200 TO REGISTER 0x0209) Table 48. PLL2 Charge Pump Control (Register 0x0200) Bits [7:0] Bit Name PLL2 CP current (A), Bits[7:0] Description These bits set the magnitude of the PLL2 charge pump current. Granularity is ~3.5 A with a full-scale magnitude of ~900 A. Table 49. PLL2 Feedback VCO CAL Divider Control (Register 0x0201) Bits [7:6] [5:0] Bit Name A divider, Bits[1:0] B divider, Bits[5:0] A Divider (Bits[7:6]) A=0 A = 0 or A = 1 A = 0 to A = 2 A = 0 to A = 2 A = 0 to A = 3 Description A divider word B divider word Feedback Divider Constraints B Divider (Bits[5:0]) B=3 B=4 B=5 B=6 B7 Allowed N Division (4 x B + A) N = 16 to 255 Table 50. PLL2 Control (Register 0x0202) Bits 7 Bit Name Lock detect power-down enable 6 5 Reserved Frequency doubler enable Description Controls power-down of the PLL2 lock detector. 1 = lock detector powered down. 0 = lock detector active. Default = 0; value must remain 0. Enables doubling of the PLL2 reference input frequency. 1 = enabled. 0 = disabled. Rev. C | Page 56 of 67 Data Sheet Bits [4:2] [1:0] AD9528 Bit Name Reserved PLL2 charge pump mode Description Reserved Controls the mode of the PLL2 charge pump. 00 = tristate. 01 = pump down. 10 = pump up. 11 (default) = normal. Table 51. PLL2 VCO Control (Register 0x0203) Bits [7:5] 4 Bit Name Reserved Doubler and R1 divider path enable 3 Reset VCO calibration dividers 2 Treat reference as valid 1 Force VCO to midpoint frequency 0 Manual VCO calibrate (not autoclearing) Description Reserved. 0 (default) = bypasses doubler and R1 divider path to PLL2 frequency detector. 1 = enables doubler and R1 divider path. 0 (default) = normal operation. 1 = resets A and B dividers. 0 (default) = uses the PLL1 VCXO indicator to determine when the reference clock to the PLL2 is valid. 1 = treats the reference clock as valid even if PLL1 does not consider it to be valid. Selects VCO control voltage functionality. 0 (default) = normal VCO operation. 1 = forces VCO control voltage to midscale. 1 = initiates VCO calibration (this is not an autoclearing bit). 0 = resets the VCO calibration. Table 52. PLL2 RF VCO Divider (M1) (Register 0x0204) Bits [7:6] 5 Bit Name Reserved PFD reference edge select 4 PFD feedback edge select 3 RF VCO divider (M1) power-down [2:0] RF VCO divider (M1), Bits[2:0] Description Reserved. 1 = falling edge. 0 = rising edge. 1 = falling edge. 0 = rising edge. 1 = powers down the M1 divider. 0 = normal operation. Bit 2 Bit 1 Bit 0 Divider Value 0 1 1 Divide by 3. 1 0 0 Divide by 4. 1 0 1 Divide by 5. Rev. C | Page 57 of 67 AD9528 Data Sheet Table 53. PLL2 Loop Filter Control Address 0x0205 0x0206 Bits [7:6] Bit Name RPOLE2 (), Bits[1:0] [5:3] RZERO (), Bits[1:0] [2:0] CPOLE1 (pF), Bits[1:0] [7:1] 0 Reserved Bypass internal RZERO resistor Description Bit 7 Bit 6 RPOLE2 () 0 0 900 0 1 450 1 0 300 1 1 225 Bit 5 Bit 4 Bit 3 RZERO () 0 0 0 3250 0 0 1 2750 0 1 0 2250 0 1 1 2100 1 0 0 3000 1 0 1 2500 1 1 0 2000 1 1 1 1850 Bit 2 Bit 1 Bit 0 CPOLE1 (pF) 0 0 0 0 0 0 1 8 0 1 0 16 0 1 1 24 1 0 0 24 1 0 1 32 1 1 0 40 1 1 1 48 Reserved. Bypasses the internal RZERO resistor (RZERO = 0 ). Requires the use of a series external zero resistor. This bit is the MSB of the loop filter control register (Register 0x0205 and Register 0x0206). 1 = internal RZERO bypassed. 0 = internal RZERO used. Table 54. PLL2 Input Divider (R1) (Register 0x0207) Bits [7:5] [4:0] Bit Name Reserved 5-bit R1 divider Description Reserved. Divide by 1 to divide by 31. 00000, 00001 = divide by 1. Table 55. PLL2 Feedback Divider (N2) (Register 0x0208) Bits [7:0] Bit Name 8-bit N2 divider Description Division = Channel Divider Bits[7:0] + 1. For example, [7:0] = 0 is divided by 1, [7:0] = 1 is divided by 2...[7:0] = 255 is divided by 256. Table 56. PLL2 R1 Reference Divider (Register 0x0208 and Register 0x0209) Address 0x0209 Bits 7 6 Bit Name Reserved N2 divider power-down [5:0] N2 phase, Bits[5:0] Description Reserved. 0: (default) normal operation. 1: N2 divider powered down Divider initial phase after a sync is asserted relative to the divider input clock (from the VCO divider output). LSB = 1/2 of a period of the divider input clock. Phase 0 = no phase offset. Phase 1 = 1/2 period offset. ... Phase 63 = 31.5 period offset. Rev. C | Page 58 of 67 Data Sheet AD9528 CLOCK DISTRIBUTION (REGISTER 0x300 TO REGISTER 0x0329) Table 57. Channel 0 to Channel 13 Control (This Same Map Applies to All 14 Channels) Address 0x0300, 0x0303, 0x0306, 0x0309, 0x030C, 0x030F, 0x0312, 0x0315, 0x0318, 0x031B, 0x031E, 0x0321, 0x0324 0x0301, 0x0304, 0x0307, 0x030A, 0x030D, 0x0310, 0x0313, 0x0316, 0x0319, 0x031C, 0x031F, 0x0322, 0x0325, 0x0328 0x0302, 0x0305, 0x0308, 0x030B, 0x030E, 0x031A, 0x0314, 0x0317, 0x031A, 0x031D, 0x0323, 0x0326, 0x0320, 0x0329 Bits [7:5] Bit Name Channel control, Bits[2:0] Description Controls which signal source is selected by the output driver. Bit 7 Bit 6 Bit 5 Output Signal Source 0 0 0 PLL2/divider output. 0 0 1 PLL1/VCXO output. 0 1 0 SYSREF (retimed by PLL2 output). 0 1 1 SYSREF (retimed by PLL1 output). 1 0 0 PLL2/divider output. 1 0 1 Inverted PLL1/VCXO output. 1 1 0 SYSREF (retimed by PLL2 output). 1 1 1 SYSREF (retimed by inverted PLL1 output). 1 = enables fine delay for the corresponding channel. 600 ps insertion delay. 0 (default) = disables fine analog delay for the corresponding channel. 15 fine delay steps. Step size = 31 ps. Determines the output logic to be applied. Bit 7 Bit 6 Output Logic type 0 0 LVDS. 0 1 LVDS (boost mode). 1 X HSTL. 4 Fine analog delay enable [3:0] Fine analog delay, Bits[3:0] [7:6] Output format, Bits[1:0] [5:0] Coarse digital delay, Bits[5:0] Divider initial phase after a sync is asserted relative to the divider input clock (from the VCO divider output). LSB = 1/2 of a period of the divider input clock. Phase = 0: no phase offset. Phase = 1: 1/2 period offset ... Phase = 63: 31.5 period offset. [7:0] Divide ratio, Bits[7:0] (LSB) Division = Channel divider Bits[7:0] + 1. For example, [7:0] = 0 is divided by 1, [7:0] = 1 is divided by 2...[7:0] = 255 is divided by 256. 8-bit channel divider. Rev. C | Page 59 of 67 AD9528 Data Sheet Table 58. Distribution Sync Address 0x032A Bits [7:1] 0 Bit Name Reserved SYNC outputs Description Reserved. Issues SYNC on transition of bit 0 from 1 to 0. Table 59. Ignore SYNC Enable Address 0x032B 0x032C Bits 7 Bit Name Channel 7 ignore sync 6 Channel 6 ignore sync 5 Channel 5 ignore sync 4 Channel 4 ignore sync 3 Channel 3 ignore sync 2 Channel 2 ignore sync 1 Channel 1 ignore sync 0 Channel 0 ignore sync 7 6 Reserved PLL2 feedback N2 divider ignore sync 5 Channel 13 ignore sync 4 Channel 12 ignore sync 3 Channel 11 ignore sync 2 Channel 10 ignore sync 1 Channel 9 ignore sync 0 Channel 8 ignore sync Description 0 = Channel 7 synchronizes to sync command. 1 = Channel 7 ignores sync command. 0 = Channel 6 synchronizes to sync command. 1 = Channel 6 ignores sync command. 0 = Channel 5 synchronizes to sync command. 1 = Channel 5 ignores sync command. 0 = Channel 4 synchronizes to sync command. 1 = Channel 4 ignores sync command. 0 = Channel 3 synchronizes to sync command. 1 = Channel 3 ignores sync command. 0 = Channel 2 synchronizes to sync command. 1 = Channel 2 ignores sync command. 0 = Channel 1 synchronizes to sync command. 1 = Channel 1 ignores sync command. 0 = Channel 0 synchronizes to sync command. 1 = Channel 0 ignores sync command. Reserved. 0 = PLL2 N2 divider synchronizes to sync command 1 = PLL2 N2 divider ignores sync command 0 = Channel 13 synchronizes to sync command 1 = Channel 13 ignores sync command 0 = Channel 12 synchronizes to sync command 1 = Channel 12 ignores sync command 0 = Channel 11 synchronizes to sync command 1 = Channel 11 ignores sync command 0 = Channel 10 synchronizes to sync command 1 = Channel 10 ignores sync command 0 = Channel 9 synchronizes to sync command 1 = Channel 9 ignores sync command 0 = Channel 8 synchronizes to sync command 1 = Channel 8 ignores sync command Rev. C | Page 60 of 67 Data Sheet AD9528 Table 60. SYSREF Bypass Resample Control Address 0x032D 0x032E Bits 7 Bit Name Channel 6 bypass SYSREF resample 6 Channel 5 bypass SYSREF resample 5 Channel 4 bypass SYSREF resample 4 Channel 3 bypass SYSREF resample 3 Channel 2 bypass SYSREF resample 2 Channel 1 bypass SYSREF resample 1 Channel 0 bypass SYSREF resample 0 Enable VCXO receiver path to distribution 7 6 Reserved Channel 13 bypass SYSREF resample 5 Channel 12 bypass SYSREF resample 4 Channel 11 bypass SYSREF resample 3 Channel 10 bypass SYSREF resample 2 Channel 9 bypass SYSREF resample 1 Channel 8 bypass SYSREF resample 0 Channel 7 bypass SYSREF resample Description 0 = not bypassed. 1 = Channel 6 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 5 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 4 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 3 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 2 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 1 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 0 bypass SYSREF resample. 0 = path disabled. 1 = enables path. Reserved. 0 = not bypassed. 1 = Channel 13 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 12 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 11 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 10 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 9 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 8 bypass SYSREF resample. 0 = not bypassed. 1 = Channel 7 bypass SYSREF resample. Table 61. SYSREF Pattern Generator K Divider Address 0x0400, 0x0401 Bits [7:0], [15:8] Bit Name K divider Description The 16-bit K divider divides the input clock to the SYSREF pattern generator to program the SYSREF pulse width. Bits[7:0] are the LSB byte, and Bits[15:8] are the MSB byte. Rev. C | Page 61 of 67 AD9528 Data Sheet Table 62. SYSREF Control Address 0x0402 0x0403 Bits 7 Bit Name SYSREF request method [6:5] SYSREF pattern generator trigger control, Bits[1:0] 4 SYSREF pattern generator clock source 3 Resample clock source for external SYSREF [2:1] SYSREF test mode, Bits[1:0] 0 [7:6] SYSREF reset SYSREF source, Bits[1:0] [5:4] SYSREF pattern generator mode, Bits[1:0] [3:1] N-shot mode, Bits[1:0] 0 SPI SYSREF request Description SYSREF request method 0 = SPI controlled 1 = Pin controlled SYSREF pattern generator trigger control 0x: level sensitive, active high 10: edge sensitive, rising edge 11: edge sensitive, falling edge 0 = PLL2 feedback divider 1 = PLL1 out 0 = device clock 1 = PLL1 out SYSREF test mode 00 = GND 01 = VDD 1x = counter output clock SYSREF reset SYSREF source 00 = external 01 = external resampled 10 = internal Pattern mode 00 = N-shot 01 = continuous 10 = PRBS 11 = stop N-shot mode 001 = 1 pulse 010 = 2 pulses 011 = 4 pulses 100 = 6 pulses 101 = 8 pulses Others = 1 pulse SPI SYSREF request In N-shot mode, the SYSREF pattern starts at the transition of this bit from 0 to 1 and bit automatically clears after the pattern completes In continuous or PRBS mode, SYSREF pattern starts at the transition of this bit from 0 to 1 and the bit stays set to 1 until user clears the bit; when the user clears the bit, the SYSREF pattern stops Table 63. SYSREF_IN Receiver Control Address 0x0404 Bits [7:3] 2 Bit Name Reserved SYSREF IN receiver power-down 1 Single-ended source negative input (CMOS mode) 0 SYSREF differential receiver enable Description Reserved. Enables control over power-down of the SYSREF input receivers. 1 = power-down control enabled (default). 0 = both receivers enabled. Selects which single-ended input pin is enabled when in the SYSREF single-ended receiver mode (Register 0x0404, Bit 0 = 0). 1 = negative receiver from SYSREF input (SYSREF_IN pin) selected. 0 = positive receiver from SYSREF input (SYSREF_IN pin) selected (default). 1 = differential receiver mode, single-ended receivers disabled. 0 = single-ended receiver mode (default). Rev. C | Page 62 of 67 Data Sheet AD9528 POWER-DOWN CONTROL (REGISTER 0x0500 TO REGISTER 0x0504) Table 64. Power-Down Control Enable Address 0x0500 Bits [7:5] Bit Name Reserved Description Reserved 4 Bias generation power-down disable or power-down 0 = power-down 3 PLL2 power-down enable 2 PLL1 power-down enable 1 Clock distribution power-down enable 0 Chip power-down enable 1 = normal operation 0 = normal operation 1 = power-down 0 = normal operation 1 = power-down 0 = normal operation 1 = power-down 0 = normal operation 1 = power-down Table 65. Output Channel Power-Down Control Address 0x0501 0x0502 Bits 7 Bit Name Channel 7 power-down 6 Channel 6 power-down 5 Channel 5 power-down 4 Channel 4 power-down 3 Channel 3 power-down 2 Channel 2 power-down 1 Channel 1 power-down 0 Channel 0 power-down [7:6] 5 Reserved Channel 13 power-down 4 Channel 12 power-down 3 Channel 11 power-down 2 Channel 10 power-down 1 Channel 9 power-down 0 Channel 8 power-down Description 0 = normal operation 1 = Channel 7 power-down 0 = normal operation 1 = Channel 6 power-down 0 = normal operation 1 = Channel 5 power-down 0 = normal operation 1 = Channel 4 power-down 0 = normal operation 1 = Channel 3 power-down 0 = normal operation 1 = Channel 2 power-down 0 = normal operation 1 = Channel 1 power-down 0 = normal operation 1 = Channel 0 power-down Reserved 0 = normal operation 1 = Channel 13 power-down 0 = normal operation 1 = Channel 12 power-down 0 = normal operation 1 = Channel 11 power-down 0 = normal operation 1 = Channel 10 power-down 0 = normal operation 1 = Channel 9 power-down 0 = normal operation 1 = Channel 8 power-down Rev. C | Page 63 of 67 AD9528 Data Sheet Table 66. LDO Regulator Enable Address 0x0503 0x0504 Bits 7 Bit Name Channel 7 LDO enable 6 Channel 6 LDO enable 5 Channel 5 LDO enable 4 Channel 4 LDO enable 3 Channel 3 LDO enable 2 Channel 2 LDO enable 1 Channel 1 LDO enable 0 Channel 0 LDO enable 7 PLL2 LDO enable 6 PLL1 LDO enable 5 Channel 13 LDO enable 4 Channel 12 LDO enable 3 Channel 11 LDO enable 2 Channel 10 LDO enable 1 Channel 9 LDO enable 0 Channel 8 LDO enable Description 0: Channel 7 LDO power down 1: normal operation 0: Channel 6 LDO power down 1: normal operation 0: Channel 5 LDO power down 1: normal operation 0: Channel 4 LDO power down 1: normal operation 0: Channel 3 LDO power down 1: normal operation 0: Channel 2 LDO power down 1: normal operation 0: Channel 1 LDO power down 1: normal operation 0: Channel 0 LDO power down 1: normal operation 0: PLL2 LDO power down 1: normal operation 0: PLL1 LDO power down 1: normal operation 0: Channel 13 LDO power down 1: normal operation 0: Channel 12 LDO power down 1: normal operation 0: Channel 11 LDO power down 1: normal operation 0: Channel 10 LDO power down 1: normal operation 0: Channel 9 LDO power down 1: normal operation 0: Channel 8 LDO power down 1: normal operation Rev. C | Page 64 of 67 Data Sheet AD9528 STATUS CONTROL (REGISTER 0x0505 TO REGISTER 0x0509) Table 67. Status Control Signals Address 0x0505 Bits [7:0] Bit Name Status Monitor 0 control 0x0506 [7:0] Status Monitor 1 control Description Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mux Out 0 0 0 0 0 0 GND 0 0 0 0 0 1 PLL1 and PLL2 locked 0 0 0 0 1 0 PLL1 locked 0 0 0 0 1 1 PLL2 locked 0 0 0 1 0 0 Both references are missing (REFA and REFB) 0 0 0 1 0 1 Both references are missing and PLL2 is locked 0 0 0 1 1 0 REFB selected (applies only to auto select mode) 0 0 0 1 1 1 REFA is correct 0 0 1 0 0 0 REFB is correct 0 0 1 0 0 1 PLL1 in Holdover 0 0 1 0 1 0 VCXO is correct 0 0 1 0 1 1 PLL1 feedback is correct 0 0 1 1 0 0 PLL2 feedback clock is correct 0 0 1 1 0 1 Fast lock in progress 0 0 1 1 1 0 REFA and REFB are correct 0 0 1 1 1 1 All clocks are correct 0 1 0 0 0 0 PLL1 feedback divide by 2 0 1 0 0 0 1 PLL1 PFD down divide by 2 0 1 0 0 1 0 PLL1 REF divide by 2 0 1 0 0 1 1 PLL1 PFD up divide by 2 0 1 0 1 0 0 GND 0 1 0 1 0 1 GND 0 1 0 1 1 0 GND 0 1 0 1 1 1 GND Note that all bit combinations after 010111 are reserved Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Mux Out 0 0 0 0 0 0 GND 0 0 0 0 0 1 PLL1 and PLL2 locked 0 0 0 0 1 0 PLL1 locked 0 0 0 0 1 1 PLL2 locked 0 0 0 1 0 0 Both references are missing (REFA and REFB) 0 0 0 1 0 1 Both references are missing and PLL2 is locked 0 0 0 1 1 0 REFB selected (applies only to auto select mode) 0 0 0 1 1 1 REFA is correct 0 0 1 0 0 0 REFB is correct 0 0 1 0 0 1 PLL1 in Holdover 0 0 1 0 1 0 VCXO is correct 0 0 1 0 1 1 PLL1 feedback is correct 0 0 1 1 0 0 PLL2 feedback clock is correct 0 0 1 1 0 1 Fast Lock in Progress 0 0 1 1 1 0 REFA and REFB are correct 0 0 1 1 1 1 All clocks are correct 0 1 0 0 0 0 GND 0 1 0 0 0 1 GND 0 1 0 0 1 0 GND 0 1 0 0 1 1 GND 0 1 0 1 0 0 PLL2 feedback divide by 2 0 1 0 1 0 1 PLL2 PFD down divide by 2 Rev. C | Page 65 of 67 AD9528 Data Sheet Address Bits Bit Name 0x0507 [7:4] 3 Reserved STATUS1 pin Output enable 2 STATUS0 pin Output enable 1 STATUS0 pin divider enable 0 STATUS1 pin divider enable Description 0 1 0 1 1 0 PLL2 REF divide by 2 0 1 0 1 1 1 PLL2 PFD up divide by 2 Note that all bit combinations after 010111 are reserved. Reserved. Enables the status on the STATUS1 pin. 1: enable status output. 0: disable status output. Enables the status on the STATUS0 pin. 1: enable status output. 0: disable status output. Enables a divide by 4 on the STATUS0 pin, allowing dynamic signals to be viewed at a lower frequency (such as the PFD input clocks). Not to be used with dc states on the status pins, which occur when the settings of Register 0x0505, Bits[5:0] are in the range of 000000 to 001111. 1: enabled. 0: disabled. Enables a divide by 4 on the STATUS1 pin, allowing dynamic signals to be viewed at a lower frequency (such as the PFD input clocks). Not to be used with dc states on the status pins, which occur when the settings of Register 0x0506, Bits[5:0] are in the range of 000000 to 001111. 1: enable. 0: disable. Table 68. Readback Registers (Readback 0 and Readback 1) Address 0x0508 0x0509 Bits 7 Bit Name PLL2 feedback status 6 PLL1 feedback status 5 VCXO status 4 Both REFA/REFB missing 3 REFB status 2 REFA status 1 PLL2 locked status 0 PLL1 locked status [7:4] 3 Reserved Holdover active status 2 Selected reference 1 Fast Lock in progress 0 VCO calibration busy status Description 1 = correct. 0 = off/clocks are missing. 1 = correct. 0 = off/clocks are missing. 1 = correct. 0 = off/clocks are missing. 1 = off/clocks are missing. 0 = correct. 1 = correct. 0 = off/clocks are missing. 1 = correct. 0 = off/clocks are missing. 1 = locked. 0 = unlocked. 1 = locked. 0 = unlocked. Reserved. 1 = holdover is active (both references are missing). 0 = normal operation. Selected reference (applies only when the device automatically selects the reference; for example, not in manual control mode). 1 = REFB. 0 = REFA. 1 = fast lock in progress. 0 = fast lock not in progress. 1 = VCO calibration in progress. 0 = VCO calibration not in progress. Rev. C | Page 66 of 67 Data Sheet AD9528 OUTLINE DIMENSIONS 10.10 10.00 SQ 9.90 0.60 0.42 0.24 9.85 9.75 SQ 9.65 55 54 1 18 37 19 36 BOTTOM VIEW 0.80 MAX 0.65 TYP 0.25 MIN 8.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PIN 1 INDICATOR 5.45 5.30 SQ 5.15 EXPOSED PAD TOP VIEW 1.00 0.85 0.80 72 0.50 BSC 0.50 0.40 0.30 12 MAX 0.30 0.23 0.18 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VNND-4 06-25-2012-C PIN 1 INDICATOR 0.60 0.42 0.24 Figure 56. 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 10 mm x 10 mm Body, Very Thin Quad (CP-72-6) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9528BCPZ AD9528BCPZ-REEL7 AD9528/PCBZ 1 Temperature Range -40C to +85C -40C to +85C Package Description 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 72-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Board Z = RoHS Compliant Part. I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). (c)2014-2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D12380-0-7/15(C) Rev. C | Page 67 of 67 Package Option CP-72-6 CP-72-6 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: AD9528BCPZ AD9528BCPZ-REEL7