MC74HC4046A Phase-Locked Loop High-Performance Silicon-Gate CMOS The MC74HC4046A is similar in function to the MC14046 Metal gate CMOS device. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The HC4046A phase-locked loop contains three phase comparators, a voltage-controlled oscillator (VCO) and unity gain op-amp DEMOUT. The comparators have two common signal inputs, COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly coupled to large voltage signals, or indirectly coupled (with a series capacitor to small voltage signals). The self-bias circuit adjusts small voltage signals in the linear region of the amplifier. Phase comparator 1 (an exclusive OR gate) provides a digital error signal PC1OUT and maintains 90 degrees phase shift at the center frequency between SIGIN and COMPIN signals (both at 50% duty cycle). Phase comparator 2 (with leading-edge sensing logic) provides digital error signals PC2OUT and PCPOUT and maintains a 0 degree phase shift between SIGIN and COMPIN signals (duty cycle is immaterial). The linear VCO produces an output signal VCOOUT whose frequency is determined by the voltage of input VCOIN signal and the capacitor and resistors connected to pins C1A, C1B, R1 and R2. The unity gain op-amp output DEMOUT with an external resistor is used where the VCOIN signal is needed but no loading can be tolerated. The inhibit input, when high, disables the VCO and all op-amps to minimize standby power consumption. Applications include FM and FSK modulation and demodulation, frequency synthesis and multiplication, frequency discrimination, tone decoding, data synchronization and conditioning, voltage-to-frequency conversion and motor speed control. http://onsemi.com MARKING DIAGRAMS 16 PDIP-16 N SUFFIX CASE 648 16 1 1 16 SOIC-16 D SUFFIX CASE 751B 16 1 * * * * * Output Drive Capability: 10 LSTTL Loads Low Power Consumption Characteristic of CMOS Devices Operating Speeds Similar to LSTTL Wide Operating Voltage Range: 3.0 to 6.0 V Low Input Current: 1.0 mA Maximum (except SIGIN and COMPIN) In Compliance with the Requirements Defined by JEDEC Standard No. 7 A Low Quiescent Current: 80 mA Maximum (VCO disabled) High Noise Immunity Characteristic of CMOS Devices Diode Protection on all Inputs Chip Complexity: 279 FETs or 70 Equivalent Gates These Devices are Pb-Free, Halogen Free and are RoHS Compliant (c) Semiconductor Components Industries, LLC, 2011 May, 2011 - Rev. 9 1 HC4046AG AWLYWW 1 16 TSSOP-16 DT SUFFIX CASE 948F 16 1 HC40 46A ALYWG G 1 16 SOEIAJ-16 F SUFFIX CASE 966 16 1 74HC4046A ALYWG 1 Features * * * * * * MC74HC4046AN AWLYYWWG A L, WL Y, YY W, WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 5 of this data sheet. Publication Order Number: MC74HC4046A/D MC74HC4046A Pin No. Symbol 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PCPOUT PC1OUT COMPIN VCOOUT INH C1A C1B GND VCOIN DEMOUT R1 R2 PC2OUT SIGIN PC3OUT VCC Name and Function Phase Comparator Pulse Output Phase Comparator 1 Output Comparator Input VCO Output Inhibit Input Capacitor C1 Connection A Capacitor C1 Connection B Ground (0 V) VSS VCO Input Demodulator Output Resistor R1 Connection Resistor R2 Connection Phase Comparator 2 Output Signal Input Phase Comparator 3 Output Positive Supply Voltage PCPout 1 16 VCC PC1out 2 15 PC3out COMPin 3 14 SIGin VCOout 4 13 PC2out INH 5 12 R2 C1A 6 11 R1 C1B 7 10 DEMout GND 8 9 VCOin Figure 1. Pin Assignment IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII IIIII III IIIIIIIIIIIIIIIIIIIIIIIIII MAXIMUM RATINGS Symbol Parameter Value Unit - 0.5 to + 7.0 V DC Input Voltage (Referenced to GND) - 1.5 to VCC + 1.5 V DC Output Voltage (Referenced to GND) - 0.5 to VCC + 0.5 V VCC DC Supply Voltage (Referenced to GND) Vin Vout Iin DC Input Current, per Pin 20 mA Iout DC Output Current, per Pin 25 mA ICC DC Supply Current, VCC and GND Pins 50 mA PD Power Dissipation in Still Air 750 500 mW Tstg Storage Temperature - 65 to + 150 _C TL Lead Temperature, 1 mm from Case for 10 Seconds Plastic DIP and SOIC Package Plastic DIP SOIC Package _C 260 Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C IIIIIIIIIIIIIIIIIIIIIIIIIII IIII IIIIIIIIIIIIII III III III IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII IIIIIIIIIIIIIIIIIIIIIIIIIII RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 3.0 6.0 V VCC DC Supply Voltage (Referenced to GND) NON-VCO 2.0 6.0 V Vin, Vout DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V - 55 + 125 _C 0 0 0 1000 500 400 ns TA Operating Temperature, All Package Types tr, tf Input Rise and Fall Time (Pin 5) VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V http://onsemi.com 2 This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND v (Vin or Vout) v VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. MC74HC4046A [Phase Comparator Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85C 125C Unit VIH Minimum High-Level Input Voltage DC Coupled SIGIN, COMPIN Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA 2.0 4.5 6.0 1.5 3.15 4.2 1.5 3.15 4.2 1.5 3.15 4.2 V VIL Maximum Low-Level Input Voltage DC Coupled SIGIN, COMPIN Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA 2.0 4.5 6.0 0.5 1.35 1.8 0.5 1.35 1.8 0.5 1.35 1.8 V VOH Minimum High-Level Output Voltage PCPOUT, PCnOUT Vin = VIH or VIL |Iout| 20 mA 2.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 2.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA VOL Maximum Low-Level Output Voltage Qa-Qh PCPOUT, PCnOUT Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA V Iin Maximum Input Leakage Current SIGIN, COMPIN Vin = VCC or GND 2.0 3.0 4.5 6.0 3.0 7.0 18.0 30.0 4.0 9.0 23.0 38.0 5.0 11.0 27.0 45.0 mA IOZ Maximum Three-State Leakage Current PC2OUT Output in High-Impedance State Vin = VIH or VIL Vout = VCC or GND 6.0 0.5 5.0 10 mA ICC Maximum Quiescent Supply Current (per Package) (VCO disabled) Pins 3, 5 and 14 at VCC Pin 9 at GND; Input Leakage at Pins 3 and 14 to be excluded Vin = VCC or GND |Iout| = 0 mA 6.0 4.0 40 160 mA VCC V - 55 to 25_C [Phase Comparator Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit 85C 125C Unit tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT (Figure 2) 2.0 4.5 6.0 175 35 30 220 44 37 265 53 45 ns tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT (Figure 2) 2.0 4.5 6.0 340 68 58 425 85 72 510 102 87 ns tPLH, tPHL Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT (Figure 2) 2.0 4.5 6.0 270 54 46 340 68 58 405 81 69 ns tPLZ, tPHZ Maximum Propagation Delay, SIGIN/COMPIN Output Disable Time to PC2OUT (Figures 3 and 4) 2.0 4.5 6.0 200 40 34 250 50 43 300 60 51 ns tPZH, tPZL Maximum Propagation Delay, SIGIN/COMPIN Output Enable Time to PC2OUT (Figures 3 and 4) 2.0 4.5 6.0 230 46 39 290 58 49 345 69 59 ns tTLH, tTHL Maximum Output Transition Time (Figure 2) 2.0 4.5 6.0 75 15 13 95 19 16 110 22 19 ns Symbol Parameter http://onsemi.com 3 MC74HC4046A [VCO Section] DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions VCC V - 55 to 25_C 85C 125C Unit VIH Minimum High-Level Input Voltage INH Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA 3.0 4.5 6.0 2.1 3.15 4.2 2.1 3.15 4.2 2.1 3.15 4.2 V VIL Maximum Low-Level Input Voltage INH Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA 3.0 4.5 6.0 0.90 1.35 1.8 0.9 1.35 1.8 0.9 1.35 1.8 V VOH Minimum High-Level Output Voltage VCOOUT Vin = VIH or VIL |Iout| 20 mA 3.0 4.5 6.0 1.9 4.4 5.9 1.9 4.4 5.9 1.9 4.4 5.9 V 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 3.0 4.5 6.0 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 0.1 Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 Vin = VCC or GND 6.0 0.1 1.0 1.0 Min Max Min Max Min Max INH = VIL 3.0 4.5 6.0 0.1 0.1 0.1 1.0 2.5 4.0 0.1 0.1 0.1 1.0 2.5 4.0 0.1 0.1 0.1 1.0 2.5 4.0 V 3.0 4.5 6.0 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 kW 3.0 4.5 6.0 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 3.0 3.0 300 300 300 3.0 4.5 6.0 40 40 40 No Limit Vin = VIH or VIL |Iout| 4.0 mA |Iout| 5.2 mA VOL Iin Maximum Low-Level Output Voltage VCOOUT Vout = 0.1 V or VCC - 0.1 V |Iout| 20 mA Maximum Input Leakage Current INH, VCOIN VVCO IN Operating Voltage Range at VCOIN over the range specified for R1; For linearity see Fig. 15A, Parallel value of R1 and R2 should be > 2.7 kW R1 Resistor Range R2 C1 Capacitor Range V mA pF [VCO Section] AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns) Guaranteed Limit Symbol VCC V Parameter - 55 to 25_C Min 85C Max Min Max 125C Min Max Unit Df/T Frequency Stability with Temperature Changes (Figure 14A, B, C) 3.0 4.5 6.0 fo VCO Center Frequency (Duty Factor = 50%) (Figure 15A, B, C, D) 3.0 4.5 6.0 DfVCO VCO Frequency Linearity 3.0 4.5 6.0 See Figures 16A, B, C % VCO Duty Factor at VCOOUT 3.0 4.5 6.0 Typical 50% % http://onsemi.com 4 %/K 3 11 13 MHz MC74HC4046A [Demodulator Section] DC ELECTRICAL CHARACTERISTICS Guaranteed Limit Symbol RS VOFF RD Parameter Test Conditions - 55 to 25_C VCC V Min Max 50 50 50 300 300 300 85C Min Max 125C Min Max Unit Resistor Range At RS > 300 kW the Leakage Current can Influence VDEMOUT 3.0 4.5 6.0 Offset Voltage VCOIN to VDEMOUT Vi = VVCOIN = 1/2 VCC; Values taken over RS Range. 3.0 4.5 6.0 See Figure 13 mV Dynamic Output Resistance at DEMOUT VDEMOUT = 1/2 VCC 3.0 4.5 6.0 Typical 25 W W kW ORDERING INFORMATION Package Shipping MC74HC4046ANG PDIP-16 (Pb-Free) 2000 Units / Box MC74HC4046ADG SOIC-16 (Pb-Free) 48 Units / Rail MC74HC4046ADR2G SOIC-16 (Pb-Free) 2500 Units / Reel MC74HC4046ADTG TSSOP-16* 96 Units / Rail MC74HC4046ADTR2G TSSOP-16* 2500 Units / Reel MC74HC4046AFG SOEIAJ-16 (Pb-Free) 50 Units / Rail MC74HC4046AFELG SOEIAJ-16 (Pb-Free) 2000 Units / Reel Device For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. http://onsemi.com 5 MC74HC4046A SWITCHING WAVEFORMS SIGIN INPUT VCC SIGIN, COMPIN INPUTS VCC 50% GND 50% VCC GND tPHL COMPIN INPUT tPLH 50% 90% PCPOUT, PC1OUT PC3OUT OUTPUTS PC2OUT 10% tTHL OUTPUT tTLH GND tPHZ tPZH 50% VOH 90% 50% Figure 2. HIGH IMPEDANCE Figure 3. VCC SIGIN INPUT TEST POINT 50% GND OUTPUT VCC COMPIN INPUT 50% OUTPUT CL* GND tPLZ tPZL PC2OUT DEVICE UNDER TEST HIGH IMPEDANCE 50% 10% *INCLUDES ALL PROBE AND JIG CAPACITANCE VOL Figure 4. Figure 5. Test Circuit http://onsemi.com 6 MC74HC4046A DETAILED CIRCUIT DESCRIPTION up to Vref of the comparators, the oscillator logic flips the capacitor which causes the mirror to charge the opposite side of the capacitor. The output from the internal logic is then taken to VCO output (Pin 4). The input to the VCO is a very high impedance CMOS input and thus will not load down the loop filter, easing the filters design. In order to make signals at the VCO input accessible without degrading the loop performance, the VCO input voltage is buffered through a unity gain Op-amp to Demod Output. This Op-amp can drive loads of 50K ohms or more and provides no loading effects to the VCO input voltage (see Figure 13). An inhibit input is provided to allow disabling of the VCO and all Op-amps (see Figure 6). This is useful if the internal VCO is not being used. A logic high on inhibit disables the VCO and all Op-amps, minimizing standby power consumption. Voltage Controlled Oscillator/Demodulator Output The VCO requires two or three external components to operate. These are R1, R2, C1. Resistor R1 and Capacitor C1 are selected to determine the center frequency of the VCO (see typical performance curves Figure 15). R2 can be used to set the offset frequency with 0 volts at VCO input. For example, if R2 is decreased, the offset frequency is increased. If R2 is omitted the VCO range is from 0 Hz. The effect of R2 is shown in Figure 25, typical performance curves. By increasing the value of R2 the lock range of the PLL is increased and the gain (volts/Hz) is decreased. Thus, for a narrow lock range, large swings on the VCO input will cause less frequency variation. Internally, the resistors set a current in a current mirror, as shown in Figure 6. The mirrored current drives one side of the capacitor. Once the voltage across the capacitor charges VREF 12 I1 + _ CURRENT MIRROR I1 + I2 = I3 R2 VCOIN 9 11 4 I2 + _ I3 R1 DEMODOUT VCOOUT + _ 10 C1 (EXTERNAL) 7 6 INH - + - Vref + 5 Figure 6. Logic Diagram for VCO feed external prescalers (counters) to enable frequency synthesis. The output of the VCO is a standard high speed CMOS output with an equivalent LS-TTL fan out of 10. The VCO output is approximately a square wave. This output can either directly feed the COMPIN of the phase comparators or http://onsemi.com 7 MC74HC4046A Phase Comparators outputs of these comparators are essentially standard 74HC outputs (comparator 2 is TRI-STATEABLE). In normal operation VCC and ground voltage levels are fed to the loop filter. This differs from some phase detectors which supply a current to the loop filter and should be considered in the design. (The MC14046 also provides a voltage). All three phase comparators have two inputs, SIGIN and COMPIN. The SIGIN and COMPIN have a special DC bias network that enables AC coupling of input signals. If the signals are not AC coupled, standard 74HC input levels are required. Both input structures are shown in Figure 7. The VCC VCC SIGIN PC2OUT 14 13 VCC COMPIN 3 PCPOUT 1 PC3OUT 15 PC1OUT 2 Figure 7. Logic Diagram for Phase Comparators Phase Comparator 1 two input signals must be in phase. When the input frequency is fmax, the VCO input must be VCC and the phase detector inputs must be 180 degrees out of phase. This comparator is a simple XOR gate similar to the 74HC86. Its operation is similar to an overdriven balanced modulator. To maximize lock range the input frequencies must have a 50% duty cycle. Typical input and output waveforms are shown in Figure 8. The output of the phase detector feeds the loop filter which averages the output voltage. The frequency range upon which the PLL will lock onto if initially out of lock is defined as the capture range. The capture range for phase detector 1 is dependent on the loop filter design. The capture range can be as large as the lock range, which is equal to the VCO frequency range. To see how the detector operates, refer to Figure 8. When two square wave signals are applied to this comparator, an output waveform (whose duty cycle is dependent on the phase difference between the two signals) results. As the phase difference increases, the output duty cycle increases and the voltage after the loop filter increases. In order to achieve lock when the PLL input frequency increases, the VCO input voltage must increase and the phase difference between COMPIN and SIGIN will increase. At an input frequency equal to fmin, the VCO input is at 0 V. This requires the phase detector output to be grounded; hence, the SIGIN COMPIN PC1OUT VCOIN VCC GND Figure 8. Typical Waveforms for PLL Using Phase Comparator 1 The XOR is more susceptible to locking onto harmonics of the SIGIN than the digital phase detector 2. For instance, a signal 2 times the VCO frequency results in the same output duty cycle as a signal equal to the VCO frequency. The difference is that the output frequency of the 2f example is twice that of the other example. The loop filter and VCO range should be designed to prevent locking on to harmonics. http://onsemi.com 8 MC74HC4046A Phase Comparator 2 and will cause the output to go high until the VCO leading edge is seen, potentially for an entire SIGIN period. This would cause the VCO to speed up during that time. When using PC1, the output of that phase detector would be disturbed for only the short duration of the noise spike and would cause less upset. This detector is a digital memory network. It consists of four flip-flops and some gating logic, a three state output and a phase pulse output as shown in Figure 6. This comparator acts only on the positive edges of the input signals and is independent of duty cycle. Phase comparator 2 operates in such a way as to force the PLL into lock with 0 phase difference between the VCO output and the signal input positive waveform edges. Figure 8 shows some typical loop waveforms. First assume that SIGIN is leading the COMPIN. This means that the VCO's frequency must be increased to bring its leading edge into proper phase alignment. Thus the phase detector 2 output is set high. This will cause the loop filter to charge up the VCO input, increasing the VCO frequency. Once the leading edge of the COMPIN is detected, the output goes TRI-STATE holding the VCO input at the loop filter voltage. If the VCO still lags the SIGIN then the phase detector will again charge up the VCO input for the time between the leading edges of both waveforms. If the VCO leads the SIGIN then when the leading edge of the VCO is seen; the output of the phase comparator goes low. This discharges the loop filter until the leading edge of the SIGIN is detected at which time the output disables itself again. This has the effect of slowing down the VCO to again make the rising edges of both waveforms coincidental. When the PLL is out of lock, the VCO will be running either slower or faster than the SIGIN. If it is running slower the phase detector will see more SIGIN rising edges and so the output of the phase comparator will be high a majority of the time, raising the VCO's frequency. Conversely, if the VCO is running faster than the SIGIN, the output of the detector will be low most of the time and the VCO's output frequency will be decreased. As one can see, when the PLL is locked, the output of phase comparator 2 will be disabled except for minor corrections at the leading edge of the waveforms. When PC2 is TRI-STATED, the PCP output is high. This output can be used to determine when the PLL is in the locked condition. This detector has several interesting characteristics. Over the entire VCO frequency range there is no phase difference between the COMPIN and the SIGIN. The lock range of the PLL is the same as the capture range. Minimal power was consumed in the loop filter since in lock the detector output is a high impedance. When no SIGIN is present, the detector will see only VCO leading edges, so the comparator output will stay low, forcing the VCO to fmin. Phase comparator 2 is more susceptible to noise, causing the PLL to unlock. If a noise pulse is seen on the SIGIN, the comparator treats it as another positive edge of the SIGIN Phase Comparator 3 This is a positive edge-triggered sequential phase detector using an RS flip-flop as shown in Figure 7. When the PLL is using this comparator, the loop is controlled by positive signal transitions and the duty factors of SIGIN and COMPIN are not important. It has some similar characteristics to the edge sensitive comparator. To see how this detector works, assume input pulses are applied to the SIGIN and COMPIN 's as shown in Figure 10. When the SIGIN leads the COMPIN, the flop is set. This will charge the loop filter and cause the VCO to speed up, bringing the comparator into phase with the SIGIN. The phase angle between SIGIN and COMPIN varies from 0 to 360 and is 180 at fo. The voltage swing for PC3 is greater than for PC2 but consequently has more ripple in the signal to the VCO. When no SIGIN is present the VCO will be forced to fmax as opposed to fmin when PC2 is used. The operating characteristics of all three phase comparators should be compared to the requirements of the system design and the appropriate one should be used. SIGIN COMPIN PC2OUT VCC HIGH IMPEDANCE OFF-STATE GND VCOIN PCPOUT Figure 9. Typical Waveforms for PLL Using Phase Comparator 2 SIGIN COMPIN PC3OUT VCOIN VCC GND Figure 10. Typical Waveform for PLL Using Phase Comparator 3 http://onsemi.com 9 MC74HC4046A VCC=6.0 V 800 VCC=3.0 V 4.0 VCC=4.5 V I I ( A) R I = (k ) VCC=3.0 V 400 VCC=4.5 V 0 VCC=6.0 V 0 1/2 VCC-1.0 V 1/2 VCC 1/2 VCC+1.0 V -4.0 1/2VCC - 500 mV VI (V) Figure 11. Input Resistance at SIGIN, COMPIN with DVI = 1.0 V at Self-Bias Point 1/2 VCC VI (V) 1/2 VCC + 500 mV Figure 12. Input Current at SIGIN, COMPIN with DVI = 500 mV at Self-Bias Point DEMOD OUT 15 6.0 VDEM OUT VCC=6.0 V RS=300k VCC=6.0 V RS=50k VCC=4.5 V RS=300k VCC=4.5 V RS=50k FREQUENCY STABILITY (%) R1=3.0kW R1=100kW 5.0 R1=300kW R1=100kW 0 R1=300kW -5.0 -10 VCC=3.0 V RS=300k VCC=3.0 V RS=50k R1=3.0kW -15 -100 0 3.0 VCOIN (V) 0 10 R1=100kW 5.0 0 -5.0 VCC=4.5 V C1=100pF; R2=; VVCOIN=1/2VCC -10 -15 -100 -50 0 50 100 AMBIENT TEMPERATURE (C) 0 50 100 AMBIENT TEMPERATURE (C) 10 FREQUENCY STABILITY (%) R1=300kW VCC = 3.0 V C1=100pF; R2=; VVCOIN=1/3VCC 150 Figure 13A. Frequency Stability versus Ambient Temperature: VCC = 3.0 V R1=3.0kW 15 -50 6.0 Figure 13. Offset Voltage at Demodulator Output as a Function of VCOIN and RS FREQUENCY STABILITY (%) 10 6.0 4.0 2.0 0 -2.0 -4.0 -6.0 -8.0 -10 -100 150 R1=3.0kW R1=300kW R1=100kW 8.0 VCC=6.0 V C1=100pF; R2=; VVCOIN=1/2VCC -50 0 50 100 150 AMBIENT TEMPERATURE (C) Figure 13B. Frequency Stability versus Ambient Temperature: VCC = 4.5 V Figure 13C. Frequency Stability versus Ambient Temperature: VCC = 6.0 V http://onsemi.com 10 MC74HC4046A 23 70 21 VCC = 4.5 V VCC = 6.0 V 60 19 VCC = 3.0 V f VCO (KHz) f VCO(MHz) 50 VCC = 4.5 V 17 15 13 R1 = 3.0 kW C1 = 39 pF 9 0.5 1.0 30 1.5 2.0 2.5 3.0 3.5 R1 = 3.0 kW C1 = 0.1 mF 10 7.0 0 40 20 VCC = 3.0 V 11 0 4.0 0 0.5 1.0 1.5 2.0 VVCOIN (V) 2.5 3.0 3.5 4.0 VVCOIN (V) Figure 14A. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) Figure 14B. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) 1.0 2.0 VCC = 4.5 V VCC = 6.0 V 0.9 VCC = 4.5 V 0.8 VCC = 6.0 V 0.7 f VCO (KHz) VCC = 3.0 V f VCO(MHz) VCC = 6.0 V 1.0 VCC = 3.0 V 0.6 0.5 0.4 0.3 0.2 R1 = 300 kW C1 = 39 pF R1 = 300 kW C1 = 0.1 mF 0.1 0 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 0 0.5 1.0 1.5 2.0 VVCOIN (V) Figure 14C. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) 2.0 3.0 3.5 4.0 4.5 Figure 14D. VCO Frequency (fVCO) as a Function of the VCO Input Voltage (VVCOIN) VCC= 4.5 V C1 = 1.0 mF 1.0 f VCO (%) 2.5 VVCOIN (V) 6.0 V f2 3.0 V f0 f0 4.5 V f1 0 6.0 V -1.0 3.0 V -2.0 0 10 R2 = ; DV = 0.5 V C1 = 39 pF 101 102 MIN 103 R1 (kW) 1/2 VCC MAX DV = 0.5 V OVER THE VCC RANGE: FOR VCO LINEARITY f0 = (f1 + f2) / 2 LINEARITY = (f0 - f0) / f0) x 100% Figure 15A. Frequency Linearity versus R1, C1 and VCC Figure 15B. Definition of VCO Frequency Linearity http://onsemi.com 11 MC74HC4046A 106 106 CL=50pF; R2=; VVCOIN=1/2 VCC FOR VCC=4.5V AND 6.0V; CL=50pF; R1=; VVCOIN=0V; Tamb=25C VVCOIN=1/3 VCC FOR VCC=3.0V; Tamb=25C VCC=6.0V, C1=40pF VCC=6.0V, C1=1.0 mF 104 PR2 ( W) 105 PR1 ( W) 105 VCC=6.0V, C1=40pF VCC=6.0V, C1=1.0 mF 104 VCC=4.5V, C1=40pF VCC=4.5V, C1=1.0 mF VCC=4.5V, C1=40pF VCC=4.5V, C1=1.0 mF VCC=3.0V, C1=40pF VCC=3.0V, C1=1.0 mF VCC=3.0V, C1=1.0 mF 103 100 101 R1 (kW) 102 100 103 101 Figure 16. Power Dissipation versus R1 VCC= 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V R1=R2=; Tamb=25C 107 102 103 106 VCO (Hz) 102 VCC=6.0 V 105 INH=GND; Tamb=25C; R2=; VVCOIN=1/3 VCC R1=3.0kW f PDEM ( W) R2 (kW) Figure 17. Power Dissipation versus R2 108 103 VCC=3.0V, C1=40pF 103 VCC=4.5 V 104 101 R1=100kW VCC=3.0 V 103 R1=300kW 100 101 102 RS (kW) 102 103 101 105 VVCOIN=1/3 VCC FOR VCC=3.0V; INH=GND; Tamb=25C 6.0 V 4.5 V 3.0 V 104 105 106 VCC=4.5V; R2= 107 f off (Hz) 106 104 108 R1=; VVCOIN=1/2 VCC FOR VCC=4.5V AND 6.0V; 2 fL (Hz) 107 VCC= 6.0 V 4.5 V 3.0 V 6.0 V 4.5 V 3.0 V 103 C1 (pF) Figure 19. VCO Center Frequency versus C1 Figure 18. DC Power Dissipation of Demodulator versus RS 108 102 106 105 R2=3.0kW 104 103 R2=100kW 102 101 103 R2=300kW 101 102 103 104 105 102 106 10-7 C1 (pF) 10-6 10-5 10-4 10-3 10-2 10-1 R1C1 Figure 20. Frequency Offset versus C1 Figure 21. Typical Frequency Lock Range (2fL) versus R1C1 http://onsemi.com 12 MC74HC4046A 20 14 R1=3.0kW C1=39pF 12 R1=10kW 10 FREQ. (MHz) R1=20kW R1=30kW 10 R1=40kW 8.0 R1=3kW R1=10kW R1=20kW R1=30kW R1=40kW R1=50kW R1=100kW R1=300kW 6.0 4.0 R1=50kW 5.0 2.0 R1=100kW 0 C1=39pF R1=300kW 0 -2.0 1.0 101 102 103 104 100 105 101 102 103 R2 (kW) 104 R2 (kW) Figure 22. R2 versus fmax Figure 23. R2 versus fmin 20 C1=39pF 2f L (MHz) FREQ. (MHz) 15 R1=10kW R1=3.0kW R1=20kW 10 R1=30kW R1=40kW R1=50kW R1=100kW R1=300kW 0 1.0 101 102 R2 (kW) 103 104 105 Figure 24. R2 versus Frequency Lock Range (2fL) http://onsemi.com 13 105 106 MC74HC4046A APPLICATION INFORMATION The following information is a guide for approximate values of R1, R2, and C1. Figures 20, 21, and 22 should be used as references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC ELECTRICAL CHARACTERISTICS tables. Phase Comparator 1 R2 = R2 0 R Phase Comparator 2 R2 = R2 0 R Phase Comparator 3 R2 = R2 0 R * Given f0 * Given f0 and fL * Given fmax and f0 * Given f0 and fL * Given fmax and f0 * Given f0 and fL * Use f0 with Figure 19 to determine R1 and C1. * Calculate fmin fmin = f0-fL * Determine the value of R1 and C1 using Figure 20 and use Figure 22 to obtain 2fL and then use this to calculate fmin. * Calculate fmin fmin = f0-fL * Determine the value of R1 and C1 using Figure 20 and Figure 22 to obtain 2fL and then use this to calculate fmin. * Calculate fmin: fmin = f0-fL (see Figure 24 for characteristics of the VCO operation) * Determine values of C1 and R2 from Figure 21. * Determine R1-C1 from Figure 22. * Determine values of C1 and R2 from Figure 21. * Determine R1-C1 from Figure 22. * Determine values of C1 and R2 from Figure 21. * Determine R1-C1 from Figure 22. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 22. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 22. * Calculate value of R1 from the value of C1 and the product of R1C1 from Figure 22. (see Figure 25 for characteristics of the VCO operation) (see Figure 25 for characteristics of the VCO operation) (see Figure 25 for characteristics of the VCO operation) http://onsemi.com 14 MC74HC4046A PACKAGE DIMENSIONS PDIP-16 CASE 648-08 ISSUE T NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. -A- 16 9 1 8 B F C L S -T- H SEATING PLANE K G D M J 16 PL 0.25 (0.010) M T A M http://onsemi.com 15 DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 MC74HC4046A PACKAGE DIMENSIONS SOIC-16 CASE 751B-05 ISSUE K -A- 16 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 9 -B- 1 P 8 PL 0.25 (0.010) 8 B M S G R K F X 45 _ C -T- SEATING PLANE J M D 16 PL 0.25 (0.010) M T B S A S SOLDERING FOOTPRINT 8X 6.40 16X 1 1.12 16 16X 0.58 1.27 PITCH 8 9 DIMENSIONS: MILLIMETERS http://onsemi.com 16 DIM A B C D F G J K M P R MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 MC74HC4046A PACKAGE DIMENSIONS TSSOP-16 CASE 948F-01 ISSUE B 16X K REF 0.10 (0.004) 0.15 (0.006) T U M T U S V S K S EEE CCC CCC EEE K1 2X L/2 16 9 J1 B -U- L SECTION N-N J PIN 1 IDENT. N 8 1 0.25 (0.010) M 0.15 (0.006) T U S A -V- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH. PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. N F DETAIL E -W- C 0.10 (0.004) -T- SEATING PLANE D H G DETAIL E DIM A B C D F G H J J1 K K1 L M SOLDERING FOOTPRINT 7.06 1 0.65 PITCH 16X 0.36 16X 1.26 DIMENSIONS: MILLIMETERS http://onsemi.com 17 MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.18 0.28 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.007 0.011 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ MC74HC4046A PACKAGE DIMENSIONS SOEIAJ-16 CASE 966-01 ISSUE A 16 LE 9 Q1 E HE 1 M_ L 8 Z DETAIL P D e VIEW P A DIM A A1 b c D E e HE L LE M Q1 Z A1 b 0.13 (0.005) c M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS AND ARE MEASURED AT THE PARTING LINE. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEAD WIDTH DIMENSION (b) DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0.46 ( 0.018). 0.10 (0.004) MILLIMETERS MIN MAX --2.05 0.05 0.20 0.35 0.50 0.10 0.20 9.90 10.50 5.10 5.45 1.27 BSC 7.40 8.20 0.50 0.85 1.10 1.50 10 _ 0_ 0.70 0.90 --0.78 INCHES MIN MAX --0.081 0.002 0.008 0.014 0.020 0.007 0.011 0.390 0.413 0.201 0.215 0.050 BSC 0.291 0.323 0.020 0.033 0.043 0.059 10 _ 0_ 0.028 0.035 --0.031 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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