MC74HC4046ADR2 - ON Semiconductor

May, 2011 − Rev. 9

1Publication Order Number:

MC74HC4046A/D

MC74HC4046A

Phase-Locked Loop

High−Performance Silicon−Gate CMOS

The MC74HC4046A is similar in function to the MC14046 Metal

gate CMOS device. The device inputs are compatible with standard

CMOS outputs; with pullup resistors, they are compatible with

LSTTL outputs.

The HC4046A phase−locked loop contains three phase

comparators, a voltage−controlled oscillator (VCO) and unity gain

op−amp DEMOUT

. The comparators have two common signal inputs,

COMPIN, and SIGIN. Input SIGIN and COMPIN can be used directly

coupled to large voltage signals, or indirectly coupled (with a series

capacitor to small voltage signals). The self−bias circuit adjusts small

voltage signals in the linear region of the amplifier. Phase comparator

1 (an exclusive OR gate) provides a digital error signal PC1OUT and

maintains 90 degrees phase shift at the center frequency between

SIGIN and COMPIN signals (both at 50% duty cycle). Phase

comparator 2 (with leading−edge sensing logic) provides digital error

signals PC2OUT and PCPOUT and maintains a 0 degree phase shift

between SIGIN and COMPIN signals (duty cycle is immaterial). The

linear VCO produces an output signal VCOOUT whose frequency is

determined by the voltage of input VCOIN signal and the capacitor

and resistors connected to pins C1A, C1B, R1 and R2. The unity gain

op−amp output DEMOUT with an external resistor is used where the

VCOIN signal is needed but no loading can be tolerated. The inhibit

input, when high, disables the VCO and all op−amps to minimize

standby power consumption.

Applications include FM and FSK modulation and demodulation,

frequency synthesis and multiplication, frequency discrimination,

tone decoding, data synchronization and conditioning,

voltage−to−frequency conversion and motor speed control.

Features

•Output Drive Capability: 10 LSTTL Loads

•Low Power Consumption Characteristic of CMOS Devices

•Operating Speeds Similar to LSTTL

•Wide Operating Voltage Range: 3.0 to 6.0 V

•Low Input Current: 1.0 mA Maximum (except SIGIN and COMPIN)

•In Compliance with the Requirements Defined by JEDEC Standard

No. 7 A

•Low Quiescent Current: 80 mA Maximum (VCO disabled)

•High Noise Immunity Characteristic of CMOS Devices

•Diode Protection on all Inputs

•Chip Complexity: 279 FETs or 70 Equivalent Gates

•These Devices are Pb−Free, Halogen Free and are RoHS Compliant

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MARKING

DIAGRAMS

SOIC−16

D SUFFIX

CASE 751B

TSSOP−16

DT SUFFIX

CASE 948F

16 PDIP−16

N SUFFIX

CASE 648

MC74HC4046AN

AWLYYWWG

HC4046AG

AWLYWW

HC40

46A

ALYWG

See detailed ordering and shipping information in the package

dimensions section on page 5 of this data sheet.

ORDERING INFORMATION

74HC4046A

ALYWG

SOEIAJ−16

F SUFFIX

CASE 966

A = Assembly Location

L, WL = Wafer Lot

Y, YY = Year

W, WW = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

MC74HC4046A

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Pin No. Symbol Name and Function

PCPOUT

PC1OUT

COMPIN

VCOOUT

INH

C1A

C1B

GND

VCOIN

DEMOUT

PC2OUT

SIGIN

PC3OUT

VCC

Phase Comparator Pulse Output

Phase Comparator 1 Output

Comparator Input

VCO Output

Inhibit Input

Capacitor C1 Connection A

Capacitor C1 Connection B

Ground (0 V) VSS

VCO Input

Demodulator Output

Resistor R1 Connection

Resistor R2 Connection

Phase Comparator 2 Output

Signal Input

Phase Comparator 3 Output

Positive Supply Voltage

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage (Referenced to GND)

ÎÎÎÎÎ

– 1.5 to VCC + 1.5

ÎÎÎ

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage (Referenced to GND)

ÎÎÎÎÎ

– 0.5 to VCC + 0.5

ÎÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Current, per Pin

ÎÎÎÎÎ

±20

ÎÎÎ

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±50

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air Plastic DIP†

SOIC Package†

ÎÎÎÎÎ

750

500

ÎÎÎ

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Lead Temperature, 1 mm from Case for 10 Seconds

Plastic DIP and SOIC Package†

ÎÎÎÎÎ

260

ÎÎÎ

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are not

valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C

SOIC Package: – 7 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage (Referenced to GND)

ÎÎÎ

3.0

ÎÎÎ

6.0

ÎÎÎ

VCC DC Supply Voltage (Referenced to GND) NON−VCO 2.0 6.0 V

ÎÎÎÎ

Vin, Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage, Output Voltage (Referenced to GND)

ÎÎÎ

VCC

ÎÎÎ

ÎÎÎÎ

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature, All Package Types

ÎÎÎ

– 55

ÎÎÎ

+ 125

ÎÎÎ

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC = 2.0 V

(Pin 5) VCC = 4.5 V

VCC = 6.0 V

ÎÎÎ

1000

500

400

ÎÎÎ

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

Figure 1. Pin Assignment

125

PC2out

SIGin

PC3out

VCC

VCOin

DEMout

VCOout

COMPin

PC1out

PCPout

GND

C1B

C1A

INH

MC74HC4046A

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[Phase Comparator Section]

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol Parameter Test Conditions

VCC

Guaranteed Limit

Unit

– 55 to

25_C≤85°C≤125°C

VIH Minimum High−Level Input

Voltage DC Coupled

SIGIN, COMPIN

Vout = 0.1 V or VCC − 0.1 V

|Iout| ≤ 20 mA

2.0

4.5

6.0

1.5

3.15

4.2

1.5

3.15

4.2

1.5

3.15

4.2

VIL Maximum Low−Level Input

Voltage DC Coupled

SIGIN, COMPIN

Vout = 0.1 V or VCC − 0.1 V

|Iout| ≤ 20 mA

2.0

4.5

6.0

0.5

1.35

1.8

0.5

1.35

1.8

0.5

1.35

1.8

VOH Minimum High−Level

Output Voltage

PCPOUT

, PCnOUT

Vin = VIH or VIL

|Iout| ≤ 20 mA

2.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin = VIH or VIL

|Iout| ≤ 4.0 mA

|Iout| ≤ 5.2 mA 4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

VOL Maximum Low−Level

Output Voltage Qa−Qh

PCPOUT

, PCnOUT

Vout = 0.1 V or VCC − 0.1 V

|Iout| ≤ 20 mA

2.0

4.5

6.0

0.1

Vin = VIH or VIL

|Iout| ≤ 4.0 mA

|Iout| ≤ 5.2 mA 4.5

6.0

0.26

0.33

0.4

Iin Maximum Input Leakage Current

SIGIN, COMPIN

Vin = VCC or GND 2.0

3.0

4.5

6.0

±3.0

±7.0

±18.0

±30.0

±4.0

±9.0

±23.0

±38.0

±5.0

±11.0

±27.0

±45.0

IOZ Maximum Three−State

Leakage Current

PC2OUT

Output in High−Impedance State

Vin = VIH or VIL

Vout = VCC or GND

6.0 ±0.5 ±5.0 ±10 mA

ICC Maximum Quiescent Supply Current

(per Package) (VCO disabled)

Pins 3, 5 and 14 at VCC

Pin 9 at GND; Input Leakage at

Pins 3 and 14 to be excluded

Vin = VCC or GND

|Iout| = 0 mA

6.0 4.0 40 160 mA

[Phase Comparator Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol Parameter

VCC

Guaranteed Limit

Unit

– 55 to

25_C≤ 85°C≤ 125°C

tPLH,

tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PC1OUT

(Figure 2)

2.0

4.5

6.0

175

220

265

tPLH,

tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PCPOUT

(Figure 2)

2.0

4.5

6.0

340

425

510

102

tPLH,

tPHL

Maximum Propagation Delay, SIGIN/COMPIN to PC3OUT

(Figure 2)

2.0

4.5

6.0

270

340

405

tPLZ,

tPHZ

Maximum Propagation Delay, SIGIN/COMPIN Output

Disable Time to PC2OUT (Figures 3 and 4)

2.0

4.5

6.0

200

250

300

tPZH,

tPZL

Maximum Propagation Delay, SIGIN/COMPIN Output

Enable Time to PC2OUT (Figures 3 and 4)

2.0

4.5

6.0

230

290

345

tTLH,

tTHL

Maximum Output Transition Time

(Figure 2)

2.0

4.5

6.0

110

MC74HC4046A

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[VCO Section]

DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)

Symbol Parameter Test Conditions

VCC

Guaranteed Limit

Unit

– 55 to

25_C≤85°C≤125°C

VIH Minimum High−Level

Input Voltage

INH

Vout = 0.1 V or VCC − 0.1 V

|Iout| ≤ 20 mA

3.0

4.5

6.0

2.1

3.15

4.2

2.1

3.15

4.2

2.1

3.15

4.2

VIL Maximum Low−Level

Input Voltage

INH

Vout = 0.1 V or VCC − 0.1 V

|Iout| ≤ 20 mA

3.0

4.5

6.0

0.90

1.35

1.8

0.9

1.35

1.8

0.9

1.35

1.8

VOH Minimum High−Level

Output Voltage

VCOOUT

Vin =V

IH or VIL

|Iout| ≤ 20 mA

3.0

4.5

6.0

1.9

4.4

5.9

1.9

4.4

5.9

1.9

4.4

5.9

Vin =V

IH or VIL

|Iout| ≤ 4.0 mA

|Iout| ≤ 5.2 mA

4.5

6.0

3.98

5.48

3.84

5.34

3.7

5.2

VOL Maximum Low−Level

Output Voltage

VCOOUT

Vout = 0.1 V or VCC − 0.1 V

|Iout| ≤ 20 mA

3.0

4.5

6.0

0.1

Vin =V

IH or VIL

|Iout| ≤ 4.0 mA

|Iout| ≤ 5.2 mA

4.5

6.0

0.26

0.33

0.4

Iin Maximum Input Leakage

Current INH, VCOIN

Vin =V

CC or GND 6.0 0.1 1.0 1.0 mA

Min Max Min Max Min Max

VVCO IN Operating Voltage Range at

VCOIN over the range

specified for R1; For linearity

see Fig. 15A, Parallel value of

R1 and R2 should be > 2.7 kW

INH = VIL 3.0

4.5

6.0

0.1

1.0

2.5

4.0

0.1

1.0

2.5

4.0

0.1

1.0

2.5

4.0

R1 Resistor Range 3.0

4.5

6.0

3.0

300

3.0

300

3.0

300

R2 3.0

4.5

6.0

3.0

300

3.0

300

3.0

300

C1 Capacitor Range 3.0

4.5

6.0

Limit

[VCO Section]

AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6.0 ns)

Symbol Parameter

VCC

Guaranteed Limit

Unit

– 55 to

25_C≤85°C≤125°C

Min Max Min Max Min Max

Df/T Frequency Stability with

Temperature Changes

(Figure 14A, B, C)

3.0

4.5

6.0

%/K

fo VCO Center Frequency

(Duty Factor = 50%)

(Figure 15A, B, C, D)

3.0

4.5

6.0

MHz

DfVCO VCO Frequency Linearity 3.0

4.5

6.0

See Figures 16A, B, C %

∂ VCO Duty Factor at VCOOUT 3.0

4.5

6.0

Typical 50% %

MC74HC4046A

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[Demodulator Section]

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Conditions

VCC

Guaranteed Limit

Unit

– 55 to

25_C≤85°C≤125°C

Min Max Min Max Min Max

RS Resistor Range At RS > 300 kW the

Leakage Current can

Influence VDEMOUT

3.0

4.5

6.0

300

VOFF Offset Voltage

VCOIN to VDEMOUT

Vi = VVCOIN = 1/2 VCC;

Values taken over RS

Range.

3.0

4.5

6.0

See Figure 13 mV

RD Dynamic Output

Resistance at DEMOUT

VDEMOUT = 1/2 VCC 3.0

4.5

6.0

Typical 25 W W

ORDERING INFORMATION

Device Package Shipping†

MC74HC4046ANG PDIP−16

(Pb−Free)

2000 Units / Box

MC74HC4046ADG SOIC−16

(Pb−Free)

48 Units / Rail

MC74HC4046ADR2G SOIC−16

(Pb−Free)

2500 Units / Reel

MC74HC4046ADTG TSSOP−16* 96 Units / Rail

MC74HC4046ADTR2G TSSOP−16* 2500 Units / Reel

MC74HC4046AFG SOEIAJ−16

(Pb−Free)

50 Units / Rail

MC74HC4046AFELG SOEIAJ−16

(Pb−Free)

2000 Units / Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

MC74HC4046A

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SWITCHING WAVEFORMS

SIGIN, COMPIN

INPUTS 50%

90%

50%

10%

PCPOUT, PC1OUT

PC3OUT

OUTPUTS

VCC

GND

tPHL tPLH

tTLH

tTHL

SIGIN

INPUT

COMPIN

INPUT

50%

90%

50%

PC2OUT

OUTPUT

VCC

GND

tPZH tPHZ

50%

VCC

GND

VOH

HIGH

IMPEDANCE

SIGIN

INPUT

COMPIN

INPUT

50%

10%

PC2OUT

OUTPUT

VCC

GND

tPZL tPLZ

50%

VCC

GND

VOL

HIGH

IMPEDANCE

TEST POINT

CL*

OUTPUT

DEVICE

UNDER

TEST

*INCLUDES ALL PROBE AND JIG CAPACITANCE

50%

Figure 2. Figure 3.

Figure 4. Figure 5. Test Circuit

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DETAILED CIRCUIT DESCRIPTION

Voltage Controlled Oscillator/Demodulator Output

The VCO requires two or three external components to

operate. These are R1, R2, C1. Resistor R1 and Capacitor C1

are selected to determine the center frequency of the VCO

(see typical performance curves Figure 15). R2 can be used

to set the offset frequency with 0 volts at VCO input. For

example, if R2 is decreased, the offset frequency is

increased. If R2 is omitted the VCO range is from 0 Hz. The

effect of R2 is shown in Figure 25, typical performance

curves. By increasing the value of R2 the lock range of the

PLL is increased and the gain (volts/Hz) is decreased. Thus,

for a narrow lock range, large swings on the VCO input will

cause less frequency variation.

Internally, the resistors set a current in a current mirror, as

shown in Figure 6. The mirrored current drives one side of

the capacitor. Once the voltage across the capacitor charges

up to Vref of the comparators, the oscillator logic flips the

capacitor which causes the mirror to charge the opposite side

of the capacitor. The output from the internal logic is then

taken to VCO output (Pin 4).

The input to the VCO is a very high impedance CMOS

input and thus will not load down the loop filter, easing the

filters design. In order to make signals at the VCO input

accessible without degrading the loop performance, the

VCO input voltage is buffered through a unity gain Op−amp

to Demod Output. This Op−amp can drive loads of 50K

ohms or more and provides no loading effects to the VCO

input voltage (see Figure 13).

An inhibit input is provided to allow disabling of the VCO

and all Op−amps (see Figure 6). This is useful if the internal

VCO is not being used. A logic high on inhibit disables the

VCO and all Op−amps, minimizing standby power

consumption.

Figure 6. Logic Diagram for VCO

VREF

VCOIN

Vref

(EXTERNAL)

DEMODOUT

CURRENT

MIRROR

I1 + I2 = I3

VCOOUT

INH

−

The output of the VCO is a standard high speed CMOS

output with an equivalent LS−TTL fan out of 10. The VCO

output is approximately a square wave. This output can

either directly feed the COMPIN of the phase comparators or

feed external prescalers (counters) to enable frequency

synthesis.

MC74HC4046A

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Phase Comparators

All three phase comparators have two inputs, SIGIN and

COMPIN. The SIGIN and COMPIN have a special DC bias

network that enables AC coupling of input signals. If the

signals are not AC coupled, standard 74HC input levels are

required. Both input structures are shown in Figure 7. The

outputs of these comparators are essentially standard 74HC

outputs (comparator 2 is TRI−STATEABLE). In normal

operation VCC and ground voltage levels are fed to the loop

filter. This differs from some phase detectors which supply

a current to the loop filter and should be considered in the

design. (The MC14046 also provides a voltage).

Figure 7. Logic Diagram for Phase Comparators

SIGIN

COMPIN

VCC VCC

VCC

PC2OUT

PCPOUT

PC3OUT

PC1OUT

Phase Comparator 1

This comparator is a simple XOR gate similar to the

74HC86. Its operation is similar to an overdriven balanced

modulator. To maximize lock range the input frequencies

must have a 50% duty cycle. Typical input and output

waveforms are shown in Figure 8. The output of the phase

detector feeds the loop filter which averages the output

voltage. The frequency range upon which the PLL will lock

onto if initially out of lock is defined as the capture range.

The capture range for phase detector 1 is dependent on the

loop filter design. The capture range can be as large as the

lock range, which is equal to the VCO frequency range.

To see how the detector operates, refer to Figure 8. When

two square wave signals are applied to this comparator, an

output waveform (whose duty cycle is dependent on the

phase difference between the two signals) results. As the

phase difference increases, the output duty cycle increases

and the voltage after the loop filter increases. In order to

achieve lock when the PLL input frequency increases, the

VCO input voltage must increase and the phase difference

between COMPIN and SIGIN will increase. At an input

frequency equal to fmin, the VCO input is at 0 V. This

requires the phase detector output to be grounded; hence, the

two input signals must be in phase. When the input

frequency is fmax, the VCO input must be VCC and the phase

detector inputs must be 180 degrees out of phase.

Figure 8. Typical Waveforms for PLL Using

Phase Comparator 1

VCC

GND

SIGIN

COMPIN

PC1OUT

VCOIN

The XOR is more susceptible to locking onto harmonics

of the SIGIN than the digital phase detector 2. For instance,

a signal 2 times the VCO frequency results in the same

output duty cycle as a signal equal to the VCO frequency.

The difference is that the output frequency of the 2f example

is twice that of the other example. The loop filter and VCO

range should be designed to prevent locking on to

harmonics.

MC74HC4046A

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Phase Comparator 2

This detector is a digital memory network. It consists of

four flip−flops and some gating logic, a three state output

and a phase pulse output as shown in Figure 6. This

comparator acts only on the positive edges of the input

signals and is independent of duty cycle.

Phase comparator 2 operates in such a way as to force the

PLL into lock with 0 phase difference between the VCO

output and the signal input positive waveform edges. Figure

8 shows some typical loop waveforms. First assume that

SIGIN is leading the COMPIN. This means that the VCO’s

frequency must be increased to bring its leading edge into

proper phase alignment. Thus the phase detector 2 output is

set high. This will cause the loop filter to charge up the VCO

input, increasing the VCO frequency. Once the leading edge

of the COMPIN is detected, the output goes TRI−STATE

holding the VCO input at the loop filter voltage. If the VCO

still lags the SIGIN then the phase detector will again charge

up the VCO input for the time between the leading edges of

both waveforms.

If the VCO leads the SIGIN then when the leading edge of

the VCO is seen; the output of the phase comparator goes

low. This discharges the loop filter until the leading edge of

the SIGIN is detected at which time the output disables itself

again. This has the effect of slowing down the VCO to again

make the rising edges of both waveforms coincidental.

When the PLL is out of lock, the VCO will be running

either slower or faster than the SIGIN. If it is running slower

the phase detector will see more SIGIN rising edges and so

the output of the phase comparator will be high a majority

of the time, raising the VCO’s frequency. Conversely, if the

VCO is running faster than the SIGIN, the output of the

detector will be low most of the time and the VCO’s output

frequency will be decreased.

As one can see, when the PLL is locked, the output of

phase comparator 2 will be disabled except for minor

corrections at the leading edge of the waveforms. When PC2

is TRI−STATED, the PCP output is high. This output can be

used to determine when the PLL is in the locked condition.

This detector has several interesting characteristics. Over

the entire VCO frequency range there is no phase difference

between the COMPIN and the SIGIN. The lock range of the

PLL is the same as the capture range. Minimal power was

consumed in the loop filter since in lock the detector output

is a high impedance. When no SIGIN is present, the detector

will see only VCO leading edges, so the comparator output

will stay low, forcing the VCO to fmin.

Phase comparator 2 is more susceptible to noise, causing

the PLL to unlock. If a noise pulse is seen on the SIGIN, the

comparator treats it as another positive edge of the SIGIN

and will cause the output to go high until the VCO leading

edge is seen, potentially for an entire SIGIN period. This

would cause the VCO to speed up during that time. When

using PC1, the output of that phase detector would be

disturbed for only the short duration of the noise spike and

would cause less upset.

Phase Comparator 3

This is a positive edge−triggered sequential phase

detector using an RS flip−flop as shown in Figure 7. When

the PLL is using this comparator, the loop is controlled by

positive signal transitions and the duty factors of SIGIN and

COMPIN are not important. It has some similar

characteristics to the edge sensitive comparator. To see how

this detector works, assume input pulses are applied to the

SIGIN and COMPIN’s as shown in Figure 10. When the

SIGIN leads the COMPIN, the flop is set. This will charge the

loop filter and cause the VCO to speed up, bringing the

comparator into phase with the SIGIN. The phase angle

between SIGIN and COMPIN varies from 0° to 360° and is

180° at fo. The voltage swing for PC3 is greater than for PC2

but consequently has more ripple in the signal to the VCO.

When no SIGIN is present the VCO will be forced to fmax as

opposed to fmin when PC2 is used.

The operating characteristics of all three phase

comparators should be compared to the requirements of the

system design and the appropriate one should be used.

Figure 9. Typical Waveforms for PLL Using

Phase Comparator 2

VCC

GND

SIGIN

COMPIN

PC2OUT

VCOIN

PCPOUT

HIGH IMPEDANCE OFF-STATE

Figure 10. Typical Waveform for PLL Using

Phase Comparator 3

VCC

GND

SIGIN

COMPIN

PC3OUT

VCOIN

MC74HC4046A

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Figure 11. Input Resistance at SIGIN, COMPIN with

DVI = 1.0 V at Self−Bias Point

Figure 12. Input Current at SIGIN, COMPIN with

DVI = 500 mV at Self−Bias Point

Figure 13. Offset Voltage at Demodulator Output as

a Function of VCOIN and RS

Figure 13A. Frequency Stability versus Ambient

Temperature: VCC = 3.0 V

800

VCC=3.0 V

VCC=4.5 V

VCC=6.0 V

1/2 VCC-1.0 V 1/2 VCC

4.0

-4.0

1/2VCC - 500 mV

VI (V)

1/2 VCC 1/2 VCC + 500 mV

6.0

03.0 6.0

VCC=4.5 V RS=300k

VCC=4.5 V RS=50k

VCC=3.0 V RS=300k

VCC=3.0 V RS=50k

DEMOD OUT

5.0

-5.0

-10

-15

-100 -50 0 50 100 150

R1=100kW

R1=300kW

R1=3.0kW

R1=100kW

R1=300kW

R1=3.0kW

VCC = 3.0 V

C1=100pF; R2=∞; VVCOIN=1/3VCC

FREQUENCY STABILITY (%)

AMBIENT TEMPERATURE (°C)

VCC=3.0 V

VCC=4.5 V

VCC=6.0 V

RIΩ)(k

400

II(A)μ

VDEMOUT

VCC=6.0 V RS=300k

VCC=6.0 V RS=50k

Figure 13B. Frequency Stability versus Ambient

Temperature: VCC = 4.5 V

Figure 13C. Frequency Stability versus Ambient

Temperature: VCC = 6.0 V

R1=100kW

R1=300kW

R1=3.0kW

5.0

-5.0

-10

-15

-100 -50 0 50 100 150

VCC=4.5 V

C1=100pF; R2=∞; VVCOIN=1/2VCC

AMBIENT TEMPERATURE (°C)

FREQUENCY STABILITY (%)

R1=100kW

R1=3.0kW

6.0

4.0

-2.0

-10

-100 -50 0 50 100 150

VCC=6.0 V

C1=100pF; R2=∞; VVCOIN=1/2VCC

AMBIENT TEMPERATURE (°C)

-8.0

-6.0

-4.0

2.0

8.0

R1=300kW

1/2 VCC+1.0 V

VI (V)

VCOIN (V)

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Figure 14A. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)

Figure 14B. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 3.0 kW

C1 = 39 pF

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

7.0

VVCOIN (V)

(MHz)fVCO

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

VVCOIN (V)

(KHz)fVCO

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 3.0 kW

C1 = 0.1 mF

Figure 14C. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)

Figure 14D. VCO Frequency (fVCO) as a Function

of the VCO Input Voltage (VVCOIN)

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

2.0

1.0

VVCOIN (V)

(MHz)fVCO

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 300 kW

C1 = 39 pF

4.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

1.0

VVCOIN (V)

(KHz)fVCO

4.5

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

VCC = 6.0 V

VCC = 4.5 V

VCC = 3.0 V

R1 = 300 kW

C1 = 0.1 mF

Figure 15A. Frequency Linearity versus

R1, C1 and VCC

Figure 15B. Definition of VCO Frequency Linearity

ΔfVCO (%)

2.0

1.0

-2.0

-1.0

100101102103

R1 (kW)

R2 = ∞; DV = 0.5 V

C1 = 39 pF

C1 = 1.0 mF

f0′

MIN 1/2 VCC MAX

DV = 0.5 V OVER THE VCC RANGE:

FOR VCO LINEARITY

f0′ = (f1 + f2) / 2

LINEARITY = (f0′ - f0) / f0′) x 100%

VCC=

4.5 V

6.0 V

3.0 V

4.5 V

6.0 V

3.0 V

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Figure 16. Power Dissipation versus R1 Figure 17. Power Dissipation versus R2

Figure 18. DC Power Dissipation of

Demodulator versus RS

Figure 19. VCO Center Frequency versus C1

R1 (kW)

105

104

103

100101102103

PR1 W)μ(

VCC=6.0V, C1=40pF

VCC=6.0V, C1=1.0 mF

VCC=4.5V, C1=40pF

VCC=3.0V, C1=40pF

VCC=3.0V, C1=1.0 mF

CL=50pF; R2=∞; VVCOIN=1/2 VCC FOR VCC=4.5V AND 6.0V;

VVCOIN=1/3 VCC FOR VCC=3.0V; Tamb=25°C

VCC=6.0V, C1=40pF

VCC=6.0V, C1=1.0 mF

VCC=4.5V, C1=40pF

VCC=4.5V, C1=1.0 mF

VCC=3.0V, C1=1.0 mF

CL=50pF; R1=∞; VVCOIN=0V; Tamb=25°C

105

104

103

100101102103

R2 (kW)

PR2 W)μ(

PDEM (W)μ

RS (kW)

103

102

101

100

101102103

R1=R2=∞; Tamb=25°C

VCC=6.0 V

VCC=4.5 V

VCC=3.0 V

101102103104105106

C1 (pF)

6.0 V

4.5 V

3.0 V

6.0 V

4.5 V

3.0 V

VCC= INH=GND; Tamb=25°C; R2=∞; VVCOIN=1/3 VCC

R1=3.0kW

R1=100kW

R1=300kW

fVCO (Hz)

108

107

106

105

104

103

102

VCC=3.0V, C1=40pF

6.0 V

4.5 V

3.0 V

Figure 20. Frequency Offset versus C1 Figure 21. Typical Frequency Lock Range (2fL)

versus R1C1

foff (Hz)

108

107

106

105

104

103

102

101

C1 (pF)

101102103104105106

6.0 V

4.5 V

3.0 V

6.0 V

4.5 V

3.0 V

6.0 V

4.5 V

3.0 V

VCC= 108

107

106

105

104

103

102

2fL (Hz)

10-7 10-6 10-5 10-4 10-3 10-2 10-1

R1C1

R1=∞; VVCOIN=1/2 VCC FOR VCC=4.5V AND 6.0V;

VVCOIN=1/3 VCC FOR VCC=3.0V; INH=GND; Tamb=25°C

R2=3.0kW

R2=100kW

R2=300kW

VCC=4.5V; R2=∞

MC74HC4046A

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Figure 22. R2 versus fmax Figure 23. R2 versus fmin

Figure 24. R2 versus Frequency Lock Range (2fL)

FREQ. (MHz)

1.0 101104105

102103

5.0

C1=39pF

R2 (kW)

100101104105106

C1=39pF

102103

-2.0

4.0

2.0

6.0

8.0

FREQ. (MHz)

R2 (kW)

R1=10kW

R1=3kW

R1=20kW

R1=30kW

R1=40kW

R1=50kW

R1=100kW

R1=300kW

R1=3.0kW

R1=20kW

R1=30kW

R1=100kW

R1=300kW

R1=50kW

R2 (kW)

1.0 101102103104105

C1=39pF

R1=10kW

R1=3.0kW

R1=20kW

R1=30kW

R1=40kW

R1=50kW

R1=100kW

R1=300kW

R1=40kW

L(MHz)

R1=10kW

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APPLICATION INFORMATION

The following information is a guide for approximate values of R1, R2, and C1. Figures 20, 21, and 22 should be used as

references as indicated below, also the values of R1, R2, and C1 should not violate the Maximum values indicated in the DC

ELECTRICAL CHARACTERISTICS tables.

Phase Comparator 1 Phase Comparator 2 Phase Comparator 3

R2 = ∞R2 0 RR2 = ∞R2 0 RR2 = ∞R2 0 R

• Given f0

• Use f0 with

Figure 19 to

determine R1 and

C1.

(see Figure 24 for

characteristics of

the VCO operation)

• Given f0 and fL

• Calculate fmin

fmin = f0−fL

• Determine values

of C1 and R2 from

Figure 21.

• Determine R1−C1

from Figure 22.

• Calculate value of

R1 from the value

of C1 and the

product of R1C1

from Figure 22.

(see Figure 25 for

characteristics of

the VCO operation)

• Given fmax and f0

• Determine the

value of R1 and

C1 using Figure

20 and use Figure

22 to obtain 2fL

and then use this

to calculate fmin.

• Given f0 and fL

• Calculate fmin

fmin = f0−fL

• Determine values

of C1 and R2 from

Figure 21.

• Determine R1−C1

from Figure 22.

• Calculate value of

R1 from the value

of C1 and the

product of R1C1

from Figure 22.

(see Figure 25 for

characteristics of

the VCO operation)

• Given fmax and f0

• Determine the

value of R1 and

C1 using Figure

20 and Figure 22

to obtain 2fL and

then use this to

calculate fmin.

• Given f0 and fL

• Calculate fmin:

fmin = f0−fL

• Determine values

of C1 and R2 from

Figure 21.

• Determine R1−C1

from Figure 22.

• Calculate value of

R1 from the value

of C1 and the

product of R1C1

from Figure 22.

(see Figure 25 for

characteristics of

the VCO operation)

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PACKAGE DIMENSIONS

PDIP−16

CASE 648−08

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

16 PL

SEATING

916

PLANE

−T−

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

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PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

16 9

SEATING

PLANE

RX 45_

8 PLP

−B−

−A−

0.25 (0.010) B S

−T−

16 PL

0.25 (0.010) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

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PACKAGE DIMENSIONS

TSSOP−16

CASE 948F−01

ISSUE B

ÇÇÇ

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A4.90 5.10 0.193 0.200

B4.30 4.50 0.169 0.177

C−−− 1.20 −−− 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.18 0.28 0.007 0.011

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL

NOT EXCEED 0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

____

SECTION N−N

SEATING

PLANE

IDENT.

PIN 1

16 9

DETAIL E

ÉÉÉ

DETAIL E

2X L/2

−U−

U0.15 (0.006) T

0.10 (0.004) V S

0.10 (0.004)

−T−

−V−

−W−

0.25 (0.010)

16X REFK

7.06

16X

0.36 16X

1.26

0.65

DIMENSIONS: MILLIMETERS

PITCH

SOLDERING FOOTPRINT

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PACKAGE DIMENSIONS

SOEIAJ−16

CASE 966−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

DETAIL P

VIEW P

0.13 (0.005) 0.10 (0.004)

16 9

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

MC74HC4046A/D

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