dsPIC30F3012/3013 dsPIC30F3012/3013 Family Silicon Errata and Data Sheet Clarification The dsPIC30F3012/3013 family devices that you have received conform functionally to the current Device Data Sheet (DS70139F), except for the anomalies described in this document. For example, to identify the silicon revision level using MPLAB IDE in conjunction with MPLAB ICD 2 or PICkitTM 3: 1. The silicon issues discussed in the following pages are for silicon revisions with the Device and Revision IDs listed in Table 1. The silicon issues are summarized in Table 2. 2. The errata described in this document will be addressed in future revisions of the dsPIC30F3012/3013 silicon. Note: 3. This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated in the last column of Table 2 apply to the current silicon revision (B1). 4. Note: Data Sheet clarifications and corrections start on page 16, following the discussion of silicon issues. The silicon revision level can be identified using the current version of MPLAB(R) IDE and Microchip's programmers, debuggers and emulation tools, which are available at the Microchip corporate web site (www.microchip.com). TABLE 1: The Device and Revision ID values for the various dsPIC30F3012/3013 silicon revisions are shown in Table 1. Device ID(1) dsPIC30F3012 0x00C1 dsPIC30F3013 0x00C3 2: If you are unable to extract the silicon revision level, please contact your local Microchip sales office for assistance. SILICON DEVREV VALUES Part Number Note 1: Using the appropriate interface, connect the device to the MPLAB ICD 2 programmer/debugger or PICkit 3. From the main menu in MPLAB IDE, select Configure>Select Device, and then select the target part number in the dialog box. Select the MPLAB hardware tool (Debugger>Select Tool). Perform a "Connect" operation to the device (Debugger>Connect). Depending on the development tool used, the part number and Device Revision ID value appear in the Output window. Revision ID for Silicon Revision(2) B0 B1 0x0x1040 0x1041 The Device and Revision IDs (DEVID and DEVREV) are located at the last two implemented addresses in program memory. Refer to the "dsPIC30F Flash Programming Specification" (DS70102) for detailed information on Device and Revision IDs for your specific device. (c) 2010 Microchip Technology Inc. DS80448D-page 1 dsPIC30F3012/3013 TABLE 2: SILICON ISSUE SUMMARY Module Feature Item Number Affected Revisions(1) Issue Summary B0 B1 CPU MAC Class Instructions with 4 Address Modification 1. Sequential MAC instructions, which prefetch data from Y data space using 4 address modification will cause an address error trap. X X CPU DAW.b Instruction 2. The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>). X X PSV Operations -- 3. In certain instructions, fetching one of the operands from program memory using Program Space Visibility (PSV) will corrupt specific bits in the STATUS Register, SR. X X CPU Nested DO Loops 4. When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. X X Interrupt Controller -- 5. An interrupt occurring immediately after modifying the CPU IPL, interrupt IPL, interrupt enable, or interrupt flag may cause an address error trap. X X CPU DISI Instruction 6. The DISI instruction will not disable interrupts if a DISI instruction is executed in the same instruction cycle that the DISI counter decrements to zero. X X Output Compare PWM Mode 7. Output compare will produce a glitch when loading 0% duty cycle in PWM mode. It will also miss the next compare after the glitch. X X Output Compare -- 8. The output compare module will produce a glitch on the output when an I/O pin is initially set high and the module is configured to drive the pin low at a specified time. X X ADC Sleep Mode 9. ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. X X PLL -- 10. If 4x or 8x PLL mode is used, the input frequency range is 5 MHz10 MHz instead of 4 MHz-10 MHz. X X Sleep Mode -- 11. Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. X X I2CTM Slave Mode 12. The I2C module loses incoming data bytes when operating as an I2C slave. X X I/O Port Pin Multiplexed with IC1 13. The Port I/O pin multiplexed with the Input Capture 1 (IC1) function cannot be used as a digital input pin when the UART auto-baud feature is enabled. X X I2C 10-bit Addressing 14. When the I2C module is configured for 10-bit addressing using the same address bits (A10 and A9) as other I2C devices, the A10 and A9 bits may not work as expected. X X Timer Sleep Mode 15. Clock switching prevents the device from waking up from Sleep. X X PLL Lock Status bit 16. The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. X X PSV Operations -- 17. An address error trap occurs in certain addressing modes when accessing the first four bytes of any PSV page. X X Note 1: Only those issues indicated in the last column apply to the current silicon revision. DS80448D-page 2 (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 TABLE 2: Module SILICON ISSUE SUMMARY (CONTINUED) Feature Item Number Affected Revisions(1) Issue Summary B0 B1 I2C 10-bit Addressing 18. The 10-bit slave does not set the RBF flag or load the I2CxRCV register, on address match if the Least Significant bits (LSbs) of the address are the same as the 7-bit reserved addresses. X X I2C 10-bit Addressing 19. When the I2C module is configured as a 10-bit slave with an address of 0x102, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02. X X I2C Bus Collision 20. When the I2C module is enabled, the dsPIC(R) DSC device generates a glitch on the SDA and SCL pins, causing a false communication start in a single-master configuration or a bus collision in a multi-master configuration. X X 32 kHz LowPower (LP) Oscillator Sleep Mode 21. The LP oscillator does not function when the device is placed in Sleep mode. X OSC2 Pin FRC 22. When the FRC Clock mode is selected, the OSC2 pin cannot be used for I/O. X OSC2 Pin Using RC15 for Digital I/O 23. For this revision of silicon, if the pin RC15 is required for digital input/output, the FPR<4:0> bits in the FOSC Configuration Fuse register may not be set up for FRC w/PLL 4x/8x/16x modes. X ADC Current Consumption in Sleep Mode 24. If the ADC module is in an enabled state when the device enters Sleep Mode, the power-down current (IPD) of the device may exceed the device data sheet specifications. X Note 1: X Only those issues indicated in the last column apply to the current silicon revision. (c) 2010 Microchip Technology Inc. DS80448D-page 3 dsPIC30F3012/3013 Silicon Errata Issues Note: This document summarizes all silicon errata issues from all revisions of silicon, previous as well as current. Only the issues indicated by the shaded column in the following tables apply to the current silicon revision (B1). 1. Module: CPU Sequential MAC class instructions, which prefetch data from Y data space using 4 address modification cause an address error trap. The trap occurs only when all the following conditions are true: 1. Two sequential MAC class instructions (or a MAC class instruction executed in a REPEAT or DO loop) that prefetch from Y data space. 2. Both instructions prefetch data from Y data space using the + = 4 or - = 4 address modification. 3. Neither of the instruction uses an accumulator write back. Work around The problem described above can be avoided by using any of the following methods: 1. Inserting any other instruction between the two MAC class instructions. 2. Adding an accumulator write back (a dummy write back if needed) to either of the MAC class instructions. 3. Do not use the + = 4 or - = 4 address modification. 4. Do not prefetch data from Y data space. 2. Module: CPU The Decimal Adjust instruction, DAW.b, may improperly clear the Carry bit, C (SR<0>), when executed. Work around Check the Carry bit status before executing the DAW.b instruction. If the Carry bit is set, set the Carry bit again after executing the DAW.b instruction. Example 1 shows how the application should process the Carry bit during a BCD addition operation. EXAMPLE 1: CHECK CARRY BIT BEFORE DAW.b .include "p30f3013.inc" ....... MOV.b #0x80, w0 ;First BCD number MOV.b #0x80, w1 ;Second BCD number ADD.b w0, w1, w2 ;Perform addition BRA NC, L0 ;If C set go to L0 DAW.b w2 ;If not,do DAW and BSET.b SR, #C ;set the carry bit BRA L1 ;and exit L0:DAW.b w2 L1: .... Affected Silicon Revisions B0 B1 X X Affected Silicon Revisions B0 B1 X X DS80448D-page 4 (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 3. Module: PSV Operations When one of the operands of instructions shown in Table 3 is fetched from program memory using Program Space Visibility (PSV), the STATUS Register, SR and/or the results may be corrupted. TABLE 3: These instructions are identified in Table 3. Example 2 demonstrates one scenario in which this occurs. Also, always use Work around 2 if the C compiler is used to generate code for dsPIC30F3012/3013 devices. AFFECTED INSTRUCTIONS Instruction(1) Examples of Incorrect Operation(2) Data Corruption IN SR<1:0> bits(3), Result in W2 ADDC ADDC SUBB SUBB.b W0, [++W1], W3 ; SR<1:0> bits(3), Result in W3 SUBBR SUBBR.b W0, [++W1], W3 ; SR<1:0> bits(3), Result in W3 CPB CPB SR<1:0> bits(3) RLC RLC [W1], W4 ; SR<1:0> bits(3), Result in W4 RRC RRC [W1], W2 ; SR<1:0> bits(3), Result in W2 ADD (Accumulator-based) ADD [W1++], A ; SR<1:0> bits(3) LAC LAC [W1], A ; SR<15:10> bits(4) Note 1: 2: 3: 4: W0, [W1++], W2 ; W0, [W1++], W4 ; Refer to the "dsPIC30F/33F Programmer's Reference Manual" (DS70157) for details on the dsPIC30F instruction set. The errata only affects these instructions when a PSV access is performed to fetch one of the source operands in the instruction. A PSV access is performed when the Effective Address of the source operand is greater than 0x8000 and the PSV bit (CORCON<2>) is set to `1'. In the examples shown, the data access from program memory is obtained via the W1 register. SR<1:0> bits represent Sticky Zero and Carry Status bits, respectively. SR<15:10> bits represent Accumulator Overflow and Saturation Status bits. EXAMPLE 2: INCORRECT RESULTS .include "p30fxxxx.inc" ....... MOV.B #0x00, W0 ;Load PSVPAG register MOV.B WREG, PSVPAG BSET CORCON, #PSV ;Enable PSV .... MOV #0x8200, W1 ;Set up W1 for ;indirect PSV access ;from 0x000200 ADD W3, [W1++], W5 ;This instruction ;works ok ADDC W4, [W1++], W6 ;Carry flag and ;W6 gets ;corrupted here! EXAMPLE 3: CORRECT RESULTS .include "p30fxxxx.inc" ....... MOV.B #0x00, w0 ;Load PSVPAG register MOV.B WREG, PSVPAG BSET CORCON, #PSV ;Enable PSV .... MOV #0x8200, W1 ;Set up W1 for ;indirect PSV access ;from 0x000200 ADD W3, [W1++], W5 ;This instruction ;works ok MOV [W1++], W2 ;Load W2 with data ;from program memory ADDC W4, W2, W6 ;Carry flag and W4 ;results are ok! Work arounds Work around 1: For Assembly Language Source Code To work around the erratum in the MPLAB ASM30 assembler, the application may perform a PSV access to move the source operand from program memory to RAM or a W register before performing the operations listed in Table 3. Example 3 demonstrates the work around for Example 2. Work around 2: For C Language Source Code For applications using C language, MPLAB C30 versions 1.20.04 or higher provide the following command-line switch that implements a work around for the erratum. -merrata=psv Refer to the "readme.txt" file in the MPLAB C30 v1.20.04 toolsuite for further details. Affected Silicon Revisions (c) 2010 Microchip Technology Inc. B0 B1 X X DS80448D-page 5 dsPIC30F3012/3013 4. Module: CPU When using two DO loops in a nested fashion, terminating the inner-level DO loop by setting the EDT bit (CORCON<11>) will produce unexpected results. Specifically, the device may continue executing code within the outer DO loop forever. This erratum does not affect the operation of the MPLAB C30 compiler. Work around The application should save the DCOUNT SFR prior to entering the inner DO loop and restore it upon exiting the inner DO loop. This work around is shown in Example 4. EXAMPLE 4: SAVE AND RESTORE DCOUNT .include "p30fxxxx.inc" ....... DO #CNT1, LOOP0 ;Outer loop start .... PUSH COUNT ;Save DCOUNT DO #CNT2, LOOP1 ;Inner loop .... ;starts BTSS Flag, #0 BSET CORCON, #EDT ;Terminate inner .... ;DO-loop early .... LOOP1: MOV W1, W5 ;Inner loop ends POP DCOUNT ;Restore DCOUNT ... LOOP0: MOV W5, W8 ;Outer loop ends Note: For details on the functionality of EDT bit, see section 2.9.2.4 in the dsPIC30F Family Reference Manual. Affected Silicon Revisions B0 B1 X X 5. Module: Interrupt Controller The following sequence of events will lead to an address error trap. The generic term "Interrupt 1" is used to represent any enabled dsPIC30F interrupt. 1. User software performs one of the following operations: - CPU IPL is raised to Interrupt 1 IPL level or higher, or - Interrupt 1 IPL is lowered to CPU IPL level or lower, or - Interrupt 1 is disabled (Interrupt 1 IE bit set to `0'), or - Interrupt 1 flag is cleared DS80448D-page 6 2. Interrupt 1 occurs between 2 and 4 instruction cycles after any of the operations listed above. Work arounds Work around 1: For Assembly Language Source Code The user may disable interrupt nesting, disable interrupts before modifying the Interrupt 1 setting or execute a DISI instruction before modifying the CPU IPL or Interrupt 1. A minimum DISI value of 4 is required if the DISI instruction is executed immediately before the CPU IPL or Interrupt 1 is modified, as shown in Example 5. It is necessary to have DISI active for four cycles after the CPU IPL or Interrupt 1 is modified. EXAMPLE 5: USING DISI .include "p30fxxxx.inc" ... DISI #4 ; protect the disable ; of INT1 BCLR IEC1, #INT1IE ; disable interrupt 1 ... ; next instruction ;protected by DISI Work around 2: For C Language Source Code For applications using the C language, MPLAB C30 versions 1.32 and higher provide several macros for modifying the CPU IPL. The SET_CPU_IPL macro provides the ability to safely modify the CPU IPL, as shown in Example 6. EXAMPLE 6: USING SET_CPU_IPL MACRO // Note: Macro defined in device include // files #define SET_CPU_IPL (ipl){ \ int DISI_save; \ \ DISI_save = DISICNT; \ asm volatile ("disi #0x3FFF");\ SRbits.IPL = ipl; \ __builtin_nop(); \ __builtin_nop(); \ DISICNT = DISI_save; } (void) 0; #include "p30fxxxx.h" . . . SET_CPU_IPL (3) . . . There is one level of DISI, so this macro saves and restores the DISI state. For temporarily modifying and restoring the CPU IPL, the macros SET_AND_SAVE_CPU_IPL and RESTORE_CPU_IPL can be used, as shown in Example 7. These macros also make use of the SET_CPU_IPL macro. (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 EXAMPLE 7: USING SET_AND_SAVE_CPU_IPL AND RESTORE_CPU_IPL MACROS // Note: Macros defined in device include files #define SET_AND_SAVE_CPU_IPL (save_to, ipl){ \ save_to = SRbits.IPL; \ SET_CPU_IPL (ipl); } (void) 0; #define RESTORE_CPU_IPL (saved_to) SET_CPU_IPL (saved_to) #include "p30fxxxx.h" . . . int save_to; SET_AND_SAVE_CPU_IPL (save_to, 3) . . . RESTORE_CPU_IPL (save_to) For modification of the Interrupt 1 setting, the INTERRUPT_PROTECT macro can be used. This macro disables interrupts before executing the desired expression, as shown in Example 8. This macro is not distributed with the compiler. EXAMPLE 8: USING INTERRUPT_PROTECT MACRO #define INTERRUPT_PROTECT (x) { \ int save_sr; \ SET_AND_SAVE_CPU_IPL (save_sr, 7);\ x; \ RESTORE_CPU_IPL (save_sr); } (void) 0; . . . INTERRUPT_PROTECT (IEC0bits.U1TXIE=0); Note: If you are using a MPLAB C30 compiler version earlier than version 1.32, you may still use the macros by adding them to your application. Affected Silicon Revisions B0 B1 X X (c) 2010 Microchip Technology Inc. DS80448D-page 7 dsPIC30F3012/3013 6. Module: CPU 7. Module: Output Compare When a user executes a DISI #7, for example, this will disable interrupts for 7 + 1 cycles (7 + the DISI instruction itself). In this case, the DISI instruction uses a counter which counts down from 7 to 0. The counter is loaded with 7 at the end of the DISI instruction. If the desired duty cycle is `0' (OCxRS = 0), the module will generate a high level glitch of 1 TCY. The second problem is that on the next cycle after the glitch, the OC pin does not go high, in other words, it misses the next compare for any value written on OCxRS. If the user code executes another DISI on the instruction cycle where the DISI counter has become zero, the new DISI count is loaded, but the DISI state machine does not properly re-engage and continue to disable interrupts. At this point, all interrupts are enabled. The next time the user code executes a DISI instruction, the feature will act normally and block interrupts. Work around In summary, it is only when a DISI execution is coincident with the current DISI count = 0, that the issue occurs. Executing a DISI instruction before the DISI counter reaches zero will not produce this error. In this case, the DISI counter is loaded with the new value, and interrupts remain disabled until the counter becomes zero. Work around When executing multiple DISI instructions within the source code, make sure that subsequent DISI instructions have at least one instruction cycle between the time that the DISI counter decrements to zero and the next DISI instruction. Alternatively, make sure that subsequent DISI instructions are called before the DISI counter decrements to zero. Affected Silicon Revisions B0 B1 X X There are two possible solutions to this problem: 1. Load a value greater than `0' to the OCxRS register when operating in PWM mode. In this case, no 0% duty cycle is achievable. 2. If the application requires 0% duty cycles, the output compare module can be disabled for 0% duty cycles, and re-enabled for non-zero percent duty cycles. Affected Silicon Revisions B0 B1 X X 8. Module: Output Compare A glitch will be produced on an output compare pin under the following conditions: * The user software initially drives the I/O pin high using the output compare module or a write to the associated PORT register. * The output compare module is configured and enabled to drive the pin low at some point in later time (OCxCON = 0x0002 or OCxCON = 0x0003). When these events occur, the output compare module will drive the pin low for one instruction cycle (TCY) after the module is enabled. Work around None. However, the user may use a timer interrupt and write to the associated PORT register to control the pin manually. Affected Silicon Revisions DS80448D-page 8 B0 B1 X X (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 9. Module: ADC ADC event triggers from the INT0 pin will not wake-up the device from Sleep mode if the SMPI bits are non-zero. This means that if the ADC is configured to generate an interrupt after a certain number of INT0 triggered conversions, the ADC conversions will not be triggered and the device will remain in Sleep. The ADC will perform conversions and wake-up the device only if it is configured to generate an interrupt after each INT0 triggered conversion (SMPI<3:0> = 0000). Work around None. If ADC event trigger from the INT0 pin is required, initialize SMPI<3:0> to `0000' (interrupt on every conversion). Affected Silicon Revisions B0 B1 X X 10. Module: PLL If 4x or 8x PLL mode is used, the input frequency range is 5 MHz-10 MHz instead of 4 MHz-10 MHz. Work around None. If 4x or 8x PLL mode is used, make sure the input crystal or clock frequency is 5 MHz or greater. Affected Silicon Revisions B0 B1 X X (c) 2010 Microchip Technology Inc. DS80448D-page 9 dsPIC30F3012/3013 11. Module: Sleep Mode Execution of the Sleep instruction (PWRSAV #0) may cause incorrect program operation after the device wakes up from Sleep. The current consumption during Sleep may also increase beyond the specifications listed in the device data sheet. Work arounds To avoid this issue, implement any of the following three work arounds, depending on the application requirements. Work around 1: Ensure that the PWRSAV #0 instruction is located at the end of the last row of program Flash memory available on the target device and fill the remainder of the row with NOP instructions. This can be accomplished by replacing all occurrences of the PWRSAV #0 instruction with a function call to a suitably aligned subroutine. The address( ) attribute provided by the MPLAB ASM30 assembler can be utilized to correctly align the instructions in the subroutine. For an application written in C, the function call would be GotoSleep( ), while for an assembly language application, the function call would be CALL _GotoSleep. The address error Trap Service Routine (TSR) software can then replace the invalid return address saved on the stack with the address of the instruction immediately following the _GotoSleep or GotoSleep( ) function call. This ensures that the device continues executing the correct code sequence after waking up from Sleep mode. Example 9 demonstrates described above. the work around EXAMPLE 9: ; ---------------------------------------------------------------------------------------------.global __reset .global _main .global _GotoSleep .global __AddressError .global __INT1Interrupt ; ---------------------------------------------------------------------------------------------.section *, code _main: BSET INTCON2, #INT1EP ; Set up INT pins to detect falling edge BCLR IFS1, #INT1IF ; Clear interrupt pin interrupt flag bits BSET IEC1, #INT1IE ; Enable ISR processing for INT pins CALL _GotoSleep ; Call function to enter SLEEP mode _continue: BRA _continue ; ---------------------------------------------------------------------------------------------; Address Error Trap __AddressError: BCLR INTCON1, #ADDRERR ; Set program memory return address to _continue POP.D W0 MOV.B #tblpage (_continue), W1 MOV #tbloffset (_continue), W0 PUSH.D W0 RETFIE ; ---------------------------------------------------------------------------------------------__INT1Interrupt: BCLR IFS1, #INT1IF ; Ensure flag is reset RETFIE ; Return from Interrupt Service Routine ; ---------------------------------------------------------------------------------------------.section *, code, address (0x1FC0) _GotoSleep: ; fill remainder of the last row with NOP instructions .rept 31 NOP .endr ; Place SLEEP instruction in the last word of program memory PWRSAV #0 DS80448D-page 10 (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 Work around 2: Work around 3: Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 512 kHz Low-Power RC (LPRC) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.002 MIPS, thereby significantly reducing the current consumption of the device. Similarly, instead of using an interrupt to wake-up the device from Sleep mode, perform another clock switch back to the original oscillator source to resume normal operation. Depending on the device, refer to Section 7. "Oscillator" (DS70054) or Section 29. "Oscillator" (DS70268) in the "dsPIC30F Family Reference Manual" (DS70046) for more details on performing a clock switch operation. Instead of executing a PWRSAV #0 instruction to put the device into Sleep mode, perform a clock switch to the 32 kHz Low-Power (LP) Oscillator with a 64:1 postscaler mode. This enables the device to operate at 0.000125 MIPS, thereby significantly reducing the current consumption of the device. Similarly, instead of using an interrupt to wake-up the device from Sleep mode, perform another clock switch back to the original oscillator source to resume normal operation. Depending on the device, refer to Section 7. "Oscillator" (DS70054) or Section 29. "Oscillator" (DS70268) in the "dsPIC30F Family Reference Manual" (DS70046) for more details on performing a clock switch operation. Note: The above work around is recommended for users for whom application hardware changes are not possible. Note: The above work around is recommended for users for whom application hardware changes are possible, and also for users whose application hardware already includes a 32 kHz LP Oscillator crystal. Affected Silicon Revisions (c) 2010 Microchip Technology Inc. B0 B1 X X DS80448D-page 11 dsPIC30F3012/3013 12. Module: I2C Work around 2: When the I2C module is configured as a slave, either in single-master or multi-master mode, the I2C receiver buffer is filled whether a valid slave address is detected or not. Therefore, an I2C receiver overflow condition occurs and this condition is indicated by the I2COV flag in the I2CSTAT register. Use this work around for applications in which the I2C receiver interrupt is required. Assuming that the RBF and the I2COV flags in the I2CSTAT register are set due to previous data transfers in the I2C bus (i.e., between master and other slaves); the following procedure can be used to receive valid data bytes: This overflow condition inhibits the ability to set the I2C receive interrupt flag (SI2CF) when the last valid data byte is received. Therefore, the I2C slave Interrupt Service Routine (ISR) is not called and the I2C receiver buffer is not read prior receiving the next data byte. 1. When a valid slave address byte is detected, SI2CF bit is set and the I2C slave interrupt service routine is called; however, the RBF and I2COV bits are already set due to data transfers between other I2C nodes. 2. Check the status of the D_A flag and the I2COV flag in the I2CSTAT register when executing the I2C slave service routine. 3. If the D_A flag is cleared and the I2COV flag are set, an invalid data byte was received but a valid address byte was received. The overflow condition occurred because the I2C receive buffer was overflowing with previous I2C data transfers between other I2C nodes. This condition only occurs after a valid slave address was detected. 4. Clear the I2COV flag and perform a dummy read of the I2C receiver buffer, I2CRCV, to clear the RBF bit and recover the valid address byte. This action will also avoid the loss of the next data byte due to an overflow condition. 5. Verify that the recovered address byte matches the current slave address byte. If they match, the next data to be received is a valid data byte. 6. If the D_A flag and the I2COV flag are both set, a valid data byte was received and a previous valid data byte was lost. It will be necessary to code for handling this overflow condition. Work arounds To avoid this issue, either of the following two work arounds can be implemented, depending on the application requirements. Work around 1: For applications in which the I2C receiver interrupt is not required, the following procedure can be used to receive valid data bytes: 1. Wait until the RBF flag is set. 2. Poll the I2C receiver interrupt SI2CIF flag. 3. If SI2CF is not set in the corresponding Interrupt Flag Status register (IFSx), a valid address or data byte has not been received for the current slave. Execute a dummy read of the I2C receiver buffer, I2CRCV; this will clear the RBF flag. Go back to step 1 until SI2CF is set and then continue to Step 4. 4. If the SI2CF is set in the corresponding Interrupt Flag Status register (IFSx), valid data has been received. Check the D_A flag to verify that an address or a data byte has been received. 5. Read the I2CRCV buffer to recover valid data bytes. This will also clear the RBF flag. 6. Clear the I2C receiver interrupt flag SI2CF. 7. Go back to step 1 to continue receiving incoming data bytes. DS80448D-page 12 Affected Silicon Revisions B0 B1 X X (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 13. Module: I/O 16. Module: PLL If the user application enables the auto-baud feature in the UART module, the I/O pin multiplexed with the IC1 (Input Capture) pin cannot be used as a digital input. However, the external interrupt function (INT1) can be used. The PLL LOCK Status bit (OSCCON<5>) can occasionally get cleared and generate an oscillator failure trap even when the PLL is still locked and functioning correctly. Work around The user application must include an oscillator failure trap service routine. In the trap service routine, first inspect the status of the Clock Failure Status bit (OSCCON<3>). If this bit is clear, return from the trap service routine immediately and continue program execution. None. Affected Silicon Revisions B0 B1 X X Work around Affected Silicon Revisions 14. Module: I2C If there are two I2C devices on the bus, one of them is acting as the Master receiver and the other as the Slave transmitter. If both devices are configured for 10-bit addressing mode, and have the same value in the A10 and A9 bits of their addresses, then when the Slave select address is sent from the Master, both the Master and Slave acknowledge it. When the Master sends out the read operation, both the Master and the Slave enter into Read mode and both of them transmit the data. The resultant data will be the ANDing of the two transmissions. Work around In all I2C devices, the addresses as well as bits A10 and A9 should be different. Affected Silicon Revisions B0 B1 X X 15. Module: Timer When the timer is being operated in Asynchronous mode using the secondary oscillator (32.768 kHz) and the device is put into Sleep mode, a clock switch to any other oscillator mode before putting the device to Sleep prevents the timer from waking the device from Sleep. B0 B1 X X 17. Module: PSV Operations An address error trap occurs in certain addressing modes when accessing the first four bytes of an PSV page. This only occurs when using the following addressing modes: * MOV.D * Register Indirect Addressing (word or byte mode) with pre/post-decrement Work around Do not perform PSV accesses to any of the first four bytes using the above addressing modes. For applications using the C language, MPLAB C30 version 3.11 or higher, provides the following command-line switch that implements a work around for the erratum. -merrata=psv_trap Refer to the readme.txt file in the MPLAB C30 v3.11 tool suite for further details. Affected Silicon Revisions B0 B1 X X Work around Do not clock switch to any other oscillator mode if the timer is being used in Asynchronous mode using the secondary oscillator (32.768 kHz). Affected Silicon Revisions B0 B1 X X (c) 2010 Microchip Technology Inc. DS80448D-page 13 dsPIC30F3012/3013 18. Module: I2C In 10-bit Addressing mode, some address matches don't set the RBF flag or load the receive register I2CxRCV, if the lower address byte matches the reserved addresses. In particular, these include all addresses with the form XX0000XXXX and XX1111XXXX, with the following exceptions: * * * * 001111000X 011111001X 101111010X 111111011X Work around Ensure that the lower address byte in 10-bit Addressing mode does not match any 7-bit reserved addresses. Affected Silicon Revisions B0 B1 X X 19. Module: I2C When the I2C module is configured as a 10-bit slave with and address of 0x102, the I2CxRCV register content for the lower address byte is 0x01 rather than 0x02; however, the module acknowledges both address bytes. Work around None. Affected Silicon Revisions B0 B1 X X 20. Module: I2C When the I2C module is enabled by setting the I2CEN bit in the I2CCON register, the dsPIC DSC device generates a glitch on the SDA and SCL pins. This glitch falsely indicates "Communication Start" to all devices on the I2C bus, and can cause a bus collision in a multi-master configuration. Additionally, when the I2CEN bit is set, the S and P bits of the I2C module are set to values `1' and `0', respectively, which indicate a "Communication Start" condition. Work arounds To avoid this issue, either of the following two work arounds can be implemented, depending on the application requirements. Work around 1: In a single-master environment, add a delay between enabling the I2C module and the first data transmission. The delay should be equal to or greater than the time it takes to transmit two data bits. In the multi-master configuration, in addition to the delay, all other I2C masters should be synchronized and wait for the I2C module to be initialized before initiating any kind of communication. Work around 2: In dsPIC DSC devices in which the I2C module is multiplexed with other modules that have precedence in the use of the pin, it is possible to avoid this glitch by enabling the higher priority module before enabling the I2C module. Use the following procedure to implement this work around: 1. Enable the higher priority peripheral module that is multiplexed on the same pins as the I2C module. 2. Set up and enable the I2C module. Disable the higher priority peripheral module that was enabled in step 1. Note: Work around 2 works only for devices that share the SDA and SCL pins with another peripheral that has a higher precedence over the port latch, such as the UART. The priority is shown in the pin diagram located in the data sheet. For example, if the SDA and SCL pins are shared with the UART and SPI pins, and the UART has higher precedence on the port latch pin. Affected Silicon Revisions DS80448D-page 14 B0 B1 X X (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 21. Module: 32 kHz Low-Power (LP) Oscillator The LP oscillator is located on the SOSCO and SOSCI device pins and serves as a secondary crystal clock source for low-power operation. The LP oscillator can also drive Timer1 for a real-time clock application. The LP oscillator does not function when the device is placed in Sleep mode. Work around If the application needs to wake up periodically from Sleep mode using an internal timer, the Watchdog Timer may be enabled prior to entering Sleep mode. When the Watchdog Timer expires, code execution will resume from the instruction immediately following the SLEEP instruction. Affected Silicon Revisions B0 B1 X 22. Module: OSC2 Pin When the FRC Clock mode is selected, the OSC2 pin cannot be used for I/O. Work around Use the FRC with PLL 4x Clock mode. After the application powers up, program the Oscillator Postscaler Selection bits (OSCCON<7:6>) to `01' to divide the clock by 4. The OSCCON is a write-protected register and an unlock sequence must be used to modify the Oscillator Postscaler Selection bits. This work around is shown in Example 10. EXAMPLE 10: .include "p30fxxxx.inc" MOV #OSCCONL, w1;prepare unlock sequence MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1];unlock sequence step 1 MOV.b w3, [w1];unlock sequence step 2 BSET.b [w1], #6;set poscalar to divide by 4 Affected Silicon Revisions B0 B1 X (c) 2010 Microchip Technology Inc. 23. Module: OSC2 Pin The port pin, RC15, is multiplexed with the primary oscillator pin, OSC2. When pin RC15 is required for digital input/output, specific bits in the Oscillator Configuration Fuse register, FOSC, may be set up as follows: * FOS<2:0> bits (FOSC<10:8>) configured for LP, LPRC, FRC, ECIO, ERCIO or ECIO w/PLL 4x/8x/16x * FPR<4:0> bits (FOSC<4:0>) may be configured for ECIO w/PLL 4x/8x/16x For this revision of silicon, if the RC15 digital I/O port function is desired, the FPR<4:0> bits in the FOSC Configuration Fuse register may not be set up for FRC w/PLL 4x/8x/16x modes. Work around None. In future revisions of silicon, port pin RC15 may also be configured for digital I/O when the FPR<4:0> bits in the FOSC Configuration Fuse register are set up for FRC w/PLL 4x/8x/16x modes. Affected Silicon Revisions B0 B1 X 24. Module: ADC If the ADC module is in an enabled state when the device enters Sleep mode as a result of executing a PWRSAV #0 instruction, the device power-down current (IPD) may exceed the specifications listed in the device data sheet. This may happen even if the ADC module is disabled by clearing the ADON bit prior to entering Sleep mode. Work around In order to remain within the IPD specifications listed in the device data sheet, the user software must completely disable the ADC module by setting the ADC Module Disable bit in the corresponding Peripheral Module Disable register (PMDx), prior to executing a PWRSAV #0 instruction. Affected Silicon Revisions B0 B1 X X DS80448D-page 15 dsPIC30F3012/3013 Data Sheet Clarifications The following typographic corrections and clarifications are to be noted for the latest version of the device data sheet (DS70139F): Note: Corrections are shown in bold. Where possible, the original bold text formatting has been removed for clarity. 1. Module: DC Characteristics: I/O Pin Input Specifications The maximum value for parameter DI19 (VIL specifications for SDAx and SCLx pins) and the minimum value for parameter DI29 (VIH specifications for SDAx and SCLx pins) were stated incorrectly in Table 20-8 of the current device data sheet. The correct values are shown in bold type in Table 4. TABLE 4: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.3V and 5.0V (10%) (unless otherwise stated) Operating temperature -40C TA +85C for Industrial -40C TA +125C for Extended DC CHARACTERISTICS Param No. Symbol VIL DI19 Characteristic DI29 DS80448D-page 16 Typ Max Units Conditions VSS -- 0.8 V SMbus enabled 2.1 -- VDD V SMbus enabled Input Low Voltage SDA, SCL VIH Min Input High Voltage SDA, SCL (c) 2010 Microchip Technology Inc. dsPIC30F3012/3013 APPENDIX A: REVISION HISTORY Rev A Document (4/2009) Initial release of this document; issued for revision B0 and B1 silicon. Includes silicon issues 1-2 (CPU), 3 (PSV Operations), 4 (CPU), 5 (Interrupt Controller), 6 (CPU), 7 (Output Compare), 8 (Output Compare), 9 (ADC), 10 (PLL), 11 (Sleep Mode), 12 (I2C), 13 (I/O), 14 (I2C), 15 (Timer), 16 (PLL), 17 (PSV Operations), 18-20 (I2C), 21 (32 kHz Low-Power (LP) Oscillator) and 22-23 (OSC2 Pin). This document replaces the following errata documents: * DS80230, "dsPIC30F3012/3013 Rev. B0 Silicon Errata" * DS80255, "dsPIC30F3012/3013 Rev. B1 Silicon Errata" Rev B Document (8/2009) Updated silicon issue 5 (Interrupt Controller). Rev C Document (1/2010) Updated silicon issue 5 (Interrupt Controller). Rev D Document (6/2010) Added silicon issue 24 (ADC) and data sheet clarification 1 (DC Characteristics: I/O Pin Input Specifications). (c) 2010 Microchip Technology Inc. DS80448D-page 17 dsPIC30F3012/3013 NOTES: DS80448D-page 18 (c) 2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-254-0 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2010 Microchip Technology Inc. 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