SiHB30N60AEL www.vishay.com Vishay Siliconix EL Series Power MOSFET FEATURES D * Low figure-of-merit (FOM) Ron x Qg D2PAK (TO-263) * Low input capacitance (Ciss) * Reduced switching and conduction losses G * Ultra low gate charge (Qg) * Avalanche energy rated (UIS) G D * Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 S S N-Channel MOSFET APPLICATIONS * Server and telecom power supplies PRODUCT SUMMARY * Switch mode power supplies (SMPS) VDS (V) at TJ max. RDS(on) typ. () at 25 C 650 VGS = 10 V Qg max. (nC) 120 Qgs (nC) 14 Qgd (nC) 19 Configuration * Power factor correction power supplies (PFC) 0.105 * Lighting - High-intensity discharge (HID) - Fluorescent ballast lighting * Industrial Single - Welding - Induction heating - Motor drives - Battery chargers - Renewable energy - Solar (PV inverters) ORDERING INFORMATION Package D2PAK (TO-263) Lead (Pb)-free and halogen-free SiHP30N60AEL-GE3 ABSOLUTE MAXIMUM RATINGS (TC = 25 C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-source voltage VDS 600 Gate-source voltage VGS 30 Continuous drain current (TJ = 150 C) VGS at 10 V TC = 25 C TC = 100 C Pulsed drain current a ID UNIT V 28 18 A IDM 68 2 W/C Single pulse avalanche energy b EAS 353 mJ Maximum power dissipation PD 250 W TJ, Tstg -55 to +150 C 32 V/ns 260 C Linear derating factor Operating junction and storage temperature range Reverse diode dv/dt d Soldering recommendations (peak temperature) c dv/dt For 10 s Notes * Initial samples marked as SiHB30N60BE a. Repetitive rating; pulse width limited by maximum junction temperature b. VDD = 120 V, starting TJ = 25 C, L = 28.2 mH, Rg = 25 , IAS = 5 A c. 1.6 mm from case d. ISD ID, di/dt = 100 A/s, starting TJ = 25 C S18-0173-Rev. A, 12-Feb-18 Document Number: 92066 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60AEL www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum junction-to-ambient RthJA - 62 Maximum junction-to-case (drain) RthJC - 0.5 UNIT C/W SPECIFICATIONS (TJ = 25 C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-source breakdown voltage VDS temperature coefficient Gate-source threshold Voltage (N) VDS VGS = 0 V, ID = 250 A 600 - - V VDS/TJ Reference to 25 C, ID = 1 mA - 0.68 - V/C VGS(th) VDS = VGS, ID = 250 A 2.0 - 4.0 V VGS = 20 V - - 100 nA VGS = 30 V - - 1 A VDS = 600 V, VGS = 0 V - - 1 VDS = 480 V, VGS = 0 V, TJ = 125 C - - 10 Gate-source leakage IGSS Zero gate voltage drain current IDSS A - 0.105 0.120 gfs VDS = 20 V, ID = 15 A - 19 - S Input capacitance Ciss 2565 - Coss - 109 - Reverse transfer capacitance Crss VGS = 0 V, VDS = 100 V, f = 1 MHz - Output capacitance - 6 - Effective output capacitance, energy related a Co(er) - 71 - Effective output capacitance, time related b Co(tr) - 367 - Drain-source on-state resistance Forward transconductance RDS(on) VGS = 10 V ID = 15 A Dynamic pF VDS = 0 V to 480 V, VGS = 0 V Total gate charge Qg Gate-source charge Qgs VGS = 10 V ID = 15 A, VDS = 480 V - 60 120 - 14 - Gate-drain charge Qgd - 19 - Turn-on delay time td(on) - 26 52 VDD = 480 V, ID = 15 A, VGS = 10 V, Rg = 9.1 - 24 48 - 79 158 - 33 66 f = 1 MHz, open drain 0.35 0.72 1.45 - - 26 - - 68 Rise time Turn-off delay time tr td(off) Fall time tf Gate input resistance Rg nC ns Drain-Source Body Diode Characteristics Continuous source-drain diode current IS Pulsed diode forward current ISM Diode forward voltage VSD Reverse recovery time trr Reverse recovery charge Qrr Reverse recovery current IRRM MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 C, IS = 15 A, VGS = 0 V TJ = 25 C, IF = IS = 15 A, di/dt = 100 A/s, VR = 400 V S - - 1.2 V - 335 670 ns - 5.4 10.8 C - 30 - A Notes a. Coss(er) is a fixed capacitance that gives the same energy as Coss while VDS is rising from 0 % to 80 % VDSS b. Coss(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 % to 80 % VDSS S18-0173-Rev. A, 12-Feb-18 Document Number: 92066 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60AEL www.vishay.com Vishay Siliconix TYPICAL CHARACTERISTICS (25 C, unless otherwise noted) 80 3.0 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 60 ID = 15 A TJ = 25 C RDS(on), Drain-to-Source On-Resistance (Normalized) ID, Drain-to-Source Current (A) TOP 40 20 0 2.5 2.0 1.5 1.0 VGS = 10 V 0.5 0 0 5 10 15 20 -60 -40 -20 VDS, Drain-to-Source Voltage (V) 50 40 30 40 60 80 100 120 140 160 100 000 TJ = 150 C VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds shorted Crss = Cgd Coss = Cds + Cgd 10 000 Ciss C, Capacitance (pF) ID, Drain-to-Source Current (A) 15 V 14 V 13 V 12 V 11 V 10 V 9V 8V 7V 6V BOTTOM 5 V 20 Fig. 4 - Normalized On-Resistance vs. Temperature Fig. 1 - Typical Output Characteristics TOP 0 TJ, Junction Temperature (C) 20 1000 Coss 100 Crss 10 10 1 0 0 5 10 15 0.1 20 0 100 VDS, Drain-to-Source Voltage (V) 200 300 400 500 600 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 2 - Typical Output Characteristics 80 14 Coss, Output Capacitance (pF) ID, Drain-to-Source Current (A) 5000 60 40 TJ = 150 C 20 12 10 Coss Eoss 8 500 6 4 VDS = 27.6 V 2 0 0 5 10 15 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S18-0173-Rev. A, 12-Feb-18 20 50 Eoss, Output Capacitance Stored Energy (J) 16 TJ = 25 C 0 0 100 200 300 400 500 VDS, Drain-to-Source Voltage (V) 600 Fig. 6 - Coss and Eoss vs. VDS Document Number: 92066 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60AEL www.vishay.com Vishay Siliconix 30 VDS = 480 V VDS = 300 V VDS = 120 V 25 9 ID, Drain Current (A) VGS, Gate-to-Source Voltage (V) 12 6 20 15 10 3 5 0 0 0 15 30 45 60 25 75 50 Qg, Total Gate Charge (nC) 75 100 125 150 TC, Case Temperature (C) Fig. 7 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 10 - Maximum Drain Current vs. Case Temperature ISD, Reverse Drain Current (A) TJ = 150 C 10 TJ = 25 C 1 VGS = 0 V 0.1 0.2 0.4 0.6 0.8 1.0 1.2 VSD, Source-Drain Voltage (V) Operation in this area limited by RDS(on) ID, Drain Current (A) 750 725 700 675 650 625 ID = 250 A 600 -60 -40 -20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (C) Fig. 8 - Typical Source-Drain Diode Forward Voltage 100 VDS, Drain-to-Source Breakdown Voltage (V) 775 100 Fig. 11 - Temperature vs. Drain-to-Source Voltage IDM limited 10 100 s Limited by RDS(on)* 1 1 ms 0.1 10 ms TC = 25 C TJ = 150 C single pulse BVDSS limited 0.01 1 10 100 1000 VDS, Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Fig. 9 - Maximum Safe Operating Area S18-0173-Rev. A, 12-Feb-18 Document Number: 92066 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60AEL www.vishay.com Vishay Siliconix 1 Normalized Effective Transient Thermal Impedance Duty cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single pulse 0.01 0.0001 0.001 0.01 0.1 1 Pulse Time (s) Fig. 12 - Normalized Thermal Transient Impedance, Junction-to-Case RD VDS VDS tp VGS D.U.T. VDD Rg + - VDD VDS 10 V Pulse width 1 s Duty factor 0.1 % IAS Fig. 13 - Switching Time Test Circuit Fig. 16 - Unclamped Inductive Waveforms VDS Qg 10 V 90 % Qgs 10 % VGS Qgd VG td(on) td(off) tr tf Charge Fig. 14 - Switching Time Waveforms Fig. 17 - Basic Gate Charge Waveform Current regulator Same type as D.U.T. L VDS Vary tp to obtain required IAS 50 k D.U.T. Rg + - VDD 12 V 0.2 F 0.3 F + IAS D.U.T. - VDS 10 V tp 0.01 VGS 3 mA Fig. 15 - Unclamped Inductive Test Circuit IG ID Current sampling resistors Fig. 18 - Gate Charge Test Circuit S18-0173-Rev. A, 12-Feb-18 Document Number: 92066 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SiHB30N60AEL www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations * Low stray inductance * Ground plane * Low leakage inductance current transformer 3 + 2 - - 4 + 1 Rg * * * * 1 Driver gate drive Period P.W. + V - DD dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test D= P.W. Period V GS = 10 V a 2 D.U.T. ISD waveform Reverse recovery current 3 D.U.T. VDS Body diode forward current dI/dt waveform Diode recovery dV/dt Re-applied voltage V DD Body diode forward drop 4 Inductor current Ripple 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 19 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?92066. S18-0173-Rev. A, 12-Feb-18 Document Number: 92066 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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