© 2002 Fairchild Semiconductor Corporation DS005946 www.fairchildsemi.com
October 1987
Revised March 2002
CD4013BC Dual D-Type Flip-Flop
CD4013BC
Dual D-Type Flip-Flop
General Description
The CD40 13B dual D- type flip-flo p is a mono lithic comp le-
mentary MOS (CMOS) integrated circuit constructed with
N- and P-channel enhancement mode transistors. Each
flip-flop h as independen t data, set, rese t, and clock inputs
and “Q” and “Q” outputs. These devices can be used for
shift registe r applications, and by connecti ng “Q” output to
the data input, for counter and toggle applications. The
logic level present at the “D” input is transferred to the Q
output during the positive-going transition of the clock
pulse. Se tting or reset ting is indep endent of the clock and
is accomplished by a high level on the set or reset line
respectively.
Features
■Wide supply voltage rang e: 3.0V to 15V
■High noise immunity: 0.45 VDD (typ.)
■Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS
Applications
• Automotive
• Data terminals
• Instrumentation
• Medical electronics
• Alarm system
• Industrial electronics
• Remote metering
• Computers
Ordering Code:
Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the ordering code.
Connection Diagram
Top View
Truth Table
No Change
x = Don't Care Case
Note 1: Lev el C hange
Order Number Package Number Package Description
CD4013BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
CD4013BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4013BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CL
(Note 1) DRSQQ
00001
10010
x00QQ
x x1001
x x0110
x x1111
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CD4013BC
Schematic D ia gr a ms
Logic Diagram
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CD4013BC
Absolute Maximum Ratings(Note 2)
(Note 3) Recommended Operating
Conditions (Note 3)
Note 2: “Absolute Maximum Ratings” are those va lues beyond which the
safety of th e device ca nnot be guaranteed, th ey are not meant to imply th at
the devices should be operated at these limits. The tables of “Recom-
mended Operating Conditions” and “Electrical Charac t eristics” pro v ide con-
ditions f or actual device o peration.
Note 3: VSS = 0V unles s ot herwise s pecified .
DC Electrical Characteristics (Note 3)
Note 4: IOH and IOL are measured on e output at a t ime.
DC Supply Voltage (VDD)−0.5 VDC to +18 VDC
Input Voltage (VIN)−0.5 VDC to VDD +0.5 VDC
Storage Temperat ure Range (TS)−65°C to +150°C
Power Dissipation (PD)
Dual-In-Line 700 mW
Small Out lin e 500 mW
Lead Temperature (TL)
(Solder ing, 10 seco nds) 260°C
DC Supply Voltage (VDD)+3 VDC to +15 VDC
Input Voltage (VIN)0 V
DC to VDD VDC
Operating Temperature Range (TA)−55°C to +125°C
Symbol Parameter Conditions −55°C+25°C+125°CUnits
Min Max Min Typ Max Min Max
IDD Quiescent Device VDD = 5V, VIN = VDD or VSS 1.0 1.0 30 µACurrent VDD = 10V, VIN = VDD or VSS 2.0 2.0 60
VDD = 15V, VIN = VDD or VSS 4.0 4.0 120
VOL LOW Level |IO| < 1.0 µA
V
Output Voltage VDD = 5V 0.05 0.05 0.05
VDD = 10V 0.05 0.05 0.05
VDD = 15V 0.05 0.05 0.05
VOH HIGH Level |IO| < 1.0 µA
V
Output Voltage VDD = 5V 4.95 4.95 4.95
VDD = 10V 9.95 9.95 9.95
VDD = 15V 14.95 14.95 14.95
VIL LOW Level |IO| < 1.0 µA
V
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 1.5 1.5 1.5
VDD = 10V, VO = 1.0V or 9.0V 3.0 3.0 3.0
VDD = 15V, VO = 1.5V or 13.5V 4.0 4.0 4.0
VIH HIGH Level |IO| < 1.0 µA
V
Input Voltage VDD = 5V, VO = 0.5V or 4.5V 3.5 3.5 3.5
VDD = 10V, VO = 1.0V or 9.0V 7.0 7.0 7.0
VDD = 15V, VO = 1.5V or 13.5V 11.0 11.0 11.0
IOL LOW Level Output VDD = 5V, VO = 0.4V 0.64 0.51 0.88 0.36 mACurrent (Note 4) VDD = 10V, VO = 0.5V 1.6 1.3 2.25 0.9
VDD = 15V, VO = 1.5V 4.2 3.4 8.8 2.4
IOH HIGH Level Output VDD = 5V, VO = 4.6V −0.64 −0.51 −0.88 −0.36 mACurrent (Note 4) VDD = 10V, VO = 9.5V −1.6 −1.3 −2.25 −0.9
VDD = 15V, VO = 13.5V −4.2 −3.4 −8.8 −2.4
IIN Input Current VDD = 15V, VIN = 0V −0.1 −10−5−0.1 −1.0 µA
VDD = 15V, VIN = 15V 0.1 10−50.1 1.0
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CD4013BC
AC Electrical Characteristics (Note 5)
TA = 25°C, CL = 50 pF, RL = 200k, unless otherwise noted
Note 5: AC Parameters are guara nt eed by DC c orrelat ed testing.
Switching Time Waveforms
Symbol Parameter Conditions Min Typ Max Units
CLOCK OPERATION
tPHL, tPLH Propagation Delay Time VDD = 5V 200 350 nsVDD = 10V 80 160
VDD = 15V 65 120
tTHL, tTLH Transition Time VDD = 5V 100 200 nsVDD = 10V 50 100
VDD = 15V 40 80
tWL, tWH Min im um Clo c k VDD = 5V 100 200 nsPulse Width VDD = 10V 40 80
VDD = 15V 32 65
tRCL, tFCL Maximum Clock Rise and VDD = 5V 15 µsFall Time VDD = 10V 10
VDD = 15V 5
tSU Min imum Set- Up T im e VDD = 5V 20 40 nsVDD = 10V 15 30
VDD = 15V 12 25
fCL Maximum Clock VDD = 5V 2.5 5 MHzFrequency VDD = 10V 6.2 12.5
VDD = 15V 7.6 15.5
SET AND RESET OPERATION
tPHL(R), Propagation Delay Time VDD = 5V 150 300 nstPLH(S) VDD = 10V 65 130
VDD = 15V 45 90
tWH(R), Minimum Set and VDD = 5V 90 180 nstWH(S) Reset Pulse Width VDD = 10V 40 80
VDD = 15V 25 50
CIN Average Input Capacitance Any Input 5 7.5 pF
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CD4013BC
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A
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CD4013BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Sma ll Outline Pack age (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
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CD4013BC Dual D-Type Flip-Flop
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package Number N14A
Fairchild does not assume an y responsibility fo r use of any circu itry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life suppor t de vices o r syst ems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instruct ions fo r use pr ovi de d in the l abe ling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A crit ical componen t in any com ponen t of a life s uppor t
device or system whose failure to perform can be rea-
sonabl y e xpec ted to cause th e fa i lure of the l ife s upport
device or system, or to affect its safety or effectiveness.
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