LF353 Wide Bandwidth Dual JFET Input Operational Amplifier General Description Features These devices are low cost, high speed, dual JFET input operational amplifiers with an internally trimmed input offset voltage (BI-FET IITM technology). They require low supply current yet maintain a large gain bandwidth product and fast slew rate. In addition, well matched high voltage JFET input devices provide very low input bias and offset currents. The LF353 is pin compatible with the standard LM1558 allowing designers to immediately upgrade the overall performance of existing LM1558 and LM358 designs. These amplifiers may be used in applications such as high speed integrators, fast D/A converters, sample and hold circuits and many other circuits requiring low input offset voltage, low input bias current, high input impedance, high slew rate and wide bandwidth. The devices also exhibit low noise and offset voltage drift. Y Typical Connection Connection Diagrams Y Y Y Y Y Y Y Y Y Y Internally trimmed offset voltage 10 mV Low input bias current 50pA Low input noise voltage 25 nV/0Hz Low input noise current 0.01 pA/0Hz Wide gain bandwidth 4 MHz High slew rate 13 V/ms Low supply current 3.6 mA High input impedance 1012X k 0.02% Low total harmonic distortion AV e 10, RL e 10k, VO e 20Vpbp, BW e 20 Hz-20 kHz Low 1/f noise corner 50 Hz Fast settling time to 0.01% 2 ms Metal Can Package (Top View) Simplified Schematic Order Number LF353H See NS Package Number H08A 1/2 Dual Dual-In-Line Package (Top View) Order Number LF353M or LF353N See NS Package Number M08A or N08E TL/H/5649 - 1 BI-FET IITM is a trademark of National Semiconductor Corporation. C1995 National Semiconductor Corporation TL/H/5649 RRD-B30M115/Printed in U. S. A. LF353 Wide Bandwidth Dual JFET Input Operational Amplifier February 1995 Absolute Maximum Ratings Lead Temp. (Soldering, 10 sec.) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Supply Voltage g 18V Power Dissipation Operating Temperature Range Tj(MAX) Differential Input Voltage Input Voltage Range (Note 2) Output Short Circuit Duration Storage Temperature Range 260 C Soldering Information Dual-In-Line Package Soldering (10 sec.) Small Outline Package Vapor Phase (60 sec.) Infrared (15 sec.) (Note 1) 0 C to a 70 C 150 C 260 C 215 C 220 C See AN-450 ``Surface Mounting Methods and Their Effect on Product Reliability'' for other methods of soldering surface mount devices. ESD Tolerance (Note 7) 1700V iJA M Package TBD g 30V g 15V Continuous b 65 C to a 150 C DC Electrical Characteristics (Note 4) Symbol Parameter LF353 Conditions MIn VOS Input Offset Voltage Units Typ Max RS e 10kX, TA e 25 C Over Temperature 5 10 13 mV mV DVOS/DT Average TC of Input Offset Voltage RS e 10 kX 10 IOS Input Offset Current Tj e 25 C, (Notes 4, 5) Tjs70 C 25 100 4 pA nA IB Input Bias Current Tj e 25 C, (Notes 4, 5) Tjs70 C 50 200 8 pA nA RIN Input Resistance Tj e 25 C AVOL Large Signal Voltage Gain VS e g 15V, TA e 25 C VO e g 10V, RL e 2 kX VO Output Voltage Swing VCM Input Common-Mode Voltage Range CMRR PSRR IS Supply Current Over Temperature VS e g 15V, RL e 10kX 25 mV/ C 1012 X 100 V/mV 15 V/mV g 12 g 13.5 V VS e g 15V g 11 a 15 b 12 V V Common-Mode Rejection Ratio RSs 10kX 70 100 dB Supply Voltage Rejection Ratio (Note 6) 70 100 3.6 dB 6.5 mA AC Electrical Characteristics (Note 4) Symbol Parameter LF353 Conditions Min Amplifier to Amplifier Coupling TA e 25 C, f e 1 Hzb20 kHz (Input Referred) SR Slew Rate VS e g 15V, TA e 25 C GBW Gain Bandwidth Product VS e g 15V, TA e 25 C en Equivalent Input Noise Voltage Equivalent Input Noise Current in Typ Units Max b 120 dB 8.0 13 V/ms 2.7 4 MHz TA e 25 C, RS e 100X, f e 1000 Hz 16 nV/0Hz Tj e 25 C, f e 1000 Hz 0.01 pA/0Hz Note 1: For operating at elevated temperatures, the device must be derated based on a thermal resistance of 115 C/W typ junction to ambient for the N package, and 158 C/W typ junction to ambient for the H package. Note 2: Unless otherwise specified the absolute maximum negative input voltage is equal to the negative power supply voltage. Note 3: The power dissipation limit, however, cannot be exceeded. Note 4: These specifications apply for VS e g 15V and 0 C s TA s a 70 C. VOS, IB and IOS are measured at VCM e 0. Note 5: The input bias currents are junction leakage currents which approximately double for every 10 C increase in the junction temperature, Tj. Due to the limited production test time, the input bias currents measured are correlated to junction temperature. In normal operation the junction temperature rises above the ambient temperature as a result of internal power dissipation, PD. Tj e TA a ijA PD where ijA is the thermal resistance from junction to ambient. Use of a heat sink is recommended if input bias current is to be kept to a minimum. Note 6: Supply voltage rejection ratio is measured for both supply magnitudes increasing or decreasing simultaneously in accordance with common practice. VS e g 6V to g 15V. Note 7: Human body model, 1.5 kX in series with 100 pF. 2 Typical Performance Characteristics Input Bias Current Input Bias Current Supply Current Positive Common-Mode Input Voltage Limit Negative Common-Mode Input Voltage Limit Positive Current Limit Negative Current Limit Voltage Swing Output Voltage Swing Gain Bandwidth Bode Plot Slew Rate TL/H/5649 - 2 3 Typical Performance Characteristics (Continued) Distortion vs Frequency Undistorted Output Voltage Swing Open Loop Frequency Response Common-Mode Rejection Ratio Power Supply Rejection Ratio Equivalent Input Noise Voltage Open Loop Voltage Gain (V/V) Output Impedance Inverter Settling Time TL/H/5649 - 3 4 Pulse Response Small Signaling Inverting Small Signal Non-Inverting TL/H/5649 - 4 TL/H/5649 - 5 Large Signal Inverting Large Signal Non-Inverting TL/H/5649 - 6 TL/H/5649 - 7 Current Limit (RL e 100X) TL/H/5649 - 8 Application Hints Exceeding the negative common-mode limit on either input will force the output to a high state, potentially causing a reversal of phase to the output. Exceeding the negative common-mode limit on both inputs will force the amplifier output to a high state. In neither case does a latch occur since raising the input back within the common-mode range again puts the input stage and thus the amplifier in a normal operating mode. These devices are op amps with an internally trimmed input offset voltage and JFET input devices (BI-FET II). These JFETs have large reverse breakdown voltages from gate to source and drain eliminating the need for clamps across the inputs. Therefore, large differential input voltages can easily be accommodated without a large increase in input current. The maximum differential input voltage is independent of the supply voltages. However, neither of the input voltages should be allowed to exceed the negative supply as this will cause large currents to flow which can result in a destroyed unit. 5 Application Hints (Continued) in a socket as an unlimited current surge through the resulting forward diode within the IC could cause fusing of the internal conductors and result in a destroyed unit. As with most amplifiers, care should be taken with lead dress, component placement and supply decoupling in order to ensure stability. For example, resistors from the output to an input should be placed with the body close to the input to minimize ``pick-up'' and maximize the frequency of the feedback pole by minimizing the capacitance from the input to ground. A feedback pole is created when the feedback around any amplifier is resistive. The parallel resistance and capacitance from the input of the device (usually the inverting input) to AC ground set the frequency of the pole. In many instances the frequency of this pole is much greater than the expected 3 dB frequency of the closed loop gain and consequently there is negligible effect on stability margin. However, if the feedback pole is less than approximately 6 times the expected 3 dB frequency a lead capacitor should be placed from the output to the input of the op amp. The value of the added capacitor should be such that the RC time constant of this capacitor and the resistance it parallels is greater than or equal to the original feedback pole time constant. Exceeding the positive common-mode limit on a single input will not change the phase of the output; however, if both inputs exceed the limit, the output of the amplifier will be forced to a high state. The amplifiers will operate with a common-mode input voltage equal to the positive supply; however, the gain bandwidth and slew rate may be decreased in this condition. When the negative common-mode voltage swings to within 3V of the negative supply, an increase in input offset voltage may occur. Each amplifier is individually biased by a zener reference which allows normal circuit operation on g 6V power supplies. Supply voltages less than these may result in lower gain bandwidth and slew rate. The amplifiers will drive a 2 kX load resistance to g 10V over the full temperature range of 0 C to a 70 C. If the amplifier is forced to drive heavier load currents, however, an increase in input offset voltage may occur on the negative voltage swing and finally reach an active current limit on both positive and negative swings. Precautions should be taken to ensure that the power supply for the integrated circuit never becomes reversed in polarity or that the unit is not inadvertently installed backwards Detailed Schematic TL/H/5649 - 9 6 Typical Applications Three-Band Active Tone Control TL/H/5649 - 10 Note 1: All controls flat. Note 2: Bass and treble boost, mid flat. Note 3: Bass and treble cut, mid flat. Note 4: Mid boost, bass and treble flat. Note 5: Mid cut, bass and treble flat. # All potentiometers are linear taper # Use the LF347 Quad for stereo applications 7 Typical Applications (Continued) Improved CMRR Instrumentation Amplifier Fourth Order Low Pass Butterworth Filter TL/H/5649 - 11 8 Typical Applications (Continued) Fourth Order High Pass Butterworth Filter # Corner frequency (fc) e # # # # 0R1R2C 1 2 # 1 e 2q 0R1ER2EC 1 2 # 1 2q Passband gain (HO e (1 a R4/R3) (1 a R4E /R3E ) First stage Q e 1.31 Second stage Q e 0.541 Circuit shown uses closest 5% tolerance resistor values for a filter with a corner frequency of 1 kHz and a passband gain of 10. Ohms to Volts Converter TL/H/5649 - 13 VO e 1V RLADDER c RX Where RLADDER is the resistance from switch S1 pole to pin 7 of the LF353. 9 10 Physical Dimensions inches (millimeters) Metal Can Package (H) Order Number LF353H NS Package Number H08A Order Number LF353M NS Package Number M08A 11 LF353 Wide Bandwidth Dual JFET Input Operational Amplifier Physical Dimensions inches (millimeters) (Continued) Molded Dual-In-Line Package Order Number LF353N NS Package N08E LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. 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