DATA SH EET
Product specification
Supersedes data of 1997 Jan 06 2002 Oct 11
INTERGRATED CIRCUITS
SAA7120H; SAA7121H
Digital video encoder
2002 Oct 11 2
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
CONTENTS
1 FEATURES
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Data manager
7.2 Encoder
7.3 Output interface/DACs
7.4 Synchronization
7.5 I2C-bus interface
7.6 Input levels and formats
7.7 Bit allocation map
7.8 I2C-bus format
7.9 Slave receiver
7.10 Slave transmitter
8 CHARACTERISTICS
8.1 Explanation of RTCI data bits
8.2 Teletext timing
9 APPLICATION INFORMATION
9.1 Analog output voltages
10 PACKAGE OUTLINE
11 SOLDERING
11.1 Introduction to soldering surface mount
packages
11.2 Reflow soldering
11.3 Wave soldering
11.4 Manual soldering
11.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
12 DATA SHEET STATUS
13 DEFINITIONS
14 DISCLAIMERS
15 PURCHASE OF PHILIPS I2C COMPONENTS
2002 Oct 11 3
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
1 FEATURES
•Monolithic CMOS 3.3 V device
•Digital PAL/NTSC encoder
•System pixel frequency 13.5 MHz
•Accepts MPEG decoded data on 8-bit wide input port;
input data format CB-Y-CR(CCIR 656)
•Three Digital-to-Analog Converters (DACs) for Y, C
and CVBS two times oversampled with 10-bit resolution
•Real-time control of subcarrier
•Cross-colour reduction filter
•Closed captioning encoding and World Standard
Teletext (WST) and North-American Broadcast Text
System (NABTS) teletext encoding including sequencer
and filter
•Line 23 Wide Screen Signalling (WSS) encoding
•Fast I2C-bus control port (400 kHz)
•Encoder can be master or slave
•Programmable horizontal and vertical input
synchronization phase
•Programmable horizontal sync output phase
•Internal Colour Bar Generator (CBG)
•2×2 bytes in lines 20 (NTSC) for copy guard
management system can be loaded via I2C-bus
•Down mode of DACs
•Controlled rise/fall times of synchronization and
blanking output signals
•Macrovision(1) Pay-per-View copy protection system
rev. 7.01 and rev. 6.1 as option; this applies to
SAA7120H only. The device is protected by USA patent
numbers 4631603, 4577216 and 4819098 and other
intellectual property rights. Use of the Macrovision
anti-copy process in the device is licensed for
non-commercialhomeuseonly.Reverseengineeringor
disassembly is prohibited. Please contact your nearest
Philips Semiconductors sales office for more information
•QFP44 package.
2 GENERAL DESCRIPTION
The SAA7120H; SAA7121H encodes digital YUV video
data to an NTSC or PAL CVBS or S-video signal.
The circuit accepts CCIR compatible YUV data with
720 active pixels per line in 4 :2:2multiplexed formats,
for example MPEG decoded data. It includes a sync/clock
generator and on-chip DACs.
(1) Macrovision is a trademark of the Macrovision Corporation.
3 ORDERING INFORMATION
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
SAA7120H QFP44 plastic quad flat package; 44 leads (lead length 1.3 mm);
body 10 ×10 ×1.75 mm SOT307-2
SAA7121H
2002 Oct 11 4
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
SYMBOL PARAMETER MIN. TYP. MAX. UNIT
VDDA analog supply voltage 3.1 3.3 3.5 V
VDDD digital supply voltage 3.0 3.3 3.6 V
IDDA analog supply current −55 62 mA
IDDD digital supply current −32 45 mA
Viinput signal voltage levels TTL compatible
Vo(p-p) analog output signal voltages Y, C and CVBS without load
(peak-to-peak value) −1.35 −V
RLload resistance 75 −300 Ω
LElf(i) low frequency integral linearity error −−±3 LSB
LElf(d) low frequency differential linearity error −−±1 LSB
Tamb ambient temperature 0 −70 °C
Fig.1 Block diagram.
handbook, full pagewidth
I
2
C-BUS
INTERFACE
DATA
MANAGER ENCODER
SYNC
CLOCK
OUTPUT
INTERFACE
D
A
40 42 41 21 7368433734
35 4 25, 28,
31
MP7
to
MP0
TTX
5, 18, 38 6, 17, 39 1, 20, 22,
23, 26, 29 219 3
30
27
24
32, 33
RESET SDA SCL
RCV1
RCV2
TTXRQ
XCLK
XTALO
XTALI
LLC VDDA4
VSSA1
VSSA2
SA
CVBS
Y
C
I
2
C-bus
control
I
2
C-bus
control I
2
C-bus
control
I
2
C-bus
control
I
2
C-bus
control
VSSD1,
VSSD2,
VSSD3
VDDD1,
VDDD2,
VDDD3
VDDA1,
VDDA2,
VDDA3
RES SPRTCI AP
clock
and timing
Y
Y
C
CB-CR
44
9 to 16
MBH787
SAA7120H
SAA7121H
2002 Oct 11 5
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
6 PINNING
SYMBOL PIN TYPE DESCRIPTION
RES 1 −reserved
SP 2 I test pin; connected to digital ground for normal operation
AP 3 I test pin; connected to digital ground for normal operation
LLC 4 I line-locked clock; this is the 27 MHz master clock for the encoder
VSSD1 5 supply digital ground 1
VDDD1 6 supply digital supply voltage 1
RCV1 7 I/O raster control 1 for video port; this pin receives/provides a VS/FS/FSEQ signal
RCV2 8 I/O raster control 2 for video port; this pin provides an HS pulse of programmable
length or receives an HS pulse
MP7 9 I MPEG ports; inputs for
“CCIR 656”
style multiplexed CB-Y-CRdata
MP6 10 I
MP5 11 I
MP4 12 I
MP3 13 I
MP2 14 I
MP1 15 I
MP0 16 I
VDDD2 17 supply digital supply voltage 2
VSSD2 18 supply digital ground 2
RTCI 19 I real-time control input; if the LLC clock is provided by an SAA7111 or SAA7151B,
RTCI should be connected to the RTCO pin of the respective decoder to improve
the signal quality
RES 20 −reserved
SA 21 I the I2C-bus slave address select input pin; LOW: slave address = 88H,
HIGH = 8CH
RES 22 −reserved
RES 23 −reserved
C 24 O analog output of the chrominance signal
VDDA1 25 supply analog supply voltage 1 for the C DAC
RES 26 −reserved
Y 27 O analog output of VBS signal
VDDA2 28 supply analog supply voltage 2 for the Y DAC
RES 29 −reserved
CVBS 30 O analog output of the CVBS signal
VDDA3 31 supply analog supply voltage 3 for the CVBS DAC
VSSA1 32 supply analog ground 1 for the DACs
VSSA2 33 supply analog ground 2 for the oscillator and reference voltage
XTALO 34 O crystal oscillator output
XTALI 35 I crystal oscillator input; if the oscillator is not used, this pin should be connected to
ground
VDDA4 36 supply analog supply voltage 4 for the oscillator and reference voltage
2002 Oct 11 6
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
XCLK 37 O clock output of the crystal oscillator
VSSD3 38 supply digital ground 3
VDDD3 39 supply digital supply voltage 3
RESET 40 I Reset input, active LOW. After reset is applied, all digital I/Os are in input mode.
The I2C-bus receiver waits for the START condition.
SCL 41 I I2C-bus serial clock input
SDA 42 I/O I2C-bus serial data input/output
TTXRQ 43 O teletext request output, indicating when bit stream is valid
TTX 44 I teletext bit stream input
SYMBOL PIN TYPE DESCRIPTION
handbook, full pagewidth
SAA7120H
SAA7121H
MBH790
1RES
SP
AP
LLC
VDDD1
VSSD1
RCV1
RCV2
MP7
MP6
MP5
MP4
MP3
MP2
MP1
MP0
VDDD2
VSSD2
RTCI
RES
SA
RES
2
3
4
5
6
7
8
9
10
11
33 VSSA2
VSSA1
VDDA3
VDDA2
VDDA1
Y
C
CVBS
RES
RES
RES
32
31
30
29
28
27
26
25
24
23
12
13
14
15
16
17
18
19
20
21
22
44 TTX
TTXRQ
SDA
SCL
XCLK
XTALI
XTALO
VDDD3
VDDA4
VSSD3
RESET
43
42
41
40
39
38
37
36
35
34
Fig.2 Pin configuration.
2002 Oct 11 7
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
7 FUNCTIONAL DESCRIPTION
The digital video encoder encodes digital luminance and
colour difference signals into analog CVBS and
simultaneously S-video signals. NTSC-M, PAL-B/G and
sub-standards are supported. Both interlaced and
non-interlaced operation is possible for all standards.
The basic encoder function consists of subcarrier
generation, colour modulation and insertion of
synchronization signals. Luminance and chrominance
signals are filtered in accordance with the standard
requirements of
“RS-170-A”
and
“CCIR 624”
.
For ease of analog post filtering the signals are twice
oversampled with respect to the pixel clock before
digital-to-analog conversion.
The total filter transfer characteristics are illustrated in
Figs 3 to 6.The DACsfor Y,C andCVBS arerealized with
full 10-bit resolution.
The 8-bit multiplexed CB-Y-CR formats are
“CCIR 656”
(D1 format) compatible, but the SAV and EAV codes can
be decoded optionally, when the device is operated in
slave mode.
Itis alsopossible toconnect aPhilips digital video decoder
(SAA7111 or SAA7151B) to this encoder. By connecting
pin RTCI to pin RTCO of a decoder, information about the
actual subcarrier, PAL-ID and (with SAA7111 and newer
types) definite subcarrier phase can be inserted.
The digital video encoder synthesizes all necessary
internal signals, colour subcarrier frequency and
synchronization signals from that clock.
Wide screen signalling data can be loaded via the I2C-bus
and is inserted into line 23 for standards using 50 Hz field
rate.
The IC also contains closed caption and extended data
services encoding (line 21), and supports anti-taping
signal generation in accordance with Macrovision.
A number of possibilities are provided for setting different
video parameters, such as:
•Black and blanking level control
•Colour subcarrier frequency
•Variable burst amplitude, etc.
During reset (RESET = LOW) and after reset is released,
all digital I/O stages are set to input mode. A reset forces
the I2C-bus interface to abort any running bus transfer and
sets register 3A to 03H, register 61 to 06H, registers 6BH
and 6EH to 00H and bit TTX60 to 0. No other control
registers are influenced by a reset.
7.1 Data manager
Real-time arbitration on the data stream to be encoded is
performed in the data manager.
Apre-defined colour look-up table locatedin this block can
be read out in a pre-defined sequence (8 steps per active
video line), achieving a colour bar test pattern generator
without the need for an external data source. The colour
bar function is under software control only.
7.2 Encoder
7.2.1 VIDEO PATH
The encoder generates out of Y, U and V baseband
signals luminance and colour subcarrier output signals,
suitable for use as CVBS or separate Y and C signals.
Luminance is modified in gain and in offset (latter
programmable in a certain range to enable different black
level set-ups). A blanking level can be set after insertion of
a fixed synchronization pulse tip level in accordance with
standard composite synchronization schemes. Other
manipulations used for the Macrovision anti-taping
process such as additional insertion of AGC super-white
pulses (programmable in height) are supported by the
SAA7120H only.
In order to enable easy analog post filtering, luminance is
interpolated from a 13.5 MHz data rate to a 27 MHz data
rate, providing luminance in 10-bit resolution. This filter is
also used to define smoothed transients for
synchronization pulses and blanking period. The transfer
characteristics of the luminance interpolation filter are
illustrated in Figs 5 and 6.
Chrominance is modified in gain (programmable
separately for U and V), standard dependent burst is
inserted, before baseband colour signals are interpolated
from a 6.75 MHz data rate to a 27 MHz data rate. One of
the interpolation stages can be bypassed, thus providing a
higher colour bandwidth, which can be made use of for
Y and C output. The transfer characteristics of the
chrominance interpolation filter are illustrated in
Figs 3 and 4.
Theamplitude, beginningand ending of the inserted burst,
is programmable in a certain range that is suitable for
standard signals and for special effects. Behind the
succeeding quadrature modulator, colour in a 10-bit
resolution is provided on the subcarrier.
The numeric ratio between Y and C outputs is in
accordance with the respective standards.
2002 Oct 11 8
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
7.2.2 TELETEXT INSERTION AND ENCODING
Pin TTX receives a WST or NABTS teletext bitstream
sampled at the LLC clock. At each rising edge of output
signal (TTXRQ) a single teletext bit has to be provided
after a programmable delay at the input pin.
Phase variant interpolation is achieved on this bitstream in
the internal teletext encoder, providing sufficient small
phase jitter on the output text lines.
TTXRQ provides a fully programmable request signal to
the teletext source, indicating the insertion period of
bitstream at lines which are selectable independently for
both fields. The internal insertion window for text is set to
360 (PAL-WST), 296 (NTSC-WST) or 288 (NABTS)
teletext bits including clock run-in bits. The protocol and
timing are illustrated in Fig.10.
7.2.3 CLOSED CAPTION ENCODER
Using this circuit, data in accordance with the specification
of closed caption or extended data service, delivered by
the control interface, can be encoded (line 21). Two
dedicated pairs of bytes (two bytes per field), each pair
preceded by run-in clocks and framing code, are possible.
Theactuallinenumberwheredatais to beencodedin,can
be modified in a certain range.
The data clock frequency is in accordance with the
definition for NTSC-M standard 32 times horizontal line
frequency.
DataLOWatthe output oftheDACscorrespondsto 0 IRE,
data HIGH at the output of the DACs corresponds to
approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz
field frequencies at 32 times the horizontal line frequency.
7.2.4 ANTI-TAPING (SAA7120H ONLY)
For more information contact your nearest Philips
Semiconductors sales office.
7.3 Output interface/DACs
In the output interface, encoded Y and C signals are
converted from digital-to-analog in a 10-bit resolution.
Y and C signals are also combined to a 10-bit CVBS
signal.
The CVBS output occurs with the same processing delay
as the Y and C outputs. Absolute amplitude at the input of
the DAC for CVBS is reduced by 15⁄16 with respect to
Y and C DACs to make maximum use of conversion
ranges.
Outputsof theDACs canbe settogether intwo groups,via
software control, to a minimum output voltage for either
purpose.
7.4 Synchronization
The synchronization of the SAA7120H; SAA7121H is able
to operate in two modes; slave mode and master mode.
In the slave mode, the circuit accepts synchronization
pulses at the bidirectional RCV1 port. The timing and
trigger behaviour related to RCV1 can be influenced by
programming the polarity and the on-chip delay of RCV1.
Active slope of RCV1 defines the vertical phase and
optionally the odd/even and colour frame phase to be
initialized, it also can be used to set the horizontal phase.
If the horizontal phase is not to be influenced by RCV1, a
horizontal pulse needs to be applied to pin RCV2. Timing
and trigger behaviour can also be influenced for the signal
at pin RCV2.
If there are missing pulses at RCV1 and/or RCV2, the time
base of the IC runs free, thus an arbitrary number of
synchronization slopes may miss, but no additional pulses
(with the incorrect phase) must occur.
If the vertical and horizontal phase is derived from RCV1,
RCV2 can be used for horizontal or composite blanking
input or output.
Alternatively, the device can be triggered by auxiliary
codes in a
“CCIR 656”
data stream at the MP port.
In the master mode, the time base of the circuit
continuously runs free. On the RCV1 port, the device can
output:
•A Vertical Sync (VS) signal with 3 or 2.5 lines duration
•An odd/even signal which is LOW in odd fields
•A Field Sequence (FSEQ) signal which is HIGH in the
first of 4 or 8 fields respectively.
On the RCV2 port, the IC can provide a horizontal pulse
withprogrammable start and stop phase;this pulse can be
inhibited in the vertical blanking period to build up, for
example, a composite blanking signal.
The polarity of both RCV1 and RCV2 is selectable by
software control.
The length of a field and the start and end of its active part
can be programmed. The active part of a field always
starts at the beginning of a line.
2002 Oct 11 9
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
7.5 I2C-bus interface
The I2C-bus interface is a standard slave transceiver,
supporting 7-bit slave addresses and 400 kbits/s
guaranteed transfer rate. It uses 8-bit subaddressing with
an auto-increment function. All registers are write only,
except one readable status byte.
The I2C-bus slave address is defined as 88H with pin 21
(SA) tied LOW and as 8CH with pin 21 (SA) tied HIGH.
7.6 Input levels and formats
The SAA7120H; SAA7121H expects digital Y, CB
and CRdata with levels (digital codes) in accordance
with
“CCIR 601”
.
For C and CVBS outputs, deviating amplitudes of the
colour difference signals can be compensated by
independent gain control setting, while gain for luminance
is set to predefined values, distinguishable for 7.5 IRE
set-up or without set-up.
Reference levels are measured with a colour bar,
100% white, 100% amplitude and 100% saturation.
Table 1
“CCIR 601”
signal component levels
COLOUR SIGNALS
YC
BC
R
White 235 128 128
Yellow 210 16 146
Cyan 170 166 16
Green 145 54 34
Magenta 106 202 222
Red 81 90 240
Blue 41 240 110
Black 16 128 128
Table 2 8-bit multiplexed format (similar to
“CCIR 601”
)
TIME BITS
01234567
Sample CB0Y0C
R
0Y1C
B
2Y2C
R
2Y3
Luminance pixel number 0123
Colour pixel number 0 2
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2002 Oct 11 10
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
7.7 Bit allocation map
Table 3 Slave receiver (slave address 88H or 8CH)
REGISTER FUNCTION SUBADDR DATA BYTE(1)
D7 D6 D5 D4 D3 D2 D1 D0
Null 00H to 25H 0 0000000
Wide screen signal 26H WSS7 WSS6 WSS5 WSS4 WSS3 WSS2 WSS1 WSS0
Wide screen signal 27H WSSON 0 WSS13 WSS12 WSS11 WSS10 WSS9 WSS8
Real-time control, burst start 28H DECCOL DECFIS BS5 BS4 BS3 BS2 BS1 BS0
Burst end 29H 0 0 BE5 BE4 BE3 BE2 BE1 BE0
Copy guard odd 0 2AH CGO07 CGO06 CGO05 CGO04 CGO03 CGO02 CGO01 CGO00
Copy guard odd 1 2BH CGO17 CGO16 CGO15 CGO14 CGO13 CGO12 CGO11 CGO10
Copy guard even 0 2CH CGE07 CGE06 CGE05 CGE04 CGE03 CGE02 CGE01 CGE00
Copy guard even 1 2DH CGE17 CGE16 CGE15 CGE14 CGE13 CGE12 CGE11 CGE10
Copy guard enable 2EH CGEN1 CGEN0 000000
Null 2FH to 39H 0 0000000
Input port control 3AH CBENB 0 0 SYMP 0 0 Y2C UV2C
Chrominance phase 5AH CHPS7 CHPS6 CHPS5 CHPS4 CHPS3 CHPS2 CHPS1 CHPS0
Gain U 5BH GAINU7 GAINU6 GAINU5 GAINU4 GAINU3 GAINU2 GAINU1 GAINU0
Gain V 5CH GAINV7 GAINV6 GAINV5 GAINV4 GAINV3 GAINV2 GAINV1 GAINV0
Gain U MSB, real-time control,
black level 5DH GAINU8 DECOE BLCKL5 BLCKL4 BLCKL3 BLCKL2 BLCKL1 BLCKL0
Gain V MSB, real-time control,
blanking level 5EH GAINV8 DECPH BLNNL5 BLNNL4 BLNNL3 BLNNL2 BLNNL1 BLNNL0
CCR, blanking level VBI 5FH CCRS1 CCRS0 BLNVB5 BLNVB4 BLNVB3 BLNVB2 BLNVB1 BLNVB0
Null 60H 0 0000000
Standard control 61H 0 DOWN INPI YGS 0 SCBW PAL FISE
RTC enable, burst amplitude 62H RTCE BSTA6 BSTA5 BSTA4 BSTA3 BSTA2 BSTA1 BSTA0
Subcarrier 0 63H FSC07 FSC06 FSC05 FSC04 FSC03 FSC02 FSC01 FSC00
Subcarrier 1 64H FSC15 FSC14 FSC13 FSC12 FSC11 FSC10 FSC09 FSC08
Subcarrier 2 65H FSC23 FSC22 FSC21 FSC20 FSC19 FSC18 FSC17 FSC16
Subcarrier 3 66H FSC31 FSC30 FSC29 FSC28 FSC27 FSC26 FSC25 FSC24
Line 21 odd 0 67H L21O07 L21O06 L21O05 L21O04 L21O03 L21O02 L21O01 L21O00
Line 21 odd 1 68H L21O17 L21O16 L21O15 L21O14 L21O13 L21O12 L21O11 L21O10
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2002 Oct 11 11
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Note
1. All bits labelled ‘0’ are reserved. They must be programmed with logic 0.
Line 21 even 0 69H L21E07 L21E06 L21E05 L21E04 L21E03 L21E02 L21E01 L21E00
Line 21 even 1 6AH L21E17 L21E16 L21E15 L21E14 L21E13 L21E12 L21E11 L21E10
RCV port control 6BH SRCV11 SRCV10 TRCV2 ORCV1 PRCV1 CBLF ORCV2 PRCV2
Trigger control 6CH HTRIG7 HTRIG6 HTRIG5 HTRIG4 HTRIG3 HTRIG2 HTRIG1 HTRIG0
Trigger control 6DH HTRIG10 HTRIG9 HTRIG8 VTRIG4 VTRIG3 VTRIG2 VTRIG1 VTRIG0
Multi control 6EH SBLBN 0 PHRES1 PHRES0 0 0 FLC1 FLC0
Closed caption, teletext enable 6FH CCEN1 CCEN0 TTXEN SCCLN4 SCCLN3 SCCLN2 SCCLN1 SCCLN0
RCV2 output start 70H RCV2S7 RCV2S6 RCV2S5 RCV2S4 RCV2S3 RCV2S2 RCV2S1 RCV2S0
RCV2 output end 71H RCV2E7 RCV2E6 RCV2E5 RCV2E4 RCV2E3 RCV2E2 RCV2E1 RCV2E0
MSBs RCV2 output 72H 0 RCV2E10 RCV2E9 RCV2E8 0 RCV2S10 RCV2S9 RCV2S8
TTX request H start 73H TTXHS7 TTXHS6 TTXHS5 TTXHS4 TTXHS3 TTXHS2 TTXHS1 TTXHS0
TTX request H delay 74H TTXHD7 TTXHD6 TTXHD5 TTXHD4 TTXHD3 TTXHD2 TTXHD1 TTXHD0
Vsync shift 75H 0 0000VS_S2 VS_S1 VS_S0
TTX odd request vertical start 76H TTXOVS7 TTXOVS6 TTXOVS5 TTXOVS4 TTXOVS3 TTXOVS2 TTXOVS1 TTXOVS0
TTX odd request vertical end 77H TTXOVE7 TTXOVE6 TTXOVE5 TTXOVE4 TTXOVE3 TTXOVE2 TTXOVE1 TTXOVE0
TTX even request vertical start 78H TTXEVS7 TTXEVS6 TTXEVS5 TTXEVS4 TTXEVS3 TTXEVS2 TTXEVS1 TTXEVS0
TTX even request vertical end 79H TTXEVE7 TTXEVE6 TTXEVE5 TTXEVE4 TTXEVE3 TTXEVE2 TTXEVE1 TTXEVE0
First active line 7AH FAL7 FAL6 FAL5 FAL4 FAL3 FAL2 FAL1 FAL0
Last active line 7BH LAL7 LAL6 LAL5 LAL4 LAL3 LAL2 LAL1 LAL0
MSB vertical 7CH TTX60 LAL8 0 FAL8 TTXEVE8 TTXOVE8 TTXEVS8 TTXOVS8
Null 7DH 0 0000000
Disable TTX line 7EH LINE12 LINE11 LINE10 LINE9 LINE8 LINE7 LINE6 LINE5
Disable TTX line 7FH LINE20 LINE19 LINE18 LINE17 LINE16 LINE15 LINE14 LINE13
REGISTER FUNCTION SUBADDR DATA BYTE(1)
D7 D6 D5 D4 D3 D2 D1 D0
2002 Oct 11 12
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
7.8 I2C-bus format
Table 4 I2C-bus address; see Table 5
Table 5 Explanation of Table 4
Notes
1. X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read; no subaddressing with read.
2. If more than 1 byte DATA is transmitted, then auto-increment of the subaddress is performed.
7.9 Slave receiver
Table 6 Subaddresses 26H and 27H
Table 7 Subaddresses 28H and 29H
S SLAVE ADDRESS ACK SUBADDRESS ACK DATA 0 ACK -------- DATA n ACK P
PART DESCRIPTION
S START condition
SLAVE ADDRESS 1000 100X or 1000 110X; note 1
ACK acknowledge, generated by the slave
SUBADDRESS; note 2 subaddress byte
DATA data byte
-------- continued data bytes and ACKs
P STOP condition
DATA BYTE LOGIC
LEVEL DESCRIPTION
WSS −wide screen signalling bits
3 to 0 = aspect ratio
7 to 4 = enhanced services
10 to 8 = subtitles
13 to 11 = reserved
WSSON 0 wide screen signalling output is disabled; default after reset
1 wide screen signalling output is enabled
DATA BYTE LOGIC
LEVEL DESCRIPTION REMARKS
BS −starting point of burst in clock cycles PAL: BS = 33 (21H); default after reset
NTSC: BS = 25 (19H)
BE −ending point of burst in clock cycles PAL: BE = 29 (1DH); default after reset
NTSC: BE = 29 (1DH)
DECCOL 0 disable colour detection bit of RTCI input
1 enable colour detection bit of RTCI input bit RTCE must be set to logic 1 (see Fig.9)
DECFIS 0 field sequence as FISE in subaddress 61
1 field sequence as FISE bit in RTCI input bit RTCE must be set to logic 1 (see Fig.9)
2002 Oct 11 13
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 8 Subaddresses 2AH to 2DH
Table 9 Subaddress 2EH
Table 10 Subaddress 3AH
Table 11 Subaddress 5AH
DATA BYTE DESCRIPTION REMARKS
CGO0 first byte of copy guard data, odd field LSBs of the respective bytes are encoded
immediately after run-in and framing code,
the MSBs of the respective bytes have to
carry the parity bit, in accordance with the
definition of line 20 encoding format
CGO1 second byte of copy guard data, odd field
CGE0 first byte of copy guard data, even field
CGE1 second byte of copy guard data, even field
DATA BYTE DESCRIPTION
CCEN1 CCEN0
0 0 copy guard encoding off
0 1 enables encoding in field 1 (odd)
1 0 enables encoding in field 2 (even)
1 1 enables encoding in both fields
DATA BYTE LOGIC
LEVEL DESCRIPTION
UV2C 0 CB,C
Rdata are twos complement
1C
B
,C
Rdata are straight binary; default after reset
Y2C 0 Y data is twos complement
1 Y data is straight binary; default after reset
SYMP 0 horizontal and vertical trigger is taken from RCV2 and RCV1 respectively; default after
reset
1 horizontal and vertical trigger is decoded out of
“CCIR 656”
compatible data at MP port
CBENB 0 data from input ports is encoded; default after reset
1 colour bar with fixed colours is encoded
DATA BYTE DESCRIPTION VALUE RESULT
CHPS phase of encoded colour subcarrier
(including burst) relative to horizontal
sync; can be adjusted in steps of
360/256 degrees
00H PAL-B/G and data from input ports
2AH PAL-B/G and data from look-up table
88H NTSC-M and data from input ports
AAH NTSC-M and data from look-up table
2002 Oct 11 14
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 12 Subaddresses 5BH and 5DH
Table 13 Subaddresses 5CH and 5EH
Table 14 Subaddress 5DH
Notes
1. Output black level/IRE = BLCKL ×2/6.29 + 34.0.
2. Output black level/IRE = BLCKL ×2/6.18 + 31.7.
DATA BYTE DESCRIPTION CONDITIONS REMARKS
GAINU variable gain for
CBsignal; input
representation in
accordance with
“CCIR 601”
white-to-black = 92.5 IRE GAINU = −2.17 ×nominal to +2.16 ×nominal
GAINU = 0 output subcarrier of U contribution = 0
GAINU = 118 (76H) output subcarrier of U contribution = nominal
white-to-black = 100 IRE GAINU = −2.05 ×nominal to +2.04 ×nominal
GAINU = 0 output subcarrier of U contribution = 0
GAINU = 125 (7DH) output subcarrier of U contribution = nominal
DATA BYTE DESCRIPTION CONDITIONS REMARKS
GAINV variable gain for
CRsignal; input
representation in
accordance with
“CCIR 601”
white-to-black = 92.5 IRE GAINV = −1.55 ×nominal to +1.55 ×nominal
GAINV = 0 output subcarrier of V contribution = 0
GAINV = 165 (A5H) output subcarrier of V contribution = nominal
white-to-black = 100 IRE GAINV = −1.46 ×nominal to +1.46 ×nominal
GAINV = 0 output subcarrier of V contribution = 0
GAINV = 175 (AFH) output subcarrier of V contribution = nominal
DATA BYTE DESCRIPTION CONDITIONS REMARKS
BLCKL variable black level; input
representation in
accordance with
“CCIR 601”
white-to-sync = 140 IRE;
note 1 recommended value: BLCKL = 42 (2AH)
BLCKL = 0; note 1 output black level = 34 IRE
BLCKL = 63 (3FH); note 1 output black level = 54 IRE
white-to-sync = 143 IRE;
note 2 recommended value: BLCKL = 35 (23H)
BLCKL = 0; note 2 output black level = 32 IRE
BLCKL = 63 (3FH); note 2 output black level = 52 IRE
DECOE real-time control logic 0 disable odd/even field control bit from RTCI
logic 1 enable odd/even field control bit from RTCI
(see Fig.9)
2002 Oct 11 15
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 15 Subaddress 5EH
Notes
1. Output black level/IRE = BLNNL ×2/6.29 + 25.4.
2. Output black level/IRE = BLNNL ×2/6.18 + 25.9; default after reset: 35H.
Table 16 Subaddress 5FH
Table 17 Logic levels and function of CCRS
DATA BYTE DESCRIPTION CONDITIONS REMARKS
BLNNL variable blanking level white-to-sync = 140 IRE;
note 1 recommended value: BLNNL = 46 (2EH)
BLNNL = 0; note 1 output blanking level = 25 IRE
BLNNL = 63 (3FH); note 1 output blanking level = 45 IRE
white-to-sync = 143 IRE;
note 2 recommended value: BLNNL = 53 (35H)
BLNNL = 0; note 2 output blanking level = 26 IRE
BLNNL = 63 (3FH); note 2 output blanking level = 46 IRE
DECPH real-time control logic 0 disable subcarrier phase reset bit from RTCI
logic 1 enable subcarrier phase reset bit from RTCI
(see Fig.9)
DATA BYTE DESCRIPTION
BLNVB variable blanking level during vertical blanking interval is typically identical to value of BLNNL
CCRS select cross-colour reduction filter in luminance; see Table 17
CCRS1 CCRS0 DESCRIPTION
0 0 no cross-colour reduction; for overall transfer characteristic of luminance see Fig.5
0 1 cross-colour reduction #1 active; for overall transfer characteristic see Fig.5
1 0 cross-colour reduction #2 active; for overall transfer characteristic see Fig.5
1 1 cross-colour reduction #3 active; for overall transfer characteristic see Fig.5
2002 Oct 11 16
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 18 Subaddress 61H
Table 19 Subaddress 62H
Table 20 Subaddress 62H
DATA BYTE LOGIC
LEVEL DESCRIPTION
FISE 0 864 total pixel clocks per line; default after reset
1 858 total pixel clocks per line
PAL 0 NTSC encoding (non-alternating V component)
1 PAL encoding (alternating V component); default after reset
SCBW 0 enlarged bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4)
1 standard bandwidth for chrominance encoding (for overall transfer characteristic of
chrominance in baseband representation see Figs 3 and 4); default after reset
YGS 0 luminance gain for white −black 100 IRE; default after reset
1 luminance gain for white −black 92.5 IRE including 7.5 IRE set-up of black
INPI 0 PAL switch phase is nominal; default after reset
1 PAL switch phase is inverted compared to nominal if RTC is enabled; see Table 19
DOWN 0 DACs for CVBS, Yand C in normal operational mode; default after reset
1 DACs for CVBS, Yand C forced to lowest output voltage
DATA BYTE LOGIC
LEVEL DESCRIPTION
RTCE 0 no real-time control of generated subcarrier frequency; default after reset
1 real-time control of generated subcarrier frequency through SAA7151B or SAA7111;
for timing see Fig.9
DATA BYTE DESCRIPTION CONDITIONS REMARKS
BSTA amplitude of colour burst; input
representation in accordance
with
“CCIR 601”
white-to-black = 92.5 IRE;
burst = 40 IRE; NTSC encoding recommended value:
BSTA = 63 (3FH)
BSTA = 0 to 2.02 ×nominal
white-to-black = 92.5 IRE;
burst = 40 IRE; PAL encoding recommended value:
BSTA = 45 (2DH)
BSTA = 0 to 2.82 ×nominal
white-to-black = 100 IRE;
burst = 43 IRE; NTSC encoding recommended value:
BSTA = 67 (43H)
BSTA = 0 to 1.90 ×nominal
white-to-black = 100 IRE;
burst = 43 IRE; PAL encoding recommended value:
BSTA = 47 (2FH); default after
reset
BSTA = 0 to 3.02 ×nominal
2002 Oct 11 17
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 21 Subaddresses 63H to 66H (four bytes to program subcarrier frequency)
Note
1. Examples:
a) NTSC-M: fsc = 227.5, fllc = 1716 →FSC = 569408543 (21F07C1FH).
b) PAL-B/G: fsc = 283.7516, fllc = 1728 →FSC = 705268427 (2A098ACBH).
Table 22 Subaddresses 67H to 6AH
Table 23 Subaddress 6BH
DATA BYTE DESCRIPTION CONDITIONS REMARKS
FSC0 to
FSC3 fsc = subcarrier frequency (in
multiples of line frequency);
fllc = clock frequency (in
multiples of line frequency) note 1
FSC3 = most significant byte;
FSC0 = least significant byte
DATA BYTE DESCRIPTION REMARKS
L21O0 first byte of captioning data, odd field LSBs of the respective bytes are encoded
immediately after run-in and framing code, the
MSBs of the respective bytes have to carry the
parity bit, in accordance with the definition of
line 21 encoding format
L21O1 second byte of captioning data, odd field
L21E0 first byte of extended data, even field
L21E1 second byte of extended data, even field
DATA BYTE LOGIC
LEVEL DESCRIPTION
PRCV2 0 polarity of RCV2 as output is active HIGH, rising edge is taken when input, respectively;
default after reset
1 polarity of RCV2 as output is active LOW, falling edge is taken when input, respectively
ORCV2 0 pin RCV2 is switched to input; default after reset
1 pin RCV2 is switched to output
CBLF 0 if ORCV2 = HIGH, pin RCV2 provides an HREF signal (horizontal reference pulse that is
defined by RCV2S and RCV2E, also during vertical blanking interval); default after reset
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization only (if TRCV2 = 1); default after reset
1 if ORCV2 = HIGH, pin RCV2 provides a ‘composite-blanking-not’ signal, for example a
reference pulse that is defined by RCV2S and RCV2E, excluding vertical blanking interval,
which is defined by FAL and LAL
if ORCV2 = LOW and bit SYMP = LOW, signal input to RCV2 is used for horizontal
synchronization (if TRCV2 = 1) and as an internal blanking signal
PRCV1 0 polarity of RCV1 as output is active HIGH, rising edge is taken when input; default after reset
1 polarity of RCV1 as output is active LOW, falling edge is taken when input
ORCV1 0 pin RCV1 is switched to input; default after reset
1 pin RCV1 is switched to output
TRCV2 0 horizontal synchronization is taken from RCV1 port (at bit SYMP = LOW) or from decoded
frame sync of “
CCIR 656”
input (at bit SYMP = HIGH); default after reset
1 horizontal synchronization is taken from RCV2 port (at bit SYMP = LOW)
SRCV1 −defines signal type on pin RCV1; see Table 24
FSC round fsc
fllc
------ 232
×
;=
2002 Oct 11 18
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 24 Logic levels and function of SRCV1
Table 25 Subaddresses 6CH and 6DH
Table 26 Subaddress 6DH
Table 27 Subaddress 6EH
Table 28 Logic levels and function of PHRES
DATA BYTE AS OUTPUT AS INPUT FUNCTION
SRCV11 SRCV10
0 0 VS VS vertical sync each field; default after reset
0 1 FS FS frame sync (odd/even)
1 0 FSEQ FSEQ field sequence, vertical sync every fourth field (PAL = 0)
or eighth field (PAL = 1)
11−−not applicable
DATA BYTE DESCRIPTION
HTRIG sets the horizontal trigger phase related to signal on RCV1 or RCV2 input
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; increasing HTRIG decreases
delays of all internally generated timing signals; reference mark: analog output horizontal sync
(leading slope) coincides with active edge of RCV used for triggering at HTRIG = 398H (398H)
DATA BYTE DESCRIPTION
VTRIG sets the vertical trigger phase related to signal on RCV1 input
increasing VTRIG decreases delays of all internally generated timing signals, measured in half lines;
variation range of VTRIG=0to31(1FH)
DATA BYTE LOGIC
LEVEL DESCRIPTION
SBLBN 0 vertical blanking is defined by programming of FAL and LAL; default after reset
1 vertical blanking is forced in accordance with
“CCIR 624”
(50 Hz) or RS170A (60 Hz)
PHRES −selects the phase reset mode of the colour subcarrier generator; see Table 28
FLC −field length control; see Table 29
DATA BYTE DESCRIPTION
PHRES1 PHRES0
0 0 no reset or reset via RTCI from SAA7111 if bit RTCE = 1; default after reset
0 1 reset every two lines
1 0 reset every eight fields
1 1 reset every four fields
2002 Oct 11 19
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 29 Logic levels and function of FLC
Table 30 Subaddress 6FH
Table 31 Logic levels and function of CCEN
Table 32 Subaddresses 70H to 72H
Table 33 Subaddresses 73H and 74H
DATA BYTE DESCRIPTION
FLC1 FLC0
0 0 interlaced 312.5 lines/field at 50 Hz, 262.5 lines/field at 60 Hz; default after reset
0 1 non-interlaced 312 lines/field at 50 Hz, 262 lines/field at 60 Hz
1 0 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
1 1 non-interlaced 313 lines/field at 50 Hz, 263 lines/field at 60 Hz
DATA BYTE LOGIC
LEVEL DESCRIPTION
CCEN −enables individual line 21 encoding; see Table 31
TTXEN 0 disables teletext insertion; default after reset
1 enables teletext insertion
SCCLN −selects the actual line, where closed caption or extended data are encoded;
line = (SCCLN + 4) for M-systems; line = (SCCLN + 1) for other systems
DATA BYTE DESCRIPTION
CCEN1 CCEN0
0 0 line 21 encoding off; default after reset
0 1 enables encoding in field 1 (odd)
1 0 enables encoding in field 2 (even)
1 1 enables encoding in both fields
DATA BYTE DESCRIPTION
RCV2S start of output signal on pin RCV2
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; first active pixel at analog outputs
(corresponding input pixel coinciding with RCV2) at RCV2S = 11AH (0FDH)
RCV2E end of output signal on pin RCV2
values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed; last active pixel at analog outputs
(corresponding input pixel coinciding with RCV2) at RCV2E = 694H (687H)
DATA BYTE DESCRIPTION REMARKS
TTXHS start of signal on pin TTXRQ; see Fig.10 PAL: TTXHS = 42H
NTSC: TTXHS = 54H
TTXHD indicates the delay in clock cycles between rising edge of
TTXRQ output and valid data at pin TTX minimum value: TTXHD = 2
2002 Oct 11 20
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 34 Subaddress 75H
Table 35 Subaddresses 76H, 77H and 7CH
Table 36 Subaddresses 78H, 79H and 7CH
Table 37 Subaddresses 7AH to 7CH
Table 38 Subaddress 7CH
DATA BYTE DESCRIPTION REMARKS
VS_S vertical sync shift between RCV1 and RCV2 (switched to
output); in master mode it is possible to shift Hsync (RCV2;
CBLF = 0) against Vsync (RCV1; SRCV1 = 00)
standard value: VS_S = 3
DATA BYTE DESCRIPTION REMARKS
TTXOVS first line of occurrence of signal on pin TTXRQ in odd field PAL: TTXOVS = 05H;
NTSC: TTXOVS = 06H
line = (TTXOVS + 4) for M-systems
line = (TTXOVS + 1) for other systems
TTXOVE last line of occurrence of signal on pin TTXRQ in odd field PAL: TTXOVE = 16H;
NTSC: TTXOVE = 10H
line = (TTXOVE + 3) for M-systems
line = TTXOVE for other systems
DATA BYTE DESCRIPTION REMARKS
TTXEVS first line of occurrence of signal on pin TTXRQ in even field PAL: TTXEVS = 04H;
NTSC: TTXEVS = 05H
line = (TTXEVS + 4) for M-systems
line = (TTXEVS + 1) for other systems
TTXEVE last line of occurrence of signal on pin TTXRQ in even field PAL: TTXEVE = 16H;
NTSC: TTXEVE = 10H
line = (TTXEVE + 3) for M-systems
line = TTXEVE for other systems
DATA BYTE DESCRIPTION
FAL first active line: measured in lines; FAL = 0 coincides with the first field synchronization pulse
first active line = (FAL + 4) for M systems
first active line = (FAL + 1) for other systems
LAL last active line: measured in lines; LAL = 0 coincides with the first field synchronization pulse
last active line = (LAL + 3) for M-systems
last active line = LAL for other systems
DATA BYTE LOGIC LEVEL DESCRIPTION
TTX60 0 enables NABTS (FISE = 1) or European TTX (FISE = 0); default after reset
1 enables world standard teletext 60 Hz (FISE = 1)
2002 Oct 11 21
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Table 39 Subaddresses 7EH and 7FH
In subaddresses 5BH, 5CH, 5DH, 5EH and 62H all IRE values are rounded up.
7.10 Slave transmitter
Table 40 Slave transmitter (slave address 89H or 8DH)
Table 41 No subaddress
DATA BYTE DESCRIPTION
LINE individual lines in both fields (PAL counting) can be disabled for insertion of teletext by the respective
bits, disabled line = LINExx (50 Hz field rate); this bit mask is effective only, if the lines are enabled by
TTXOVS/TTXOVE and TTXEVS/TTXEVE
REGISTER
FUNCTION SUBADDRESS DATA BYTE
D7 D6 D5 D4 D3 D2 D1 D0
Status byte −VER2 VER1 VER0 CCRDO CCRDE FSEQ2 FSEQ1 O_E
DATA BYTE LOGIC LEVEL DESCRIPTION
VER −version identification of the device: it will be changed with all versions of the IC that
have different programming models; current version is 001 binary
CCRDO 1 closed caption bytes of the odd field have been encoded
0 the bit is reset after information has been written to the subaddresses
67H and 68H; it is set immediately after the data has been encoded
CCRDE 1 closed caption bytes of the even field have been encoded
0 the bit is reset after information has been written to the subaddresses
69H and 6AH; it is set immediately after the data has been encoded
FSEQ −state of the internal field sequence counter, with bit O_E as LSB
(repetition rate: NTSC = 4 fields, PAL = 8 fields)
O_E 1 during even field
0 during odd field
2002 Oct 11 22
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
handbook, full pagewidth
6 8 10 12 14
6
0
024
MBE737
−6
−12
−18
−30
−24
−36
−42
−54
−48
f (MHz)
Gv
(dB)
(1) (2)
Fig.3 Chrominance transfer characteristic 1.
(1) SCBW = 1.
(2) SCBW = 0.
handbook, halfpage
0 0.4 0.8 1.6
2
0
−4
−6
−2
MBE735
1.2 f (MHz)
Gv
(dB)
(1)
(2)
Fig.4 Chrominance transfer characteristic 2.
(1) SCBW = 1.
(2) SCBW = 0.
2002 Oct 11 23
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Fig.5 Luminance transfer characteristic 1.
(1) CCRS1 = 0; CCRS0 = 1.
(2) CCRS1 = 1; CCRS0 = 0. (3) CCRS1 = 1; CCRS0 = 1.
(4) CCRS1 = 0; CCRS0 = 0.
handbook, full pagewidth
6
(1)
(2)
(4)
(3)
8101214
6
0
024
MGD672
−6
−12
−18
−30
−24
−36
−42
−54
−48
f (MHz)
Gv
(dB)
handbook, halfpage
02
(1)
6
1
0
−1
−2
−3
−4
−5
MBE736
4f (MHz)
Gv
(dB)
Fig.6 Luminance transfer characteristic 2.
(1) CCRS1 = 0; CCRS0 = 0.
2002 Oct 11 24
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
8 CHARACTERISTICS
VDDD = 3.0 to 3.6 V; Tamb = 0 to 70 °C; unless otherwise specified.
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
Supply
VDDA analog supply voltage 3.1 3.5 V
VDDD digital supply voltage 3.0 3.6 V
IDDA analog supply current note 1 −62 mA
IDDD digital supply current VDDD = 3.3 V; note 1 −45 mA
Inputs: LLC, RCV1, RCV2, MP7 to MP0, RTCI, SA, RESET and TTX
VIL LOW-level input voltage −0.5 +0.8 V
VIH HIGH-level input voltage 2.0 VDDD + 0.3 V
ILI input leakage current −1µA
Ciinput capacitance clocks −10 pF
data −8pF
I/Os at
high-impedance −8pF
Outputs: RCV1, RCV2 and TTXRQ
VOL LOW-level output voltage IOL =2mA −0.4 V
VOH HIGH-level output voltage IOH =−2 mA 2.4 −V
I2C-bus: SDA and SCL
VIL LOW-level input voltage −0.5 +0.3VDDD V
VIH HIGH-level input voltage 0.7VDDD VDDD + 0.3 V
Iiinput current Vi= LOW or HIGH −10 +10 µA
VOL LOW-level output voltage (pin SDA) IOL =3mA −0.4 V
Iooutput current during acknowledge 3 −mA
Clock timing: LLC
TLLC cycle time note 2 34 41 ns
δduty factor tHIGH/TLLC note 3 40 60 %
trrise time note 2 −5ns
t
ffall time note 2 −6ns
Input timing: RCV1, RCV2, MP7 to MP0, RTCI, SA and TTX
tSU;DAT input data set-up time 6 −ns
tHD;DAT input data hold time 3 −ns
2002 Oct 11 25
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
Notes
1. At maximum supply voltage with highly active input signals.
2. The data is for both input and output direction.
3. With LLC in input mode. In output mode, with a crystal connected to XTALO/XTALI duty factor is typically 50%.
4. If an internal oscillator is used, crystal deviation of nominal frequency is directly proportional to the deviation of
subcarrier frequency and line/field frequency.
5. For full digital range, without load, VDDA = 3.3 V. The typical voltage swing is 1.35 V, the typical minimum output
voltage (digital zero at DAC) is 0.2 V.
Crystal oscillator
fnnominal frequency (usually 27 MHz) 3rd harmonic −30 MHz
∆f/fnpermissible deviation of nominal frequency note 4 −50 ×10−6+50 ×10−6
CRYSTAL SPECIFICATION
Tamb ambient temperature 0 70 °C
CLload capacitance 8 −pF
RSseries resistance −80 Ω
C1motional capacitance (typical) 1.5 −20% 1.5 + 20% fF
C0parallel capacitance (typical) 3.5 −20% 3.5 + 20% pF
Data and reference signal output timing
CLoutput load capacitance 7.5 40 pF
thoutput hold time 4 −ns
tdoutput delay time −25 ns
C, Y and CVBS outputs
Vo(p-p) output signal voltage (peak-to-peak value) note 5 1.25 1.50 V
Rint internal serial resistance 1 3 Ω
RLoutput load resistance 75 300 Ω
B output signal bandwidth of DACs −3dB 10 −MHz
LElf(i) low frequency integral linearity error of DACs −±3 LSB
LElf(d) low frequency differential linearity error of DACs −±1 LSB
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
2002 Oct 11 26
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
handbook, full pagewidth
MBE742
LLC clock output 0.6 V
1.5 V
2.6 V
2.0 V
0.8 V
2.4 V
0.6 V
input data
output data
not valid valid
valid
not valid valid
valid
LLC clock input
0.8 V
1.5 V
2.4 V
tHIGH
tHD; DAT
TLLC
tHIGH TLLC
td
tHD; DAT
tHD; DAT
tSU; DAT
tf
tf
tr
tr
Fig.7 Clock data timing.
handbook, full pagewidth
MP(n)
LLC
CB(0) Y(0) CR(0) Y(1) CB(2)
RCV2
MGB699
The data demultiplexing phase is coupled to the internal horizontal phase.
The phase of the RCV2 signal is programmed to 262 for 50 Hz and to 234 for 60 Hz in this example in output mode (RCV2S).
Fig.8 Functional timing.
2002 Oct 11 27
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
8.1 Explanation of RTCI data bits
1. The HPLL increment is not evaluated by the
SAA7120H; SAA7121H.
2. The SAA7120H; SAA7121H generates the subcarrier
frequency from the FSCPLL increment if enabled
(see item 7.).
3. The PAL bit indicates the line with inverted (R −Y)
component of colour difference signal.
4. If the reset bit is enabled (RTCE = 1; DECPH = 1;
PHRES = 00), the phase of the subcarrier is reset in
each line whenever the reset bit of RTCI input is set to
logic 1.
5. Ifthe FISEbit isenabled (RTCE = 1; DECFIS = 1),the
SAA7120H; SAA7121H takes this bit instead of the
FISE bit in subaddress 61H.
6. Iftheodd/evenbitisenabled(RTCE = 1;DECOE = 1),
the SAA7120H; SAA7121H ignores its internally
generated odd/even flag and takes the odd/even bit
from RTCI input.
7. If the colour detection bit is enabled (RTCE = 1;
DECCOL = 1) and no colour was detected (colour
detection bit = 0), the subcarrier frequency is
generated by the SAA7120H; SAA7121H. In the other
case (colour detection bit = 1) the subcarrier
frequency is evaluated out of FSCPLL increment.
If the colour detection bit is disabled (RTCE = 1;
DECCOL = 0), the subcarrier frequency is evaluated
out of FSCPLL increment, independent of the colour
detection bit of RTCI input.
handbook, full pagewidth
128
13
14 19 6764 69 72 74
68
01
0 022
RTCI
HPLL
increment
(1)
FSCPLL increment
(2)
HIGH-to-LOW transition
count start 4 bits
reserved
valid
sample invalid
sample
not used in SAA7120H/21H
3 bits
reserved
8/LLC
MBH789
LOW
time slot:
(3)(4) (6) (7)
(8)
(5)
Fig.9 RTCI timing.
(1) SAA7111/12 provides 14 to 0 bits, resulting in 2 reserved bits before FSCPLL increment.
(2) SAA7151 provides 21 to 0 bits only, resulting in 5 reserved bits before sequence bit.
(3) Sequence bit: PAL: 0 = (R −Y) line normal, 1 = (R −Y) line inverted; NTSC: 0 = no change.
(4) Reset bit: only from SAA7111 and SAA7112 decoder.
(5) FISE bit: 0 = 50 Hz, 1 = 60 Hz.
(6) Odd/even bit: odd_even from external.
(7) Colour detection: 0 = no colour detected, 1 = colour detected.
(8) Reserved bits: 229 with 50 Hz systems, 226 with 60 Hz systems.
2002 Oct 11 28
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
8.2 Teletext timing
Time tFD is the time needed to interpolate input data TTX
and insert it into the CVBS and Y output signal, such that
it appears at tTTX = 9.78 µs (PAL) or tTTX = 10.5 µs
(NTSC) after the leading edge of the horizontal
synchronization pulse.
Time tPD is the pipeline delay time introduced by the
source that is gated by TTXRQ in order to deliver TTX
data. This delay is programmable by register TTXHD. For
every active HIGH state at output pin TTXRQ, a new
teletext bit must be provided by the source.
Sincethe beginning ofthe pulsesrepresentingthe TTXRQ
signal and the delay between the rising edge of TTXRQ
and valid teletext input data are fully programmable
(TTXHS and TTXHD), the TTX data is always inserted at
the correct position after the leading edge of outgoing
horizontal synchronization pulse.
Time tTTXWin is the internally used insertion window for
TTX data; it has a constant length that allows insertion of
360 teletextbitsatatextdatarate of 6.9375 Mbits/s(PAL),
296 teletextbitsatatextdatarateof5.7272 Mbits/s(WST)
or 288 teletext bits at a text data rate of 5.7272 Mbits/s
(NABTS).The insertionwindow is notopened ifthe control
bit TTXEN is logic 0.
Using appropriate programming, all suitable lines of the
odd field (TTXOVS and TTXOVE) plus all suitable lines of
the even field (TTXEVS and TTXEVE) can be used for
teletext insertion.
handbook, full pagewidth
tTTXWin
tTTX
tPD tFD
CVBS/Y
TTX
TTXRQ
textbit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
MBH788
Fig.10 Teletext timing.
2002 Oct 11 29
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
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9 APPLICATION INFORMATION
handbook, full pagewidth
2 Ω
(1)
4.7 Ω
75 Ω
AGND
30 CVBS
DAC1
DAC2
DAC3
VDDA3
UCVBS
1.23 V (p-p)
(2)
10 Ω
75 Ω
AGND
Y
UY
1.00 V (p-p)
(2)
MBH786
10 Ω
75 Ω
AGND
AGND
DGND
C
UC
0.89 V (p-p)
(2)
31
AGNDAGND
VDDA2
28
32, 33
5, 18, 38
VDDA1
+3.3 V analog
+3.3 V digital
VSSD1, VSSD2, VSSD3
VDDD1, VDDD2, VDDD3
VSSA1, VSSA2
25366, 17, 3935 34
XTALI XTALO
10 pF 10 pF
X1
use one capacitor
for each VDDD
2 Ω
(1)
27
VDDA4
2 Ω
(1)
24
0.1 µF 0.1 µF
AGND
0.1 µF
AGND
0.1 µF
DGND
DGND
0.1 µF
10 µH
1 nF
3rd harmonic
27.0 MHz
digital
inputs and
outputs
SAA7120H
SAA7121H
Fig.11 Application circuit.
(1) Typical value.
(2) For 100⁄100 colour bar.
2002 Oct 11 30
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
9.1 Analog output voltages
Theanalog outputvoltages aredependent onthe open-loopvoltage of the operational amplifiers for full-scale conversion
(typical value 1.35 V), the internal series resistor (typical value 2 Ω), the external series resistor and the external load
impedance.
The digital output signals in front of the DACs under nominal conditions occupy different conversion ranges, as indicated
in Table 42 for a 100⁄100 colour bar signal.
Values for the external series resistors result in a 75 Ω load.
Table 42 Digital output signals conversion range
CONVERSION RANGE (peak-to-peak)
CVBS
SYNC-TIP TO PEAK-CARRIER (digits) Y (VBS)
SYNC-TIP TO WHITE (digits)
1016 881
2002 Oct 11 31
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
10 PACKAGE OUTLINE
UNIT A1A2A3bpcE
(1) eH
E
LL
pZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC EIAJ
mm 0.25
0.05 1.85
1.65 0.25 0.40
0.20 0.25
0.14 10.1
9.9 0.8 1.3
12.9
12.3 1.2
0.8 10
0
o
o
0.15 0.10.15
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
0.95
0.55
SOT307-2 95-02-04
97-08-01
D(1) (1)(1)
10.1
9.9
HD
12.9
12.3
E
Z
1.2
0.8
D
e
E
B
11
c
E
H
D
ZD
A
ZE
e
vMA
X
1
44
34 33 23 22
12
y
θ
A1
A
Lp
detail X
L
(A )
3
A2
pin 1 index
D
HvMB
bp
bp
wM
wM
0 2.5 5 mm
scale
QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2
A
max.
2.10
2002 Oct 11 32
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
11 SOLDERING
11.1 Introduction to soldering surface mount
packages
Thistextgivesa very briefinsighttoacomplex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering can still be used for
certainsurfacemountICs,butit is not suitableforfinepitch
SMDs. In these situations reflow soldering is
recommended.
11.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
tothe printed-circuit boardby screenprinting,stencilling or
pressure-syringe dispensing before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Throughput times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
11.3 Wave soldering
Conventional single wave soldering is not recommended
forsurfacemountdevices(SMDs)or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
•Forpackageswithleadsonfour sides, the footprintmust
be placed at a 45°angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
11.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
2002 Oct 11 33
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
11.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. Formore detailed informationon the BGApackagesrefer tothe
“(LF)BGAApplication Note
”(AN01026); order acopy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the
“Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”
.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE(1) SOLDERING METHOD
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN,
HVSON, SMS not suitable(3) suitable
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
2002 Oct 11 34
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
12 DATA SHEET STATUS
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
LEVEL DATA SHEET
STATUS(1) PRODUCT
STATUS(2)(3) DEFINITION
I Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
II Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
III Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Relevant changes will
be communicated via a Customer Product/Process Change Notification
(CPCN).
13 DEFINITIONS
Short-form specification The data in a short-form
specification is extracted from a full data sheet with the
same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limiting values definition Limiting values given are in
accordance with the Absolute Maximum Rating System
(IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device.
These are stress ratings only and operation of the device
attheseor at anyotherconditionsabove thosegiveninthe
Characteristics sections of the specification is not implied.
Exposure to limiting values for extended periods may
affect device reliability.
Application information Applications that are
described herein for any of these products are for
illustrative purposes only. Philips Semiconductors make
norepresentationorwarrantythatsuchapplicationswillbe
suitable for the specified use without further testing or
modification.
14 DISCLAIMERS
Life support applications These products are not
designed for use in life support appliances, devices, or
systems where malfunction of these products can
reasonably be expected to result in personal injury. Philips
Semiconductorscustomersusingorsellingtheseproducts
for use in such applications do so at their own risk and
agree to fully indemnify Philips Semiconductors for any
damages resulting from such application.
Right to make changes Philips Semiconductors
reserves the right to make changes in the products -
including circuits, standard cells, and/or software -
described or contained herein in order to improve design
and/or performance. When the product is in full production
(status ‘Production’), relevant changes will be
communicated via a Customer Product/Process Change
Notification (CPCN). Philips Semiconductors assumes no
responsibility or liability for the use of any of these
products, conveys no licence or title under any patent,
copyright, or mask work right to these products, and
makes no representations or warranties that these
products are free from patent, copyright, or mask work
right infringement, unless otherwise specified.
2002 Oct 11 35
Philips Semiconductors Product specification
Digital video encoder SAA7120H; SAA7121H
15 PURCHASE OF PHILIPS I2C COMPONENTS
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent to use the
components in the I2C system provided the system conforms to the I2C specification defined by
Philips. This specification can be ordered using the code 9398 393 40011.
© Koninklijke Philips Electronics N.V. 2002 SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Philips Semiconductors – a world wide company
Contact information
For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825
For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
Printed in The Netherlands 753505/02/pp36 Date of release: 2002 Oct 11 Document order number: 9397 750 09829
