General Description
The MAX1870A step-up/step-down multichemistry bat-
tery charger charges with battery voltages above and
below the adapter voltage. This highly integrated
charger requires a minimum number of external compo-
nents. The MAX1870A uses a proprietary step-up/step-
down control scheme that provides efficient charging.
Analog inputs control charge current and voltage, and
can be programmed by the host or hardwired.
The MAX1870A accurately charges two to four lithium-
ion (Li+) series cells at greater than 4A. A programma-
ble input current limit is included, which avoids
overloading the AC adapter when supplying the load
and the battery charger simultaneously. This reduces
the maximum adapter current, which reduces cost. The
MAX1870A provides analog outputs to monitor the cur-
rent drawn from the AC adapter and charge current. A
digital output indicates the presence of an AC adapter.
When the adapter is removed, the MAX1870A con-
sumes less than 1µA from the battery.
The MAX1870A is available in a 32-pin thin QFN (5mm
x 5mm) package and is specified over the -40°C to
+85°C extended temperature range. The MAX1870A
evaluation kit (MAX1870AEVKIT) is available to help
reduce design time.
Applications
Notebook and Subnotebook Computers
Handheld Terminals
Features
♦Step-Up/Step-Down Control Scheme
♦±0.5% Charge-Voltage Accuracy
♦±9% Charge-Current Accuracy
♦±8% Input Current-Limit Accuracy
♦Programmable Maximum Battery Charge Current
♦Analog Inputs Control Charge Current, Charge
Voltage, and Input Current Limit
♦Analog Output Indicates Adapter Current
♦Input Voltage from 8V to 28V
♦Battery Voltage from 0 to 17.6V
♦Charges Li+ or NiCd/NiMH Batteries
♦Tiny 32-Pin Thin QFN (5mm x 5mm) Package
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
MAX1870A
REFIN
DCIN
CSSP
CSSN
DHI
DBST
CSIP
CSIN
BATT
SHDN
ASNS
VCTL
IINP
PGND
SYSTEM
LOAD
N
P
GND
ICTL
CLS
CELLS
FROM WALL ADAPTER
CSSS
VHN
VHP
BLKP
REF
LDO
DLOV
Typical Operating Circuit
19-3243; Rev 1; 9/05
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
EVALUATION KIT
AVAILABLE
Pin Configuration appears at end of data sheet.
PART TEMP RANGE PIN-PACKAGE
MAX1870AETJ
-40°C to +85°C 32 Thin QFN
MAX1870AETJ+
-40°C to +85°C 32 Thin QFN
+Denotes lead-free package.
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
DCIN, CSSP, CSSS, CSSN,
VHP, VHN, DHI to GND ......................................-0.3V to +30V
VHP, DHI to VHN .....................................................-0.3V to +6V
BATT, CSIP, CSIN, BLKP to GND ..........................-0.3V to +20V
CSIP to CSIN, CSSP to CSSN,
CSSP to CSSS, PGND to GND ..........................-0.3V to +0.3V
CCI, CCS, CCV, REF, IINP to GND ..........-0.3V to (VLDO + 0.3V)
DBST to GND..........................................-0.3V to (VDLOV + 0.3V)
DLOV, VCTL, ICTL, REFIN, CELLS,
CLS, LDO, ASNS, SHDN to GND .........................-0.3V to +6V
LDO Current........................................................................50mA
Continuous Power Dissipation (TA= +70°C)
32-Pin Thin QFN 5mm x 5mm
(derate 21mW/°C above +70°C)......................................1.7W
Operating Temperature Range
MAX1870AETJ.................................................-40°C to +85°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) ................................ +300°C
PARAMETER CONDITIONS
MIN
TYP
UNITS
CHARGE-VOLTAGE REGULATION
VCTL Range 0 3.6 V
VVCTL = VLDO (2 cells)
-0.5
+0.5
VVCTL = VLDO (3 cells)
-0.5
+0.5
VVCTL = VLDO (4 cells)
-0.5
+0.5
VVCTL = VREFIN (2 cells)
-0.8
+0.8
VVCTL = VREFIN (3 cells)
-0.8
+0.8
VVCTL = VREFIN (4 cells)
-0.8
+0.8
VVCTL = VREFIN / 20 (2 cells)
-1.2
+1.2
VVCTL = VREFIN / 20 (3 cells)
-1.2
+1.2
Battery Regulation Voltage
Accuracy
VVCTL = VREFIN / 20 (4 cells)
-1.2
+1.2
%
VCTL Default Threshold VCTL rising 4.0 4.1 4.2 V
0 < VVCTL < VREFIN -1 +1
DCIN = 0, VREFIN = VVCTL = 3.6V -1 +1
VCTL Input Bias Current
VCTL = DCIN = 0, VREFIN = 3.6V -1 +1
µA
CHARGE-CURRENT REGULATION
ICTL Range 0 3.6 V
VICTL = VREFIN 67 73 79
VICTL = VREFIN x 0.8 54 59 64
Quick-Charge-Current Accuracy
VICTL = VREFIN x 0.583 39 43 47
mV
Trickle-Charge-Current Accuracy
VICTL = VREFIN x 0.0625 3.0 4.5 6.0 mV
BATT/CSIP/CSIN Input Voltage
Range 0 19 V
DCIN = 0 0.1 2
ICTL = 0 0.1 2 CSIP Input Current
ICTL = REFIN
350
600
µA
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
_______________________________________________________________________________________ 3
PARAMETER CONDITIONS
MIN
TYP
UNITS
DCIN = 0 0.1 2
ICTL = 0 0.1 2 CSIN Input Current
ICTL = REFIN 0.1 2
µA
ICTL Power-Down-Mode
Threshold Voltage
REFIN /
100
REFIN /
55
REFIN /
32 V
0 < VICTL < VREFIN -1 +1
ICTL Input Bias Current ICTL = DCIN = 0, VREFIN = 3.6V -1 +1
µA
INPUT-CURRENT REGULATION
CLS = REF 97
105
113
Charger-Input Current-Limit
Accuracy (VCSSP - VCSSN) CSSS = CSSP CLS = REF x 0.845 81 88 95
mV
CLS = REF 97
105
113
System-Input Current-Limit
Accuracy (VCSSP - VCSSS) CSSN = CSSP CLS = REF x 0.845 81 88 95
mV
CSSP/CSSS/CSSN Input Voltage
Range 8 28 V
VCSSP = VCSSN = VCSSS = VDCIN = 6V -1 +1
CSSP Input Current VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V
700 1200
µA
VCSSP = VCSSN = VCSSS = VDCIN = 6V -1 +1
CSSS/CSSN Input Current VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V -1 +1
µA
CLS Input Range
VREF / 2 VREF
V
CLS Input Bias Current CLS = REF -1 +1 µA
IINP Transconductance VCSSP - VCSSS = 102mV, CSSN = CSSP 2.5
2.8
3.1
µA/mV
VCSSP - VCSSN = 200mV, VIINP = 0V
350
IINP Output Current VCSSP - VCSSS = 200mV, VIINP = 0V
350
µA
VCSSP - VCSSN = 200mV, IINP float 3.5
IINP Output Voltage VCSSP - VCSSS = 200mV, IINP float 3.5
V
SUPPLY AND LINEAR REGULATOR
DCIN Input Voltage Range 8 28 V
DCIN falling 4 6.2
DCIN Undervoltage Lockout DCIN rising 6.3
7.85
V
DCIN Quiescent Current 8.0V < VDCIN < 28V 3.5 6 mA
BATT Input Voltage Range 0 19 V
DCIN = 0 0.1 1
BATT Input Bias Current VBATT = 2V to 19V
300
500
µA
LDO Output Voltage No load 5.3 5.4 5.5 V
LDO Load Regulation 0 < ILDO < 10mA 70
150
mV
LDO Undervoltage Lockout VDCIN = 8V, LDO rising
4.00
5.0
5.25
V
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
4 _______________________________________________________________________________________
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE
REF Output Voltage IREF = 0µA
4.076 4.096 4.116
V
REF Load Regulation 0 < IREF < 500µA 5 10 mV
REF Undervoltage-Lockout Trip
Point VREF falling
3.1
3.9 V
REFIN Input Range 2.5 3.6 V
REFIN UVLO Rising
1.9
2.2 V
REFIN UVLO Hysteresis 50 mV
VDCIN = 18V 50 100
REFIN Input Bias Current DCIN = 0, VREFIN = 3.6V -1 +1
µA
SWITCHING REGULATOR
C ycl e- b y- C ycl e S tep - U p M axi m um
C ur r ent- Li m i t S ense V ol tag e VDCIN = 12V, VBATT = 16.8V 135
150
165 mV
C ycl e- b y- C ycl e S tep - D ow n
M axi m um C ur r ent- Li m i t S ense
V ol tag e
VDCIN = 19V, VBATT = 16.8V 135
150
165 mV
Step-Down On-Time VDCIN = 18V, VBATT = 16.8V 2.2
2.4
2.6 µs
Minimum Step-Down Off-Time VDCIN = 18V, VBATT = 16.8V
0.15 0.4 0.50
µs
Step-Up Off-Time VDCIN = 12V, VBATT = 16.8V 1.6
1.8
2.0 µs
Minimum Step-Up On-Time VDCIN = 12V, VBATT = 16.8V
0.15 0.3 0.40
µs
MOSFET DRIVERS
VHP - VHN Output Voltage 8V < VVHP < 28V, no load 4.5 5 5.5 V
VHN Load Regulation 0 < IVHN < 10mA 70 150 mV
DHI On-Resistance High ISOURCE = 10mA 2 5 Ω
DHI On-Resistance Low ISINK = 10mA 1 3 Ω
DCIN = 0
0.1
1 µA
VHP Input Bias Current VDCIN = 18V
1.3
2 mA
ICTL = 0
0.1
2
BLKP Input Bias Current VICTL = VREFIN = 3.3V
100
400
µA
DLOV Supply Current DBST low 5 10 µA
DBST On-Resistance High ISOURCE = 10mA 2 5 Ω
DBST On-Resistance Low ISINK = 10mA 1 3 Ω
ERROR AMPLIFIERS
GMV Amplifier Loop
Transconductance V C TL = RE FIN , V
BAT T = 16.8V 0.05
0.1 0.20 µA/mV
GMI Amplifier Loop
Transconductance ICTL = REFIN, VCSIP - VCSIN = 72mV 1.8
2.4
3.0
µA/mV
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
_______________________________________________________________________________________ 5
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
VCLS = REF, VCSSP - VCSSN = 102mV, VCSSP = VCSSS 1.2
1.7
2.2
GMS Amplifier Loop
Transconductance VCLS = REF, VCSSP - VCSSS = 102mV, VCSSP = VCSSN 1.2
1.7
2.2
µA/mV
VCTL = REFIN, VBATT = 15.8V 50
CCV Output Current VCTL = REFIN, VBATT = 17.8V -50
µA
ICTL = REFIN, VCSIP - VCSIN = 0mV 150
CCI Output Current ICTL = REFIN, VCSIP - VCSIN = 150mV
-150
µA
CLS = REF, VCSSP = VCSSN, VCSSP = VCSSS 100
CCS Output Current CLS = REF, VCSSP - VCSSN = 200mV,
VCSSP - VCSSS = 200mV
-100
µA
CCI/CCS/CCV Clamp Voltage 1.1V < VCCV < 3.5V, 1.1V < VCCS < 3.5V,
1.1V < VCCI < 3.5V 100
300
500 mV
LOGIC LEVELS
ASNS Output-Voltage Low VIINP = GND, ISINK = 1mA 0.4 V
ASNS Output-Voltage High VIINP = 4V, ISOURCE = 1mA LDO -
0.5 V
VIINP rising 1.1
1.15
1.2 V
ASNS Current Detect Hysteresis 50 mV
VSHDN = 0 to VREFIN -1 +1
SHDN Input Bias Current DCIN = 0, VREFIN = 5V, VSHDN = 0 to VREFIN -1 +1
µA
SHDN Threshold SHDN falling, VREFIN = 2.8V to 3.6V 22
23.5
25 % of
REFIN
SHDN Hysteresis 1
% of
REFIN
CELLS Input Low Voltage
0.75
V
CELLS Float Voltage 40 50 60 % of
REFIN
CELLS Input High Voltage
RE FIN -
0.75V
V
CELLS Input Bias Current CELLS = 0 to REFIN -2 +2 µA
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= 0°C to +85°C, unless otherwise noted. Typical
values are at TA= +25°C.)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
6 _______________________________________________________________________________________
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
CHARGE-VOLTAGE REGULATION
VCTL Range 0 3.6 V
VVCTL = VLDO (2 cells)
-0.8
+0.8
VVCTL = VLDO (3 cells)
-0.8
+0.8
VVCTL = VLDO (4 cells)
-0.8
+0.8
VVCTL = VREFIN (2 cells)
-1.2
+1.2
VVCTL = VREFIN (3 cells)
-1.2
+1.2
VVCTL = VREFIN (4 cells)
-1.2
+1.2
VVCTL = VREFIN / 20 (2 cells)
-1.4
+1.4
VVCTL = VREFIN / 20 (3 cells)
-1.4
+1.4
Battery Regulation Voltage
Accuracy
VVCTL = VREFIN / 20 (4 cells)
-1.4
+1.4
%
VCTL Default Threshold VCTL rising 4.0 4.2 V
CHARGE-CURRENT REGULATION
ICTL Range 0 3.6 V
VICTL = VREFIN 66 80
VICTL = VREFIN x 0.8 53 65
Quick-Charge-Current Accuracy
VICTL = VREFIN x 0.583 38 48
mV
BATT/CSIP/CSIN Input Voltage
Range 0 19 V
CSIP Input Current
ICTL = REFIN
600
µA
ICTL Power-Down-Mode
Threshold Voltage
REFIN /
100
REFIN /
32 V
INPUT-CURRENT REGULATION
CLS = REF 95 115
Charger-Input Current-Limit
Accuracy (VCSSP - VCSSN) CSSS = CSSP CLS = REF x 0.845 79 97
mV
CLS = REF 95 115
System-Input Current-Limit
Accuracy (VCSSP - VCSSS) CSSN = CSSP CLS = REF x 0.845 79 97
mV
CSSP/CSSS/CSSN Input Voltage
Range 8 28 V
CSSP Input Current
VCSSP = VCSSN = VCSSS = VDCIN = 8V, 28V
1200
µA
CLS Input Range
VREF / 2 VREF
V
IINP Transconductance VCSSP - VCSSS = 102mV, CSSN = CSSP 2.5 3.1
µA/mV
VCSSP - VCSSN = 200mV, VIINP = 0V
350
IINP Output Current VCSSP - VCSSS = 200mV, VIINP = 0V
350
µA
VCSSP - VCSSN = 200mV, IINP float 3.5
IINP Output Voltage VCSSP - VCSSS = 200mV, IINP float 3.5
V
ELECTRICAL CHARACTERISTICS
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= -40°C to +85°C.) (Note 1)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
_______________________________________________________________________________________ 7
PARAMETER CONDITIONS
MIN TYP MAX
UNITS
SUPPLY AND LINEAR REGULATOR
DCIN Input Voltage Range 8 28 V
DCIN falling 4
DCIN Undervoltage Lockout DCIN rising
7.85
V
DCIN Quiescent Current 8.0V < VDCIN < 28V 6 mA
BATT Input Voltage Range 0 19 V
BATT Input Bias Current
VBATT = 2V to 19V
500
µA
LDO Output Voltage No load 5.3 5.5 V
LDO Undervoltage Lockout VDCIN = 8V, LDO rising
4.00
5.25
V
REFERENCE
REF Output Voltage IREF = 0µA
4.060
4.132
V
REF Load Regulation 0 < IREF < 500µA 10 mV
REF Undervoltage-Lockout Trip
Point VREF falling 3.9 V
REFIN Input Range 2.5 3.6 V
REFIN UVLO Rising 2.2 V
REFIN Input Bias Current VDCIN = 18V 100 µA
SWITCHING REGULATOR
C ycl e- b y- C ycl e S tep - U p M axi m um
C ur r ent- Li m i t S ense V ol tag e VDCIN = 12V, VBATT = 16.8V 130 170 mV
C ycl e- b y- C ycl e S tep - D ow n
M axi m um C ur r ent- Li m i t S ense
V ol tag e
VDCIN = 19V, VBATT = 16.8V 130 170 mV
Step-Down On-Time VDCIN = 18V, VBATT = 16.8V 2.2 2.6 µs
Minimum Step-Down Off-Time VDCIN = 18V, VBATT = 16.8V
0.15
0.50
µs
Step-Up Off-Time VDCIN = 12V, VBATT = 16.8V 1.6 2.0 µs
Minimum Step-Up On-Time VDCIN = 12V, VBATT = 16.8V
0.15
0.40
µs
MOSFET DRIVERS
VHP - VHN Output Voltage 8V < VVHP < 28V, no load 4.5 5.5 V
VHN Load Regulation 0 < IVHN < 10mA 150 mV
DHI On-Resistance High ISOURCE = 10mA 5 Ω
DHI On-Resistance Low ISINK = 10mA 3 Ω
VHP Input Bias Current
VDCIN = 18V
2
mA
BLKP Input Bias Current
VICTL = VREFIN = 3.3V
400
µA
DLOV Supply Current DBST low 10 µA
DBST On-Resistance High ISOURCE = 10mA 5 Ω
DBST On-Resistance Low ISINK = 10mA 3 Ω
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= -40°C to +85°C.) (Note 1)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
8 _______________________________________________________________________________________
PARAMETER CONDITIONS
MIN
TYP
MAX
UNITS
ERROR AMPLIFIERS
GMV Amplifier Loop
Transconductance V C TL = RE FIN , V
BAT T = 16.8V
0.05
0.20
µA/mV
GMI Amplifier Loop
Transconductance ICTL = REFIN, VCSIP - VCSIN = 72mV 1.8 3.0
µA/mV
VCLS = REF, VCSSP - VCSSN = 102mV, VCSSP = VCSSS 1.2 2.2
GMS Amplifier Loop
Transconductance VCLS = REF, VCSSP - VCSSS = 102mV, VCSSP = VCSSN 1.2 2.2
µA/mV
VCTL = REFIN, VBATT = 15.8V 50
CCV Output Current VCTL = REFIN, VBATT = 17.8V -50
µA
ICTL = REFIN, VCSIP - VCSIN = 0mV
150
CCI Output Current ICTL = REFIN, VCSIP - VCSIN = 150mV
-150
µA
CLS = REF, VCSSP = VCSSN, VCSSP = VCSSS
100
CCS Output Current CLS = REF, VCSSP - VCSSN = 200mV,
VCSSP - VCSSS = 200mV
-100
µA
CCI/CCS/CCV Clamp Voltage 1.1V < VCCV < 3.5V, 1.1V < VCCS < 3.5V,
1.1V < VCCI < 3.5V
100
500 mV
LOGIC LEVELS
ASNS Output-Voltage Low VIINP = GND, ISINK = 1mA 0.4 V
ASNS Output-Voltage High VIINP = 4V, ISOURCE = 1mA LDO -
0.5 V
ASNS Current Detect VIINP rising 1.1
1.15
1.2 V
SHDN Threshold SHDN falling, VREFIN = 2.8V to 3.6V 22 25 % of
REFIN
CELLS Input Low Voltage
0.75
V
CELLS Float Voltage 40 60 % of
REFIN
CELLS Input High Voltage
RE FIN -
0.75V
V
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, VDCIN = VCSSP = VCSSN = VCSSS = VVHP = 18V, VBATT = VCSIP = VCSIN = VBLKP = 12V, VREFIN = 3.0V, VICTL =
0.75 x VREFIN, VCTL = LDO, CELLS = FLOAT, GND = PGND = 0, VDLOV = 5.4V, TA= -40°C to +85°C.) (Note 1)
Note 1: Specifications to -40°C are guaranteed by design, not production tested.
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
_______________________________________________________________________________________ 9
BATTERY INSERTION AND REMOVAL
MAX1870Atoc01
VBATT
18V
16V
ICHARGE
5A/div
0
CCI AND CCV
CCI
CCV
0
2V
4V
20V
2.00ms/div
BATTERY REMOVAL
BATTERY
INSERTION
CCV
CCI
BATTERY-REMOVAL RESPONSE
MAX1870Atoc02
VBATT
21V
18V
20V
19V
16V
17V
10.0μs/div
RCV = 10kΩ, COUT = 22μF
RCV = 10kΩ, COUT = 44μF
RCV = 20kΩ, COUT = 44μF
SYSTEM LOAD-TRANSIENT RESPONSE
MAX1870Atoc03
4A
2A
0A
INDUCTOR CURRENT
SYSTEM LOAD
INPUT CURRENT
BATTERY CURRENT
5A
0A
2A
0A
0A
5A
200μs
STEP-DOWN MODE
SYSTEM LOAD-TRANSIENT RESPONSE
MAX1870Atoc04
4A
2A
0A
INDUCTOR CURRENT
SYSTEM LOAD
INPUT CURRENT
BATTERY CURRENT
5A
0A
2A
0A
0A
5A
100μs
HYBRID MODE
CHARGE-CURRENT STEP RESPONSE
MAX1870Atoc05
2A
0A
1V
INDUCTOR CURRENT
BATTERY CURRENT
0V
CCI
0A
2A
0V
5V
VICTL
400μs
STEP-DOWN
MODE
CHARGE-CURRENT STEP RESPONSE
MAX1870Atoc06
2A
0A
1V
INDUCTOR CURRENT
BATTERY CURRENT
0V
CCI
0A
2A
0V
5V
VICTL
400μs
HYBRID MODE
Typical Operating Characteristics
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA= +25°C, unless otherwise noted.)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
10 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA= +25°C, unless otherwise noted.)
EFFICIENCY vs. BATTERY VOLTAGE
MAX1870A toc07
BATTERY VOLTAGE (V)
EFFICIENCY (%)
12481614610
65
70
75
80
90
85
95
60
218
VIN = 12V
VIN = 16V
EFFICIENCY vs. CHARGE CURRENT
MAX1870A toc08
CHARGE CURRENT (A)
EFFICIENCY (%)
2.01.50.5 1.0
65
70
75
80
90
85
95
100
60
02.5
VBATT = 16.8V
VBATT = 8.4V
VBATT = 12.6V
BATTERY VOLTAGE ERROR IN CV MODE
MAX1870A toc09
CHARGE CURRENT (A)
BATTERY VOLTAGE ERROR (%)
2.01.50.5 1.0
-0.4
-0.3
-0.2
-0.1
0.2
0
0.4
0.1
0.3
0.5
-0.5
02.5
VBATT = 16.8V
VBATT = 12.6V
VBATT = 8.4V
BATTERY VOLTAGE ERROR vs. VCTL
MAX1870Atoc10
VCTL (V)
BATTERY VOLTAGE ERROR (%)
3.002.001.00
0.05
0.10
0.15
0.20
0.25
0
0 4.00
CHARGE-CURRENT ERROR vs. ICTL
MAX1870Atoc11
VICTL (V)
CHARGE-CURRENT ERROR (mA)
2.502.001.501.000.50
-70
-60
-50
-40
-30
-20
-10
0
10
20
-80
0 3.00
CHARGE-CURRENT ERROR
vs. BATTERY VOLTAGE
MAX1870Atoc12
VBATT (V)
CHARGE-CURRENT ERROR (%)
15105
-10
-5
0
5
10
15
-15
020
ICHG = 0.15A
ICHG = 2.4A
ICHG = 1.9A
ICHG = 1.4A
IINP ERROR vs. SYSTEM LOAD
MAX1870Atoc13
SYSTEM LOAD (A)
IINP ERROR (mV)
3.02.00.5 1.5 3.52.51.0
-4
-2
0
2
4
-3
-1
1
3
5
-5
0 4.0
INPUT CURRENT-LIMIT ERROR
vs. SYSTEM CURRENT
MAX1870A toc14
SYSTEM CURRENT (A)
INPUT CURRENT-LIMIT ERROR (%)
3.02.50.5 1.51.0 2.0
-8
-6
-4
-2
4
0
8
2
6
10
-10
0 3.5
VBATT = 16V
VBATT = 14V
VBATT = 10V VBATT = 8V
VBATT = 6V
VBATT = 12V
INPUT CURRENT-LIMIT ERROR
vs. CLS
MAX1870A toc15
VCLS (V)
INPUT CURRENT-LIMIT ERROR (mA)
4.002.001.00 3.00
-250
-200
-150
-100
50
-50
150
0
100
200
-300
0 5.00
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 11
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA= +25°C, unless otherwise noted.)
REF LOAD REGULATION
MAX1870A toc16
LOAD CURRENT (μA)
VREF (V)
20001000500 1500
4.04
4.05
4.06
4.08
4.07
4.10
4.09
4.11
4.03
02500
REFERENCE ERROR vs. TEMPERATURE
MAX1870Atoc17
TEMPERATURE (°C)
REFERENCE ERROR (%)
806020 400-20
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0
-40 100
LDO LOAD REGULATION
MAX1870A toc18
LOAD (mA)
VLDO (V)
403010 20
5.26
5.32
5.28
5.36
5.30
5.34
5.38
5.24
050
VIN = 28V
VIN = 16V
VIN = 9V
LDO vs. TEMPERATURE
MAX1870A toc19
TEMPERATURE (°C)
LDO VOLTAGE ERROR (%)
8040-20 06020
-0.2
0.2
0.6
0
0.4
0.8
-0.4
-40 100
OUTPUT VOLTAGE RIPPLE
vs. BATTERY VOLTAGE
MAX1870Atoc20
VBATT (V)
RMS OUTPUT RIPPLE (mV)
15105
20
40
60
80
100
120
140
160
180
0
020
STEP-UP/STEP-DOWN
SWITCHING WAVEFORM
MAX1870Atoc21
0V
D4
10V
0V
CATHODE
D3 ANODE
INDUCTOR CURRENT
4A
VBATT
(AC-COUPLED)
200mV/div
2A
10V
20V
2.00μs
VIN = 16V
VBATT = 16V
STEP-DOWN
SWITCHING WAVEFORM
MAX1870Atoc22
0V
D4
10V
0V
CATHODE
D3 ANODE
INDUCTOR CURRENT
4A
VBATT
(AC-COUPLED)
10mV/div
2A
10V
20V
2.00μs
VIN = 16V
VBATT = 12V
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(Circuit of Figure 1, VDCIN = 16V, CELLS = REFIN, VCLS =VREF, VICTL = VREFIN = 3.3V, TA= +25°C, unless otherwise noted.)
Pin Description
PIN NAME FUNCTION
1LDO
Device Power Supply. Output of the 5.4V linear regulator supplied from DCIN. Bypass LDO to GND with
a 1µF or greater ceramic capacitor.
2 REF 4.096V Voltage Reference. Bypass REF to GND with a 1µF or greater ceramic capacitor.
3 CLS Source Current-Limit Input. Voltage input for setting the current limit of the input source. See the Setting
the Input Current Limit section.
4, 8 GND Analog Ground
5 CCV Voltage Regulation Loop Compensation Point. Connect a 10kΩ resistor in series with a 0.01µF capacitor
to GND.
6 CCI Charge-Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor to GND.
7 CCS Input-Current Regulation Loop Compensation Point. Connect a 0.01µF capacitor to GND.
9 REFIN Reference Input. ICTL and VCTL are ratiometric with respect to REFIN for increased accuracy.
10 ASNS Adapter Sense Output. Logic output is high when input current is greater than 1.5A (using 30mΩ sense
resistors and a 10kΩ resistor from IINP to GND).
11 VCTL Charge-Voltage Control Input. Drive VCTL from 0 to VREFIN to adjust the charge voltage from 4V to 4.4V
per cell. See the Setting the Charge Voltage section.
STEP-UP
SWITCHING WAVEFORM
MAX1870Atoc23
0V
D4
10V
0V
CATHODE
D3 ANODE
INDUCTOR CURRENT
4A
VBATT
(AC-COUPLED)
50mV/div
2A
10V
20V
2.00μs
VIN = 12V
VBATT = 16V
STEP-UP/STEP-DOWN
LIGHT LOAD
MAX1870Atoc24
0V
D4
10V
0V
CATHODE
D3 ANODE
INDUCTOR CURRENT
4A
VBATT
(AC-COUPLED)
50mV/div
2A
10V
20V
2.00μs
VIN = 16V
VBATT = 16V
CHARGE CURRENT = 300mA
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 13
Pin Description (continued)
PIN NAME FUNCTION
12 ICTL Charge-Current Control Input. Drive ICTL from VREFIN / 32 to VREFIN to adjust the charge current. See the
Setting the Charge Current section. Drive ICTL to GND to disable charging.
13 CELLS Cell-Count Selection Input. Connect CELLS to GND for two Li+ cells. Float CELLS for three Li+ cells, or
connect CELLS to REFIN for four Li+ cells.
14 IINP
Input-Current Monitor Output. IINP is a replica of the input current sensed by the MAX1870. It represents
the sum of the current consumed by the charger and the current consumed by the system. IINP has a
transconductance of 2.8µA/mV.
15 SHDN Shutdown Comparator Input. Pull SHDN low to stop charging. Optionally connect a thermistor to stop
charging when the battery temperature is too hot.
16 BATT Battery-Voltage Feedback Input
17 CSIN Charge Current-Sense Negative Input
18 CSIP Charge Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN. Connect a
2.2µF capacitor from CSIP to GND.
19 BLKP Power Connection for Current-Sense Amplifier. Connect BLKP to BATT.
20, 21 I.C. Internally Connected. Do not connect this pin.
22 DBST Step-Up Power MOSFET (NMOS) Gate-Driver Output
23 PGND Power Ground
24 I.C. Internally Connected. Do not connect this pin.
25 DLOV Low-Side Driver Supply. Bypass DLOV with a 1µF capacitor to GND.
26 VHN Power Connection for the High-Side MOSFET Driver. Bypass VHP to VHN with a 1µF or greater ceramic
capacitor.
27 DHI High-Side Power MOSFET (PMOS) Driver Output. Connect to the gate of the high-side step-down
MOSFET.
28 VHP Power Connection for the High-Side MOSFET Driver. Bypass VHP to VHN with a 1µF or greater ceramic
capacitor.
29 CSSN Negative Terminal for Current-Sense Resistor for Charger Current. Connect a 2.2µF capacitor from CSSN
to GND.
30 CSSS Negative Terminal for Current-Sense Resistor for System Load Current
31 CSSP Positive Terminal for Input Current-Sense Resistors. Connect a current-sense resistor from CSSP to
CSSN. Connect an equivalent sense resistor from CSSP to CSSS.
32 DCIN DC Supply Voltage Input. Bypass DCIN with a 1µF or greater ceramic capacitor to power ground.
Paddle Paddle. Connect to GND.
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
14 ______________________________________________________________________________________
MAX1870A
234
VHP
VHN
CSSP
CSSN
DHI
DBST
CSIP
CSIN
BATT
DLOV
LDO
BLKP
CSSS
16
12
13
28
26
31
29
27
22
14
9
10
11
DCIN
REF
CLS
CCV
CCI
CCS
REFIN
ASNS
VCTL
ICTL
CELLS
IINP
PGND
32
18
17
25
1
15
7
6
5
3
2
AC
ADAPTER
VDD
HOST
DIGITAL INPUT
D/A OUTPUT
D/A OUTPUT
HI-IMPEDANCE
OUTPUT
LOGIC OUTPUT
A/D INPUT
GND
SYSTEM LOAD
+
-
R3
R4
R7
10kΩ
C6
0.01μF
C8
22μF
C9
44μF
C7
1μF
RS2
30mΩ
L1
10μH
C11
1μF
C12
1μF
M2
M1
19
N
P
RS1b
30mΩ
GND
30
RS1a
30mΩ
R6
33Ω
C5
1μF
C1
1μF
D1
D2
OPTIONAL REVERSE-
ADAPTER PROTECTION
2.2μF
2.2μF
D3
D4
R5
10kΩ
C2
0.01μF
C3
0.01μF
C4
0.01μF
SHDN
Figure 1. µC-Controlled Typical Application Circuit
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 15
23476
VHP
VHN
CSSP
CSSN
DHI
DBST
CSIP
CSIN
BATT
DLOV
LDO
BLKP
CSSS
16
28
26
31
29
27
22
DCIN
REF
CELLS
CLS
PGND
32
18
17
25
1
3
REFIN
9
VCTL
11
ICTL
12
ASNS
10
IINP
14
CCV
5
15
2
13
SYSTEM LOAD
C8
22μF
C9
44μF
C7
1μF
RS2
30mΩ
L1
10μH
C11
1μF
C12
1μF
M2
M1
19
N
P
RS1b
30mΩ
GNDCCSCCI
30
RS1a
30mΩ
R6
33Ω
C5
1μF
C1
1μF
2.2μF
2.2μF
D3
D4
R4
OPEN
R3
SHORT
R9
OPEN
R10
OPEN
R1
SHORT
R12
OPEN
LDO
R7
10kΩ
R5
10kΩ
C6
0.01μF
C3
0.01μF
C4
0.01μF
C2
0.01μF
SHDN
AC
ADAPTER
+
-
D1
D2
OPTIONAL
MAX1870A
OPTIONAL REVERSE-
ADAPTER PROTECTION
Figure 2. Stand-Alone Typical Application Circuit
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
16 ______________________________________________________________________________________
Detailed Description
The MAX1870A includes all of the functions necessary
to charge Li+, NiMH, and NiCd batteries. A high-effi-
ciency H-bridge topology DC-DC converter controls
charge voltage and current. A proprietary control
scheme offers improved efficiency and smaller inductor
size compared to conventional H-bridge controllers and
operates from input voltages above and below the bat-
tery voltage. The MAX1870A includes analog control
inputs to limit the AC adapter current, charge current,
and battery voltage. An analog output (IINP) delivers a
current proportional to the source current. The Typical
Application Circuit shown in Figure 1 uses a microcon-
troller (µC) to control the charge current or voltage,
while Figure 2 shows a typical application with the
charge voltage and current fixed to specific values for
the application. The voltage at ICTL and the value of
RS2 set the charge current. The voltage at VCTL and
the CELLS inputs set the battery regulation voltage for
the charger. The voltage at CLS and the value of R3 and
R4 set the source current limit.
The MAX1870A features a voltage-regulation loop
(CCV) and two current-regulation loops (CCI and CCS).
CCV is the compensation point for the battery voltage
regulation loop. CCI and CCS are the compensation
points for the battery charge current and supply current
loops, respectively. The MAX1870A regulates the
adapter current by reducing battery charge current
according to system load demands.
Setting the Charge Voltage
The MAX1870A provides high-accuracy regulation of
the charge voltage. Apply a voltage to VCTL to adjust
the battery-cell voltage limit. Set VCTL to a voltage
between 0 and VREFIN for a 10% adjustment of the bat-
tery cell voltage, or connect VCTL to LDO for a default
setting of 4.2V per cell. The limited adjustment range
reduces the sensitivity of the charge voltage to external
resistor tolerances. The overall accuracy of the charge
voltage is better than ±1% when using ±1% resistors to
divide down the reference to establish VCTL. The per-
cell battery-termination voltage is a function of the bat-
tery chemistry and construction. Consult the battery
manufacturer to determine this voltage. Calculate bat-
tery voltage using the following equation:
where NCELLS is the cell count selected by CELLS.
VCTL is ratiometric with respect to REFIN to improve
accuracy when using resistive voltage-dividers.
Connect CELLS as shown in Table 1 to charge two,
three, or four cells. The cell count can either be hard-
wired or software controlled. The internal error amplifier
(GMV) maintains voltage regulation (see Figure 3 for
the Functional Diagram). Connect a 10kΩresistor in
series with a 0.01µF capacitor from CCV to GND to
compensate the battery voltage loop. See the Voltage
Loop Compensation section for more information.
Setting the Charge Current
Set the maximum charge current using ICTL and the
current-sense resistor RS2 connected between CSIP
and CSIN. The current threshold is set by the ratio of
VICTL / VREFIN. Use the following equation to program
the battery charge current:
where VCSIT is the full-scale charge current-sense
threshold, 73mV (typ). The input range for ICTL is
VREFIN / 32 to VREFIN. To shut down the MAX1870A,
force ICTL below VREFIN / 100.
The internal error amplifier (GMI) maintains charge-
current regulation (see Figure 3 for the Functional
Diagram). Connect a 0.01µF capacitor from CCI to GND
to compensate the charge-current loop. See the Charge-
Current Loop Compensation section for more information.
Setting the Input Current Limit
The total input current, from a wall adapter or other DC
source, is a function of the system supply current and
the battery charge current. The MAX1870A limits the wall
adapter current by reducing the charge current when the
input current exceeds the input current-limit set point. As
the system supply current rises, the available charge
current decreases linearly to zero in proportion to the
system current. After the charge current has fallen to
zero, the MAX1870A cannot further limit the wall adapter
current if the system current continues to increase.
IV
RxV
V
CHG CSIT
S
ICTL
REFIN
=
2
VNxVVx
V
V
BATT CELLS VCTL
REFIN
=+
⎛
⎝
⎜⎞
⎠
⎟
404.
Table 1. Cell-Count Programming Table
CELLS CELL COUNT
GND 2
Float 3
REFIN 4
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 17
MAX1870A
CSSN
CSSP
CSSS
CLS
CCS
ICTL
CCI
CSIP
CSIN
CCV
BATT
CELLS
VCTL
A = 18V/V
A = 18V/V
CSS
CURRENT-
SENSE
AMPLIFIERS 3.6V
(6.7A FOR 30mΩ)
IMAX1
INPUT-CURRENT BLOCK
GMS
IINP ASNS
Gm
0.81mV
(1.5A FOR 30mΩ)
50mV
REFIN
x
400mV
REFIN
x
GMI
A = 18V/V
CSI
22.5mV
(42mA ON
30mΩ)
(6.7A FOR 30mΩ)
3.6V
IZX
IMAX2
CHARGE-CURRENT BLOCK
+ 4.0V
4.2V GMV
REF CELL-
SELECT
LOGIC
BATTERY-VOLTAGE BLOCK
SHUTDOWN LOGIC
5.4V LINEAR
REGULATOR
4.096V
REFERENCE
DCIN LDO REF REFIN
1/55
CHG
RDY
ICTL
23% OF
REFIN
GND
PGND
DLOV
VHN
DHI
VHP
DBST
SHDN
LEVEL
SHIFT
STEP-UP/DOWN
CURRENT-MODE
STATE MACHINE
IMAX1
LVC IMIN
0.15V
LVC
LOW-
SIDE
DRIVER
HIGH-
SIDE
DRIVER
Figure 3. Functional Diagram
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
18 ______________________________________________________________________________________
The input source current is the sum of the MAX1870A
quiescent current, the charger input current, and the
system load current. The MAX1870A’s 6mA maximum
quiescent current is minimal compared to the charge
and load currents. The actual wall adapter current is
determined as follows:
where ηis the efficiency of the DC-DC converter (85%
to 95% typ), ISYS_LOAD is the system load current,
IADAPTER is the adapter current, and ICHARGE is the
charge current.
By controlling the input current, the current require-
ments of the AC wall adapter are reduced, minimizing
system size and cost. Since charge current is reduced
to control input current, priority is given to system loads.
An internal amplifier compares the sum of (VCSSP -
VCSSN) and (VCSSP - VCSSS) to a scaled voltage set by
the CLS input. Drive VCLS directly or set with a resistive
voltage-divider between REF and GND. Connect CLS
to REF for the maximum input current limit of 105mV.
Sense resistors RS1a and RS1b set the maximum-
allowable wall adapter current. Use the same values for
RS1a, RS1b, and RS2. Calculate the maximum wall
adapter current as follows:
where VCSST is the full-scale source current-sense volt-
age threshold, and is 105mV (typ). The internal error
amplifier (GMS) maintains input-current regulation (see
Figure 3 for the Functional Diagram). Typically, connect
a 0.01µF capacitor from CCS to GND to compensate
the source current loop (GMS). See the Charge-Current
and Wall-Adapter-Current Loop Compensation for more
information.
Input Current Measurement
The MAX1870A includes an input-current monitor out-
put, IINP. IINP is a scaled-down replica of the system
load current plus the input-referred charge current. The
output voltage range for IINP is 0 to 3.5V. The voltage
of IINP is proportional to the output current by the fol-
lowing equation:
VIINP = IADAPTER x RS1_ x GIINP x R7
where IADAPTER is the DC current supplied by the
AC adapter, GIINP is the transconductance of IINP
(2.8µA/mV typ), and R7 is the resistor connected
between IINP and ground.
In the Typical Application Circuit, the duty cycle and
AC load current affect the accuracy of VIINP (see the
Typical Operating Characteristics).
LDO Regulator
LDO provides a 5.4V supply derived from DCIN. The
low-side MOSFET driver is powered by DLOV, which
must be connected to LDO as shown in Figure 1. LDO
also supplies the 4.096V reference (REF) and most of
the internal control circuitry. Bypass LDO to GND with a
1µF or greater ceramic capacitor. Bypass DLOV to
PGND with a 1µF or greater ceramic capacitor.
AC Adapter Detection
The MAX1870A includes a logic output, ASNS, which
indicates AC adapter presence. When the system load
draws more than 1.5A (for 30mΩsense resistors and
R7 is 10kΩ), the ASNS logic output pulls high.
Shutdown
When the AC adapter is removed, the MAX1870A shuts
down to a low-power state, and typically consumes less
than 1µA from the battery through the combined load of
the CSIP, CSIN, BLKP, and BATT inputs. The charger
enters this low-power state when DCIN falls below the
undervoltage-lockout (UVLO) threshold of 7.5V.
Alternatively, drive SHDN below 23.5% of VREFIN or
drive ICTL below VREFIN / 100 to inhibit charge. This
suspends switching and pulls CCI, CCS, and CCV to
ground. The LDO, input current monitor, and control
logic all remain active in this state.
Step-Up/Step-Down
DC-DC Controller
The MAX1870A is a step-up/step-down DC-DC con-
troller. The MAX1870A controls a low-side n-channel
MOSFET and a high-side p-channel MOSFET to a con-
stant output voltage with input voltage variation above,
near, and below the output. The MAX1870A implements
a control scheme that delivers higher efficiency with
smaller components and less output ripple when com-
pared with other step-up/step-down control algorithms.
This occurs because the MAX1870A operates with
lower inductor currents, as shown in Figure 4.
The MAX1870A proprietary algorithm offers the follow-
ing benefits:
•Inductor current requirements are minimized.
•Low inductor-saturation current requirements allow
the use of physically smaller inductors.
•Low inductor current improves efficiency by reducing
I2R losses in the MOSFETs, inductor, and sense
resistors.
IV
VxV
RS
ADAPTER MAX CLS
REF
CSST
__
=1
II IxV
Vx
ADAPTER SYS LOAD CHARGE BATT
IN
=+
_η
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 19
•Continuous output current for VIN > 1.4 x VOUT
reduces output ripple.
The MAX1870A uses the state machine shown in Figure
5. The controller switches between the states A, B, and C,
depending on VIN and VBATT. State D provides PFM
operation during light loads. Under moderate and heavy
loads the MAX1870A operates in PWM.
Step-Down Operation
(VIN > 1.4 x VBATT)
During medium and heavy loads when VIN > 1.4 x
VBATT, the MAX1870A alternates between state A and
state B, keeping MOSFET M2 off (Figure 5). Figure 6
shows the inductor current in step-down operation.
During this mode, the MAX1870A regulates the step-
down off-time. Initially, DHI switches M1 off (state A) and
the inductor current ramps down with a dI/dt of VBATT / L
until a target current is reached (determined by the error
integrator). After the target current is reached, DHI
switches M1 on (state B), and the inductor current ramps
up with a dI/dt of (VIN - VBATT) / L. M1 remains on until a
step-down on-time timer expires. This on-time is calculat-
ed based on the input and output voltage to maintain
pseudo-fixed-frequency 400kHz operation. At the end of
state B, another step-down off-time (state A) is initiated
and the cycle repeats. The off-time is valley regulated
according to the error signal. The error signal is set by
the charge current or source current if either is at its limit,
or the battery voltage if both charge current and source
current are below their respective current limits.
During light loads, when the inductor current falls to
zero during state A, the controller switches to state D to
reduce power consumption and avoid shuttling current
in and out of the output.
Step-Up Operation (VIN < 0.9 x VBATT)
When VIN < 0.9 x VBATT, the MAX1870A alternates
between state B and state C, keeping MOSFET M1 on.
In this mode, the controller looks like a simple step-up
controller. Figure 7 shows the inductor current in step-
A) CONVENTIONAL
ALGORITHM
B) MAX1870A
ALGORITHM
2 x ICHARGE
SHADED REGIONS REPRESENT
CHARGE DELIVERED
TIME
Figure 4. Inductor Current for VIN = VBATT
Table 2. MAX1870A H-Bridge Controller Advantages
MAX1870A H-BRIDGE CONTROLLER TRADITIONAL H-BRIDGE CONTROLLER
• Only 1 MOSFET switched per cycle
• Continuous output current in step-down mode
• 2 MOSFETs switched per cycle
• Always discontinuous output current
(requires higher inductor currents)
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
20 ______________________________________________________________________________________
up operation. During this mode, the MAX1870A regu-
lates the step-up on-time. Initially DBST switches M2 on
(state C) and the inductor current ramps up with a dI/dt
of VIN / L. After the inductor current crosses the target
current (set by the error integrators), DBST switches M2
off (state B) and the inductor current ramps down with
a dI/dt of (VBATT - VIN) / L. M2 remains off until a step-
up off-time timer expires. This off-time is calculated
based on the input and output voltage to maintain
400kHz pseudo-fixed-frequency operation. The step-up
on-time is regulated by the error signal, set according
to the charge current or source current if either is at its
limit, or the battery voltage if both charge current and
source current are below their respective current limits.
Step-Up/Step-Down Operation
(0.9 x VBATT < VIN < 1.4 x VBATT)
The MAX1870A features a step-up/step-down mode
that eliminates dropout. Figure 8 shows the inductor
current in step-up/step-down operation. When VIN is
within 10% of VBATT, the MAX1870A alternates through
states A, B, and C, following the order A, B, C, B, A, B,
C, etc., with the majority of the time spent in state B.
Since more time is spent in state B, the inductor ripple
current is reduced, improving efficiency.
The time in state C is peak-current regulated, and the
remaining time is spent in state B (Figure 8A). During
this operating mode, the average inductor current is
approximately 20% higher than the load current.
The time in state A is valley current and the remaining
time is spent in state B (Figure 8B). During this mode,
the average inductor current is approximately 10%
higher than the load current.
Alternative algorithms require inductor currents twice
as high, resulting in four times larger I2R losses and
inductors typically four times larger in volume.
IMIN, IMAX, CCMP, and ZCMP
The MAX1870A state machine utilizes five comparators
to decide which state to be in and when to switch
states (Figure 3). The MAX1870A generates an error
VIN VOUT
M1 D3
D4 M2
STEP-DOWN OFF
VIN VOUT
M1
M2
STEP-DOWN ON
STATE BSTATE A STATE C
VIN VOUT
M1
M2
STEP-DOWN PFM
IDLE STATE D
VIN VOUT
M1
M2
+-
STEP-DOWN
PWM
STEP-UP
PWM
STEP-UP OFF STEP-UP ON
D4
D2
D4
D3
D3
D3
Figure 5. MAX1870A State Machine
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 21
STATE B
STATE A
PRECALCULATED STEP-DOWN ON-TIME
VALLEY REGULATED OFF-TIME
dl
dt
VIN - VOUT
L
=
dl
dt
VOUT
L
=
VIN > 1.4 x VBATT DUTY = VIN / VOUT
Figure 6. MAX1870A Step-Down Inductor Current Waveform
signal based on the integrated error of the input cur-
rent, charge current, and battery voltage. The error sig-
nal, determined by the lowest voltage clamp (LVC),
sets the threshold for current-mode regulation. The fol-
lowing comparators are used for regulation:
• IMIN: The MAX1870A operates in discontinuous
conduction if LVC is below 0.15V, and does not ini-
tiate another step-down on-time. In discontinuous
step-up conduction, the peak current is set by
IMIN. The peak inductor current in discontinuous
step-up mode is:
where VIMIN is the IMIN comparator threshold,
0.15V, and ACSI is the charge current-sense ampli-
fier gain, 18V/V.
IV
AxRS
PK IMIN
CSI
>2
STATE B
STATE C
PRECALCULATED OFF-TIME
PEAK REGULATED ON-TIME
dl
dt
VIN - VOUT
L
=
dl
dt
VOUT
L
=
VIN > 0.9 x VBATT DUTY = 1 - VIN / VOUT
Figure 7. Step-Up Inductor-Current Waveform
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
22 ______________________________________________________________________________________
• CCMP: CCMP compares the current-mode control
point, LVC, to the inductor current. In step-down
mode, the off-time (state A) is terminated when the
inductor current falls below the current threshold
set by LVC. In step-up mode, the on-time (state C)
is terminated when the inductor current rises above
the current threshold set by LVC.
• IMAX: The IMAX comparators provide a cycle-by-
cycle inductor current limit. This circuit compares
the inductor current (CSI in step-down mode or
CSS in step-up mode) to the internally fixed cycle-
by-cycle current limit. The current-sense voltage
limit is 200mV. With RS1_ = RS2 = 30mΩ, which
corresponds to 6.7A. If the inductor current-sense
voltage is greater than VIMAX (200mV), a step-up
on-time is terminated or a step-down on-time is not
permitted.
• ZCMP: The ZCMP comparator detects when the
inductor current crosses zero. If the ZCMP output
goes high during a step-down off-time, the
MAX1870A switches to the idle state (state D) to
conserve power.
STATE C
STATE B
STATE A
STATE B
STATE A
STATE B
STATE C STATE B
A)
B)
MINIMUM
STEP-DOWN
OFF-TIME
PRECALCULATED STEP-UP
OFF-TIME
PRECALCULATED STEP-DOWN
ON-TIME
PRECALCULATED STEP-DOWN
ON-TIME
MINIMUM
STEP-UP
ON-TIME
PEAK REGULATED
STEP-UP
ON-TIME
VALLEY REGULATED
STEP-DOWN
OFF-TIME
dl
dt
VBATT - VIN
L
=
dl
dt
VIN
L
=dl
dt
VBATT
L
=
Figure 8. MAX1870A Step-Up/Step-Down Inductor-Current Waveform
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 23
Switching Frequency
The MAX1870A includes input and output-voltage feed-
forward to maintain pseudo-fixed-frequency (400kHz)
operation. The time in state B is set according to the
input voltage, output voltage, and a time constant. In
step-up/step-down mode the switching frequency is
effectively cut in half to allow for both the step-up cycle
and the step-down cycle. The switching frequency is
typically between 350kHz and 405kHz for VIN between
8V and 28V. See the Typical Operating Characteristics.
Compensation
Each of the three regulation loops (the battery voltage,
the charge current, and the input current limit) are com-
pensated separately using the CCV, CCI, and CCS
pins, respectively. Compensate the voltage regulation
loop with a 10kΩresistor in series with a 0.01µF capaci-
tor from CCV to GND. Compensate the charge current
loop and source current loop with 0.01µF capacitors
from CCI to GND and from CCS to GND, respectively.
Voltage Loop Compensation
When regulating the charge voltage, the MAX1870A
behaves as a current-mode step-down or step-up
power supply. Since a current-mode controller regulates
its output current as a function of the error signal, the
duty-cycle modulator can be modeled as a GM stage
(Figure 9). Results are similar in step-down, step-up, or
step-up/down, with the exception of a load-dependent
right-half-plane zero that occurs in step-up mode.
The required compensation network is a pole-zero pair
formed with CCV and RCV. CCV is chosen to be large
enough that its impedance is relatively small compared
to RCV at frequencies near crossover. RCV sets the
gain of the error amplifier near crossover. RCV and
COUT determine the crossover frequency and, there-
fore, the closed-loop response of the system and the
response time upon battery removal.
RESR is the equivalent series resistance (ESR) of the
charger’s output capacitor (COUT). RLis the equivalent
charger output load, RL= ΔVBATT / ΔICHG = RBATT.
The equivalent output impedance of the GMV amplifier,
ROGMV, is greater than 10MΩ. The voltage loop
transconductance (GMV = ΔICCV / ΔVBATT) scales
inversely with the number of cells. GMV = 0.1µA/mV for
four cells, 0.133µA/mV for three cells, and 0.2µA/mV for
two cells. The DC-DC converter’s transconductance
depends upon the charge current-sense resistor RS2:
where ACSI = 18, and RS2 = 30mΩin the Typical
Application Circuits, so GMPWM = 1.85A/V.
Use the following equation to calculate the loop transfer
function (LTF):
The poles and zeros of the voltage-loop transfer func-
tion are listed from lowest frequency to highest frequen-
cy in Table 3.
Near crossover, CCV has much lower impedance than
ROGMV. Since CCV is in parallel with ROGMV, CCV dom-
inates the parallel impedance near crossover.
Additionally, RCV has a much higher impedance than
CCV and dominates the series combination of RCV and
CCV, so:
COUT also has a much lower impedance than RLnear
crossover, so the parallel impedance is mostly capaci-
tive and:
If RESR is small enough, its associated output zero has
a negligible effect near crossover and the loop transfer
function can be simplified as follows:
R
sC x R sC
L
OUT L OUT
()1
1
+≅
RxsCxR
sC x R R near crossover
OGMV CV CV
CV OGMV
CV
()
()
,
1
1
+
+≅
LTF GM x R x sC R
sC x R x
R
sC x R xG x sC xR
PWM OGMV CV CV
CV OGMV
L
OUT L
MV OUT ESR
=+
+
++
()
()
()
()
1
1
11
GM AxRS
PWM
CSI
=1
2
GMOUT
REF
GMV
RL
RESR
COUT
RO
RCV
CCV
BATT
CCV
Figure 9. CCV Simplified Loop Diagram
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
24 ______________________________________________________________________________________
Setting the LTF = 1 to solve for the unity-gain frequency
yields:
For stability, choose a crossover frequency lower than
1/10th of the switching frequency. The crossover fre-
quency must also be below the RHP zero, calculated at
maximum charge current, minimum input voltage, and
maximum battery voltage.
Choosing a crossover frequency of 13kHz and solving for
RCV using the component values listed in Figure 1 yields:
MODE = VCC (4 cells) GMV = 0.1µA/mV
COUT = 22µF GMPWM = 1.85A/V
VBATT= 16.8V fCO_CV = 13kHz
RL= 0.2ΩfOSC = 400kHz
To ensure that the compensation zero adequately can-
cels the output pole, select fZ_CV ≤fP_OUT.
CCV ≥(RL / RCV) x COUT
CCV ≥440pF
Figure 10 shows the Bode Plot of the voltage-loop fre-
quency response using the values calculated above.
Charge-Current and Wall-Adapter-Current
Loop Compensation
When the MAX1870A regulates the charge current or the
wall adapter current, the system stability does not
depend on the output capacitance. The simplified
schematic in Figure 11 describes the operation of the
MAX1870A when the charge-current loop (CCI) is in con-
trol. The simplified schematic in Figure 12 describes the
operation of the MAX1870A when the source-current
RxC xf
GMV x GM k
CV OUT CO CV
PWM
==
210
π_Ω
fGMxG
R
xC
CO CV PWM MV CV
OUT
_=⎛
⎝
⎜
⎞
⎠
⎟
2π
LTF GM x R
sC G
PWM CV
OUT
MV
=
Table 3. Constant Voltage Loop Poles and Zeros
NO.
NAME
CALCULATION DESCRIPTION
1
CCV Pole
Lowest Frequency Pole created by CCV and GMV’s finite output
resistance. Since ROGMV is very large (ROGMV > 10MΩ), this is
a low-frequency pole.
2
CCV Zero
Voltage-Loop Compensation Zero. If this zero is lower than the
output pole, fP_OUT, then the loop transfer function
approximates a single-pole response near the crossover
frequency. Choose CCV to place this zero at least 1 decade
below crossover to ensure adequate phase margin.
3Output
Pole
Outp ut P ol e For m ed w i th the E ffecti ve Load Resi stance RL and the
Outp ut C ap aci tance C
OU T
. RL i nfl uences the D C g ai n b ut d oes not
affect the stab i l i ty of the system or the cr ossover fr eq uency.
4Output
Zero
Output ESR Zero. This zero can keep the loop from crossing
unity gain if fZ_OUT is less than the desired crossover
frequency. Therefore, choose a capacitor with an ESR zero
greater than the crossover frequency.
5
RHP Zero
S tep - U p M od e RH P Z er o. Thi s zer o occur s b ecause of the i ni ti al
op p osi ng r esp onse of a step - up conver ter . E ffor ts to i ncr ease the
i nd uctor cur r ent r esul t i n an i m m ed i ate d ecr ease i n cur r ent
d el i ver ed , al thoug h eventual l y r esul t i n an i ncr ease i n cur r ent
d el i ver ed . Thi s zer o i s d ep end ent on char g e cur r ent and m ay
cause the system to g o unstab l e at hi g h cur r ents w
hen i n step - up
m od e. A r i g ht- hal f- p l ane zer o i s d etr i m ental to b oth p hase and
g ai n. To ensur e stab i l i ty und er m axi m um l oad i n step - up m od e,
the cr ossover fr eq uency m ust b e l ow er than hal f of fR H P Z
.
fxR C
PCV
OGMV CV
_=1
2π
fxR C
ZCV
CV CV
_=1
2π
fxR C
P OUT
L OUT
_=1
2π
fxR C
Z OUT
ESR OUT
_=1
2π
fV
xLI
V
xLI V
RHPZ IN
L
IN
OUT OUT
=
=
2
2
2
π
π
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 25
loop (CCS) is in control. Since the output capacitor’s
impedance has little effect on the response of the current
loop, only a single pole is required to compensate this
loop. ACSI and ACSS are the internal gains of the current-
sense amplifiers. RS2 is the charge current-sense resis-
tor. RS1a and RS1b are the adapter current-sense
resistors. ROGMI and ROGMS are the equivalent output
impedance of the GMI and GMS amplifiers, which are
greater than 10MΩ. GMI is the charge-current amplifier
transconductance (2.4µA/mV). GMS is the adapter-cur-
rent amplifier transconductance (1.7µA/mV.) GMPWM is
the DC-DC converter transconductance (1.85A/V).
Use the following equation to calculate the loop transfer
function:
which describes a single-pole system. Since GMPWM =
the loop-transfer function simplifies to:
Use the following equations to calculate the crossover
frequency:
For stability, choose a crossover frequency lower than
1/10th of the switching frequency and lower than half of
the RHP zero.
CCI = 10 GMI / (2πx fOSC), CCS = 10 GMS / (2πx fOSC)
This zero is inversely proportional to charge current
and may cause the system to go unstable at high cur-
rents when in step-up mode. A right-half-plane zero is
detrimental to both phase and gain. To also ensure sta-
bility under maximum load in step-up mode, the CCI
crossover frequency must also be lower than fRHPZ.
The right-half-plane zero does not affect CCS.
Choosing a crossover frequency of 30kHz and using
the component values listed in Figure 1 yields CCI and
CCS_ > 10nF. Values for CCI / CCS greater than ten
times the minimum value may slow down the current
loop response excessively. Figure 13 shows the Bode
Plot of the input-current frequency response using the
values calculated above.
MOSFET Drivers
DHI and DBST are optimized for driving moderately-
sized power MOSFETs. Use low-inductance and low-
resistance traces from driver outputs to MOSFET gates.
DHI typically sources 1.6A and sinks 0.8A to or from
the gate of the p-channel MOSFET. DHI swings from
VHP to VHN. VHN is a negative LDO that regulates with
respect to VHP to provide high-side gate drive.
Connect VHP to DCIN. Bypass VHN with a 1µF capaci-
tor to VHP.
fV
xLI
V
LI V
RHPZ WorstCase IN MIN
L
IN MIN
OUTMAX OUTMAX
___
==
22
2
ππ
fGMI
CfGMS
C
CO CI
CI
CO CS
CS
__
,==
22ππ
LTF GM R
sR x C
OGM
OGM C
=+
__
__
1
1
AxRS
CS _ _
LTF GM x A x RS x GM R
sR x C
PWM CS OGM
OGM C
=+
__ _ _
__
1
CCV LOOP RESPONSE
MAGNITUDE (dB)
-135
-90
-45
0
80
60
40
20
-40
-20
0
1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+061.E-01
FREQUENCY (Hz)
MAG
PHASE
Figure 10. CCV Loop Response
GMPWM
REF
GMI
ROGMI
CCI
CCI
RS2
ACSI
CSI
Figure 11. CCI Simplified Loop Diagram
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
26 ______________________________________________________________________________________
LDO provides a 5.4V supply derived from DCIN and
delivers over 10mA. The n-channel MOSFET driver
DBST is powered by DLOV and can source 2.5A and
sink 5A. Since LDO provides power to the internal ana-
log circuitry, use an RC filter from LDO to DLOV as
shown in Figure 1 to minimize noise at LDO. LDO also
supplies the 4.096V reference (REF) and most of the
internal control circuitry. Bypass LDO with a 1µF or
greater capacitor to GND.
Applications Information
Component Selection
Table 4 lists the recommended components and refers
to the circuit of Figure 1. The following sections describe
how to select these components.
MOSFETs
The MAX1870A requires one p-channel MOSFET and
one n-channel MOSFET. Component substitutions are
permissible as long as the on-resistance and gate
charge are equal or lower and the voltage, current, and
power-dissipation ratings are high enough. If using a
lower-power application, scale down the MOSFETs with
lower gate charge and the MOSFET’s on-resistance
can be scaled up. For example, in a system designed
to deliver half as much current, MOSFETs selected with
twice the on-resistance and half as much gate charge
ensure equal or better efficiency, and reduce size and
cost. If resistive losses dominate, it can be possible to
reduce the gate charge at the cost of on-resistance
and still achieve a similar efficiency.
Make sure that the linear regulators can drive the
selected MOSFETs. The average current required to
drive a given MOSFET is:
ILDO = QgM2 x fswitch
IVHN = QgM1 x fswitch
where fswitch is 400kHz (typ).
GMPWM
ROGMS
CCS
CCS
CLS CSS
GMS
ACSS
CSSP
CSSN/
CSSS
RS1_
Figure 12. CCS Simplified Loop Diagram
CCI LOOP RESPONSE
MAGNITUDE (dB)
-90
-45
0
80
60
40
20
-40
-20
0
100
1k100.1 100k
FREQUENCY (Hz)
CCS LOOP RESPONSE
MAGNITUDE (dB)
-90
-45
0
80
60
40
20
-40
-20
0
100
1k100.1 100k 10M
FREQUENCY (Hz)
PHASE PHASE
MAG
MAG
Figure 13. CCI and CCS Loop Response
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 27
MOSFET Power Dissipation
Table 5 shows the resistive losses and switching losses
in each of the MOSFETs during either step-up or step-
down operation. Table 5 provides a first-order estimate,
but does not consider second-order effects such as
ripple current or nonlinear gate drive.
For typical applications where VBATT / 2 < VIN < 2 x
VBATT, the resistive losses are primarily dissipated in M1
since M2 operates at a lower duty cycle. Switching loss-
es are dissipated in M1 when in step-down mode and in
M2 when in step-up mode. Ratio the MOSFETs so that
resistive losses roughly equal switching losses when at
maximum load and typical input/output conditions. The
resistive loss equations are a good approximation in
hybrid mode (VIN near VBATT). Both M1 and M2 switch-
ing losses apply in hybrid mode.
Switching losses can become a heat problem when the
maximum AC adapter voltage is applied in step-down
operation or minimum AC adapter voltage is applied
with a maximum battery voltage. This behavior occurs
because of the squared term in the CV2f switching-loss
equation. Table 5 provides only an estimate and is not
a substitute for breadboard evaluation.
Inductor Selection
Select the inductor to minimize power dissipation in the
MOSFETs, inductor, and sense resistors. To optimize
resistive losses and RMS inductor current, set the LIR
(inductor current ripple) to 0.3. Because the maximum
resistive power loss occurs at the step-up boundary of
hybrid mode, select LIR for operating in this mode. Select
the inductance according to the following equation:
Larger inductance values can be used; however, they
contribute extra resistance that can reduce efficiency.
Smaller inductance values increase RMS currents and
can also reduce efficiency.
Saturation Current Rating
The inductor must have a saturation current rating high
enough so it does not saturate at full charge, maximum
output voltage, and minimum input voltage. In step-up
operation, the inductor carries a higher current than in
step-down operation with the same load. Calculate the
inductor saturation current rating by the following
equation:
Input-Capacitor Selection
The input capacitor must meet the ripple current
requirement (IRMS) imposed by the switching currents.
Nontantalum chemistries (ceramic, aluminum, or OS-
IVxI
V
TxV x V
V
xL
SAT OUT MAX CHG MAX
IN MIN
IN MIN IN MIN
OUT MAX
≥+
−
⎛
⎝
⎜⎞
⎠
⎟
__
_
__
_
1
2
LxV xt
LIR I
IN
CHG
=2min
Table 4. Component List
DESIGNATION PART SPECIFICATIONS
INDUCTORS
L1
Sumida CDRH104R-100
Sumida CDRH104R-7R0
Sumida CDRH104R-5R2
Sumida CDRH104R-3R8
10µH, 4.4A, 35mΩ power inductor
7µH, 4.8A, 27mΩ power inductor
5.2µH, 5.5A, 22mΩ power inductor
3.8µH, 6A, 13mΩ power inductor
P-CHANNEL MOSFETs
M1
Siliconix Si4435DY
Fairchild FDC602P
Fairchild FDS4435A
Fairchild FDW256P
P-FET 35mΩ, QG = 17nC, VDSMAX = 30V, 8-pin SO
P-FET 35mΩ, QG = 14nC, VDSMAX = 20V, 6-pin SuperSOT
P-FET 25mΩ, QG = 21nC, VDSMAX = 30V, 8-pin SO
P-FET 20mΩ, QG = 28nC, VDSMAX = 30V, 8-pin TSSOP
N/P-CHANNEL MOSFET PAIRS
M1/M2 Fairchild FDW2520C (8-pin TSSOP) N-FET 18mΩ, QG = 14nC, VDSMAX = 20V,
P-FET 35mΩ, QG = 14nC, VDSMAX = 20V
N-CHANNEL MOSFETs
M2 IRF7811W N-FET, 9mΩ, QG = 18nC, VDSMAX = 30V, 8-pin SO
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
28 ______________________________________________________________________________________
CON) are preferred due to their resilience to power-up
surge currents.
The input capacitors should be sized so that the temper-
ature rise due to ripple current in continuous conduction
does not exceed approximately 10°C. Choose a capaci-
tor with a ripple current rating higher than 0.5 x ICHG.
Output-Capacitor Selection
The output capacitor absorbs the inductor ripple current
in step-down mode, or a peak-to-peak ripple current
equal to the inductor current when in step-up or hybrid
mode. As such, both capacitance and ESR are impor-
tant parameters in specifying the output capacitor. The
actual amplitude of the ripple is the combination of the
two. Ceramic devices are preferable because of their
resilience to surge currents. The worst-case output ripple
occurs during hybrid mode when the input voltage is at
its minimum. See the Typical Operating Characteristics.
Select a capacitor that can handle 0.5 x ICHG x VBATT /
VIN while keeping the rise in capacitor temperature less
than 10°C. Also, select the output capacitor to tolerate
the surge current delivered from the battery when it is
initially plugged into the charger.
Battery-Removal Response
Upon battery removal, the MAX1870A continues to reg-
ulate a constant inductor current until the battery volt-
age, VBATT, exceeds the regulation threshold. The
MAX1870A’s response time depends on the bandwidth
of the CCV loop, fCO (see the Voltage Loop
Compensation section). For applications where battery
overshoot is critical, either increase COUT or increase
fCO by increasing RCV. See Battery Insertion and
Removal in the Typical Operating Characteristics.
System Load Transient
The MAX1870A battery charger features a very fast
response time to system load transients. Since the
input current loop is configured as a single-pole sys-
tem, the MAX1870A responds quickly to system load
transients (see the System Load-Transient Response
graph in the Typical Operating Characteristics). This
reduces the risk of tripping the overcurrent threshold of
the wall adapter and minimizes requirements for
adapter oversizing.
Table 5. MOSFET Resistive and Switching Losses
STEP-DOWN MODE STEP-UP MODE
DESIGNATION
DC LOSSES
M1
D4 0
M2 0
D3 ICHG x VDIODE ICHG x VDIODE
SWITCHING LOSSES
M1 0
D4 0 0
M2 0
D3 0 0
Note: CLX is the total parasitic capacitance at the drain terminals of M1 and M2. IGATE is the peak gate-drive source/sink current of
M1 or M2.
V
VxI xR
BATT
DCIN
CHG DS ON
⎛
⎝
⎜⎞
⎠
⎟2()
V
VxI xR
BATT
DCIN
CHG DS ON
⎛
⎝
⎜⎞
⎠
⎟
2
()
1−
⎛
⎝
⎜⎞
⎠
⎟
V
VxI V
BATT
DCIN
CHG Diode
12
−
⎛
⎝
⎜⎞
⎠
⎟⎛
⎝
⎜⎞
⎠
⎟
V
VxV
VxI xR
DCIN
BATT
BATT
DCIN
CHG DS ON()
VxCxfI
I
DCIN MAX LX SW CHG
GATE
()
2
VxCxfI
IxV
BATT MAX LX SW CHG
GATE DCIN MAX
()
()
3
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 29
Layout and Bypassing
Bypass DCIN with a 1µF to ground (Figure 1). Optional
diodes D1 and D2 protect the MAX1870A when the DC
power-source input is reversed. A signal diode for D1 is
adequate because DCIN only powers the LDO and the
internal reference. Good PC board layout is required to
achieve specified noise, efficiency, and stable perfor-
mance. The PC board layout artist must be given
explicit instructions—preferably, a pencil sketch show-
ing the placement of the power-switching components
and high-current routing. Refer to the PC board layout
in the MAX1870A evaluation kit for examples. A ground
plane is essential for optimum performance. In most
applications, the circuit is located on a multilayer
board, and full use of the four or more copper layers is
recommended. Use the top layer for high-current con-
nections (PGND, DHI, VHP, VHN, BLKP, and DLOV),
the bottom layer for quiet connections (CSSP, CSSN,
CSSS, CSIP, CSIN, REF, CCV, CCI, CCS, DCIN, LDO
and GND), and the inner layers for an uninterrupted
ground plane. Use the following step-by-step guide:
1) Place the high-power connections first, with their
grounds adjacent:
•Minimize the current-sense resistor trace lengths,
and ensure accurate current sensing with Kelvin
connections. Use independent branches for CSSP,
CSSS, CSSN, CSIP, and CSIN.
•Minimize ground trace lengths in the high-current
paths.
•Minimize other trace lengths in the high-current paths.
•Use >5mm wide traces for high-current paths.
Ideally, surface-mount power components are flush
against one another with their ground terminals almost
touching. These high-current grounds are then connect-
ed to each other with a wide, filled zone of top-layer cop-
per, so they do not go through vias. Other high-current
paths should also be minimized, but focus primarily on
short ground and current-sense connections to eliminate
about 90% of all PC board layout problems.
2) Place the IC and signal components. Keep the main
switching nodes (inductor connections) away from
sensitive analog components (current-sense traces
and REF capacitor). Important: the IC must be no
further than 10mm from the current-sense resis-
tors. Keep the gate-drive traces (DHI and DBST)
shorter than 20mm, and route them away from the
current-sense lines and REF. Place ceramic bypass
capacitors close to the IC. The bulk capacitors can
be placed further away. Bypass CSSP, CSSN, CSIN,
and CSIP to analog GND to reduce switching noise
and maintain input-current and charger-current accu-
racy. Place the current-sense input filter capacitors
under the part, connected directly to GND.
3) Use a single-point star ground placed directly
below the part. Connect the input ground trace,
power ground (subground plane), and normal
ground to this node.
Figure 14 shows a partial layout of the power path and
components. Refer to the EV kit data sheet for more
information.
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
30 ______________________________________________________________________________________
MAX1870A
THIN QFN
TOP VIEW
32
31
30
29
28
27
26
9
10
11
12
13
14
15
18
19
20
21
22
23
24
7
6
5
4
3
2
1
REF
LDO
CLS
GND
CCV
CCI
CCS
8
GND
DCIN
CSSP
CSSS
CSSN
VHP
DHI
VHN
25
DLOV
I.C.
PGND
DBST
I.C.
I.C.
BLKP
CSIP
17 CSIN
SHDN
IINP
16
BATT
CELLS
ICTL
VCTL
ASNS
REFIN
Pin Configuration
NP
M1
M2
D3 D4
RS1a
RS1b
C8
C9
RS2
IN
BATT
PGND
LOAD
L1
Figure 14. Recommended Layout for the MAX1870A
Chip Information
TRANSISTOR COUNT: 6484
PROCESS: BiCMOS
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
______________________________________________________________________________________ 31
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
QFN THIN.EPS
D2
(ND-1) X e
e
D
C
PIN # 1
I.D.
(NE-1) X e
E/2
E
0.08 C
0.10 C
A
A1 A3
DETAIL A
E2/2
E2
0.10 M C A B
PIN # 1 I.D.
b
0.35x45°
D/2 D2/2
L
C
L
C
e e
L
CC
L
k
LL
DETAIL B
L
L1
e
XXXXX
MARKING
H
12
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
L
e/2
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
3.353.15T2855-1 3.25 3.353.15 3.25
MAX.
3.20
EXPOSED PAD VARIATIONS
3.00T2055-2 3.10
D2
NOM.MIN.
3.203.00 3.10
MIN. E2
NOM. MAX.
NE
ND
PKG.
CODES
1. DIMENSIONING & TOLERANCING CONFORM TO ASME Y14.5M-1994.
2. ALL DIMENSIONS ARE IN MILLIMETERS. ANGLES ARE IN DEGREES.
3. N IS THE TOTAL NUMBER OF TERMINALS.
4. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012. DETAILS OF TERMINAL #1 IDENTIFIER ARE
OPTIONAL, BUT MUST BE LOCATED WITHIN THE ZONE INDICATED. THE TERMINAL #1
IDENTIFIER MAY BE EITHER A MOLD OR MARKED FEATURE.
5. DIMENSION b APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN
0.25 mm AND 0.30 mm FROM TERMINAL TIP.
6. ND AND NE REFER TO THE NUMBER OF TERMINALS ON EACH D AND E SIDE RESPECTIVELY.
7. DEPOPULATION IS POSSIBLE IN A SYMMETRICAL FASHION.
8. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
9. DRAWING CONFORMS TO JEDEC MO220, EXCEPT EXPOSED PAD DIMENSION FOR T2855-1,
T2855-3, AND T2855-6.
NOTES:
SYMBOL
PKG.
N
L1
e
E
D
b
A3
A
A1
k
10. WARPAGE SHALL NOT EXCEED 0.10 mm.
JEDEC
T1655-1 3.203.00 3.10 3.00 3.10 3.20
0.70 0.800.75
4.90
4.90
0.25
0.25
0
--
4
WHHB
4
16
0.350.30 5.10
5.105.00
0.80 BSC.
5.00
0.05
0.20 REF.
0.02
MIN. MAX.NOM.
16L 5x5
3.10
T3255-2 3.00 3.20 3.00 3.10 3.20
2.70
T2855-2 2.60 2.602.80 2.70 2.80
L0.30 0.500.40
------
WHHC
20
5
5
5.00
5.00
0.30
0.55
0.65 BSC.
0.45
0.25
4.90
4.90
0.25
0.65
--
5.10
5.10
0.35
20L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-1
28
7
7
5.00
5.00
0.25
0.55
0.50 BSC.
0.45
0.25
4.90
4.90
0.20
0.65
--
5.10
5.10
0.30
28L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
---
WHHD-2
32
8
8
5.00
5.00
0.40
0.50 BSC.
0.30
0.25
4.90
4.90
0.50
--
5.10
5.10
32L 5x5
0.20 REF.
0.75
0.02
NOM.
0
0.70
MIN.
0.05
0.80
MAX.
0.20 0.25 0.30
DOWN
BONDS
ALLOWED
NO
YES3.103.00 3.203.103.00 3.20T2055-3 3.103.00 3.203.103.00 3.20T2055-4
T2855-3 3.15 3.25 3.35 3.15 3.25 3.35
T2855-6 3.15 3.25 3.35 3.15 3.25 3.35
T2855-4 2.60 2.70 2.80 2.60 2.70 2.80
T2855-5 2.60 2.70 2.80 2.60 2.70 2.80
T2855-7 2.60 2.70 2.80 2.60 2.70 2.80
3.203.00 3.10T3255-3 3.203.00 3.10
3.203.00 3.10T3255-4 3.203.00 3.10
NO
NO
NO
NO
NO
NO
NO
NO
YES
YES
YES
YES
3.203.00T1655-2 3.10 3.00 3.10 3.20 YES
NO3.203.103.003.10T1655N-1 3.00 3.20
3.353.15T2055-5 3.25 3.15 3.25 3.35 YES
3.35
3.15T2855N-1 3.25 3.15 3.25 3.35 NO
3.35
3.15T2855-8 3.25 3.15 3.25 3.35 YES
3.203.10T3255N-1 3.00 NO
3.203.103.00
L
0.40
0.40
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
**
SEE COMMON DIMENSIONS TABLE
±0.15
11. MARKING IS FOR PACKAGE ORIENTATION REFERENCE ONLY.
H
22
21-0140
PACKAGE OUTLINE,
16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
-DRAWING NOT TO SCALE-
12. NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY.
3.30T4055-1 3.20 3.40 3.20 3.30 3.40 ** YES
0.0500.02
0.600.40 0.50
10
-----
0.30 40
10
0.40 0.50
5.10
4.90 5.00
0.25 0.35 0.45
0.40 BSC.
0.15
4.90 0.250.20
5.00 5.10
0.20 REF.
0.70
MIN.
0.75 0.80
NOM.
40L 5x5
MAX.
13. LEAD CENTERLINES TO BE AT TRUE POSITION AS DEFINED BY BASIC DIMENSION "e", ±0.05.
MAX1870A
Step-Up/Step-Down
Li+ Battery Charger
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.