Balanced Modulator/Demodulator
Data Sheet
AD630
Rev. F Document Feedback
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FEATURES
Recovers signal from 100 dB noise
2 MHz channel bandwidth
45 V/µs slew rate
Low crosstalk: −120 dB at 1 kHz, −100 dB at 10 kHz
Pin programmable, closed-loop gains of ±1 and ±2
0.05% closed-loop gain accuracy and match
100 µV channel offset voltage (AD630)
350 kHz full power bandwidth
Chips available
APPLICATIONS
Balanced modulation and demodulation
Synchronous detection
Phase detection
Quadrature detection
Phase sensitive detection
Lock in amplification
Square wave multiplication
FUNCTIONAL BLOCK DIAGRAM
CM OFF
ADJ CM OFF
ADJ DIFF OFF
ADJ DIFF OFF
ADJ
2.5kΩ
AMP A
2.5kΩ
AMP B
–V
10kΩ
10kΩ
5kΩ
COMP
R
IN
A
CH A+
CH A–
R
IN
B
CH B+
CH B–
SEL B
SEL A
COMP
+V
S
V
OUT
R
B
R
F
R
A
CHANNEL
STATUS
B/A
–V
S
A
B
00784-001
BIAS
+V
S
Figure 1.
GENERAL DESCRIPTION
The AD630 is a high precision balanced modulator/demodulator
that combines a flexible commutating architecture with the
accuracy and temperature stability afforded by laser wafer trimmed
thin film resistors. A network of on-board applications resistors
provides precision closed-loop gains of ±1 and ±2 with 0.05%
accuracy (AD630B). These resistors may also be used to accurately
configure multiplexer gains of 1, 2, 3, or 4. External feedback
enables high gain or complex switched feedback topologies.
The AD630 can be thought of as a precision op amp with two
independent differential input stages and a precision compara-
tor that is used to select the active front end. The rapid response
time of this comparator coupled with the high slew rate and fast
settling of the linear amplifiers minimize switching distortion.
The AD630 is used in precision signal processing and instru-
mentation applications that require wide dynamic range. When
used as a synchronous demodulator in a lock-in amplifier
configuration, the AD630 can recover a small signal from
100 dB of interfering noise (see the Lock-In Amplifier
Applications section). Although optimized for operation up to
1 kHz, the circuit is useful at frequencies up to several hundred
kilohertz.
Other features of the AD630 include pin programmable fre-
quency compensation; optional input bias current compensation
resistors, common-mode and differential-offset voltage adjust-
ment, and a channel status output that indicates which of the
two differential inputs is active.
PRODUCT HIGHLIGHTS
1. The application flexibility of the AD630 makes it the best
choice for applications that require precisely fixed gain,
switched gain, multiplexing, integrating-switching
functions, and high speed precision amplification.
2. The 100 dB dynamic range of the AD630 exceeds that of
any hybrid or IC balanced modulator/demodulator and is
comparable to that of costly signal processing instruments.
3. The op amp format of the AD630 ensures easy imple-
mentation of high gain or complex switched feedback
functions. The application resistors facilitate the implemen-
tation of most common applications with no additional parts.
4. The AD630 can be used as a 2-channel multiplexer with gains
of 1, 2, 3, or 4. The channel separation of 100 dB at 10 kHz
approaches the limit achievable with an empty IC package.
5. Laser trimming of the comparator and amplifying channel
offsets eliminate the need for external nulling in most cases.
AD630 Data Sheet
Rev. F | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 4
Thermal Resistance ...................................................................... 4
Chip Availability ........................................................................... 4
ESD Caution .................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
Typical Performance Characteristics ............................................. 9
Test Circuits ..................................................................................... 11
Theory of Operation ...................................................................... 12
Two Ways To Look At The AD630 .......................................... 12
How the AD630 Works .............................................................. 12
Circuit Description .................................................................... 13
Other Gain Configurations ....................................................... 14
Switched Input Impedance........................................................ 14
Frequency Compensation ......................................................... 14
Offset Voltage Nulling ............................................................... 15
Channel Status Output .............................................................. 15
Applications Information .............................................................. 16
Balanced Modulator ................................................................... 16
Balanced Demodulator .............................................................. 16
Precision Phase Comparator .................................................... 16
Precision Rectifier Absolute Value ........................................... 16
LVDT Signal Conditioner ......................................................... 17
AC Bridge .................................................................................... 17
Lock-In Amplifier Applications ............................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 20
REVISION HISTORY
7/15—Rev. E to Rev. F
Updated Format .................................................................. Universal
Changes to Features Section, General Description Section,
Product Highlights Section, and Figure 1 ..................................... 1
Added Applications Section ............................................................ 1
Changes to Table 3 ............................................................................ 4
Added Table 4; Renumbered Sequentially .................................... 5
Added Figure 4; Renumbered Sequentially and Table 5 ............. 6
Added Figure 5 and Table 6 ............................................................. 7
Added Table 7 .................................................................................... 8
Changes to Figure 7, Figure 8, and Figure 9.................................. 9
Changes to Figure 13, Figure 14, and Figure 15 ......................... 10
Added Test Circuits Section and Figure 16 to Figure 19 ........... 11
Added Theory of Operation Section............................................ 12
Change to Figure 24 ....................................................................... 13
Updated Outline Dimensions ....................................................... 19
Changes to Ordering Guide .......................................................... 20
6/04—Rev. D to Rev. E
Changes to Ordering Guide ............................................................. 3
Replaced Figure 12 ............................................................................ 9
Changes to AC Bridge Section ......................................................... 9
Replaced Figure 13 ......................................................................... 10
Changes to Lock-In Amplifier Applications ............................... 10
Updated Outline Dimensions ....................................................... 11
6/01—Rev. C to Rev. D
Changes to Specification Table ........................................................ 2
Changes to Thermal Characteristics ............................................... 3
Changes to Ordering Guide ............................................................. 3
Changes to Pin Configurations ....................................................... 3
Changes to Outline Dimensions .................................................. 11
Data Sheet AD630
Rev. F | Page 3 of 20
SPECIFICATIONS
At 25°C and ±VS = ±15 V, unless otherwise noted.
Table 1.
Parameter
AD630J/AD630A AD630K/AD630B AD630S
Unit Min Typ Max Min Typ Max Min Typ Max
GAIN
Open-Loop Gain 90 110 100 120 90 110 dB
±1, ±2 Closed-Loop Gain Error 0.1 0.05 0.1 %
Closed-Loop Gain Match 0.1 0.05 0.1 %
Closed-Loop Gain Drift 2 2 2 ppm/°C
CHANNEL INPUTS
VIN Operational Limit1 (−VS + 4) to (+VS − 1) (−VS + 4) to (+VS − 1) (−VS + 4) to (+VS − 1) V
Input Offset Voltage 500 100 500 µV
TMIN to TMAX 800 160 1000 µV
Input Bias Current 100 300 100 300 100 300 nA
Input Offset Current 10 50 10 50 10 50 nA
Channel Separation at 10 kHz 100 100 100 dB
COMPARATOR
VIN Operational Limit1 (−VS + 3) to (+VS − 1.5) (−VS + 3) to (+VS − 1.5) (−VS + 3) to (+VS − 1.3) V
Switching Window ±1.5 ±1.5 ±1.5 mV
TMIN to TMAX ±2.0 ±2.0 ±2.5 mV
Input Bias Current 100 300 100 300 100 300 nA
Response Time (−5 mV to +5 mV Step) 200 200 200 ns
Channel Status
ISINK at VOL = −VS + 0.4 V2 1.6 1.6 1.6 mA
Pull-Up Voltage (−VS + 33) (−VS + 33) (−VS + 33) V
DYNAMIC PERFORMANCE
Unity Gain Bandwidth 2 2 2 MHz
Slew Rate3 45 45 45 V/µs
Settling Time to 0.1% (20 V Step)
3
3
3
µs
OPERATING CHARACTERISTICS
Common-Mode Rejection 85 105 90 110 90 110 dB
Power Supply Rejection 90 110 90 110 90 110 dB
Supply Voltage Range ±5 ±16.5 ±5 ±16.5 ±5 ±16.5 V
Supply Current 4 5 4 5 4 5 mA
OUTPUT VOLTAGE, AT RL = 2 kΩ
TMIN to TMAX ±10 ±10 ±10 V
Output Short-Circuit Current 25 25 25 mA
TEMPERATURE RANGES
N Package 0 70 0 70 °C
D Package −25 +85 −25 +85 −55 +125 °C
1 If one terminal of each differential channel or comparator input is kept within these limits the other terminal may be taken to the positive supply.
2 ISINK at VOL = (−VS + 1 V) is typically 4 mA.
3 Pin 12 open. Slew rate with Pin 12 and Pin 13 shorted is typically 35 V/µs.
AD630 Data Sheet
Rev. F | Page 4 of 20
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Rating
Supply Voltage ±18 V
Internal Power Dissipation 600 mW
Output Short-Circuit to Ground Indefinite
Storage Temperature
Ceramic Package −65°C to +150°C
Plastic Package −55°C to +125°C
Lead Temperature Range (Soldering, 10 sec) 300°C
Maximum Junction Temperature
150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Table 3. Thermal Resistance
Package Type θJC θJA Unit
20-Lead PDIP (N-20) 24 61 °C/W
20-Lead SBDIP (D-20) 35 120 °C/W
20-Lead LCC (E-20-4) 35 120 °C/W
20-Lead SOIC_W (RW-20) 38 75 °C/W
CHIP AVAILABILITY
The AD630 is available in laser trimmed, passivated chip form.
Figure 2 shows the AD630 metallization pattern, bonding pads,
and dimensions. AD630 chips are available; consult factory for
details.
00784-002
14
15
16
17
18
7 8
65
4
19
20
1
2
3
13
12
0.089
(2.260)
0.99
(2.515)
11
10
9
Figure 2. Chip Metallization and Pinout
Dimensions shown in inches and (millimeters)
Contact factory for latest dimensions
ESD CAUTION
Data Sheet AD630
Rev. F | Page 5 of 20
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
00784-030
R
IN
A
1
CH A+
2
DIFF OFF ADJ
3
DIFF OFF ADJ
4
CH A–
20
CH B–
19
CH B+
18
R
IN
B
17
CM O FF ADJ
5
R
A
16
CM O FF ADJ
6
R
F
15
CHANNEL S TAT US B/A
7
R
B
14
–V
S8
V
OUT
13
SEL B
9
COMP
12
SEL A
10
+V
S
11
AD630
TOP VIEW
(No t t o Scal e)
Figure 3. 20-Lead SOIC Pin Configuration
Table 4. 20-Lead SOIC Pin Function Descriptions
Pin No. Mnemonic Description
1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A
2 CH A+ Noninverting Input of Op Amp A
3 DIFF OFF ADJ Differential Offset Adjustment
4 DIFF OFF ADJ Differential Offset Adjustment
5 CM OFF ADJ Common-Mode Offset Adjustment
6 CM OFF ADJ Common-Mode Offset Adjustment
7 CHANNEL STATUS B/A B or A Channel Status
8 −VS Negative Supply
9 SEL B B Channel Comparator Input
10 SEL A A Channel Comparator Input
11 +VS Positive Supply
12 COMP Pin to Connect Internal Compensation Capacitor
13 VOUT Output Voltage
14 RB 10 kΩ Gain Setting Resistor
15 RF 10 kΩ Feedback Resistor
16 RA 5 kΩ Feedback Resistor
17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B
18 CH B+ Noninverting Input of Op Amp B
19 CH B− Inverting Input of Op Amp B
20 CH A− Inverting Input of Op Amp A
AD630 Data Sheet
Rev. F | Page 6 of 20
00784-031
R
IN
A
CH A+
DIFF OFF ADJ
DIFF OFF ADJ
CH A–
CH B–
CH B+
R
IN
B
CM O FF ADJ R
A
CM O FF ADJ R
F
CHANNEL S TAT US B/A R
B
–V
S
V
OUT
SEL B COMP
SEL A +V
S
1
2
3
4
20
19
18
17
5
6
7
16
15
14
813
912
10 11
AD630
TOP VIEW
(No t t o Scal e)
Figure 4. 20-Lead PDIP Pin Configuration
Table 5. 20-Lead PDIP Pin Function Descriptions
Pin No. Mnemonic Description
1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A
2 CH A+ Noninverting Input of Op Amp A
3 DIFF OFF ADJ Differential Offset Adjustment
4 DIFF OFF ADJ Differential Offset Adjustment
5 CM OFF ADJ Common-Mode Offset Adjustment
6 CM OFF ADJ Common-Mode Offset Adjustment
7
CHANNEL STATUS B/
A
B or A Channel Status
8 −VS Negative Supply
9 SEL B B Channel Comparator Input
10 SEL A A Channel Comparator Input
11 +VS Positive Supply
12 COMP Pin to Connect Internal Compensation Capacitor
13 VOUT Output Voltage
14 RB 10 kΩ Gain Setting Resistor
15 RF 10 kΩ Feedback Resistor
16 RA 5 kΩ Feedback Resistor
17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B
18
CH B+
Noninverting Input of Op Amp B
19 CH B− Inverting Input of Op Amp B
20 CH A− Inverting Input of Op Amp A
Data Sheet AD630
Rev. F | Page 7 of 20
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5TOP VIEW
(Not to Scale)
AD630
R
IN
A
R
IN
B
CH B+
CH B–
CH A–
CH A+
DIFF OFF ADJ
DIFF OFF ADJ
R
B
R
F
R
A
CM OFF ADJ
CM OFF ADJ
–V
S
SEL B
SEL A +V
S
COMP
V
OUT
CHANNEL STATUS B/A
00784-003
Figure 5. 20-Lead CERDIP Pin Configuration
Table 6. 20-Lead CERDIP Pin Function Descriptions
Pin No. Mnemonic Description
1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A
2 CH A+ Noninverting Input of Op Amp A
3 DIFF OFF ADJ Differential Offset Adjustment
4 DIFF OFF ADJ Differential Offset Adjustment
5 CM OFF ADJ Common-Mode Offset Adjustment
6 CM OFF ADJ Common-Mode Offset Adjustment
7 CHANNEL STATUS B/A B or A Channel Status
8 −VS Negative Supply
9 SEL B B Channel Comparator Input
10 SEL A A Channel Comparator Input
11 +VS Positive Supply
12 COMP Pin to Connect Internal Compensation Capacitor
13 VOUT Output Voltage
14 RB 10 kΩ Gain Setting Resistor
15 RF 10 kΩ Feedback Resistor
16 RA 5 kΩ Feedback Resistor
17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B
18 CH B+ Noninverting Input of Op Amp B
19 CH B− Inverting Input of Op Amp B
20 CH A− Inverting Input of Op Amp A
AD630 Data Sheet
Rev. F | Page 8 of 20
20 19123
18
14
15
16
17
4
5
6
7
8
9 11 12 13
TOP VIEW
(Not to Scale)
AD630
DIFF OFF ADJ
CM O FF ADJ
CM O FF ADJ
CHANNEL STATUS B/A
–V
S
CH B+
R
IN
B
R
A
R
F
R
B
DIFF
OFF ADJ
CH A+
R
IN
A
CH A–
CH B–
SEL B
SEL A
+V
S
COMP
V
OUT
00784-004
10
Figure 6. 20-Terminal CLCC Pin Configuration
Table 7. 20-Terminal CLCC Pin Function Descriptions
Pin No. Mnemonic Description
1 RINA 2.5 kΩ Resistor to Noninverting Input of Op Amp A
2 CH A+ Noninverting Input of Op Amp A
3 DIFF OFF ADJ Differential Offset Adjustment
4 DIFF OFF ADJ Differential Offset Adjustment
5 CM OFF ADJ Common-Mode Offset Adjustment
6 CM OFF ADJ Common-Mode Offset Adjustment
7 CHANNEL STATUS B/A B or A Channel Status
8 −VS Negative Supply
9 SEL B B Channel Comparator Input
10 SEL A A Channel Comparator Input
11 +VS Positive Supply
12 COMP Pin to Connect Internal Compensation Capacitor
13 VOUT Output Voltage
14 RB 10 kΩ Gain Setting Resistor
15 RF 10 kΩ Feedback Resistor
16 RA 5 kΩ Feedback Resistor
17 RINB 2.5 kΩ Resistor to Noninverting Input of Op Amp B
18 CH B+ Noninverting Input of Op Amp B
19 CH B− Inverting Input of Op Amp B
20 CH A− Inverting Input of Op Amp A
Data Sheet AD630
Rev. F | Page 9 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
FREQUENCY (Hz)
15
10
5
100k 1M10k1k
OUTPUT VOLTAGE (±V)
0
R
L
= 2kΩ
C
L
= 100pF
00784-005
Figure 7. Output Voltage vs. Frequency (See Figure 16)
10
15
5
RESISTIVE LOAD (Ω)
OUTPUT VOLTAGE (±V)
0
100k 1M10k1k100101
C
L
= 100pF
f = 1kHz
00784-006
Figure 8. Output Voltage vs. Resistive Load (See Figure 16)
10
18
5
0 5 10 15 20
SUPPLY VOLTAGE (±V)
OUTPUT VOLTAGE (±V)
15
f = 1kHz
C
L
= 100pF
0
00784-007
Figure 9. Output Voltage Swing vs. Supply Voltage (See Figure 16)
100k10k1k100101
FREQUENCY (Hz)
COM M ON-MODE RE JE CTI ON (d B)
120
60
0
100
80
40
20
00784-008
Figure 10. Common-Mode Rejection vs. Frequency
INPUT VOLTAGE (V)
dV
O
dt
(V/µs)
60
0
–60
–2–3–4–5 –1 1 2 3 4 50
40
20
–40
–20
UNCOMPENSATED
COMPENSATED
00784-009
Figure 11.
dt
dVO
vs. Input Voltage
FREQUENCY (Hz)
120
60
0
1M100
100
80
20
40
10 1k 10k
UNCOMPENSATED
10M
0
45
90
OPEN-LOOP GAIN ( dB)
135
180
COMPENSATED
OPEN-LOOP PHASE (Degrees)
1100k
00784-010
Figure 12. Gain and Phase vs. Frequency
AD630 Data Sheet
Rev. F | Page 10 of 20
20mV
500ns
20mV
100
90
10
0%
20mV/DIV
(V
o
)
20mV/DIV
(V
i
)
TO P TRACE: Vo
BOTTOM TRACE: Vi
00784-011
Figure 13. Channel-to-Channel Switch-Settling Characteristic
(See Figure 17)
100
90
10
0%
100mV
500ns
50mV1mV
50mV/DIV
(Vi)
1mV/DIV
(A)
TOP T RACE : Vi
MIDDLE TRACE: SETTLING
ERROR (A)
BOTTOM TRACE: Vo
100mV/DIV
(Vo)
00784-013
Figure 14. Small Signal Noninverting Step Response (See Figure 18)
100
90
10
0%
10V
10V1mV
TOP T RACE : Vi
MIDDLE TRACE: SETTLING
ERROR (B)
BOTTOM TRACE: Vo
5µs
±10V 20kHz
(Vi
)
1mV/DIV
(B)
10V/DIV
(V
o
)
00784-012
Figure 15. Large Signal Inverting Step Response (See Figure 19)
Data Sheet AD630
Rev. F | Page 11 of 20
TEST CIRCUITS
2kΩ
5kΩ5kΩ
Vi
VO
100pF
0
0784-105
Figure 16. Test Circuit for Output Voltage vs. Frequecy, Resistive Load,
and Supply Voltage (See Figure 7, Figure 8, and Figure 9)
5kΩ10kΩ
10kΩ
Vi
CH A
CH B 12
VO
2
20
19
18
13
9
10
14
16 15
00784-111
Figure 17. Test Circuit for Channel-to-Channel Switch-Settling
Characteristic (See Figure 13)
12
CH A
MIDDLE
TRACE
(A)
10kΩ
10kΩ
V
O
BOTTOM
TRACE
TEKTRONIX
7A13
10kΩ
1kΩ
30pF
10kΩ
V
i
TOP
TRACE
2
20
13
14 15
00784-113
Figure 18. Test Circuit for Small Signal Noninverting Step Response
(See Figure 14)
12
CH A
10kΩ
10kΩ
V
O
BOTTOM
TRACE
10kΩ
V
i
TOP
TRACE
(B)
MIDDLE
TRACE
10kΩ
HP5082-2811
20
2
13
14 15
0
0784-112
Figure 19. Test Circuit for Large Signal Noninverting Step Response
(See Figure 15)
AD630 Data Sheet
Rev. F | Page 12 of 20
THEORY OF OPERATION
TWO WAYS TO LOOK AT THE AD630
The functional block diagram of the AD630 (see Figure 1)
shows the pin connections of the internal functions. An
alternative architectural diagram is shown in Figure 20. In this
diagram, the individual A and B channel preamps, the switch,
and the integrator output amplifier are combined in a single op
amp. This amplifier has two differential input channels, only
one of which is active at a time.
11
15
2
20
19
18
17
8
7
12
14
13
9
10
R
A
5kΩ
2.5kΩ
R
F
10kΩ
1
16
2.5kΩ
+V
S
R
B
10kΩ
SEL B
SEL A
CHANNEL STAT US B/A
A
B
–V
S
00784-014
Figure 20. Architectural Block Diagram
HOW THE AD630 WORKS
The basic mode of operation of the AD630 may be easier to
recognize as two fixed gain stages, which can be inserted into
the signal path under the control of a sensitive voltage compar-
ator. When the circuit is switched between inverting and
noninverting gain, it provides the basic modulation/demodulation
function. The AD630 is unique in that it includes laser wafer
trimmed thin-film feedback resistors on the monolithic chip.
The configuration shown in Figure 21 yields a gain of ±2 and
can be easily changed to ±1 by shifting RB from its ground
connection to the output.
The comparator selects one of the two input stages to complete
an operational feedback connection around the AD630. The
deselected input is off and has a negligible effect on operation.
A
B
RA
5kΩ
RF
10kΩ
VO
RB
10kΩ
Vi
2
20
19
18 13
1516
14 9
10
00784-015
Figure 21. AD630 Symmetric Gain (±2)
When Channel B is selected, the RA and RF resistors are
connected for inverting feedback as shown in the inverting gain
configuration diagram in Figure 22. The amplifier has sufficient
loop gain to minimize the loading effect of RB at the virtual
ground produced by the feedback connection. When the sign of
the comparator input is reversed, Input B is deselected and Input A
is selected. The new equivalent circuit is the noninverting gain
configuration shown in Figure 23. In this case, RA appears
across the op amp input terminals, but because the amplifier
drives this difference voltage to zero, the closed-loop gain is
unaffected.
The two closed-loop gain magnitudes are equal when RF/RA =
1 + RF/RB, which results from making RA equal to RFRB/(RF +
RB) the parallel equivalent resistance of RF and RB.
The 5 kΩ and the two 10 kΩ resistors on the AD630 chip can be
used to make a gain of 2 as shown in Figure 22 and Figure 23.
By paralleling the 10 kΩ resistors to make RF equal to 5 kΩ and
omitting RB, the circuit can be programmed for a gain of ±1 (as
shown in Figure 28). These and other configurations using the
on-chip resistors present the inverting inputs with a 2.5 kΩ
source impedance. The more complete AD630 diagrams show
2.5 kΩ resistors available at the noninverting inputs which can
be conveniently used to minimize errors resulting from input
bias currents.
R
A
5kΩ
R
F
10kΩ
R
B
10kΩ
V
i
V
O
= – R
F
R
A
V
i
00784-016
Figure 22. Inverting Gain Configuration
R
A
5kΩ
R
F
10kΩ
R
B
10kΩ
V
i
V
O
=
(
1+ R
F
R
B
)
V
i
00784-017
Figure 23. Noninverting Gain Configuration
Data Sheet AD630
Rev. F | Page 13 of 20
CIRCUIT DESCRIPTION
The simplified schematic of the AD630 is shown in Figure 24. It
has been subdivided into three major sections, the comparator,
the two input stages, and the output integrator. The comparator
consists of a front end made up of Q52 and Q53, a flip-flop load
formed by Q3 and Q4, and two current steering switching cells
Q28, Q29 and Q30, Q31. This structure is designed so that a
differential input voltage greater than 1.5 mV in magnitude
applied to the comparator inputs completely selects one of the
switching cells. The sign of this input voltage determines which
of the two switching cells is selected.
The collectors of each switching cell connect to an input
transconductance stage. The selected cell conveys bias currents
i22 and i23 to the input stage it controls, causing it to become
active. The deselected cell blocks the bias to its input stage,
which, as a consequence, remains off.
The structure of the transconductance stages is such that it
presents a high impedance at its input terminals and draws
no bias current when deselected. The deselected input does
not interfere with the operation of the selected input ensuring
maximum channel separation.
Another feature of the input structure is that it enhances the
slew rate of the circuit. The current output of the active stage
follows a quasihyperbolic sine relationship to the differential
input voltage. This means that the greater the input voltage, the
harder this stage drives the output integrator, and the faster the
output signal moves. This feature helps ensure rapid, symmetric
settling when switching between inverting and noninverting
closed loop configurations.
The output section of the AD630 includes a current mirror load
(Q24 and Q25), an integrator voltage gain stage (Q32), and a
complementary output buffer (Q44 and Q74). The outputs of
both transconductance stages are connected in parallel to the
current mirror. Because the deselected input stage produces no
output current and presents a high impedance at its outputs,
there is no conflict. The current mirror translates the differen-
tial output current from the active input transconductance
amplifier into single-ended form for the output integrator. The
complementary output driver then buffers the integrator output
to produce a low impedance output.
20
11
3456
19
218
13
12
SEL A
SEL B
DIFF
OFFADJ DIFF
OFFADJ CM
OFFADJ CM
OFFADJ
COMP
Q74
Q44
CH B– CH B+CH A+CH A–
i
55
Q4
Q3
Q28 Q31
Q30
Q32
C122
C121
i
i
73
22
i
23
–V
S
V
OUT
Q52 Q53
+V
S
Q65
Q34
Q33
Q62
Q35 Q36
Q67 Q70
Q25
Q24
Q29
10
9
8
00784-018
Figure 24. AD630 Simplified Schematic
AD630 Data Sheet
Rev. F | Page 14 of 20
OTHER GAIN CONFIGURATIONS
Many applications require switched gains other than the ±1 and
±2, which the self-contained applications resistors provide. The
AD630 can be readily programmed with three external resistors
over a wide range of positive and negative gain by selecting and
RB and RF to give the noninverting gain 1 + RF/RB and subse-
quent RA to give the desired inverting gain. Note that when the
inverting magnitude equals the noninverting magnitude, the
value of RA is found to be RBRF/(RB + RF). That is, RA equals
the parallel combination of RB and RF to match positive and
negative gain.
The feedback synthesis of the AD630 may also include reactive
impedance. The gain magnitudes match at all frequencies if the
A impedance is made to equal the parallel combination of the
B and F impedances. The same considerations apply to the
AD630 as to conventional op amp feedback circuits. Virtually
any function that can be realized with simple noninverting L
network feedback can be used with the AD630. A common
arrangement is shown in Figure 25. The low frequency gain of
this circuit is 10. The response has a pole (−3 dB) at a frequency
f 1/(2 π 100 kΩ × C) and a zero (3 dB from the high
frequency asymptote) at about 10 times this frequency. The
2 kΩ resistor in series with each capacitor mitigates the loading
effect on circuitry driving this circuit, eliminates stability
problems, and has a minor effect on the pole-zero locations.
As a result of the reactive feedback, the high frequency
components of the switched input signal are transmitted at
unity gain while the low frequency components are amplified.
This arrangement is useful in demodulators and lock-in
amplifiers. It increases the circuit dynamic range when the
modulation or interference is substantially larger than the
desired signal amplitude. The output signal contains the desired
signal multiplied by the low frequency gain (which may be
several hundred for large feedback ratios) with the switching
signal and interference superimposed at unity gain.
C
–V
S
A
B
10kΩ
V
O
11.11kΩ
12
V
i
100kΩ
2kΩC
2kΩ
2
20
19
18
13
7
8
9
10
SEL B
SEL A
CHANNEL
STATUS
B/A
00784-019
Figure 25. AD630 with External Feedback
SWITCHED INPUT IMPEDANCE
The noninverting mode of operation is a high input impedance
configuration while the inverting mode is a low input imped-
ance configuration. This means that the input impedance of
the circuit undergoes an abrupt change as the gain is switched
under control of the comparator. If the gain is switched when
the input signal is not zero, as it is in many practical cases, a
transient is delivered to the circuitry driving the AD630. In
most applications, this requires the AD630 circuit to be driven
by a low impedance source, which remains stiff at high
frequencies. This is generally a wideband buffer amplifier.
FREQUENCY COMPENSATION
The AD630 combines the convenience of internal frequency
compensation with the flexibility of external compensation by
means of an optional self-contained compensation capacitor.
In gain of ±2 applications, the noise gain that must be addressed
for stability purposes is actually 4. In this circumstance, the
phase margin of the loop is on the order of 60° without the
optional compensation. This condition provides the maximum
bandwidth and slew rate for closed loop gains of |2| and above.
When the AD630 is used as a multiplexer, or in other
configurations where one or both inputs are connected for
unity gain feedback, the phase margin is reduced to less than
20°. This may be acceptable in applications where fast slewing is
a first priority, but the transient response is not optimum. For
these applications, the self-contained compensation capacitor
may be added by connecting Pin 12 to Pin 13. This connection
reduces the closed-loop bandwidth somewhat and improves the
phase margin.
For intermediate conditions, such as a gain of ±1 where the
loop attenuation is 2, determine the use of the compensation
by whether bandwidth or settling response must be optimized.
Also, use optional compensation when the AD630 is driving
capacitive loads or whenever conservative frequency compen-
sation is desired.
Data Sheet AD630
Rev. F | Page 15 of 20
OFFSET VOLTAGE NULLING
The offset voltages of both input stages and the comparator
have been pretrimmed so that external trimming is only
required in the most demanding applications. The offset
adjustment of the two input channels is accomplished by
means of a differential and common-mode scheme. This
facilitates fine adjustment of system errors in switched gain
applications. With the system input tied to 0 V, and a switching
or carrier waveform applied to the comparator, a low level square
wave appears at the output. The differential offset adjustment
potentiometers can be used to null the amplitude of this square
wave (Pin 3 and Pin 4). The common-mode offset adjustment
can be used to zero the residual dc output voltage (Pin 5 and
Pin 6). Implement these functions using 10 kΩ trim potenti-
ometers with wipers connected directly to Pin 8 as shown in
Figure 28 and Figure 29.
CHANNEL STATUS OUTPUT
The channel status output, Pin 7, is an open collector output
referenced to −VS that can be used to indicate which of the two
input channels is active. The output is active (pulled low) when
Channel A is selected. This output can also be used to supply
positive feedback around the comparator. This produces
hysteresis which serves to increase noise immunity. Figure 26
shows an example of how hysteresis may be implemented. Note
that the feedback signal is applied to the inverting (−) terminal
of the comparator to achieve positive feedback. This is because
the open collector channel status output inverts the output
sense of the internal comparator.
1MΩ
100kΩ
100kΩ
–15V
+5V
100Ω
7
8
9
10
00784-020
Figure 26. Comparator Hysteresis
The channel status output may be interfaced with TTL inputs
as shown in Figure 27. This circuit provides appropriate level
shifting from the open-collector AD630 channel status output
to TTL inputs.
–15V
+5V
TTL INPUT
AD630
+15V
IN914s
6.8kΩ
22kΩ
100kΩ
2N2222
7
8
00784-021
Figure 27. Channel Status—TTL Interface
AD630 Data Sheet
Rev. F | Page 16 of 20
APPLICATIONS INFORMATION
BALANCED MODULATOR
Perhaps the most commonly used configuration of the AD630
is the balanced modulator. The application resistors provide
precise symmetric gains of ±1 and ±2. The ±1 arrangement
is shown in Figure 28 and the ±2 arrangement is shown in
Figure 29. These cases differ only in the connection of the
10 kΩ feedback resistor (Pin 14) and the compensation
capacitor (Pin 12). Note the use of the 2.5 kΩ bias current
compensation resistors in these examples. These resistors
perform the identical function in the ±1 gain case. Figure 30
demonstrates the performance of the AD630 when used to
modulate a 100 kHz square wave carrier with a 10 kHz sinusoid.
The result is the double sideband suppressed carrier waveform.
These balanced modulator topologies accept two inputs, a
signal (or modulation) input applied to the amplifying channels
and a reference (or carrier) input applied to the comparator.
MODULATED
OUTPUT
SIGNAL
CARRIER
INPUT
CM
OFF ADJ DIFF
OFF ADJ
AMP A
AMP B
–V
10kΩ 10kΩ
5kΩ
9
10
COMP
1
15
7
16
14
13
12
2
20
+V
S
–V
S
AD630
A
B
2.5kΩ
2.5kΩ
19
18
17
11
8
65
10kΩ
4 3
10kΩ
MODULATION
INPUT
00784-022
Figure 28. AD630 Configured as a Gain-of-One Balanced Modulator
MODULATED
OUTPUT
SIGNAL
CARRIER
INPUT
CM
OF F ADJ DIFF
OF F ADJ
2.5kΩ AM P A
AMP B
–V
10kΩ 10kΩ
5kΩ
9
10
COMP
1
15
7
16
14
13
12
2
20
+V
S
–V
S
AD630
A
B
2.5kΩ
19
18
17
11
8
6 5
10kΩ
4 3
10kΩ
MODULATION
INPUT
00784-023
Figure 29. AD630 Configured as a Gain-of-Two Balanced Modulator
5V 5V 20µs
MODULATION
INPUT
CARRIER
INPUT
OUTPUT
SIGNAL
10V
00784-024
Figure 30. Gain-of-Two Balanced Modulator Sample Waveforms
BALANCED DEMODULATOR
The balanced modulator topology described in the Balanced
Modulator section also acts as a balanced demodulator if a
double sideband suppressed carrier waveform is applied to
the signal input and the carrier signal is applied to the reference
input. The output under these circumstances is the baseband
modulation signal. Higher order carrier components that can
be removed with a low-pass filter are also present. Other names
for this function are synchronous demodulation and phase-
sensitive detection.
PRECISION PHASE COMPARATOR
The balanced modulator topologies of Figure 28 and Figure 29
can also be used as precision phase comparators. In this case,
an ac waveform of a particular frequency is applied to the signal
input and a waveform of the same frequency is applied to the
reference input. The dc level of the output (obtained by low-
pass filtering) is proportional to the signal amplitude and phase
difference between the input signals. If the signal amplitude is
held constant, the output can be used as a direct indication of
the phase. When these input signals are 90° out of phase, they
are said to be in quadrature and the AD630 dc output is zero.
PRECISION RECTIFIER ABSOLUTE VALUE
If the input signal is used as its own reference in the balanced
modulator topologies, the AD630 acts as a precision rectifier.
The high frequency performance is superior to that which can
be achieved with diode feedback and op amps. There are no
diode drops that the op amp must leap over with the commu-
tating amplifier.
Data Sheet AD630
Rev. F | Page 17 of 20
LVDT SIGNAL CONDITIONER
Many transducers function by modulating an ac carrier. A
linear variable differential transformer (LVDT) is a transducer
of this type. The amplitude of the output signal corresponds to
core displacement. Figure 31 shows an accurate synchronous
demodulation system, which can be used to produce a dc
voltage that corresponds to the LVDT core position. The
inherent precision and temperature stability of the AD630
reduce demodulator drift to a second-order effect.
A
B
10kΩ
10kΩ
5kΩ
2.5kΩ
2.5kΩ
C100kΩ D
1µF
AD630
±2 DEMODULATO R
AD544
FOLLOWER
B
PHASE
SHIFTER
A
E1000
SCHAEVITZ
LVDT
2.5kHz
2V p-p
SINUSOIDAL
EXCITATION
16
1
14
17
9
10
20
19 12
13
15
00784-025
Figure 31. LVDT Signal Conditioner
AC BRIDGE
Bridge circuits that use dc excitation are often plagued by
errors caused by thermocouple effects, 1/f noise, dc drifts in the
electronics, and line noise pick-up. One way to get around these
problems is to excite the bridge with an ac waveform, amplify
the bridge output with an ac amplifier, and synchronously
demodulate the resulting signal. The ac phase and amplitude
information from the bridge is recovered as a dc signal at the
output of the synchronous demodulator. The low frequency
system noise, dc drifts, and demodulator noise all get mixed to
the carrier frequency and can be removed by means of a low-
pass filter. Dynamic response of the bridge must be traded
off against the amount of attenuation required to adequately
suppress these residual carrier components in the selection
of the filter.
Figure 33 is an example of an ac bridge system with the AD630
used as a synchronous demodulator. The bridge is excited by
a 1 V 400 Hz excitation. Trace A in Figure 32 is the amplified
bridge signal. Trace B is the output of the synchronous
demodulator and Trace C is the filtered dc system output.
500µs/DIV
B. 200mV/DIV
C. 200mV/DIV
3
[ T ]
T
A. 200mV/DIV
00784-027
Figure 32. AC Bridge Waveforms (1 V Excitation)
AD8221
REF
+IN
–IN
49.9Ω
350Ω
350Ω 350Ω
350Ω
CH B–
SEL B
CH A–
SEL A
R
A
R
F
R
IN
A
R
IN
B
–V
S
+15V
V
OUT
+V
S
COMP
AD630AR
12
13
1 8
R
B
1410
17
16
15
19
20
911
–15V
4.99kΩ 4.99kΩ 4.99kΩ
2µF 2µF 2µF
A
CB
1V
400Hz
00784-026
Figure 33. AC Bridge System
AD630 Data Sheet
Rev. F | Page 18 of 20
LOCK-IN AMPLIFIER APPLICATIONS
Lock-in amplification is a technique used to separate a small,
narrow-band signal from interfering noise. The lock-in
amplifier acts as a detector and narrow-band filter combined.
Very small signals can be detected in the presence of large
amounts of uncorrelated noise when the frequency and phase
of the desired signal are known.
The lock-in amplifier is basically a synchronous demodulator
followed by a low-pass filter. An important measure of per-
formance in a lock-in amplifier is the dynamic range of its
demodulator. The schematic diagram of a demonstration circuit
which exhibits the dynamic range of an AD630 as it might be
used in a lock-in amplifier is shown in Figure 35. Figure 34 is
an oscilloscope photo demonstrating the large dynamic range
of the AD630. The photo shows the recovery of a signal modu-
lated at 400 Hz from a noise signal approximately 100,000 times
larger.
100
90
10
5V 5V 5s
5mV
MODULATED SIGNAL (A)
(UNATTENUATED)
ATTENUATED SIGNAL
PLUS NOISE (B)
OUTPUT
0%
00784-029
Figure 34. Lock-In Amplifier Waveforms
The test signal is produced by modulating a 400 Hz carrier
with a 0.1 Hz sine wave. The signals produced, for example,
by chopped radiation (that is, IR, optical) detectors may have
similar low frequency components. A sinusoidal modulation
is used for clarity of illustration. This signal is produced by a
circuit similar to Figure 28 and is shown in the upper trace of
Figure 34. It is attenuated 100,000 times normalized to the
output, B, of the summing amplifier. A noise signal that might
represent, for example, background and detector noise in the
chopped radiation case, is added to the modulated signal by the
summing amplifier. This signal is simply band limited, clipped
white noise. Figure 34 shows the sum of attenuated signal plus
noise in the center trace. This combined signal is demodulated
synchronously using phase information derived from the
modulator, and the result is low-pass filtered using a 2-pole
simple filter which also provides a gain of 100 to the output.
This recovered signal is the lower trace of Figure 34.
The combined modulated signal and interfering noise used for
this illustration is similar to the signals often requiring a lock-in
amplifier for detection. The precision input performance of the
AD630 provides more than 100 dB of signal range and its
dynamic response permits it to be used with carrier frequencies
more than two orders of magnitude higher than in this example.
A more sophisticated low-pass output filter aids in rejecting
wider bandwidth interference.
A
B
10kΩ
100R
COUTPUT
LOW-PASS
FILTER
A
B
C
R
100R
AD630
10kΩ
5kΩ
2.5kΩ
2.5kΩ
20
19
17
1
16
AD542
13
AD542
14
10
9
CLIPPED
BAND LIMITED
WHITE NOISE
100dB
ATTENUATION
0.1Hz
MODULATED
400Hz
CARRIER
CARRIER
PHASE
REFERENCE
15
00784-028
Figure 35. Lock-In Amplifier
Data Sheet AD630
Rev. F | Page 19 of 20
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
20
110
11
0.300 (7.62)
0.280 (7.11)
PIN 1
0.080 (2.03) MAX
0.005 (0.13) MIN
SEATING
PLANE
0.023 (0.58)
0.014 (0.36)
0.060 (1.52)
0.015 (0.38)
0.200 (5.08)
MAX
0.200 (5.08)
0.125 (3.18) 0.070 (1.78)
0.030 (0.76)
0.100
(2.54)
BSC
0.150
(3.81)
MIN
0.320 (8.13)
0.300 (7.62)
0.015 (0.38)
0.008 (0.20)
1.060 (28.92)
0.990 (25.15)
Figure 36. 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
(D-20)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE RO UNDE D- OF F INCH E QUIVALENTS FOR
REF ERE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CO NFI GURED AS WHO LE OR HALF L E ADS .
COMPLIANT TO JE DE C S TANDARDS MS- 001
070706-A
0.022 ( 0.56)
0.018 ( 0.46)
0.014 ( 0.36)
0.150 ( 3.81)
0.130 ( 3.30)
0.115 (2.92)
0.070 ( 1.78)
0.060 ( 1.52)
0.045 ( 1.14)
20
110
11
0.100 ( 2.54)
BSC
1.060 ( 26.92)
1.030 ( 26.16)
0.980 ( 24.89)
0.210 ( 5.33)
MAX
SEATING
PLANE
0.015
(0.38)
MIN
0.005 ( 0.13)
MIN
0.280 ( 7.11)
0.250 ( 6.35)
0.240 ( 6.10)
0.060 ( 1.52)
MAX
0.430 ( 10.92)
MAX
0.014 ( 0.36)
0.010 ( 0.25)
0.008 ( 0.20)
0.325 ( 8.26)
0.310 ( 7.87)
0.300 ( 7.62)
0.015 ( 0.38)
GAUGE
PLANE
0.195 ( 4.95)
0.130 ( 3.30)
0.115 (2.92)
Figure 37. 20-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
(N-20)
Dimensions shown in inches and (millimeters)
AD630 Data Sheet
Rev. F | Page 20 of 20
CONTROLLING DIMENSIONSARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE RO UNDE D- OF F INCH E QUIVALENTS FOR
REF ERE NCE ON LY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 ( 0.71)
0.022 ( 0.56)
45° TYP
0.015 ( 0.38)
MIN
0.055 ( 1.40)
0.045 ( 1.14)
0.050 ( 1.27)
BSC
0.075 ( 1.91)
REF
0.011 ( 0.28)
0.007 ( 0.18)
R TYP
0.095 ( 2.41)
0.075 ( 1.90)
0.100 ( 2.54) REF
0.200 ( 5.08)
REF
0.150 ( 3.81)
BSC
0.075 ( 1.91)
REF
0.358 ( 9.09)
0.342 ( 8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 ( 2.54)
0.064 ( 1.63)
0.088 ( 2.24)
0.054 ( 1.37)
022106-A
Figure 38. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
(E-20-1)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-013-AC
13.00 (0.5118)
12.60 (0.4961)
0.30 (0.0118)
0.10 (0.0039)
2.65 (0.1043)
2.35 (0.0925)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
0.75 (0.0295)
0.25 (0.0098)
45°
1.27 (0.0500)
0.40 (0.0157)
COPLANARITY
0.10 0.33 (0.0130)
0.20 (0.0079)
0.51 (0.0201)
0.31 (0.0122)
SEATING
PLANE
8°
0°
20 11
10
1
1.27
(0.0500)
BSC
06-07-2006-A
Figure 39. 20-Lead Standard Small Outline Package [SOIC_W]
Wide Body
(RW-20)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD630JNZ 0°C to 70°C 20-Lead Plastic Dual In-Line Package [PDIP] N-20
AD630KNZ 0°C to 70°C 20-Lead Plastic Dual In-Line Package [PDIP] N-20
AD630ARZ −25°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W] RW-20
AD630ARZ-RL −25°C to +85°C 20-Lead Standard Small Outline Package [SOIC_W], 13" Tape and Reel RW-20
AD630ADZ −25°C to +85°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20
AD630BDZ −25C to +85°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20
AD630SD −55°C to +125°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20
AD630SD/883B −55°C to +125°C 20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP] D-20
5962-8980701RA
−55°C to +125°C
20-Lead Side-Brazed Ceramic Dual In-Line Package [SBDIP]
D-20
AD630SE/883B −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
5962-89807012A −55°C to +125°C 20-Terminal Ceramic Leadless Chip Carrier [LCC] E-20-1
AD630SCHIPS −55°C to +125°C Chip
1 Z = RoHS Compliant Part.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D00784-0-7/15(F)
