NC7WZ00K8X - FAIRCHILD SEMICONDUCTOR

®

NC7WZ00 Rev. 1.11.0

March 2008

NC7WZ00

TinyLogic

®

UHS Dual 2-Input NAND Gate

Features

■

Space saving US8 surface mount package

■

MicroPak™ leadless package

■

Ultra High Speed; t

PD

2.4ns typ. into 50pF at 5V V

CC

■

High Output Drive; ±24mA at 3V V

CC

■

Broad V

CC

Operating Range; 1.65V–5.5V

■

Matches the performance of LCX when operated at

3.3V V

CC

■

Power down high impedance inputs/output

■

Overvoltage tolerant inputs facilitate 5V to 3V

translation

■

General Description

The NC7WZ00 is a dual 2-Input NAND Gate from

Fairchild's Ultra High Speed Series of TinyLogic



. The

device is fabricated with advanced CMOS technology to

achieve ultra high speed with high output drive while

maintaining low static power dissipation over a broad

V

CC

operating range. The device is specified to operate

over the 1.65V to 5.5V V

CC

operating range. The inputs

and output are high impedance when V

CC

is 0V. Inputs

tolerate voltages up to 7V independent of V

CC

operating

voltage.

Ordering Information

Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.

All packages are lead free per JEDEC: J-STD-020B standard.

Order

Number

Package

Number

Product Code

Top Mark Package Description Supplied As

NC7WZ00K8X MAB08A WZ00 8-Lead US8, JEDEC MO-187,

Variation CA 3.1mm Wide

3k Units on Tape and

Reel

NC7WZ00L8X MAC08A N6 8-Lead MicroPak, 1.6 mm Wide 5k Units on Tape and

Reel

Proprietary noise/EMI reduction circuitry implemented

NC7WZ00 — TinyLogic UHS Dual 2-Input NAND Gate

NC7WZ00 Rev. 1.11.0 2

NC7WZ00 — TinyLogic

®

UHS Dual 2-Input NAND Gate

Connection Diagram

(Top View)

Pin One Orientation Diagram

AAA represents Product Code Top Mark – see

ordering code

Note:

Orientation of Top Mark determines Pin One

location. Read the top product code mark left to right, Pin

One is the lower left pin (see diagram).

Pad Assignments for MicroPak

(Top Thru View)

Pin Description

Logic Symbol

IEEE/IEC

Function Table

Y

=

AB

H

=

HIGH Logic Level

L

=

LOW Logic Level

Pin Names Description

A

n

, B

n

Inputs

Y

n

Output

Inputs Output

AB Y

LL H

LH H

HL H

HH L

NC7WZ00 Rev. 1.11.0 3

NC7WZ00 — TinyLogic

®

UHS Dual 2-Input NAND Gate

Absolute Maximum Ratings

Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be

operable above the recommended operating conditions and stressing the parts to these levels is not recommended.

In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.

The absolute maximum ratings are stress ratings only.

Recommended Operating Conditions

(1)

The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended

operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not

recommend exceeding them or designing to absolute maximum ratings.

Note:

1. Unused inputs must be held HIGH or LOW. They may not float.

Symbol Parameter Rating

V

CC

Supply Voltage –0.5V to +7V

V

IN

DC Input Voltage –0.5V to +7V

V

OUT

DC Output Voltage –0.5V to +7V

I

IK

DC Input Diode Current @ V

IN

<

–0.5V –50mA

I

OK

DC Output Diode Current @ V

OUT

<

–0.5V –50mA

I

OUT

DC Output Current ±50mA

I

CC

/I

GND

DC V

CC

/GND Current ±100mA

T

STG

Storage Temperature –65°C to +150°C

T

J

Junction Temperature Under Bias 150°C

T

L

Junction Lead Temperature (Soldering, 10 seconds) 260°C

P

D

Power Dissipation @ +85°C 250mW

Symbol Parameter Rating

V

CC

Supply Voltage Operating 1.65V to 5.5V

Supply Voltage Data Retention 1.5V to 5.5V

V

IN

Input Voltage 0V to 5.5V

V

OUT

Output Voltage 0V to V

CC

T

A

Operating Temperature –40°C to +85°C

t

r

, t

f

Input Rise and Fall Time

V

CC

=

1.65V ± 0.15V, 2.5V ± 0.2V 0ns/V to 20ns/V

V

CC

=

3.3V ±0.3V 0ns/V to 10ns/V

V

CC

=

5.0V ±0.5V 0ns/V to 5ns/V

θ

JA

Thermal Resistance 250°C/W

NC7WZ00 Rev. 1.11.0 4

NC7WZ00 — TinyLogic

®

UHS Dual 2-Input NAND Gate

DC Electrical Characteristics

Symbol Parameter V

CC

(V) Conditions

T

A

=

25°C

T

A

=

–40°C

to +85°C

UnitsMin. Typ. Max. Min. Max.

V

IH

HIGH Level

Input Voltage

1.65–1.95 0.75 x V

CC

0.75 x V

CC

V

2.3–5.5 0.70 x V

CC

0.70 x V

CC

V

IL

LOW Level

Input Voltage

1.65–1.95 0.25 x V

CC

0.25 x V

CC

V

2.3–5.5 0.30 x V

CC

0.30 x V

CC

V

OH

HIGH Level

Output Voltage

1.65 V

IN

=

V

IL

I

OH

=

–100µA 1.55 1.65 1.55 V

2.3 2.2 2.3 2.2

3.0 2.9 3.0 2.9

4.5 4.4 4.5 4.4

1.65 I

OH

=

–4mA 1.29 1.52 1.69

2.3 I

OH

=

–8mA 1.9 2.15 1.9

3.0 I

OH

=

–16mA 2.4 2.80 2.4

3.0 I

OH

=

–24mA 2.3 2.68 2.3

4.5 I

OH

=

–32mA 3.8 4.20 3.8

V

OL

LOW Level

Output Voltage

1.65 V

IN

=

V

IH

I

OL

=

100µA 0.0 0.1 0.1 V

2.3 0.0 0.1 0.1

3.0 0.0 0.1 0.1

4.5 0.0 0.1 0.1

1.65 I

OL

=

4mA 0.08 0.24 0.24

2.3 I

OL

=

8mA 0.10 0.3 0.3

3.0 I

OL

=

16mA 0.15 0.4 0.4

3.0 I

OL

=

24mA 0.22 0.55 0.55

4.5 I

OL

=

32mA 0.22 0.55 0.55

I

IN

Input Leakage

Current

0–5.5 V

IN

=

5.5V, GND ±0.1 ±1 µA

I

OFF

Power Off

Leakage

Current

0.0 V

IN

or V

OUT

= 5.5V 1 10 µA

ICC Quiescent

Supply Current

1.65–5.5 VIN = 5.5V, GND 1 10 µA

NC7WZ00 Rev. 1.11.0 5

NC7WZ00 — TinyLogic® UHS Dual 2-Input NAND Gate

AC Electrical Characteristics

Note:

2. CPD is defined as the value of the internal equivalent capacitance which is derived from dynamic operating current

consumption (ICCD) at no output loading and operating at 50% duty cycle. (See Figure 2.) CPD is related to ICCD

dynamic operating current by the expression: ICCD = (CPD)(VCC)(fIN) +(ICCstatic).

AC Loading and Waveforms

CL includes load and stray capacitance

Input PRR = 1.0 MHz; tw = 500ns

Figure 1. AC Test Circuit

Input = AC Waveform; tr = tf = 1.8ns;

PRR = 10 MHz; Duty Cycle = 50%

Figure 2. ICCD Test Circuit

Figure 3. AC Waveforms

Symbol Parameter VCC (V) Conditions

TA = +25°C

TA = –40°C

to +85°C

Units

Figure

NumberMin. Typ. Max. Min. Max.

tPLH, tPHL Propagation Delay 1.8 ± 0.15 CL = 15pF,

RL = 1MΩ

2.0 5.3 9.6 2.0 9.8 ns Figure 1

Figure 3

2.5 ± 0.2 1.2 3.2 5.3 1.2 5.7

3.3 ± 0.3 0.8 2.4 3.7 0.8 4.0

5.0 ± 0.5 0.5 1.9 2.9 0.5 3.2

tPLH, tPHL Propagation Delay 3.3 ± 0.3 CL = 50pF,

RL = 500Ω

1.2 3.0 4.6 1.2 4.9 ns Figure 1

Figure 3

5.0 ± 0.5 0.8 2.4 3.6 0.8 3.9

CIN Input Capacitance 0 2.5 pF

CPD Power Dissipation

Capacitance

3.3 (2) 13 pF Figure 2

5.0 17

NC7WZ00 Rev. 1.11.0 6

NC7WZ00 — TinyLogic® UHS Dual 2-Input NAND Gate

Tape and Reel Specifications

Tape Format for US8

Tape Dimensions inches (millimeters)

Tape Format for MicroPak

Tape Dimensions inches (millimeters)

Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status

K8X Leader (Start End) 125 (typ.) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ.) Empty Sealed

Package Designator Tape Section Number of Cavities Cavity Status Cover Tape Status

L8X Leader (Start End) 125 (typ.) Empty Sealed

Carrier 3000 Filled Sealed

Trailer (Hub End) 75 (typ.) Empty Sealed

NC7WZ00 Rev. 1.11.0 7

NC7WZ00 — TinyLogic® UHS Dual 2-Input NAND Gate

Tape and Reel Specifications (Continued)

Reel Dimensions inches (millimeters)

Tape

Size ABCDN W1 W2 W3

8mm 7.0

(177.8)

0.059

(1.50)

0.512

(13.00)

0.795

(20.20)

2.165

(55.00)

0.331 +0.059/–0.000

(8.40 +1.50/–0.00)

0.567

(14.40)

W1 +0.078/–0.039

(W1 +2.00/–1.00)

NC7WZ00 Rev. 1.11.0 8

NC7WZ00 — TinyLogic® UHS Dual 2-Input NAND Gate

Physical Dimensions

Figure 4. 8-Lead US8, JEDEC MO-187, Variation CA 3.1mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

0.30 TYP

SEATING PLANE

0.10-0.18

0.13 A B C

C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH,

D. DIMENSIONS AND TOLERANCES PER ANSI Y14.5M, 1982.

AND TIE BAR EXTRUSIONS.

MAB08AREVC

0.50TYP

B. DIMENSIONS ARE IN MILLIMETERS.

A. CONFORMS TO JEDEC REGISTRATION MO-187

-C-

0.17-0.27

0.10

0.00

DETAIL A

0°-8°

0.4 TYP

-B-

0.70±0.10

ALL LEAD TIPS

0.2 C B A

3.1±.1

0.15

PIN #1 IDENT.

0.90 MAX

ALL LEAD TIPS

0.1 C

1.55

8

14

2.3±0.1

5

-A-

0.70

2.70

3.40

1.00

0.5 TYP

DETAIL A

1.80

GAGE PLANE

0.12

NC7WZ00 Rev. 1.11.0 9

NC7WZ00 — TinyLogic® UHS Dual 2-Input NAND Gate

Physical Dimensions (Continued)

Figure 5. 8-Lead MicroPak, 1.6 mm Wide

Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner

without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or

obtain the most recent revision. Package speciﬁcations do not expand the terms of Fairchild’s worldwide terms and conditions,

speciﬁcally the warranty therein, which covers Fairchild products.

Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:

http://www.fairchildsemi.com/packaging/

NC7WZ00 Rev. 1.11.0 10

TRADEMARKS

Thefollowing includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global

subsidiaries, and is not intended to be an exhaustive list of all such trademarks.

ACEx®

Build it Now™

CorePLUS™

CROSSVOLT™

CTL™

Current Transfer Logic™

EcoSPARK®

EZSWITCH™ *

™

®

Fairchild®

Fairchild Semiconductor®

FACT Quiet Series™

FACT®

FAST®

FastvCore™

FlashWriter®*

FPS™

FRFET®

Global Power ResourceSM

Green FPS™

Green FPS™e-Series™

GTO™

i-Lo™

IntelliMAX™

ISOPLANAR™

MegaBuck™

MICROCOUPLER™

MicroFET™

MicroPak™

MillerDrive™

Motion-SPM™

OPTOLOGIC®

OPTOPLANAR®

®

PDP-SPM™

Power220®

POWEREDGE®

Power-SPM™

PowerTrench®

Programmable Active Droop™

QFET®

QS™

QT Optoelectronics™

Quiet Series™

RapidConfigure™

SMART START™

SPM®

STEALTH™

SuperFET™

SuperSOT™-3

SuperSOT™-6

SuperSOT™-8

SupreMOS™

SyncFET™®

The Power Franchise®

TinyBoost™

TinyBuck™

TinyLogic®

TINYOPTO™

TinyPower™

TinyPWM™

TinyWire™

µSerDes™

UHC®

Ultra FRFET™

UniFET™

VCX™

*EZSWITCH™ and FlashWriter®are trademarks of System General Corporation, used under license by Fairchild Semiconductor.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS

HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE

APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS

PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S

WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.

As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body or

(b) support or sustain life, and (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in a significant injury of the user.

2. A critical component in any component of a life support,

device, or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In Design This datasheet contains the design specifications for product

development. Specifications may change in any manner without notice.

Preliminary First Production

This datasheet contains preliminary data; supplementary data will be

published at a later date. Fairchild Semiconductor reserves the right to

make changes at any time without notice to improve design.

No Identification Needed Full Production

This datasheet contains final specifications. Fairchild Semiconductor

reserves the right to make changes at any time without notice to improve

the design.

Obsolete Not In Production

This datasheet contains specifications on a product that has been

discontinued by Fairchild Semiconductor. The datasheet is printed for

reference information only.

Rev. I33

NC7WZ00 — TinyLogic® UHS Dual 2-Input NAND Gate