REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED D Added two device types with access times of 25 ns and 20 ns for vendor CAGE 1FN41. Added low power version. Added F-16 package. Editorial changes throughout. Source for 01, 02, and 06 devices no longer available. Added devices 08-12. Added 28 J leaded chip carrier package. Updated boilerplate, editorial changes throughout. Updated to new boilerplate format. Added new footnote to ICC1 in table I, renumbered the rest of footnotes. Added additional conditions to ICC1 conditions block. Changed the max limit for devices 11 and 12 for ICC2 from 5 mA to 15 mA. Made changes to table I for device type 08; tSS, fMAXS, and tSFS.. Updated boilerplate, editorial changes throughout. ksr E Boilerplate update, part of 5 year review. ksr 07-06-22 Robert M. Heber F Made changes to "Margin test method" in paragraph 4.2c, added footnote 7/ to Table I for parameter "Clock to feedback", and changed the maximum capacitance in Table I; CI from 8 to 20 pF and CO from 8 to 15 pF. ksr 10-03-17 Charles F. Saffle A B C 92-04-21 M. A. Frye 94-10-21 M. A. Frye 00-02-22 Raymond Monnin 02-09-06 Raymond Monnin REV SHEET REV F F F F F F F F SHEET 15 16 17 18 19 20 21 22 REV STATUS REV F F F F F F F F F F F F F F OF SHEETS SHEET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PMIC N/A PREPARED BY Kenneth Rice STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 CHECKED BY http://www.dscc.dla.mil Ray Monnin APPROVED BY Michael A. Frye DRAWING APPROVAL DATE 88 - 09 - 16 REVISION LEVEL F MICROCIRCUIT, MEMORY, DIGITAL, CMOS, ULTRAVIOLET ERASABLE, PROGRAMMABLE LOGIC ARRAY, MONOLITHIC SILICON SIZE A SHEET DSCC FORM 2233 APR 97 . CAGE CODE 5962-88726 67268 1 OF 22 5962-E213-10 1. SCOPE 1.1 Scope. This drawing describes device requirements for MIL-STD-883 compliant, non-JAN class level B microcircuits in accordance with MIL-PRF-38535, appendix A. 1.2 Part or Identifying Number (PIN). The complete PIN is as shown in the following example: 5962-88726 Drawing number 01 Device type (see 1.2.1) L Case outline (see 1.2.2) A ____ Lead finish (see 1.2.3) 1.2.1 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 Generic number V750 02 V750 03 V750 04 V750 06 V750L 07 V750L 08 V750B 09 V750B 10 V750B 11 V750BL 12 V750BL Circuit function 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array 22-input 10-output and-or-logic array Address access time 40 ns 35 ns 25 ns 20 ns 35 ns 25 ns 10 ns 15 ns 25 ns 15 ns 25 ns 1.2.2 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter L 3 X Y Descriptive designator GDIP3-T24 CQCC1-N28 GDFP1-F24 CQCC1-J28 Terminals 24 28 24 28 Package style dual-in-line package 1/ square chip carrier 1/ flat pack package 1/ J leaded chip carrier 1/ 1.2.3 Lead finish. The lead finish is as specified in MIL-PRF-38535, appendix A. ____________________ 1/ Lid shall be transparent to permit ultraviolet light erasure. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 2 1.3 Absolute maximum ratings. 2/ Supply voltage range ................................................................ -0.5 V dc to +7.0 V dc Input voltage range ................................................................... -2.0 V dc to +7.0 V dc 3/ Output voltage applied .............................................................. -0.5 V dc to +7.0 V dc 3/ Output sink current ................................................................... 16 mA Thermal resistance, junction-to-case (JC) ................................ See MIL-STD-1835 Maximum power dissipation (PD) 4/ ........................................ 1.2 W Maximum junction temperature ................................................ +175C Lead temperature (soldering, 10 seconds maximum) ............... +300C 1.4 Recommended operating conditions. Supply voltage (VCC) ................................................................. 4.5 V dc to 5.5 V dc High level input voltage (VIH) .................................................... 2.0 V dc minimum Low level input voltage (VIL) ...................................................... 0.8 V dc maximum 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATION MIL-PRF-38535 - Integrated Circuits, Manufacturing, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 MIL-STD-1835 - Test Method Standard Microcircuits. Interface Standard Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 MIL-HDBK-780 - List of Standard Microcircuit Drawings. Standard Microcircuit Drawings. (Copies of these documents are available online at https://assist.daps.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item requirements shall be in accordance with MIL-PRF-38535, appendix A for nonJAN class level B devices and as specified herein. Product built to this drawing that is produced by a Qualified Manufacturer Listing (QML) certified and qualified manufacturer or a manufacturer who has been granted transitional certification to MILPRF-38535 may be processed as QML product in accordance with the manufacturers approved program plan and qualifying activity approval in accordance with MIL-PRF-38535. This QML flow as documented in the Quality Management (QM) plan may make modifications to the requirements herein. These modifications shall not affect form, fit, or function of the device. These modifications shall not affect the PIN as described herein. A "Q" or "QML" certification mark in accordance with MILPRF-38535 is required to identify when the QML flow option is used. ______________________ 2/ All voltages referenced to VSS. 3/ Minimum voltage is -0.6 V dc which may undershoot to -2.0 V dc for pulses of less than 20 ns. Maximum output pin voltage is VCC +0.75 V dc which may overshoot to +7.0 V dc for pulses of less than 20 ns. 4/ Must withstand the added PD due to short circuit test, e.g., IOS. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 3 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38535, appendix A and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.2 herein. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 1. 3.2.3 Truth table(s). The truth table(s) shall be as specified on figure 2. 3.2.3.1 Unprogrammed devices. The truth table for unprogrammed devices for contracts involving no altered item drawing shall be as specified on figure 2. When required in group A, B, or C inspections (see 4.3), the device shall be programmed by the manufacturer prior to test with a minimum of 50 percent of the total number of gates programmed or to any altered item drawing pattern which includes at least 25 percent of the total number of gates programmed. 3.2.3.2 Programmed devices. The requirements for supplying programmed devices are not part of this drawing. 3.2.4 Logic diagram. The logic diagram shall be as specified on figure 3. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table I and shall apply over the full case operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are described in table I. 3.5 Marking. Marking shall be in accordance with MIL-PRF-38535, appendix A. The part shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's PIN may also be marked. For packages where marking of the entire SMD PIN number is not feasible due to space limitations, the manufacturer has the option of not marking the "5962-" on the device. 3.5.1 Certification/compliance mark. A compliance indicator "C" shall be marked on all non-JAN devices built in compliance to MIL-PRF-38535, appendix A. The compliance indicator "C" shall be replaced with a "Q" or "QML" certification mark in accordance with MIL-PRF-38535 to identify when the QML flow option is used. 3.6 Processing EPLDS. All testing requirements and quality assurance provisions herein shall be satisfied by the manufacturer prior to delivery. 3.6.1 Erasure of EPLDS. When specified, devices shall be erased in accordance with the procedures and characteristics specified in 4.4. 3.6.2 Programmability of EPLDS. When specified, devices shall be programmed to the specified pattern using the procedures and characteristics specified in 4.5 and table III. 3.6.3 Verification of erasure of programmability of EPLDS. When specified, devices shall be verified as either programmed to the specified pattern or erased. As a minimum, verification shall consist of performing a functional test (subgroup 7) to verify that all bits are in the proper state. Any bit that does not verify to be in the proper state shall constitute a device failure, and shall be removed from the lot. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to be listed as an approved source of supply in MIL-HDBK-103 (see 6.6 herein). The certificate of compliance submitted to DSCC-VA prior to listing as an approved source of supply shall affirm that the manufacturer's product meets the requirements of MIL-PRF-38535, appendix A and the requirements herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38535, appendix A shall be provided with each lot of microcircuits delivered to this drawing. 3.9 Notification of change. Notification of change to DSCC-VA shall be required for any change that affects this drawing. 3.10 Verification and review. DSCC, DSCC's agent, and the acquiring activity retain the option to review the manufacturer's facility and applicable required documentation. Offshore documentation shall be made available onshore at the option of the reviewer. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 4 TABLE I. Electrical performance characteristics Test Symbol Conditions 1/ 4.5 V VCC 5.5 V -55C TC +125C Unless otherwise specified Group A Subgroups Device types Limits Min High level output voltage VOH IO = - 4.0 mA 1,2,3 All Low level output voltage VOL IO = 8.0 mA 1,2,3 01-04, 06, 07 IO = 12 mA Unit Max 2.4 V 0.5 V 10 uA uA 08-12 High impedance 2/ output leakage current IOZ VCC = 5.5 V, VO = 5.5 V, VO = GND 1,2,3 All High level input current IIH VIH = 5.5 V 1,2,3 All 10 VIH = 2.4 V 1,2,3 All 10 Low level input current IIL VIH = 0.4 V 1,2,3 All -10 VIH = GND 1,2,3 All -10 Operating supply current ICC1 VCC = 5.5 V, f = 1MHz, Outputs open, VIN = VCC or GND 3/ 1,2,3 01-04, 06, 07 140 08-12 190 VCC = 5.5 V, VIN = GND, outputs open 1,2,3 01-04 140 08-10 190 06, 07 15 11,12 15 Standby supply current ICC2 IOS VCC = 5.5 V Input capacitance CI 5/ 6/ Output capacitance CO 5/ 6/ Output short circuit current 4/ Functional tests 1,2,3 All VI = 0 V, VCC = 5.0 V, TA = 25C, f = 1 MHz (see 4.3.1c) 4 VO = 0 V, VCC = 5.0 V, TA = 25C, f = 1 MHz (see 4.3.1c) 4 see note 4 of table II -10 -30 uA mA mA 120 mA All 20 pF All 15 pF 7, 8A, 8B See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 5 TABLE I. Electrical performance characteristics - Continued. Test Input or feedback to nonregistered output Clock to output Input to output enable Input to output disable Symbol tPD tCO tEA Conditions 1/ 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified VCC = 4.5 V, CL = 50 pF, see figures 4 and 5 VCC = 4.5 V , CL = 50 pF, see figures 4 and 5 VCC = 4.5 V , CL = 5 pF, see figures 4 and 5 tER Group A subgroups Device Limits Min 9, 10, 11 9, 10, 11 9, 10, 11 9, 10, 11 Unit Max 01 40 02 35 06 30 03, 07, 10, 12 25 04 20 08 10 09, 11 15 01 35 02,06 30 03,07 10,12 22 04 20 09,11 14 08 10 01 40 02,06 35 03,07, 10,12 25 04 20 09,11 15 08 10 01 40 02,06 35 03,07, 10,12 25 04 20 09,11 15 08 10 ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 6 TABLE I. Electrical performance characteristics - Continued. Test Symbol Conditions 1/ 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Min Clock period tP Clock pulse width 5/ 6/ tCL Clock to feedback VCC = 4.5 V , CL = 5 pF, see figures 4 and 5 VCC = 4.5 V , CL = 50 pF, see figures 4 and 5 tCF 9, 10, 11 9, 10, 11 9, 10, 11 7/ Input setup time 6/ 5/ tS VCC = 4.5 V , CL = 50 pF, see figures 4 and 5 9, 10, 11 01 35 02,06 30 03,07 22 04 18 10,12 17 09,11 14 08 11 01 17 02,06 15 03,07 10 10,12 8.5 04 8 09,11 7 08 5.5 01 15 02,06 12 03, 04,07, 10,12 10 09,11 9 08 7.5 01 20 02,06 18 03,07, 10,12 12 04,11 10 09 8 08 4 Unit Max ns ns ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 7 TABLE I. Electrical performance characteristics - Continued. Conditions Test Symbol 1/ 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups Device type Limits Min Hold time 5/ 6/ Maximum clock frequency 5/ 6/ Asynchronous reset pulse width Asynchronous reset recovery time tH VCC = 4.5 V , CL = 50 pF, see figures 4 and 5 9, 10, 11 fMAX 9, 10, 11 9, 10, 11 tAW 9, 10, 11 tAR 01 15 02,06 10 03,07, 09,10 5 11,12 7 08 2 01 28 02,06 33 11 41 03,07,09 45 04 55 10,12 29 08 71 01 40 02,06 35 03,07, 10,12 20 04,09,11 15 08 10 01 40 02,06 35 03,07, 10,12 20 04,09,11 15 08 10 Unit Max ns MHz ns ns See footnotes at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 8 TABLE I. Electrical performance characteristics - Continued. Conditions 1/ Test Feedback setup time Asynchronous reset to registered output reset Clock period, input pin clock Clock pulse width, input pin clock Clock to feedback, input pin clock Input setup time, input pin clock Symbol tSF 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups VCC = 4.5 V , CL = 50 pF, see figures 4 and 5 9, 10, 11 Device type Limits Min 9, 10, 11 tAP tPS 9, 10, 11 fWS 9, 10, 11 tCFS 9, 10, 11 tSS 9, 10, 11 01,02 18 06 15 03,07 09,10, 11,12 7 04 5 08 4 Unit Max ns 01 40 02,06 35 03,07, 10,12 25 04 20 09,11 15 08 12 08 10 09,11 12 10,12 16 08 5 09,11 6 10,12 8 08 ns ns 5 09,11 5.5 10,12 7 08 6.5 09 8 10 9 11 10 12 12 ns ns ns See footnote at end of table. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 9 TABLE I. Electrical performance characteristics - Continued. Conditions 1/ Test Symbol Hold time, input pin clock tHS Maximum clock frequency, input pin clock fMAXS Asynchronous reset recovery time, input pin clock Clock to output, input pin clock Setup time, synchronous preset product term clock Feedback setup time, input pin clock Setup time, synchronous preset, input pin clock 4.5 V VCC 5.5 V -55C TC +125C unless otherwise specified Group A subgroups VCC = 4.5 V , CL = 50 pF, see figures 4 and 5 9, 10, 11 08-12 9, 10, 11 08 74 09 58 10 41 11 52 12 37 Device type Limits Min tARS 9, 10, 11 9, 10, 11 tCOS 9, 10, 11 tSP tSFS 9, 10, 11 tSPS 9, 10, 11 Unit Max 0 ns 08 10 09,11 15 10,12 25 08 0 7 09,11 0 9 10,12 0 15 04 12 01,02 18 08 7 09,11 8 03,06, 07,10,12 15 08 6.5 09,11 7 10,12 9 08 5 09,11 11 10,12 15 MHz ns ns ns ns ns 1/ All voltages are referenced to ground. 2/ I/O terminal leakage is the worst case of IIX or IOZ. 3/ Icc for typical functional pattern 3mA/MHz for devices 06&07, 5mA/MHz for devices 10-12, worst case based on initial characterization. 4/ Only one output shorted at a time. 5/ Tested only initially and after any design changes. 6/ Test applies only to register outputs. 7/ Values guaranteed by design and are not tested. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 10 Device types 01-04, 06-12 Case outlines L, X Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 3, Y Terminal symbol CK/I I I I I I I I I I I GND I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O VCC --------- NC CK/I I I I I I NC I I I I I GND NC I I/O I/O I/O I/O I/O NC I/O I/O I/O I/O I/O VCC FIGURE 1. Terminal connections. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 11 Truth table Input pins Output pins I I I I I I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O X X X X X X X X X X X X Z Z Z Z Z Z Z Z Z Z NOTES: 1. Z = three-state. 2. X = don't care. FIGURE 2. Truth table. (Unprogrammed) STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 12 S2 S1 S0 Output configuration 0 0 0 Active low, combined terms, registered 0 0 1 Active low, combined terms, combinatorial 0 1 0 Active low, separate terms, registered 0 1 1 Active low, separate terms, combinatorial 1 0 0 Active high, combined terms, registered 1 0 1 Active high, combined terms, combinatorial 1 1 0 Active high, separate terms, registered 1 1 1 Active high, separate terms, combinatorial FIGURE 3. Logic diagram (unprogrammed) - for devices 01 - 04 and 06, 0 7. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 13 FIGURE 3. Logic diagram (unprogrammed) - for devices 08 - 12 STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 14 FOR DEVICES 01 - 07 FOR DEVICES 08 - 12 *Including jig and scope (minimum value) FIGURE 4. Output test circuit. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 15 NOTE: Timing measurement reference is 1.5 V. Input ac driving levels are 0.0 V and 3.0 V, unless otherwise specified. FIGURE 5. Switching waveforms. (All device types) STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 16 NOTE: Timing measurement reference is 1.5 V. Input ac driving levels are 0.0 V and 3.0 V, unless otherwise specified. FIGURE 5. Switching waveforms Continued. (Device types 08 - 12) STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 17 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38535, appendix A. 4.2 Screening. Screening shall be in accordance with method 5004 of MIL-STD-883, and shall be conducted on all devices prior to quality conformance inspection. The following additional criteria shall apply: a. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA = +125C, minimum. b. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. c. A data retention stress test shall be included as part of the screening procedure and shall consist of the following steps: (Steps 1 through 4 may be performed at the wafer level. The maximum storage temperature shall not exceed 200C for packaged devices and 300C for unassembled devices.) Margin test method. (1) (2) Program a minimum of 95% of the total number of cells, including the slowest programming cell (see 3.6.2). Bake, unbiased, for 72 hours at +140C, or for 48 hours at +150C, or for 8 hours at +200C, or for unassembled devices only 2 hours at 300C. (3) Perform electrical test (see 4.2b) at 25 including a margin test at Vm = 5.8 V and loose timing (i.e., = 1 s). (4) Erase (see 3.6.1). (5) Program a minimum of 50 percent of the total number of cells, including the slowest programming cell (see 3.6.2). (6) Perform electrical test (see 4.2b) at 25 including a margin test at Vm = 5.8 V and loose timing (i.e., = 1 s). (7) Perform burn-in (see 4.2a). (8) Perform electrical test (see 4.2b) at 25 including a margin test at Vm = 5.8 V and loose timing (i.e., = 1 s). (9) Perform electrical test (see 4.2b) at +125C and -55C. (10) Erase (see 3.6.1). Devices may be submitted for groups A, C, and D testing prior to erasure provided the devices have been 100 percent seal tested in accordance with method 5004 of MIL-STD-883. (11) Verify erasure (see 3.6.3). 4.3 Quality conformance inspection. Quality conformance inspection shall be in accordance with method 5005 of MIL-STD-883 including groups A, B, C, and D inspections. The following additional criteria shall apply. 4.3.1 Group A inspection. a. Tests shall be as specified in table II herein. b. Subgroups 5 and 6 in table I, method 5005 of MIL-STD-883 shall be omitted. c. Subgroup 4 (CI and CO measurement) shall be measured only for the initial test and after process or design changes which may affect input or output capacitance. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 18 TABLE II. Electrical test requirements. 1/ 2/ 3/ 4/ MIL-STD-883 test requirements Subgroups (in accordance with MIL-STD-883, method 5005, table 1) Interim electrical parameters (method 5004) (pre burn-in) 1 Final electrical test parameters (method 5004) for programmed devices 1*, 2, 3, 7*, 8A, 8B Final electrical test parameters (method 5004) for unprogrammed devices 1*, 2, 3, 7*, 8A, 8B, 9 Group A test requirements (method 5005) 1, 2, 3, 4**, 7, 8A, 8B, 9, 10, 11 Group C and D end-point electrical parameters (method 5005) 1/ 2/ 3/ 4/ 2, 3, 7, 8A, 8B * indicates PDA applies to subgroups 1 and 7. ** see 4.3.1c. Any or all subgroups may be combined when using high-speed testers. Subgroups 7 and 8 functional tests shall verify that no fuses are blown for unprogrammed devices or that the altered item drawing pattern exists for programmed devices. 4.3.2 Groups C and D inspections. a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test conditions, method 1005 of MIL-STD-883. (1) Test condition C or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing or acquiring activity upon request. The test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA = +125C, minimum. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.4 Erasing procedures. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 angstroms (A). The integrated dose (i.e., ultraviolet intensity x exposure time) for erasure should be a minimum of fifteen (15) Ws/cm2. The erasure time with this dosage is approximately 15 to 20 minutes using an ultraviolet lamp 2 with a 1200 W/cm power rating. The device should be placed within one inch of the lamp tubes during erasure. The maximum integrated dose the device can be exposed to without damage is 7258 Ws/cm2 (1 week at 12,000 W/cm2). Exposure of the device to high intensity ultraviolet light for long periods may cause permanent damage. 4.5 Programming procedures for method A. The programming characteristics in table III and the following procedures shall be used for programming the device. a. Connect the device in the electrical configuration for programming the waveforms of figure 6 and programming characteristics of table III shall apply. b. Initially and after each erasure all bits are in the "1" state. A programmed "0" can be changed to a "1" by ultraviolet light erasure (see 4.4). c. Programming occurs when the Vpp is at 12.5 V and PGM pulse is at 12.5 V. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 19 TABLE III. Programming characteristics for method A. Test Symbol Conditions 1/ TA = +25C 5C, VCC = 6.0 V 0.25 V VPP = 12.5 V 0.5 V VIN = VIL or VIH Device types Input current (all inputs) ILI Input low level (all inputs) VIL All Input high level VIH All Output low voltage during verify VOL IOL = 16 mA All Output high voltage during verify VOH IOH = -4.0 mA All VCC supply current ICC2 Limits Min All Max 10 uA -0.6 0.8 V 2.0 VCC+ .75 V 0.5 V 2.4 01-04, 06,07 Vpp pin = VPP Unit V 140 08-12 190 All 30 mA VPP supply current (program) IPP2 Address setup time tAS All 2 us OE setup time tOES All 2 us Data setup time tDS All 2 us Address hold time tAH All 0 us Data hold time tDH All 2 us Output enable to output float delay tDFP 2/ All 0 VCC = setup time tVCS All 2 PGM initial program pulse width tPW 3/ PGM overprogram pulse width us 1.05 08-12 .095 .105 18 225 .475 65.63 All tDV ns 0.95 08-12 Data valid from OE 130 01-04, 06,07 01-04, 06,07 4/ tOPW mA 70 ms ms ns 1/ VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2/ This parameter is only sampled and is not 100 percent tested. Output float is defined as the point where data is no longer driven, see timing diagram. 3/ Initial program pulse width tolerance is 1 ms 5 percent. 4/ The length of the overprogram pulse may vary from 18 ms to 225 ms as a function of the iteration counter value X. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 20 FIGURE 6. Programming waveforms. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 21 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38535, appendix A. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractor prepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated with the users of record for the individual documents. This coordination will be accomplished using DD Form 1692, Engineering Change Proposal. 6.4 Record of users. Military and industrial users shall inform Defense Supply Center Columbus (DSCC) when a system application requires configuration control and the applicable SMD. DSCC will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronics devices (FSC 5962) should contact DSCC-VA, telephone (614) 692-0544. 6.5 Comments. Comments on this drawing should be directed to DSCC-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-0547. 6.6 Approved sources of supply. Approved sources of supply are listed in MIL-HDBK-103. The vendors listed in MILHDBK-103 have agreed to this drawing and a certificate of compliance (see 3.6 herein) has been submitted to and accepted by DSCC-VA. STANDARD MICROCIRCUIT DRAWING DEFENSE SUPPLY CENTER COLUMBUS COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-88726 A REVISION LEVEL F SHEET 22 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 10-03-17 Approved sources of supply for SMD 5962-88726 are listed below for immediate acquisition only and shall be added to MIL-HDBK-103 and QML-38535 during the next revision. MIL-HDBK-103 and QML-38535 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DSCC-VA. This bulletin is superseded by the next dated revision of MIL-HDBK-103 and QML-38535. DSCC maintains an online database of all current sources of supply at http://www.dscc.dla.mil/Programs/Smcr/. Standardized military drawing PIN 1/ Vendor CAGE number 5962-8872601LA 0C7V7 3/ QPV750-40DM/883 ATV750-40DM/883 5962-88726013A 0C7V7 3/ QPV750-40LM/883 ATV750-40LM/883 5962-8872601XA 3/ ATV750-40YM/883 5962-8872602LA 0C7V7 3/ QPV750-35DM/883 ATV750-35DM/883 5962-88726023A 0C7V7 3/ QPV750-35LM/883 ATV750-35LM/883 5962-8872602XA 3/ ATV750-35YM/883 5962-8872602YA 3/ ATV750-35KM/883 5962-8872603LA 0C7V7 3/ QPV750-25DM/883 ATV750-25DM/883 5962-88726033A 0C7V7 3/ QPV750-25LM/883 ATV750-25LM/883 5962-8872603XA 3/ ATV750-25YM/883 5962-8872603YA 3/ ATV750-25KM/883 5962-8872604LA 0C7V7 3/ QPV750-20DM/883 ATV750-20DM/883 5962-88726043A 0C7V7 3/ QPV750-20LM/883 ATV750-20LM/883 Vendor similar PIN 2/ See footnotes at end of list. The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin. Page 1 of 3 STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued. Standardized military drawing PIN 1/ Vendor CAGE number 5962-8872604XA 3/ ATV750-20YM/883 5962-8872604YA 3/ ATV750-20KM/883 5962-8872606LA 3/ ATV750L-25DM/883 5962-88726063A 3/ ATV750L-25LM/883 5962-8872606XA 3/ ATV750L-30YM/883 5962-8872607LA 3/ ATV750L-25DM/883 5962-88726073A 3/ ATV750L-25LM/883 5962-8872607XA 3/ ATV750L-25YM/883 5962-8872607YA 3/ ATV750L-25KM/883 5962-8872608LA 0C7V7 QPV750B-10DM/883 ATV750B-10DM/883 3/ 5962-88726083A 0C7V7 Vendor Similar PIN 2/ 3/ QPV750B-10DM/883 ATV750B-10LM/883 5962-8872608YA 3/ ATV750B-10KM/883 5962-8872609LA 0C7V7 QPV750B-15DM/883 ATV750B-15DM/883 3/ 5962-88726093A 0C7V7 3/ QPV750B-15DM/883 ATV750B-15LM/883 5962-8872609YA 3/ ATV750B-15KM/883 5962-8872610LA 0C7V7 QPV750B-25DM/883 ATV750B-25DM/883 3/ 5962-88726103A 0C7V7 3/ QPV750B-25LM/883 ATV750B-25LM/883 See footnotes at end of list. The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in this information bulletin. Page 2 of 3 STANDARD MICROCIRCUIT DRAWING BULLETIN - Continued. Standardized military drawing PIN 1/ 5962-8872610YA 5962-8872611LA 5962-88726113A 5962-8872611YA 5962-8872612LA 5962-88726123A 5962-8872612YA Vendor Similar PIN 3/ 2/ ATV750B-25KM/883 3/ ATV750BL-15DM/883 3/ ATV750BL-15LM/883 3/ ATV750BL-15KM/883 3/ ATV750BL-25DM/883 3/ ATV750BL-25LM/883 3/ ATV750BL-25KM/883 1/ The lead finish shown for each PIN representing hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. 3/ Not available from an approved source. Vendor CAGE number 0C7V7 Vendor CAGE number Vendor name and address Margin test method Programming method A A QP Semiconductor 2945 Oakmead Village Court Santa Clara, CA 95051 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin. Page 3 of 3