SK2100 - Maestro - Datasheet.Directory

450MHz Differential Twisted-Pair Drivers

EL5173, EL5373

The EL5173 and EL5373 are single and triple high bandwidth

amplifiers with a fixed gain of 2. They are primarily targeted for

applications such as driving twisted-pair lines in component video

applications. The inputs can be in either single-ended or

differential form but the outputs are always in differential form.

The output common mode level for each channel is set by the

associated REF pin, which has a -3dB bandwidth of over

190MHz. Generally, these pins are grounded but can be tied to

any voltage reference.

All outputs are short circuit protected to withstand temporary

overload condition.

The EL5173 and EL5373 are specified for operation over the

full -40°C to +85°C temperature range.

Features

• Fully differential inputs and outputs

• Differential input range ±2.3V

• 450MHz 3dB bandwidth at fixed gain of 2

• 900V/µs slew rate (EL5173)

• 1100V/µs slew rate (EL5373)

• Single 5V or dual ±5V supplies

• 40mA maximum output current

• Low power - 12mA per channel

• Pb-free available (RoHS compliant)

Applications

•Twisted-pair drivers

• Differential line drivers

• VGA over twisted-pairs

• ADSL/HDSL drivers

• Single-ended to differential amplification

• Transmission of analog signals in a noisy environment

Pinouts

EL5173

(8 LD SOIC, MSOP)

TOP VIEW

EL5373

(24 LD QSOP)

TOP VIEW

IN+

IN-

REF

OUT

VS-

VS+

OUTB

INP1

INN1

REF1

INP2

INN2

REF2

INP3

INN3

REF3

OUT1

OUT1B

VSP

VSN

OUT2

OUT2B

OUT3

OUT3B

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.

All other trademarks mentioned are the property of their respective owners.

August 28, 2012

FN7312.9

EL5173, EL5373

2FN7312.9

August 28, 2012

Pin Descriptions

EL5173 EL5373

PIN FUNCTIONPIN NUMBER PIN NAME PIN NUMBER PIN NAME

1 IN+ 2, 6, 10 INP1,

INP2, INP3

Non-inverting inputs

2EN1ENENABLE

3 IN- 3, 7, 11 INN1, INN2, INN3 Inverting inputs, note that on EL5173, this pin is also the

REF pin

4 REF 4, 8, 12 REF1, REF2, REF3 Reference inputs, sets common-mode output voltage

5 OUTB 14, 17, 23 OUT3B, OUT2B, OUT1B Inverting outputs

6 VS+ 21 VSP Positive supply

7 VS- 20 VSN Negative supply

8 OUT 15, 18, 24 OUT3, OUT2, OUT1 Non-inverting outputs

- NC 5, 9, 13, 16, 19, 22 NC No connect; grounded for best crosstalk performance

Ordering Information

PART NUMBER

(Notes 1, 2, 3)

PART

MARKING

PACKAGE

(Pb-free)

PKG.

DWG. #

EL5173ISZ 5173ISZ 8 Ld SOIC M8.15E

EL5173IYZ BAAYA 8 Ld MSOP M8.118A

EL5373IUZ EL5373IUZ 24 Ld QSOP MDP0040

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte

tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device information page for EL5173, EL5373. For more information on MSL please see tech brief

TB363.

EL5173, EL5373

3FN7312.9

August 28, 2012

IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are

at the specified temperature and are pulsed tests, therefore: TJ = TC = TA

Absolute Maximum Ratings (TA = +25°C) Thermal Information

Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.6V

Supply Voltage Slew Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1V/µs max.

Supply Voltage Rate-of-rise (dV/dT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V/µs

Input Voltage (IN+, IN- to VS+, VS-) . . . . . . . . . . . . . VS- - 0.3V to VS+ + 0.3V

Differential Input Voltage (IN+ to IN-). . . . . . . . . . . . . . . . . . . . . . . . . . ±4.8V

Maximum Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±60mA

Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+135°C

Recommended Operating Temperature . . . . . . . . . . . . . . . -40°C to +85°C

Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves

Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified.

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 4) TYP

MAX

(Note 4) UNIT

AC PERFORMANCE

BW -3dB Bandwidth 450 MHz

BW ±0.1dB Bandwidth 60 MHz

SR Slew Rate - EL5173 VOUT = 2VP-P, 20% to 80% 750 900 V/µs

Slew Rate - EL5373 VOUT = 2VP-P, 20% to 80% 900 1100 V/µs

tSTL Settling Time to 0.1% VOUT = 2VP-P 10 ns

OS Overshoot VODP-P = 2V 10 %

tOVR Output Overdrive Recovery Time 10 ns

VREFBW (-3dB) VREF -3dB Bandwidth AV =1, CLD = 2.7pF 190 MHz

VREFSR+ VREF Slew Rate - Rise VOUT = 2VP-P, 20% to 80% 200 V/µs

VREFSR- VREF Slew Rate - Fall VOUT = 2VP-P, 20% to 80% 125 V/µs

VNInput Voltage Noise f = 10kHz 25 nV/√Hz

HD2 Second Harmonic Distortion VOUT = 2VP-P, 5MHz 84 dBc

HD2 Second Harmonic Distortion VOUT = 2VP-P, 20MHz 71 dBc

HD3 Third Harmonic Distortion VOUT = 2VP-P, 5MHz 62 dBc

HD3 Third Harmonic Distortion VOUT = 2VP-P, 20MHz 53 dBc

dG Differential Gain at 3.58MHz RLD = 300Ω, AV = 2 0.05 %

dθDifferential Phase at 3.58MHz RLD = 300Ω, AV = 2 0.08 °

eSChannel Separation - for EL5373 only at 1MHz 90 dB

INPUT CHARACTERISTICS

VOS Input Referred Offset Voltage ±3 ±30 mV

IIN Input Bias Current (VIN, VINB)EL5173 -21-11-5µA

EL5373 -21 -13 -5 µA

IREF INput Bias Current at REF VREF = +3.2V 1 5 µA

VREF = -3.2V -1 +1 µA

Gain Gain Accuracy VIN = ±1V 1.97 1.99 2.01 V

RIN Differential Input Resistance 150 kΩ

CIN Differential Input Capacitance 1 pF

DMIR Differential Mode Input Range ±2 ±2.3 V

EL5173, EL5373

4FN7312.9

August 28, 2012

CMIR+ Common Mode Positive Input Range at

VIN+, VIN-

3.1 3.4 V

CMIR- Common Mode Negative Input Range at

VIN+, VIN-

-4.5 -4.2 V

VREFIN+ Reference Input - Positive VIN+ = VIN- = 0V 3.3 3.7 V

VREFIN- Reference Input - Negative VIN+ = VIN- = 0V -3.3 -3 V

VREFOS Output Offset Relative to VREF -100 50 +100 mV

CMRR Input Common Mode Rejection Ratio VIN = ±2.5V 60 80 dB

OUTPUT CHARACTERISTICS

VOUT

(EL5173)

Positive Output Voltage Swing RLD = 200Ω3.3 3.67 V

Negative Output Voltage Swing -3.3 -3 V

VOUT

(EL5373)

Positive Output Voltage Swing RLD = 200Ω3.7 4 V

Negative Output Voltage Swing -3.7 -3.4 V

IOUT(Max) Maximum Output Current RL = 10Ω (EL5173) ±45 ±55 mA

RL = 10Ω (EL5373) ±40 ±50 mA

ROUT Output Impedance 60 mΩ

SUPPLY

VSUPPLY Supply Operating Range VS+ to VS-4.7511V

IS(ON) Power Supply Current - Per Channel 9 12 14 mA

IS(OFF)+ (EL5173) Positive Power Supply Current - Disabled EN pin tied to 4.8V 60 80 100 µA

IS(OFF)- (EL5173) Negative Power Supply Current - Disabled -150 -120 -90 µA

IS(OFF)+ (EL5373) Positive Power Supply Current - Disabled EN pin tied to 4.8V 0.5 2 10 µA

IS(OFF)- (EL5373) Negative Power Supply Current - Disabled -150 -120 -90 µA

PSRR Power Supply Rejection Ratio VS from ±4.5V to ±5.5V 60 73 dB

ENABLE

tEN Enable Time 100 ns

tDS Disable Time 1.2 µs

VIH EN Pin Voltage for Power-Up VS+ - 1.5 V

VIL EN Pin Voltage for Shut-Down VS+ - 0.5 V

IIH-EN EN Pin Input Current High - Per Channel At VEN = 5V 40 60 µA

IIL-EN EN Pin Input Current Low - Per Channel At VEN = 0V -5 -2.5 µA

NOTE:

4. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization

and are not production tested.

Electrical Specifications VS+ = +5V, VS- = -5V, TA = +25°C, VIN = 0V, RLD = 200Ω, CLD = 1pF, Unless Otherwise Specified. (Continued)

PARAMETER DESCRIPTION CONDITIONS

MIN

(Note 4) TYP

MAX

(Note 4) UNIT

EL5173, EL5373

5FN7312.9

August 28, 2012

Connection Diagrams

FIGURE 1. EL5173

FIGURE 2. EL5373

IN+

IN-

REF

OUT

VS-

VS+

OUTB

INP

INN

REF

RS1

50Ω

RS2

50ΩRS3

50ΩCL2 50ΩLOADN

CL1

RRT2 LOADP

-5V

+5V

RRT2

50Ω

INP1

INN1

REF1

INP2

INN2

REF2

INP3

INN3

REF3

OUT1

OUT1B

VSP

VSN

OUT2

OUT2B

OUT3

OUT3B

RSR3

50Ω

RSN3

50Ω

RSP3

50Ω

RSR2

50Ω

RSN2

50Ω

RSP2

50Ω

RSR1

50Ω

RSN1

50Ω

RSP1

50Ω

INP1

INN1

REF1

INP2

INN2

REF2

INP3

INN3

REF3

ENABLE

-5V

+5V

50Ω

RRT3B LD3B

50Ω

RRT3 LD3

50Ω

RRT2B LD2B

50Ω

RRT2 LD2

50Ω

RRT1B LD1B

50Ω

RRT1 LD1

EL5173, EL5373

6FN7312.9

August 28, 2012

Typical Performance Curves

FIGURE 3. FREQUENCY RESPONSE FIGURE 4. FREQUENCY RESPONSE vs RLD

FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE vs CLD FIGURE 6. FREQUENCY RESPONSE vs VREF

FIGURE 7. PSRR vs FREQUENCY FIGURE 8. COMMON MODE REJECTION vs FREQUENCY

FREQUENCY (Hz)

10M 100M 1G

GAIN (dB)

VODP-P = 200mV

10 VS = ±5V, RLD = 200Ω

VODP-P = 700mV

1M 100M 1G

FREQUENCY (Hz)

100k

GAIN (dB)

VS = ±5V, CLD = 1pF

10M

RLD = 1kΩ

RLD = 500Ω

RLD = 100Ω

RLD = 200Ω

FREQUENCY (Hz)

10M 100M 1G

GAIN (dB)

11 VS = ±5V, RLD = 200Ω, VODP-P = 200mV

CLD = 2.3pF

CLD = 0pF

CLD = 5pF

CLD = 16pF

100M 1G

FREQUENCY (Hz)

GAIN (dB)

-1

-2

-3

-4

-5

10M

VREF = 200mVP-P

VREF = 1VP-P

-10

-30

-50

-60

-80

-90 1M 10M 100M

PSRR (dB)

FREQUENCY (Hz)

-70

-40

-20

100k

PSRR-

PSRR+

100k 1M 10M 100M 1G

FREQUENCY (Hz)

COMMON MODE REJECTION (dB)

VOCM/VINCM

-10

-30

-50

-60

-80

-90

-70

-40

-20

VODM/VINCM

VINCM -

+VOCM

VODM

100Ω

EL5173, EL5373

7FN7312.9

August 28, 2012

FIGURE 9. DIFFERENTIAL MODE OUTPUT BALANCE ERROR vs

FREQUENCY

FIGURE 10. INPUT VOLTAGE NOISE vs FREQUENCY

FIGURE 11. CHANNEL SEPARATION vs FREQUENCY FIGURE 12. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE

FIGURE 13. SUPPLY CURRENT vs SUPPLY VOLTAGE FIGURE 14. HARMONIC DISTORTION vs DIFFERENTIAL OUTPUT

VOLTAGE

Typical Performance Curves (Continued)

100k 1M 10M 100M 1G

FREQUENCY (Hz)

BALANCE ERROR (dB)

VOCM/VODM

-10

-20

-30

-40

-50

-60

VIN

+VOCM

VODM

100Ω

RTR

100

1000

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

VOLTAGE NOISE (nV/√Hz)

-110

-100

-80

-70

-60

-40

-30

100k 1M 10M 100M 1G

FREQUENCY (Hz)

CHANNEL SEPARATION (dB)

-50

-90

CH1 --> CH2

CH3 --> CH1

CH2 --> CH3

CH1 --> CH3

CH3 --> CH2

CH2 --> CH1

300

320

360

380

420

440

460

468911

VS (V)

BW (MHz)

400

340

57 10

VODMP-P = 200mV, RLD = 200Ω

11.3

11.4

11.6

11.8

11.9

468911

VS (V)

IS (mA)

11.7

11.5

57 10

-55

-40

12 456 89

DIFFERENTIAL OUTPUT VOLTAGE (V)

DISTORTION (dB)

-45

-50

-75

-60

-65

-70

-90

-80

-85

HD3 (f = 20MHz)

HD3 (f = 5MHz)

HD2 (f = 5MHz)

VS = ±5V, RLD = 200Ω

HD2 (f = 20MHz)

EL5173, EL5373

8FN7312.9

August 28, 2012

FIGURE 15. HARMONIC DISTORTION vs RLD FIGURE 16. HARMONIC DISTORTION vs FREQUENCY

FIGURE 17. SMALL SIGNAL TRANSIENT RESPONSE FIGURE 18. LARGE SIGNAL TRANSIENT RESPONSE

FIGURE 19. OUTPUT IMPEDANCE (DISABLED) FIGURE 20. OUTPUT IMPEDANCE (ENABLED)

Typical Performance Curves (Continued)

-50

-90

DISTORTION (dB)

-80

-70

-60

200 700

RLD (W)

100 600 900400 1000

-100 300 500 800

HD2 (f = 20MHz)

HD3 (f = 20MHz)

-40 VS = ±5V, VODMP-P = 2V

HD3 (f = 5MHz)

HD2 (f = 5MHz)

-45

-50

-60

-70

-80

-85

DISTORTION (dB)

-75

-65

-55

FREQUENCY (Hz)

-90

HD3

-40

5M 25M0M 35M15M 40M10M 20M 30M

VS = ±5V, RLD = 200Ω, VODMP-P = 2V

HD2

20ns/DIV

100mV/DIV

20ns/DIV

0.5V/DIV

EMPTY

BOARD

DISABLED

OUT1B

OUT1

EL5173, EL5373

9FN7312.9

August 28, 2012

Simplified Schematic

FIGURE 21. DISABLED RESPONSE FIGURE 22. ENABLED RESPONSE

FIGURE 23. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

FIGURE 24. PACKAGE POWER DISSIPATION vs AMBIENT

TEMPERATURE

Typical Performance Curves (Continued)

1.136W

θJA = +88°C/W

QSOP24

1.4

1.2

1.0

0.8

0.6

0.2

00 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-7 HIGH EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.4

909mW

θJA = +110°C/W

SO8

870mW

θJA = +115°C/W

MSOP8/10

486mW

θJA = +206°C/W

MSOP8

870mW

θJA = +115°C/W

QSOP24

1.2

1.0

0.8

0.6

0.4

00 255075100 150

AMBIENT TEMPERATURE (°C)

POWER DISSIPATION (W)

12585

JEDEC JESD51-3 LOW EFFECTIVE THERMAL

CONDUCTIVITY TEST BOARD

0.2

625mW

θJA = +160°C/W

SO8

REF

R10

RCD

OUT+

OUT-

R7R8

VB1

FBNFBPIN-IN+

VB2

VS+

VS-

200Ω

400Ω

EL5173, EL5373

10 FN7312.9

August 28, 2012

Description of Operation and

Application Information

Product Description

The EL5173 and EL5373 are wide bandwidth, low power and

single/differential ended to differential output amplifiers. They

have a fixed gain of 2. The EL5173 is a single channel

differential amplifier. The EL5373 is a triple channel

differential amplifier. The EL5173 and EL5373 have a -3dB

bandwidth of 450MHz while driving a 200Ω differential load.

The EL5173 and EL5373 are available with a power-down

feature to reduce the power while the amplifiers are disabled.

Input, Output and Supply Voltage Range

The EL5173 and EL5373 have been designed to operate with a

single supply voltage of 5V to 10V or split supplies with its total

voltage from 5V to 10V. The amplifiers have an input common

mode voltage range from -4.5V to 3.4V for ±5V supply. The

differential mode input range (DMIR) between the two inputs

is from -2.3V to +2.3V. The input voltage range at the REF pin is

from -3.3V to 3.7V. If the input common mode or differential

mode signal is outside the above-specified ranges, it will cause

the output signal to become distorted.

The output of the EL5173 and EL5373 can swing from -3.3V to

3.6V at 200Ω differential load at ±5V supply. As the load

resistance becomes lower, the output swing is reduced.

Differential and Common Mode Gain

Settings

As shown in the “Simplified Schematic” on page 9, since the

feedback resistors RF and the gain resistor are integrated with

200Ω and 400Ω, the EL5173 and EL5373 have a fixed gain of

2. The common mode gain is always one.

Driving Capacitive Loads and Cables

The EL5173 and EL5373 can drive 16pF differential capacitor

in parallel with 200Ω differential load with less than 3.5dB of

peaking. If less peaking is desired in applications, a small

series resistor (usually between 5Ω to 50Ω) can be placed in

series with each output to eliminate most peaking. However,

this will reduce the gain slightly.

When used as a cable driver, double termination is always

recommended for reflection-free performance. For those

applications, a back-termination series resistor at the

amplifier’s output will isolate the amplifier from the cable and

allow extensive capacitive drive. However, other applications

may have high capacitive loads without a back-termination

resistor. Again, a small series resistor at the output can help to

reduce peaking.

Disable/Power-Down

The EL5173 and EL5373 can be disabled and placed their

outputs in a high impedance state. The turn-off time is about

1.2µs and the turn-on time is about 100ns. When disabled, the

amplifier’s supply current is reduced to 40µA for IS+ and

2.5µA for IS- typically, thereby effectively eliminating the power

consumption. The amplifier’s power-down can be controlled by

standard CMOS signal levels at the ENABLE pin. The applied

logic signal is relative to VS+ pin. Letting the EN pin float or

applying a signal that is less than 1.5V below VS+ will enable

the amplifier. The amplifier will be disabled when the signal at

EN pin is above VS+ - 0.5V.

Output Drive Capability

The EL5173 and EL5373 have internal short circuit protection.

Its typical short circuit current is ±55mA. If the output is

shorted indefinitely, the power dissipation could easily

increase such that the part will be destroyed. Maximum

reliability is maintained if the output current never exceeds

±60mA. This limit is set by the design of the internal metal

interconnect.

Power Dissipation

With the high output drive capability of the EL5173 and EL5373,

it is possible to exceed the +125°C absolute maximum junction

temperature under certain load current conditions. Therefore, it

is important to calculate the maximum junction temperature for

the application to determine if the load conditions or package

types need to be modified for the amplifier to remain in the safe

operating area.

The maximum power dissipation allowed in a package is

determined according to Equation 1:

Where:

•T

JMAX = Maximum junction temperature

•T

AMAX = Maximum ambient temperature

•θJA = Thermal resistance of the package

The maximum power dissipation actually produced by an IC is

the total quiescent supply current times the total power supply

voltage, plus the power in the IC due to the load, or as

expressed in Equation 2:

Where:

VSTOT = Total supply voltage = VS+ - VS-

ISMAX = Maximum quiescent supply current per channel

ΔVO = Maximum differential output voltage of the

application

RLD = Differential load resistance

ILOAD = Load current

i = Number of channels

By setting the two PDMAX equations equal to each other, we

can solve the output current and RLOAD to avoid the device

overheat.

PDMAX TJMAX TAMAX

–

ΘJA

---------------------------------------------

=(EQ. 1)

(EQ. 2)

PD i VSTOT ISMAX

×V(STOT ΔVO)–ΔVO

RLD

------------

×+

⎝⎠

⎜⎟

⎛⎞

×=

EL5173, EL5373

11 FN7312.9

August 28, 2012

Power Supply Bypassing and Printed Circuit

Board Layout

As with any high frequency device, a good printed circuit board

layout is necessary for optimum performance. Lead lengths

should be as short as possible. The power supply pin must be

well bypassed to reduce the risk of oscillation. For normal

single supply operation, where the VS- pin is connected to the

ground plane, a single 4.7µF tantalum capacitor in parallel

with a 0.1µF ceramic capacitor from VS+ to GND will suffice.

This same capacitor combination should be placed at each

supply pin to ground if split supplies are to be used. In this

case, the VS- pin becomes the negative supply rail.

For good AC performance, parasitic capacitance should be

kept to minimum. Use of wire-wound resistors should be

avoided because of their additional series inductance. Use of

sockets should also be avoided if possible. Sockets add

parasitic inductance and capacitance that can result in

compromised performance. Minimizing parasitic capacitance

at the amplifier’s inverting input pin is very important. The

feedback resistor should be placed very close to the inverting

input pin. Strip line design techniques are recommended for

the signal traces.

Typical Applications

0Ω

VFB

VINB

VREF

EL5175/

EL5375

EL5173/

EL5373 VOUT

ZO = 100Ω

VIN

50Ω

FIGURE 25. TWISTED PAIR CABLE DRIVER

EL5173, EL5373

12 FN7312.9

August 28, 2012

Package Outline Drawing

M8.15E

8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE

Rev 0, 08/09

Unless otherwise specified, tolerance : Decimal ± 0.05

The pin #1 identifier may be either a mold or mark feature.

Interlead flash or protrusions shall not exceed 0.25mm per side.

Dimension does not include interlead flash or protrusions.

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

Dimensions are in millimeters.1.

NOTES:

DETAIL "A"

SIDE VIEW “A

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

0.25 AMC B

0.10 C

ID MARK

PIN NO.1

(0.35) x 45°

SEATING PLANE

GAUGE PLANE

0.25

(5.40)

(1.50)

4.90 ± 0.10

3.90 ± 0.10

1.27 0.43 ± 0.076

0.63 ±0.23

4° ± 4°

DETAIL "A" 0.22 ± 0.03

0.175 ± 0.075

1.45 ± 0.1

1.75 MAX

(1.27) (0.60)

6.0 ± 0.20

Reference to JEDEC MS-012.

SIDE VIEW “B”

EL5173, EL5373

13 FN7312.9

August 28, 2012

Package Outline Drawing

M8.118A

8 LEAD MINI SMALL OUTLINE PLASTIC PACKAGE (MSOP)

Rev 0, 9/09

Plastic or metal protrusions of 0.15mm max per side are not

Dimensions “D” and “E1” are measured at Datum Plane “H”.

This replaces existing drawing # MDP0043 MSOP 8L.

Plastic interlead protrusions of 0.25mm max per side are not

Dimensioning and tolerancing conform to JEDEC MO-187-AA

Dimensions are in millimeters.1.

NOTES:

DETAIL "X"

SIDE VIEW 1

TYPICAL RECOMMENDED LAND PATTERN

TOP VIEW

SIDE VIEW 2

included.

GAUGE

PLANE

3°±3°

0.25 CAB

0.10 C

0.08 CAB

0.25

0.55 ± 0.15

0.95 BSC

0.18 ± 0.05

1.10 Max

4.40

3.00

5.80

0.65

3.0±0.1 4.9±0.15

1.40

0.40

0.65 BSC

PIN# 1 ID

DETAIL "X"

0.33 +0.07/ -0.08 0.10 ± 0.05

3.0±0.1

0.86±0.09

SEATING PLANE

and AMSE Y14.5m-1994.

EL5173, EL5373

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted

in the quality certifications found at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time

without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be

accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN7312.9

August 28, 2012

For additional products, see www.intersil.com/product_tree

Quarter Size Outline Plastic Packages Family (QSOP)

0.010 CAB

SEATING

PLANE

DETAIL X

EE1

1(N/2)

(N/2)+1

PIN #1

I.D. MARK

0.004 C

SEE DETAIL "X"

4°±4°

GAUGE

PLANE

0.010

0.007 CAB

MDP0040

QUARTER SIZE OUTLINE PLASTIC PACKAGES FAMILY

SYMBOL

INCHES

TOLERANCE NOTESQSOP16 QSOP24 QSOP28

A 0.068 0.068 0.068 Max. -

A1 0.006 0.006 0.006 ±0.002 -

A2 0.056 0.056 0.056 ±0.004 -

b 0.010 0.010 0.010 ±0.002 -

c 0.008 0.008 0.008 ±0.001 -

D 0.193 0.341 0.390 ±0.004 1, 3

E 0.236 0.236 0.236 ±0.008 -

E1 0.154 0.154 0.154 ±0.004 2, 3

e 0.025 0.025 0.025 Basic -

L 0.025 0.025 0.025 ±0.009 -

L1 0.041 0.041 0.041 Basic -

N 16 24 28 Reference -

Rev. F 2/07

NOTES:

1. Plastic or metal protrusions of 0.006” maximum per side are not

included.

2. Plastic interlead protrusions of 0.010” maximum per side are not

included.

3. Dimensions “D” and “E1” are measured at Datum Plane “H”.

4. Dimensioning and tolerancing per ASME Y14.5M-1994.