SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 D Floating Bootstrap or Ground-Reference D D D D D D D D D D D D D PACKAGE (TOP VIEW) High-Side Driver Adaptive Dead-Time Control 50-ns Max Rise/Fall Times With 3.3-nF Load 2.4-A Typical Output Current 4.5-V to 15-V Supply Voltage Range TTL-Compatible Inputs Internal Schottky Bootstrap Diode SYNC Control for Synchronous or Nonsynchronous Operation CROWBAR for OVP, Protects Against Faulted High-Side Power FETs Low Supply Current....3 mA Typical Ideal for High-Current Single or Multiphase Power Supplies -40C to 125C Operating Virtual Junction Temperature Range Available in SOIC and TSSOP PowerPAD Packages ENABLE IN CROWBAR NC SYNC DT PGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 BOOT NC HIGHDR BOOTLO LOWDR NC VCC PWP PACKAGE (TOP VIEW) ENABLE IN CROWBAR NC SYNC DT PGND 1 14 2 13 3 12 Thermal 4 Pad 11 5 10 6 9 7 8 BOOT NC HIGHDR BOOTLO LOWDR NC VCC NC - No internal connection description The TPS2834 and TPS2835 are MOSFET drivers for synchronous-buck power stages. These devices are ideal for designing a high-performance power supply using switching controllers that do not include on-chip MOSFET drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive loads. The high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive dead-time control circuit eliminates shoot-through currents through the main power FETs during switching transitions, and provides high efficiency for the buck regulator. The TPS2834 and TPS2835 have additional control functions: ENABLE, SYNC, and CROWBAR. Both high-side and low-side drivers are off when ENABLE is low. The driver is configured as a nonsynchronous-buck driver disabling the low-side driver when SYNC is low. The CROWBAR function turns on the low-side power FET, overriding the IN signal, for overvoltage protection against faulted high-side power FETs. The TPS2834 has a noninverting input, while the TPS2835 has an inverting input. These drivers are available in 14-terminal SOIC and thermally enhanced TSSOP PowerPAD packages and operate over a junction temperature range of -40C to 125C. Related Synchronous MOSFET Drivers DEVICE NAME ADDITIONAL FEATURES INPUTS TPS2830 TPS2831 Noninverted ENABLE, SYNC, and CROWBAR CMOS W/O ENABLE, SYNC, and CROWBAR CMOS W/O ENABLE, SYNC, and CROWBAR TTL TPS2832 TPS2833 Noninverted TPS2836 TPS2837 Inverted Inverted Noninverted Inverted Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments Incorporated. Copyright 2002, Texas Instruments Incorporated !"#$%! & '("")% $& ! *(+,'$%! -$%). "!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%& &%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-) %)&%3 ! $,, *$"$#)%)"&. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 AVAILABLE OPTIONS PACKAGED DEVICES TJ SOIC (D) - 40C to 125C TSSOP (PWP) TPS2834D TPS2835D TPS2834PWP TPS2835PWP The D and PWP packages are available taped and reeled. Add R suffix to device type (e.g., TPS2834DR) functional block diagram 8 14 1 M (TPS2834 Only) 250 k 2 12 11 VCC BOOT HIGHDR BOOTLO IN VCC (TPS2835 Only) 10 250 k 7 6 DT ENABLE 1 5 SYNC CROWBAR 2 POST OFFICE BOX 655303 3 * DALLAS, TEXAS 75265 LOWDR PGND SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION BOOT 14 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 F and 1 F. BOOTLO 11 O This terminal connects to the junction of the high-side and low-side MOSFETs. CROWBAR 3 I CROWBAR can to be driven by an external OVP circuit to protect against a short across the high-side MOSFET. If CROWBAR is driven low, the low-side driver will be turned on and the high-side driver will be turned off, independent of the status of all other control terminals. DT 6 I Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs. ENABLE 1 I If ENABLE is low, both drivers are off. HIGHDR 12 O Output drive for the high-side power MOSFET IN 2 I Input signal to the MOSFET drivers (noninverting input for the TPS2834; inverting input for the TPS2835). 10 O Output drive for the low-side power MOSFET LOWDR NC 4, 9, 13 No internal connection PGND 7 SYNC 5 I Power ground. Connect to the FET power ground. Synchronous rectifier enable terminal. If SYNC is low, the low-side driver is always off; If SYNC is high, the low-side driver provides gate drive to the low-side MOSFET. VCC 8 I Input supply. Recommended that a 1-F capacitor be connected from VCC to PGND. detailed description low-side driver The low-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. high-side driver The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A, source and sink. The high-side driver can be configured as a GND-reference driver or as a floating bootstrap driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum voltage that can be applied from BOOT to ground is 30 V. dead-time (DT) control Dead-time control prevents shoot-through current from flowing through the main power FETs during switching transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until the voltage at the junction of the power FETs (Vdrain) is low; the TTL-compatible DT terminal connects to the junction of the power FETs. ENABLE The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a TTL-compatible digital terminal. IN The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2834 has a noninverting input; the TPS2835 has an inverting input. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 detailed description (continued) SYNC The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the low-side FET is always off. SYNC is a TTL-compatible digital terminal. CROWBAR The CROWBAR terminal overrides the normal operation of the driver. When CROWBAR is low, the low-side FET turns on to act as a clamp, protecting the output voltage of the dc/dc converter against overvoltages due to a short across the high-side FET. VIN should be fused to protect the low-side FET. CROWBAR is a TTL-compatible digital terminal. absolute maximum ratings over operating free-air temperature (unless otherwise noted) Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V Input voltage range: BOOT to PGND (high-side driver ON) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 30 V BOOTLO to PGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V BOOT to BOOTLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V ENABLE, SYNC, and CROWBAR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 16 V DT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to 30 V Continuous total power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating virtual junction temperature range, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40C to 125C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to 150C Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . 260C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: Unless otherwise specified, all voltages are with respect to PGND. DISSIPATION RATING TABLE DERATING FACTOR PWP with solder TA 25C 2668 PWP without solder 1024 10.24 mW/C 563 409 D 749 7.49 mW/C 412 300 PACKAGE 26.68 mW/C TA = 70C 1467 TA = 85C 1067 JUNCTION-CASE THERMAL RESISTANCE TABLE PWP Junction-case thermal resistance Test Board Conditions: 1. Thickness: 0.062I 2. 3I x 3I (for packages <27 mm long) 3. 4I x 4I (for packages >27 mm long) 4. 2-oz copper traces located on the top of the board (0.071 mm thick) 5. Copper areas located on the top and bottom of the PCB for soldering 6. Power and ground planes, 1-oz copper (0.036 mm thick) 7. Thermal vias, 0.33 mm diameter, 1.5 mm pitch 8. Thermal isolation of power plane For more information, refer to TI technical brief literature number SLMA002. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 2.07 C/W SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 recommended operating conditions MIN NOM MAX UNIT Supply voltage, VCC 4.5 15 V Input voltage 4.5 28 V BOOT to PGND electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) supply current PARAMETER VCC VCC TEST CONDITIONS Supply voltage range MIN TYP 4.5 Quiescent current V(ENABLE) = LOW, V(ENABLE) = HIGH, VCC =15 V VCC =15 V V(ENABLE) = HIGH, f(SWX) = 200 kHz, C(HIGHDR) = 50 pF, See Note 2 VCC =12 V, BOOTLO grounded, C(LOWDR) = 50 pF, MAX 15 100 300 3 400 UNIT V A A mA NOTE 2: Ensured by design, not production tested. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 5 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued) output drivers PARAMETER High-side sink (see Note 3) Peak output current High-side source (see Note 3) Low-side sink (see Note 3) Low-side source (see Note 3) TEST CONDITIONS Duty cycle < 2%, tpw < 100 s (see Note 2) Duty cycle < 2%, tpw < 100 s (see Note 2) Duty cycle < 2%, tpw < 100 s (see Note 2) Duty cycle < 2%, tpw < 100 s (see Note 2) MIN TYP V(BOOT) - V(BOOTLO) = 4.5 V, V(HIGHDR) = 4 V 0.7 1.1 V(BOOT) - V(BOOTLO) = 6.5 V, V(HIGHDR) = 5 V 1.1 1.5 V(BOOT) - V(BOOTLO) = 12 V, V(HIGHDR) = 10.5 V 2 2.4 V(BOOT) - V(BOOTLO) = 4.5 V, V(HIGHDR) = 0.5V 1.2 1.4 V(BOOT) - V(BOOTLO) = 6.5 V, V(HIGHDR) = 1.5 V 1.3 1.6 V(BOOT) - V(BOOTLO) = 12 V, V(HIGHDR) = 1.5 V 2.3 2.7 1.3 1.8 2 2.5 VCC = 4.5 V, V(LOWDR) = 4 V VCC = 6.5 V, V(LOWDR) = 5 V VCC = 12 V, V(LOWDR) = 10.5 V VCC = 4.5 V, VLOWDR)) = 0.5V VCC = 6.5 V, V(LOWDR)) = 1.5 V VCC = 12 V, V(LOWDR0) = 1.5 V V(BOOT) - V(BOOTLO) = 4.5 V, V(HIGHDR)= 0.5 V High-side sink (see Note 3) Output resistance High-side source (see Note 3) V(BOOT) - V(BOOTLO) = 6.5 V, V(HIGHDR) = 0.5 V V(BOOT) - V(BOOTLO) = 12 V, V(HIGHDR) = 0.5 V V(BOOT) - V(BOOTLO) = 4.5 V, V(HIGHDR) = 4 V V(BOOT) - V(BOOTLO) = 6.5 V, V(HIGHDR)= 6 V V(BOOT) - V(BOOTLO) = 12 V, V(HIGHDR) =11.5 V V(DRV) = 4.5 V, V(LOWDR)= 0.5 V Low-side sink (see Note 3) Low-side source (see Note 3) 3 3.5 1.4 1.7 2 2.4 2.5 3 MAX UNIT A A A A 5 5 5 75 75 75 9 V(DRV) = 6.5 V, V(LOWDR) = 0.5 V V(DRV) = 12 V, V(LOWDR) = 0.5 V 7.5 V(DRV) = 4.5 V, V(LOWDR) = 4 V V(DRV) = 6.5 V, V(LOWDR)= 6 V 75 6 75 V(DRV) = 12 V, V(LOWDR) = 11.5 V 75 NOTES: 2: Ensured by design, not production tested. 3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 electrical characteristics over recommended operating virtual junction temperature range, VCC = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued) dead-time control PARAMETER VIH VIL High-level input voltage VIH VIL High-level input voltage Low-level input voltage Low-level input voltage TEST CONDITIONS LOWDR Over the VCC range (see Note 2) DT Over the VCC range MIN TYP MAX 0.7VCC 1 2 UNIT V V 1 V NOTE 2: Ensured by design, not production tested. digital control terminals (IN, CROWBAR, SYNC, ENABLE) PARAMETER VIH VIL TEST CONDITIONS High-level input voltage MIN TYP MAX 2 V Over the VCC range Low-level input voltage UNIT 1 V switching characteristics over recommended operating virtual junction temperature range, ENABLE = High, CL = 3.3 nF (unless otherwise noted) PARAMETER TEST CONDITIONS HIGHDR output (see Note 2) Rise time LOWDR output (see Note 2) HIGHDR output (see Note 2) LOWDR output (see Note 2) HIGHDR going low (excluding dead time) (see Note 2) Propagation delay time Propagation delay time Driver nonoverlap time LOWDR going high (excluding dead time) (see Note 2) LOWDR going low (excluding dead time) (see Note 2) DT to LOWDR and LOWDR to HIGHDR (see Note 2) TYP MAX V(BOOTLO) = 0 V V(BOOTLO) = 0 V 60 V(BOOT) = 12 V, VCC = 4.5 V V(BOOTLO) = 0 V 50 50 V(BOOT) = 4.5 V, V(BOOT) = 6.5 V, UNIT ns 40 VCC = 6.5 V VCC = 12 V V(BOOT) = 12 V, VCC = 4.5 V Fall time MIN V(BOOT) = 4.5 V, V(BOOT) = 6.5 V, 30 ns 30 V(BOOTLO) = 0 V V(BOOTLO) = 0 V V(BOOTLO) = 0 V 50 40 ns 40 40 VCC = 6.5 V VCC = 12 V 30 ns 30 V(BOOT) = 4.5 V, V(BOOT) = 6.5 V, V(BOOTLO) = 0 V V(BOOTLO) = 0 V 95 V(BOOT) = 12 V, V(BOOT) = 4.5 V, V(BOOTLO) = 0 V V(BOOTLO) = 0 V 70 V(BOOT) = 6.5 V, V(BOOTLO) = 0 V 70 V(BOOT) = 12 V, VCC = 4.5 V V(BOOTLO) = 0 V 60 80 ns 80 ns 80 VCC = 6.5 V VCC = 12 V 70 ns 60 VCC = 4.5 V VCC = 6.5 V 40 170 25 135 VCC = 12 V 15 85 ns NOTE 2: Ensured by design, not production tested. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 TYPICAL CHARACTERISTICS FALL TIME vs SUPPLY VOLTAGE RISE TIME vs SUPPLY VOLTAGE 50 50 CL = 3.3 nF TJ = 25C 45 40 40 t f - Fall Time - ns t r - Rise Time - ns CL = 3.3 nF TJ = 25C 45 High Side 35 30 Low Side 25 35 High Side 30 25 20 20 15 15 10 Low Side 10 4 5 6 7 9 10 11 12 13 8 VCC - Supply Voltage - V 14 15 4 5 6 Figure 1 VCC = 6.5 V CL = 3.3 nF 45 11 12 13 14 15 VCC = 6.5 V CL = 3.3 nF 40 t f - Fall Time - ns High Side t r - Rise Time - ns 10 50 40 35 30 Low Side 25 High Side 35 30 25 Low Side 20 20 15 15 -25 0 25 50 75 100 125 10 -50 -25 0 25 Figure 3 Figure 4 POST OFFICE BOX 655303 50 75 TJ - Junction Temperature - C TJ - Junction Temperature - C 8 9 FALL TIME vs JUNCTION TEMPERATURE 50 10 -50 8 Figure 2 RISE TIME vs JUNCTION TEMPERATURE 45 7 VCC - Supply Voltage - V * DALLAS, TEXAS 75265 100 125 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 TYPICAL CHARACTERISTICS HIGH-TO-LOW PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, HIGH TO LOW LEVEL 150 t PHL - High-to-Low Propagation Delay Time - ns t PLH - Low-to-High Propagation Delay Time - ns LOW-TO-HIGH PROPAGATION DELAY TIME vs SUPPLY VOLTAGE, LOW TO HIGH LEVEL CL = 3.3 nF TJ = 25C 140 130 120 110 100 90 80 70 60 Low Side 50 40 30 20 4 5 6 7 9 10 11 12 13 8 VCC - Supply Voltage - V 14 15 150 CL = 3.3 nF TJ = 25C 140 130 120 110 100 90 80 70 High Side 60 50 40 Low Side 30 20 4 5 6 7 Figure 5 VCC = 6.5 V CL = 3.3 nF 120 110 100 High Side 90 80 70 60 Low Side 50 40 30 20 -50 11 12 13 14 15 HIGH-TO-LOW PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE t PHL - High-to-Low Propagation Delay Time - ns t PLH - Low-to-High Propagation Delay Time - ns 150 130 10 Figure 6 LOW-TO-HIGH PROPAGATION DELAY TIME vs JUNCTION TEMPERATURE 140 9 8 VCC - Supply Voltage - V -25 25 75 0 50 100 TJ - Junction Temperature - C 125 150 140 130 VCC = 6.5 V CL = 3.3 nF 120 110 100 90 High Side 80 70 60 50 Low Side 40 30 20 -50 -25 0 25 50 75 100 125 TJ - Junction Temperature - C Figure 7 Figure 8 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 TYPICAL CHARACTERISTICS DRIVER-OUTPUT FALL TIME vs LOAD CAPACITANCE DRIVER-OUTPUT RISE TIME vs LOAD CAPACITANCE 1000 1000 VCC = 6.5 V TJ = 25C t f - Fall Time - ns t r - Rise Time - ns VCC = 6.5 V TJ = 25C 100 High Side Low Side 10 1 0.01 1 0.1 10 100 High Side Low Side 10 1 0.01 100 10 100 CL - Load Capacitance - nF CL - Load Capacitance - nF Figure 9 Figure 10 SUPPLY CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs SUPPLY VOLTAGE 25 6000 TJ = 25C CL = 50 pF 5500 TJ = 25C CL = 50 pF 5000 20 4500 ICC - Supply Current - mA ICC - Supply Current - A 1 0.1 500 kHz 4000 300 kHz 3500 200 kHz 3000 100 kHz 50 kHz 25 kHz 2500 2000 1500 1000 2 MHz 15 10 1 MHz 5 500 0 0 4 6 8 10 12 14 16 4 VCC - Supply Voltage - V 8 10 Figure 12 POST OFFICE BOX 655303 12 VCC - Supply Voltage - V Figure 11 10 6 * DALLAS, TEXAS 75265 14 16 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 TYPICAL CHARACTERISTICS PEAK SOURCE CURRENT vs SUPPLY VOLTAGE PEAK SINK CURRENT vs SUPPLY VOLTAGE 4 4 TJ = 25C TJ = 25C 3.5 3 3 Low Side Peak Sink Current - A Peak Source Current - A 3.5 2.5 2 High Side 1.5 Low Side 2.5 2 High Side 1.5 1 1 0.5 0.5 0 0 4 6 8 10 12 14 16 4 6 VCC - Supply Voltage - V 8 Figure 13 14 16 Figure 14 INPUT THRESHOLD VOLTAGE vs SUPPLY VOLTAGE INPUT THRESHOLD VOLTAGE vs JUNCTION TEMPERATURE 2.0 2.0 TJ = 25C VCC = 6.5 V V IT - Input Threshold Voltage - V V IT - Input Threshold Voltage - V 12 10 VCC - Supply Voltage - V 1.8 1.6 1.4 1.2 1.0 4 6 8 10 12 14 16 1.8 1.6 1.4 1.2 1.0 -50 -25 0 25 50 75 100 125 TJ - Junction Temperature - C VCC - Supply Voltage - V Figure 15 Figure 16 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 APPLICATION INFORMATION Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A pulse-width-modulation (PWM) controller and a TPS2835 driver. The converter operates over an input range from 4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load. The converter achieves an efficiency of 94% for VIN = 5 V, Iload=1 A, and 93% for VIN = 5 V, Iload = 3 A. VIN + C10 100 F C5 100 F + R1 1 k U1 TPS2835 1 2 3 4 5 6 7 BOOT ENABLE R6 1 M 14 13 IN NC 12 CROWBAR HIGHDR 11 BOOTLO NC 10 SYNC LOWDR 9 DT NC PGND VCC 8 C15 1.0 F Q1 Si4410 R7 3.3 Q2 Si4410 GND OUT U2 TL5001A 2 C2 VCC 0.033 F R2 1.6 k 3 COMP FB 4 5 SCP RT 7 C6 1000 pF C4 0.022 F R3 180 R4 2.32 k GND C1 1 F 8 R9 90.9 k R10 1.0 k Figure 17. 3.3-V 3-A Synchronous-Buck Converter Circuit 12 3.3 V C7 100 F + C12 100 F + C3 0.0022 F 6 DTC R8 121 k C13 10 F RTN C8 0.1 F 1 L1 27 H R11 4.7 C14 1 F C9 0.22 F C11 0.47 F R5 0 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 SLVS223B - NOVEMBER 1999 - REVISED AUGUST 2002 APPLICATION INFORMATION Great care should be taken when laying out the PC board. The power-processing section is the most critical and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and C12 should also be connected to Q2 source. Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive traces. The bypass capacitor (C14) should be tied directly across VCC and PGND. The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible. The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply will be relatively free of noise. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) (Requires Login) TPS2834D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2834DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2834DR ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2834DRG4 ACTIVE SOIC D 14 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2834PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2834PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2834PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2834PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2835D ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2835DG4 ACTIVE SOIC D 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM TPS2835PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2835PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR TPS2835PWPR ACTIVE HTSSOP PWP 14 TBD Call TI Call TI TPS2835PWPRG4 ACTIVE HTSSOP PWP 14 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 17-Aug-2012 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS2834DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 TPS2834PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 17-Aug-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS2834DR SOIC D 14 2500 367.0 367.0 38.0 TPS2834PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. 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