SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DFloating Bootstrap or Ground-Reference
High-Side Driver
DAdaptive Dead-Time Control
D50-ns Max Rise/Fall Times With 3.3-nF Load
D2.4-A Typical Output Current
D4.5-V to 15-V Supply Voltage Range
DTTL-Compatible Inputs
DInternal Schottky Bootstrap Diode
DSYNC Control for Synchronous or
Nonsynchronous Operation
DCROWBAR for OVP, Protects Against
Faulted High-Side Power FETs
DLow Supply Current....3 mA Typical
DIdeal for High-Current Single or Multiphase
Power Supplies
D−40°C to 125°C Operating Virtual Junction
Temperature Range
DAvailable in SOIC and TSSOP PowerPAD
Packages
description
The TPS2834 and TPS2835 are MOSFET drivers for synchronous-buck power stages. These devices are ideal
for designing a high-performance power supply using switching controllers that do not include on-chip MOSFET
drivers. The drivers are designed to deliver minimum 2-A peak currents into large capacitive loads. The
high-side driver can be configured as ground-reference or as floating-bootstrap. An adaptive dead-time control
circuit eliminates shoot-through currents through the main power FETs during switching transitions, and
provides high efficiency for the buck regulator. The TPS2834 and TPS2835 have additional control functions:
ENABLE, SYNC, and CROWBAR. Both high-side and low-side drivers are off when ENABLE is low. The driver
is configured as a nonsynchronous-buck driver disabling the low-side driver when SYNC is low. The CROWBAR
function turns on the low-side power FET, overriding the IN signal, for overvoltage protection against faulted
high-side power FETs.
The TPS2834 has a noninverting input, while the TPS2835 has an inverting input. These drivers are available
in 14-terminal SOIC and thermally enhanced TSSOP PowerPAD packages and operate over a junction
temperature range of −40°C to 125°C.
Related Synchronous MOSFET Drivers
DEVICE NAME ADDITIONAL FEATURES INPUTS
TPS2830
ENABLE, SYNC, and CROWBAR
CMOS
Noninverted
TPS2831 ENABLE, SYNC, and CROWBAR CMOS Inverted
TPS2832
W/O ENABLE, SYNC, and CROWBAR
CMOS
Noninverted
TPS2833 W/O ENABLE, SYNC, and CROWBAR CMOS Inverted
TPS2836
W/O ENABLE, SYNC, and CROWBAR
TTL
Noninverted
TPS2837 W/O ENABLE, SYNC, and CROWBAR TTL Inverted
Copyright 2002, Texas Instruments Incorporated
!"#$%! & '("")% $& ! *(+,'$%! -$%).
"!-('%& '!!"# %! &*)''$%!& *)" %/) %)"#& ! )0$& &%"(#)%&
&%$-$"- 1$""$%2. "!-('%! *"!')&&3 -!)& !% )')&&$",2 ',(-)
%)&%3 ! $,, *$"$#)%)"&.
PowerPAD is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
14
13
12
11
10
9
8
PWP PACKAGE
(TOP VIEW)
NC − No internal connection
ENABLE
IN
CROWBAR
NC
SYNC
DT
PGND
BOOT
NC
HIGHDR
BOOTLO
LOWDR
NC
VCC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
ENABLE
IN
CROWBAR
NC
SYNC
DT
PGND
BOOT
NC
HIGHDR
BOOTLO
LOWDR
NC
VCC
D PACKAGE
(TOP VIEW)
Thermal
Pad
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
AVAILABLE OPTIONS
PACKAGED DEVICES
TJSOIC
(D) TSSOP
(PWP)
−40°C to 125°CTPS2834D
TPS2835D TPS2834PWP
TPS2835PWP
The D and PWP packages are available taped and reeled. Add R
suffix to device type (e.g., TPS2834DR)
functional block diagram
DT
6
IN
VCC
LOWDR
BOOTLO
HIGHDR
BOOT
PGND
2
8
14
12
11
10
VCC
7
ENABLE 1SYNC 5
CROWBAR 3
(TPS2834 Only)
(TPS2835 Only)
1 MΩ
250 kΩ
250 kΩ
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME NO.
I/O
DESCRIPTION
BOOT 14 I Bootstrap terminal. A ceramic capacitor is connected between BOOT and BOOTLO to develop the floating
bootstrap voltage for the high-side MOSFET. The capacitor value is typically between 0.1 µF and 1 µF.
BOOTLO 11 OThis terminal connects to the junction of the high-side and low-side MOSFETs.
CROWBAR 3 I CROWBAR can to be driven by an external OVP circuit to protect against a short across the high-side
MOSFET. If CROWBAR is driven low, the low-side driver will be turned on and the high-side driver will be
turned off, independent of the status of all other control terminals.
DT 6 I Dead-time control terminal. Connect DT to the junction of the high-side and low-side MOSFETs.
ENABLE 1 I If ENABLE is low, both drivers are off.
HIGHDR 12 O Output drive for the high-side power MOSFET
IN 2 I Input signal to the MOSFET drivers (noninverting input for the TPS2834; inverting input for the TPS2835).
LOWDR 10 O Output drive for the low-side power MOSFET
NC 4, 9, 13 No internal connection
PGND 7 Power ground. Connect to the FET power ground.
SYNC 5 I Synchronous rectifier enable terminal. If SYNC is low, the low-side driver is always off; If SYNC is high, the
low-side driver provides gate drive to the low-side MOSFET.
VCC 8 I Input supply. Recommended that a 1-µF capacitor be connected from VCC to PGND.
detailed description
low-side driver
The low-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A,
source and sink.
high-side driver
The high-side driver is designed to drive low rDS(on) N-channel MOSFETs. The current rating of the driver is 2 A,
source and sink. The high-side driver can be configured as a GND-reference driver or as a floating bootstrap
driver. The internal bootstrap diode is a Schottky, for improved drive efficiency. The maximum voltage that can
be applied from BOOT to ground is 30 V.
dead-time (DT) control
Dead-time control prevents shoot-through current from flowing through the main power FETs during switching
transitions by controlling the turnon times of the MOSFET drivers. The high-side driver is not allowed to turn
on until the gate drive voltage to the low-side FET is low, and the low-side driver is not allowed to turn on until
the voltage at the junction of the power FETs (Vdrain) is low; the TTL-compatible DT terminal connects to the
junction of the power FETs.
ENABLE
The ENABLE terminal enables the drivers. When enable is low, the output drivers are low. ENABLE is a
TTL-compatible digital terminal.
IN
The IN terminal is a TTL-compatible digital terminal that is the input control signal for the drivers. The TPS2834
has a noninverting input; the TPS2835 has an inverting input.
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
SYNC
The SYNC terminal controls whether the drivers operate in synchronous or nonsynchronous mode. In
synchronous mode, the low-side FET is operated as a synchronous rectifier. In nonsynchronous mode, the
low-side FET is always off. SYNC is a TTL-compatible digital terminal.
CROWBAR
The CROWBAR terminal overrides the normal operation of the driver. When CROWBAR is low, the low-side
FET turns on to act as a clamp, protecting the output voltage of the dc/dc converter against overvoltages due
to a short across the high-side FET. VIN should be fused to protect the low-side FET. CROWBAR is a
TTL-compatible digital terminal.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range:BOOT to PGND (high-side driver ON) −0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOTLO to PGND −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
BOOT to BOOTLO −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ENABLE, SYNC, and CROWBAR −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IN −0.3 V to 16 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DT −0.3 V to 30 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature soldering 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: Unless otherwise specified, all voltages are with respect to PGND.
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°CDERATING FACTOR TA = 70°C TA = 85°C
PWP with solder‡2668 26.68 mW/°C 1467 1067
PWP without solder‡1024 10.24 mW/°C 563 409
D 749 7.49 mW/°C 412 300
JUNCTION-CASE THERMAL RESISTANCE TABLE
PWP Junction-case thermal resistance 2.07 °C/W
‡Test Board Conditions:
1. Thickness: 0.062I
2. 3I × 3I (for packages <27 mm long)
3. 4I × 4I (for packages >27 mm long)
4. 2-oz copper traces located on the top of the board (0.071 mm thick)
5. Copper areas located on the top and bottom of the PCB for soldering
6. Power and ground planes, 1-oz copper (0.036 mm thick)
7. Thermal vias, 0.33 mm diameter, 1.5 mm pitch
8. Thermal isolation of power plane
For more information, refer to TI technical brief literature number SLMA002.
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.5 15 V
Input voltage BOOT to PGND 4.5 28 V
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted)
supply current
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VCC Supply voltage range 4.5 15 V
V(ENABLE) = LOW, VCC =15 V 100
A
V(ENABLE) = HIGH, VCC =15 V 300 400 µA
VCC Quiescent current V(ENABLE) = HIGH,
f(SWX) = 200 kHz,
C(HIGHDR) = 50 pF,
See Note 2
VCC =12 V,
BOOTLO grounded,
C(LOWDR) = 50 pF, 3 mA
NOTE 2: Ensured by design, not production tested.
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
output drivers
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Duty cycle < 2%,
V(BOOT) – V(BOOTLO) = 4.5 V,
V(HIGHDR) = 4 V 0.7 1.1
High-side sink (see Note 3) Duty cycle < 2%,
tpw < 100 µs
(see Note 2)
V(BOOT) – V(BOOTLO) = 6.5 V,
V(HIGHDR) = 5 V 1.1 1.5 A
(see Note 2)
V(BOOT) – V(BOOTLO) = 12 V,
V(HIGHDR) = 10.5 V 2 2.4
Duty cycle < 2%,
V(BOOT) – V(BOOTLO) = 4.5 V,
V(HIGHDR) = 0.5V 1.2 1.4
Peak output
current
High-side source
(see Note 3)
Duty cycle < 2%,
tpw < 100 µs
(see Note 2)
V(BOOT) – V(BOOTLO) = 6.5 V,
V(HIGHDR) = 1.5 V 1.3 1.6 A
current
(see Note 3)
(see Note 2)
V(BOOT) – V(BOOTLO) = 12 V,
V(HIGHDR) = 1.5 V 2.3 2.7
Duty cycle < 2%,
VCC = 4.5 V, V(LOWDR) = 4 V 1.3 1.8
Low-side sink (see Note 3)
Duty cycle < 2%,
t
pw
< 100 µs
(see Note 2)
VCC = 6.5 V, V(LOWDR) = 5 V 2 2.5 A
Low-side sink (see Note 3)
tpw < 100 µs
(see Note 2) VCC = 12 V, V(LOWDR) = 10.5 V 3 3.5
A
Low-side source
Duty cycle < 2%,
VCC = 4.5 V, VLOWDR)) = 0.5V 1.4 1.7
Low-side source
(see Note 3)
Duty cycle < 2%,
t
pw
< 100 µs
(see Note 2)
VCC = 6.5 V, V(LOWDR)) = 1.5 V 2 2.4 A
(see Note 3)
tpw < 100 µs
(see Note 2) VCC = 12 V, V(LOWDR0) = 1.5 V 2.5 3
A
V(BOOT) – V(BOOTLO) = 4.5 V,
V(HIGHDR)= 0.5 V 5
High-side sink (see Note 3) V(BOOT) – V(BOOTLO) = 6.5 V,
V(HIGHDR) = 0.5 V 5Ω
V(BOOT) – V(BOOTLO) = 12 V,
V(HIGHDR) = 0.5 V 5
V(BOOT) – V(BOOTLO) = 4.5 V,
V(HIGHDR) = 4 V 75
Output
resistance
High-side source (see Note 3) V(BOOT) – V(BOOTLO) = 6.5 V,
V(HIGHDR)= 6 V 75 Ω
resistance
V(BOOT) – V(BOOTLO) = 12 V,
V(HIGHDR) =11.5 V 75
V(DRV) = 4.5 V, V(LOWDR)= 0.5 V 9
Low-side sink (see Note 3) V(DRV) = 6.5 V, V(LOWDR) = 0.5 V 7.5 Ω
Low-side sink (see Note 3)
V(DRV) = 12 V, V(LOWDR) = 0.5 V 6
Ω
V(DRV) = 4.5 V, V(LOWDR) = 4 V 75
Low-side source (see Note 3) V(DRV) = 6.5 V, V(LOWDR)= 6 V 75 Ω
Low-side source (see Note 3)
V(DRV) = 12 V, V(LOWDR) = 11.5 V 75
NOTES: 2: Ensured by design, not production tested.
3. The pullup/pulldown circuits of the drivers are bipolar and MOSFET transistors in parallel. The peak output current rating is the
combined current from the bipolar and MOSFET transistors. The output resistance is the rDS(on) of the MOSFET transistor when
the voltage on the driver output is less than the saturation voltage of the bipolar transistor.
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating virtual junction temperature range,
VCC = 6.5 V, ENABLE = High, CL = 3.3 nF (unless otherwise noted) (continued)
dead-time control
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage
LOWDR
Over the VCC range (see Note 2)
0.7VCC
V
VIL Low-level input voltage LOWDR Over the VCC range (see Note 2) 1V
VIH High-level input voltage
DT
Over the VCC range
2 V
VIL Low-level input voltage
DT
Over the V
CC
range
1 V
NOTE 2: Ensured by design, not production tested.
digital control terminals (IN, CROWBAR, SYNC, ENABLE)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VIH High-level input voltage
Over the VCC range
2 V
VIL Low-level input voltage Over the VCC range 1 V
switching characteristics over recommended operating virtual junction temperature range,
ENABLE = High, CL = 3.3 nF (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
V(BOOT) = 4.5 V, V(BOOTLO) = 0 V 60
HIGHDR output (see Note 2) V(BOOT) = 6.5 V, V(BOOTLO) = 0 V 50 ns
Rise time
HIGHDR output (see Note 2)
V(BOOT) = 12 V, V(BOOTLO) = 0 V 50
ns
Rise time VCC = 4.5 V 40
LOWDR output (see Note 2) VCC = 6.5 V 30 ns
LOWDR output (see Note 2)
VCC = 12 V 30
ns
V(BOOT) = 4.5 V, V(BOOTLO) = 0 V 50
HIGHDR output (see Note 2) V(BOOT) = 6.5 V, V(BOOTLO) = 0 V 40 ns
Fall time
HIGHDR output (see Note 2)
V(BOOT) = 12 V, V(BOOTLO) = 0 V 40
ns
Fall time VCC = 4.5 V 40
LOWDR output (see Note 2) VCC = 6.5 V 30 ns
LOWDR output (see Note 2)
VCC = 12 V 30
ns
HIGHDR going low (excluding
V(BOOT) = 4.5 V, V(BOOTLO) = 0 V 95
HIGHDR going low (excluding
dead time) (see Note 2)
V(BOOT) = 6.5 V, V(BOOTLO) = 0 V 80 ns
Propagation delay time
dead time) (see Note 2)
V(BOOT) = 12 V, V(BOOTLO) = 0 V 70
ns
Propagation delay time LOWDR going high (excluding
dead time) (see Note 2)
V(BOOT) = 4.5 V, V(BOOTLO) = 0 V 80
LOWDR going high (excluding
dead time) (see Note 2)
V(BOOT) = 6.5 V, V(BOOTLO) = 0 V 70 ns
V(BOOT) = 12 V, V(BOOTLO) = 0 V 60
ns
LOWDR going low (excluding
VCC = 4.5 V 80
Propagation delay time LOWDR going low (excluding
dead time) (see Note 2)
VCC = 6.5 V 70 ns
Propagation delay time
dead time) (see Note 2)
VCC = 12 V 60
ns
DT to LOWDR and LOWDR to
VCC = 4.5 V 40 170
Driver nonoverlap time DT to LOWDR and LOWDR to
HIGHDR (see Note 2)
VCC = 6.5 V 25 135 ns
Driver nonoverlap time
HIGHDR (see Note 2)
VCC = 12 V 15 85
ns
NOTE 2: Ensured by design, not production tested.
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 1
10 46 810
15
RISE TIME
vs
SUPPLY VOLTAGE
50
13
VCC − Supply Voltage − V
35
40
45
20
25
30
tr− Rise Time − ns
5791112
Low Side
High Side
CL = 3.3 nF
TJ = 25°C
1514
Figure 2
FALL TIME
vs
SUPPLY VOLTAGE
tf− Fall Time − ns
10 46 810
15
50
13
VCC − Supply Voltage − V
35
40
45
20
25
30
5791112
Low Side
High Side
CL = 3.3 nF
TJ = 25°C
1514
Figure 3
RISE TIME
vs
JUNCTION TEMPERATURE
tr− Rise Time − ns
TJ − Junction Temperature − °C
10 0 50 100
15
50
125
35
40
45
20
25
30
25 75−50 −25
VCC = 6.5 V
CL = 3.3 nF
Low Side
High Side
Figure 4
FALL TIME
vs
JUNCTION TEMPERATURE
tf− Fall Time − ns
TJ − Junction Temperature − °C
10 0 50 100
15
50
125
35
40
45
20
25
30
25 75
Low Side
High Side
VCC = 6.5 V
CL = 3.3 nF
−50 −25
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 5
20 46 810
30
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, LOW TO HIGH LEVEL
150
13
VCC − Supply Voltage − V
70
80
90
40
50
60
5791112
120
130
140
100
110
Low Side
tPLH − Low-to-High Propagation Delay Time − ns
CL = 3.3 nF
TJ = 25°C
1514
Figure 6
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
SUPPLY VOLTAGE, HIGH TO LOW LEVEL
VCC − Supply Voltage − V
20 46 810
30
150
13
70
80
90
40
50
60
5791112
120
130
140
100
110
Low Side
High Side
tPHL − High-to-Low Propagation Delay Time − ns
CL = 3.3 nF
TJ = 25°C
1514
Figure 7
LOW-TO-HIGH PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
20 0 50 100
30
150
125
70
80
90
40
50
60
25 75
120
130
140
100
110
tPLH − Low-to-High Propagation Delay Time − ns
−25−50
VCC = 6.5 V
CL = 3.3 nF
High Side
Low Side
Figure 8
HIGH-TO-LOW PROPAGATION DELAY TIME
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
20 0 50 100
30
150
125
70
80
90
40
50
60
25 75
120
130
140
100
110
tPHL − High-to-Low Propagation Delay Time − ns
Low Side
High Side
VCC = 6.5 V
CL = 3.3 nF
−25−50
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 9
DRIVER-OUTPUT RISE TIME
vs
LOAD CAPACITANCE
CL − Load Capacitance − nF
tr− Rise Time − ns
100
10
1
1000
0.01 1 10 100
VCC = 6.5 V
TJ = 25°C
Low Side
High Side
0.1
Figure 10
DRIVER-OUTPUT FALL TIME
vs
LOAD CAPACITANCE
CL − Load Capacitance − nF
tf− Fall Time − ns
100
10
1
1000
0.01 1 10 100
VCC = 6.5 V
TJ = 25°C
Low Side
High Side
0.1
Figure 11
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
046 810
500
5000
14
3500
4000
4500
1000
1500
2500
12
CC
I Supply Current − −Aµ
2000
3000
300 kHz
200 kHz
100 kHz
50 kHz
25 kHz
16
6000
5500
500 kHz
TJ = 25°C
CL = 50 pF
Figure 12
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
046 810 14
10
12
CC
I Supply Current − mA−
5
16
15
20
25
1 MHz
TJ = 25°C
CL = 50 pF
2 MHz
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 13
PEAK SOURCE CURRENT
vs
SUPPLY VOLTAGE
Peak Source Current − A
VCC − Supply Voltage − V
046 810
0.5
4
14
2.5
3
3.5
1
1.5
2
12
Low Side
High Side
TJ = 25°C
16
Figure 14
PEAK SINK CURRENT
vs
SUPPLY VOLTAGE
Peak Sink Current − A
VCC − Supply Voltage − V
046 810
0.5
4
14
2.5
3
3.5
1
1.5
2
12
Low Side
High Side
TJ = 25°C
16
1.0
1.2
1.4
1.6
1.8
2.0
4 6 8 10 12 14 16
Figure 15
INPUT THRESHOLD VOLTAGE
vs
SUPPLY VOLTAGE
VCC − Supply Voltage − V
VIT − Input Threshold Voltage − V
TJ = 25°C
Figure 16
1.0
1.2
1.4
1.6
1.8
2.0
−50 −25 0 25 50 75 100 125
INPUT THRESHOLD VOLTAGE
vs
JUNCTION TEMPERATURE
TJ − Junction Temperature − °C
VIT − Input Threshold Voltage − V
VCC = 6.5 V
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Figure 17 shows the circuit schematic of a 100-kHz synchronous-buck converter implemented with a TL5001A
pulse-width-modulation (PWM) controller and a TPS2835 driver. The converter operates over an input range from
4.5 V to 12 V and has a 3.3-V output. The circuit can supply 3 A continuous load. The converter achieves an efficiency
of 94% for VIN = 5 V, Iload=1 A, and 93% for VIN = 5 V, Iload = 3 A.
C14
1 µF
R9
90.9 kΩ
R8
121 kΩ
C9
0.22 µF
VCC
RT
FB
COMP
GND
OUT
DTC
SCP
U2
TL5001A
1
2
6
5
8
3
4
7
C1
1 µFR10
1.0 kΩ
R2
1.6 kΩ
C2
0.033 µF
C3
0.0022 µF
C8
0.1 µF
C4
0.022 µFR3
180 Ω
R4
2.32 kΩ
GND
Q2
Si4410
R7
3.3 Ω
C6
1000 pF
VIN
C5
100 µF
C10
100 µF
C11
0.47 µF
3.3 V
C13
10 µF
C7
100 µF
C12
100 µF
Q1
Si4410 L1
27 µH
IN
BOOTLO
HIGHDR
NC
BOOT
ENABLE
CROWBAR
NC
U1
TPS2835
1
2
3
4
14
13
12
11
SYNC
DT
PGND
5
6
7VCC
NC
LOWDR 10
9
8
R1
1 kΩ
C15
1.0 µF
R6
1 MΩ
R5
0 Ω
R11
4.7 Ω
RTN
+
+
++
Figure 17. 3.3-V 3-A Synchronous-Buck Converter Circuit
SLVS223B − NOVEMBER 1999 − REVISED AUGUST 2002
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
Great care should be taken when laying out the PC board. The power-processing section is the most critical
and will generate large amounts of EMI if not properly configured. The junction of Q1, Q2, and L1 should be very
tight. The connection from Q1 drain to the positive sides of C5, C10, and C11 and the connection from Q2 source
to the negative sides of C5, C10, and C11 should be as short as possible. The negative terminals of C7 and
C12 should also be connected to Q2 source.
Next, the traces from the MOSFET driver to the power switches should be considered. The BOOTLO signal from
the junction of Q1 and Q2 carries the large gate drive current pulses and should be as heavy as the gate drive
traces. The bypass capacitor (C14) should be tied directly across VCC and PGND.
The next most sensitive node is the FB node on the controller (terminal 4 on the TL5001A). This node is very
sensitive to noise pickup and should be isolated from the high-current power stage and be as short as possible.
The ground around the controller and low-level circuitry should be tied to the power ground as the output. If these
three areas are properly laid out, the rest of the circuit should not have other EMI problems and the power supply
will be relatively free of noise.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TPS2834D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2834DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2834DR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2834DRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2834PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2834PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2834PWPR ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2834PWPRG4 ACTIVE HTSSOP PWP 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2835D ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2835DG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TPS2835PWP ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2835PWPG4 ACTIVE HTSSOP PWP 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR
TPS2835PWPR ACTIVE HTSSOP PWP 14 TBD Call TI Call TI
TPS2835PWPRG4 ACTIVE HTSSOP PWP 14 TBD Call TI Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 17-Aug-2012
Addendum-Page 2
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TPS2834DR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TPS2834PWPR HTSSOP PWP 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS2834DR SOIC D 14 2500 367.0 367.0 38.0
TPS2834PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 17-Aug-2012
Pack Materials-Page 2
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