SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Suitable for IEEE Standard 896
Applications†
D
SN75ALS056 is an Octal Transceiver
D
SN75ALS057 is a Quad Transceiver
D
High-Speed Advanced Low-Power Schottky
(ALS) Circuitry
D
Low Power Dissipation:
52.5 mW/Channel Max
D
High-Impedance pnp Inputs
D
Logic-Level 1-V Bus Swing Reduces Power
Consumption
D
Trapezoidal Bus Output Waveform Reduces
Noise Coupling to Adjacent Lines
D
Power-Up/Power-Down Protection
(Glitch Free)
D
Open-Collector Driver Outputs Allow
Wired-OR Connections
D
Designed to Be a Faster, Lower-Power
Functional Equivalent of National DS3896,
DS3897
description
The SN75ALS056 is an eight-channel,
monolithic, high-speed, advanced low-power
Schottky (ALS) device designed for two-way data
communication in a densely populated
backplane. The SN75ALS057 is a four-channel
version with independent driver-input (Dn) and
receiver-output (Rn) pins and a separate driver
disable for each driver (En).
These transceivers feature open-collector driver outputs with series Schottky diodes to reduce capacitive
loading to the bus. By using a 2-V pullup termination on the bus, the output signal swing is approximately 1 V,
which reduces the power necessary to drive the bus load capacitance. The driver outputs generate trapezoidal
waveforms that reduce crosstalk between channels. The drivers are capable of driving an equivalent dc load
as low as 18.5 Ω. The receivers have internal low-pass filters to further improve noise immunity.
The SN75ALS056 and SN75ALS057 are characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
A1
A2
A3
A4
VCC
A5
A6
A7
A8
CS
B1
B2
B3
B4
GND
B5
B6
B7
B8
T/R
SN75ALS057 . . . DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
D1
R1
D2
R2
VCC
D3
R3
D4
R4
TE
B1
E1
B2
E2
GND
B3
E3
B4
E4
RE
SN75ALS056 . . . DW OR N PACKAGE
(TOP VIEW)
†The transceivers are suitable for IEEE Standard 896 applications to the extent of the operating conditions and characteristics specified in this
data sheet.
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbol†
SN75ALS056
SN75ALS057
4
3
2
1
11
A4
A3
A2
A1
T/R
B4
B3
B2
B1
17
18
19
20
3EN1 (A-B)
3EN2 (B-A)
1
2
10
CS G3
8
7
A7
A6
A5
B7
B6
B5
13
14
615
9
A8 B8
12
14
6
4
17
3
2
19
1
11
10
E3
D3
R2
E2
D2
R1
E1
D1
RE
TE
B3
B2
B1
15
18
20
EN1 (D-B)
EN2 (B-R)
1
2
B4
13
&
9
12
8
7
R4
E4
D4
R3
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic diagram (positive logic)
SN75ALS057
T/R 11
10
CS
1
A1 B1
20
Xmit
9
A8 B8
12
Rcv
B1
20
Rcv
Xmit
TE 10
RE 11
D1 1
E1 19
2
R1
9
12
8
R4
E4
D4 B4
13
SN75ALS056
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN75ALS056
TRANSMIT/RECEIVE
CONTROLS CHANNELS
CS T/R A ↔ B
L H T(A B)
L L R(B A)
H X D
SN75ALS057
TRANSMIT/RECEIVE
CONTROLS CHANNELS
TE RE En D B B R
L L L D R
LLH T R
LHL D D
LHH T D
HLX D R
HHX D D
H = high level, L = low level, R = receive, T = transmit,
D = disable, X = irrelevant
Direction of data transmission is from An to Bn for the SN75ALS056 and from Dn to Bn for the SN75ALS057.
Direction of data reception is from Bn to An for the SN75ALS056 and from Bn to Rn for the SN75ALS057. Data
transfer is inverting in both directions.
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of inputs and outputs
ESD
Protect
DRIVER OUTPUT RECEIVER INPUT CONTROL INPUTS
RECEIVER OUTPUT DRIVER INPUT
GND
Bn
VCC
GND
40 µA
VCC
GND
48 Ω20 kΩ
An
or
Rn-Dn
SN75ALS057
Only
En
All resistor values shown are nominal.
17.5 kΩ
TE/RE
Input
15 kΩ2.5 kΩ
VCC
ESD
Protect
ESD
Protect
ESD
Protect ESD
Protect†
†Additional ESD protection is on the SN75ALS057, which has separate receiver-output and driver-input pins.
absolute maximum ratings over operating free-air temperature (unless otherwise noted)‡
Supply voltage, VCC (see Note 1) 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver input voltage, VI 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver output voltage, VO 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver input voltage, VI 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver output voltage, VO 5.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: DW or N package 260 °C. . . . . . . . . . . . . . .
‡Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: Voltage values are with respect to network ground terminal.
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 125°C
POWER RATING
DW 1025 mW 8.2 mW/°C 656 mW —
N 1150 mW 9.2 mW/°C 736 mW —
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level driver and control input voltage, VIH 2 V
Low-level driver and control input voltage, VIL 0.8 V
Bus termination voltage 1.9 2.1 V
Operating free-air temperature, TA0 70 °C
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS†
SN75ALS056
UNIT
PARAMETER
TEST
CONDITIONS†
MIN TYP†MAX
UNIT
VIK Input clamp voltage at An, T/R, or CS II = –18 mA –1.5 V
VIT Receiver input threshold voltage at Bn 1.405 1.69 V
VOH High-level output voltage at An Bn at 1.2 V, CS at 0.8 V,
T/R at 0.8V, IOH = – 400 µA2.4 V
An Bn at 2 V ,CS at 0.8 V,
T/R at 0.8 V, IOL = 16 mA 0.5
VOL Low-level output voltage Bn An at 2 V, CS at 0.8 V,
T/R at 2 V, VL = 2 V,
RL =18.5 Ω,, See Figure 1 0.75 1.2 V
An, T/R or CS VI = VCC 40
IIH High-level input current Bn VI = 2 V, VCC = 0 or 5.25 V,
An at 0.8 V, T/R at 0.8 V 100 µA
IIL Low level input current at An, T/R, or CS VI = 0.4 V –400 µA
IOS Short-circuit output current at An An at 0, Bn at 1.2 V,
CS at 0.8 V, T/R at 0.8 V –40 –120 mA
ICC Supply current 75 mA
CO(B) Driver output capacitance 4.5 pF
†Typical values are at VCC = 5 V, TA = 25°C.
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
SN75ALS057
UNIT
PARAMETER
TEST
CONDITIONS
MIN TYP†MAX
UNIT
VIK Input clamp voltage at Dn, En, TE, or RE II = –18 mA –1.5 V
VIT Receiver input threshold voltage at Bn 1.41 1.69 V
VOH High-level output voltage at Rn Bn at 1.2 V, RE at 0.8 V,
IOH = –400 µA2.4 V
Rn Bn at 2 V, RE at 0.8 V,
IOL = 16 mA 0.5
VOL Low-level output voltage Bn Dn at 2 V, En at 2 V,
TE at 0.8 V, VL = 2 V,
RL = 18.5 Ω, See Figure 1 0.75 1.2 V
Dn, En,
TE, or RE VI = VCC 40
IIH High-level input current Bn VI = 2 V, VCC = 0 or 5.25 V,
Dn at 0.8 V, En at 0.8 V,
TE at 0.8 V 100 µA
IIL Low-level input current at Dn, En, TE, or RE VI = 0.4 V –400 µA
IOS Short-circuit output current at Rn Rn at 0, Bn at 1.2 V,
RE at 0.8 V –40 –120 mA
ICC Supply current 40 mA
CO(B) Driver output capacitance 4.5 pF
†Typical values are at VCC = 5 V, TA = 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS SN75ALS056
DRIVER UNIT
(INPUT)
(OUTPUT)
MIN TYP†MAX
tPLH1 Propagation delay time,
low-to-high-level output
CS
Bn
An and T/R at 2 V, VL = 2 V,
RL118ΩC
L30
p
F
24
ns
tPHL1 Propagation delay time,
high-to-low-level output
CS
Bn
R
L
1
=
18
Ω
,,
C
L =
30
p
F
,
RL2 not connected, See Figure 2 20
ns
tPLH2 Propagation delay time,
low-to-high-level output
An
Bn
CS at 0.8 V, T/R at 2 V,
VL = 2 V, RL1 = 18 Ω,,
RL2 not connected CL30
p
F
19
ns
tPHL2 Propagation delay time
high-to-low-level output
An
Bn
R
L
2
no
t
connec
t
e
d
,
C
L =
30
p
F
,
See Figure 2, 18
ns
tPLH3 Propagation delay time,
low-to-high-level output
T/R
Bn
VI(An) = 5 V, CS at 0.8 V,
RL1 = 18 Ω, CL = 30 pF,
RL2 not connected VL=2V
25
ns
tPHL3 Propagation delay time,
high-to-low-level output
T/R
Bn
R
L
2
not
connected
,
V
L =
2
V
,
See Figure 3, 35
ns
tTLH T ransition time,
low-to-high-level output
An
Bn
CS at 0.8 V, T/R at 2 V,
V
L
= 2 V, C
L
= 30 pF, 1 3 11
ns
tTHL Transition time,
high-to-low-level output
An
Bn
L,L,
RL1 = 18 Ω, RL2 not connected,
See Figure 2 1 3 6
ns
†Typical values are at VCC = 5 V, TA = 25°C
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS SN75ALS056
RECEIVER UNIT
(INPUT)
(OUTPUT)
MIN MAX
tPLH4 Propagation delay time,
low-to-high-level output
Bn
An
CS at 0.8 V, T/R at 0.8 V, R
L
1 = 390 Ω,18
ns
tPHL4 Propagation delay time,
high-to-low-level output
Bn
An
,,
L
,
RL2 = 1.6 kΩ, CL = 30 pF, See Figure 4 18
ns
tPLZ1 Output disable time from
low level T/R An CS at 0.8 V, VI(Bn) = 2 V, VL = 5 V,
RL1 = 390 Ω, RL2 not connected,
CL = 15 pF, See Figure 3 20 ns
tPZL1 Output enable time to
low level T/R An CS at 0.8 V, VI(Bn) = 2 V, VL = 5 V,
RL1 = 390 Ω, RL2 = 1.6 kΩ,
CL = 30 pF, See Figure 3 40 ns
tPHZ1 Output disable time from
high level T/R An CS at 0.8 V, VI(Bn) = 0, VL = 0,
RL1 = 390 Ω, RL2 not connected,
CL = 15 pF, See Figure 3 17 ns
tPZH1 Output enable time to
high level T/R An CS at 0.8 V, VI(Bn) = 0, VL = 0,
RL1 not connected, RL2 = 1.6 kΩ,
CL = 30 pF, See Figure 3 15 ns
tPLZ2 Output disable time from
low level CS An Bn at 2 V, T/R at 0.8 V, CL = 5 pF,
VL = 5 V, RL1 = 390 Ω,
RL2 not connected, See Figure 5 18 ns
tPZL2 Output enable time to
low level CS An Bn at 2 V, T/R at 0.8 V, CL = 30 pF,
VL = 5 V, RL1 = 390 Ω, RL2 = 1.6 kΩ,
See Figure 5 15 ns
tPHZ2 Output disable time from
high level CS An Bn at 0.8 V, T/R at 0.8 V, CL = 5 pF,
VL = 0, RL1 = 390 Ω,
RL2 not connected, See Figure 5 8 ns
tPZH2 Output enable time to
high level CS An Bn at 0.8 V, T/R at 0.8 V, CL = 30 pF,
VL = 0, RL1 not connected,
RL2 = 1.6 kΩ, See Figure 5 17 ns
tw(NR) Receiver noise rejection
pulse duration Bn An CS at 0.8 V, T/R at 0.8 V, RL1 = 390 Ω,
RL2 = 1.6 kΩ, CL = 30 pF, VL = 5 V,
See Figure 6 3 ns
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS SN75ALS057
DRIVER UNIT
(INPUT)
(OUTPUT)
MIN TYP†MAX
tPLH1 Propagation delay time,
low-to-high-level output
TE
Bn
Dn, En, RE at 2 V, VL = 2 V,
RL2 not connected RL118Ω
24
ns
tPHL1 Propagation delay time,
high-to-low-level output
TE
Bn
R
L
2
no
t
connec
t
e
d
,
R
L
1
=
18
Ω
,
See Figure 2, CL = 30 pF 20
ns
tPLH2 Propagation delay time,
low-to-high-level output
Dn or En
Bn
TE at 0.8 V, RE at 2 V,
V
L
= 2 V
,
R
L
1 = 18 Ω
,
19
ns
tPHL2 Propagation delay time,
high-to-low-level output
Dn
or
En
Bn
VL
2
V,
R
L
1
18
Ω,
R
L
2 not connected,CL = 30 pF,
See Figure 2 18
ns
tTLH T ransition time,
low-to-high-level output
Dn or En
Bn
RE at 2 V, VL = 2 V,
TE at 0.8 V, RL1 = 18 Ω,, 1 3 11
ns
tTHL Transition time,
high-to-low-level output
Dn
or
En
Bn
,L,,
RL2 not connected, CL = 30 pF,
See Figure 2 1 3 6
ns
†Typical values are at VCC = 5 V, TA = 25°C.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PARAMETER FROM
(INPUT)
TO
(OUTPUT)
TEST CONDITIONS SN75ALS057
RECEIVER UNIT
(INPUT)
(OUTPUT)
MIN MAX
tPLH4 Propagation delay time,
low-to-high-level output
Bn
Rn
RE at 0.8 V, TE at 2 V, VL = 5 V,
RL1 390 ΩRL216kΩC
L30 pF
18
ns
tPHL4 Propagation delay time,
high-to-low-level output
Bn
Rn
R
L
1
=
390
Ω
,,
R
L
2
=
1
.
6
kΩ
,,
C
L =
30
p
F
,
See Figure 4 18
ns
tPLZ2 Output disable time
from low level RE Rn Bn at 2 V, TE at 2 V, VL = 5 V,
CL = 5 pF, RL1 = 390 Ω,
RL2 not connected, See Figure 5 18 ns
tPZL2 Output enable time to
low level RE Rn Bn at 2 V, TE at 2 V, VL = 5 V,
CL = 30 pF, RL1 = 390 Ω, RL2 = 1.6 kΩ,
See Figure 5 15 ns
tPHZ2 Output disable time
from high level RE Rn Bn at 0.8 V, TE at 2 V, VL = 0,
CL = 5 pF, RL1 = 390 Ω,
RL2 not connected, See Figure 5 17 ns
tPZH2 Output enable time to
high level RE Rn Bn at 0.8 V, TE at 2 V, VL = 0,
CL = 30 pF, RL1 not connected,
RL2 = 1.6 kΩ, See Figure 5 17 ns
tw(NR) Receiver noise
rejection pulse duration Bn Rn TE at 2 V, RE at 0.8 V, VL = 0,
RL1 = 390 Ω, RL2 = 1.6 kΩ, CL = 30 pF,
See Figure 6 3 ns
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (continued)
PARAMETER FROM
(INPUT) TO
(OUTPUT) TEST CONDITIONS
SN75ALS057
DRIVER PLUS
RECEIVER UNIT
()
()
MIN MAX
tPLH6 Propagation delay time,
low-to-high-level output
Dn
Rn
RE at 0.8 V, TE at 0.8 V, RL1 = 390 Ω,40
ns
tPHL6 Propagation delay time,
high-to-low-level output
Dn
Rn
L
RL2 = 1.6 kΩ,, CL = 30 pF, See Figure 7 40
ns
PARAMETER MEASUREMENT INFORMATION
VL
VO
(Bn)
SN75ALS056
or
SN75ALS057
RL1
Figure 1. Driver Low-Level-Output-Voltage Test Circuit
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
VOLTAGE WAVEFORMS
CS, TE 1.5 V
tPHL1
1.5 V
tPHL2
tTHL
90% 1.55 V
10%
tPLH1
3 V
0
3 V
0
(An, Dn, En)
VOH
VOL
VO(Bn) 90%
tTLH
10%
1.55 V
1.5 V
1.5 V
VI
(Bn)
RL1
VO
VL
CL (includes jig capacitance)
SN75ALS056
or
SN75ALS057
VI(CS, TE, An, Dn, En)
tPLH2
RL2
NOTE A: tr = tf ≤ 5 ns from 10% to 90%
Figure 2. Driver Test Circuit and Voltage Waveforms
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
VOLTAGE WAVEFORMS
RL2
VL
RL1
O
V
CL (includes jig capacitance)
(Bn,An)
SN75ALS056
VI(T/R)
VI(An, Bn)
1.55 V
1.5 V
1.55 V
1.5 V
tPZH1
tPZL1
tPLH3
1.5 V
3 V
0
tPHL3
VI(T/R)
1.5 V
tPLZ1
tPHZ1 0.5 V
0.5 V
VO(Bn)
VO(An)
VO(An)
5 V
15 pF
390 Ω
S1
S1 Closed
S2 Open
S1 Open
S2 Closed
S2
1.6 kΩ
NOTE A: tr = tf ≤ 5 ns from 10% to 90%
Figure 3. Propagation Delay From T/R to An or Bn Test Circuit and Voltage Waveforms
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TEST CIRCUIT
VOLTAGE WAVEFORMS
tPHL4
1.55 V
1.5 V
VO(An, Rn)
VI(Bn)
VOL
VOH
1 V
2 V
1.5 V
tPLH4
1.55 V
CL (includes jig capacitance)
(An,Rn) VO
5 V
VI(Bn)
RL2
RL1
SN75ALS056
or
SN75ALS057
NOTE A: tr = tf ≤ 5 ns from 10% to 90%
Figure 4. Receiver Test Circuit and Voltage Waveforms
TEST CIRCUIT
VOLTAGE WAVEFORMS
tPZH2
tPZL2
1.5 V
1.5 V
1.5 V
0.5 V
0.5 V
tPLZ2
tPHZ2
1.5 V
0
3 V
VO(An, Rn)
VL
RL1
RL2CL (includes jig capacitance)
(An,Rn) VO
VI(CS, RE) SN75ALS056
or
SN75ALS057
VO(An, Rn)
VI(CS, RE)
NOTE A: tr = tf ≤ 5 ns from 10% to 90%
Figure 5. Propagation Delay From CS to An or RE to Rn Test Circuit and Voltage Waveforms
SN75ALS056, SN75ALS057
TRAPEZOIDAL-WAVEFORM INTERFACE BUS TRANSCEIVERS
SLLS028G – AUGUST 1987 – REVISED JUNE 1998
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
TEST CIRCUIT
Bus Logic
Low Level
tw is increased until the output voltage
fall just reaches 2 V.
High Level
Bus Logic
tw is increased until the output voltage rise
just reaches 0.8 V.
VOLTAGE WAVEFORMS
1.25 V
2 V
1.55 V
tw(NR)
tw(NR)
1.55 V
V1
1.85 V
1.1 V
(An, Rn)
5 V
VO
SN75ALS057
or
SN75ALS056
VI(Bn)
RL1
RL2CL (includes jig capacitance)
NOTE A: tr = tf ≤ 5 ns from 10% to 90%
Figure 6. Receiver Noise-Immunity Test Circuit and Voltage Waveforms
TEST CIRCUIT
VOLTAGE WAVEFORMS
tPHL6
1.5 V
1.5 V
tPLH6
1.5 V
1.5 V
VO(Rn)
0
3 V
VI(Dn)
30 pF
2 V
18 Ω
(Rn)
5 V
VO
SN75ALS057
(Bn)
RL1
RL2CL (includes jig capacitance)
VI(Dn)
NOTE A: tr = tf ≤ 5 ns from 10% to 90%
Figure 7. Driver Plus Receiver Delay-Times Test Circuits and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN75ALS056DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS056DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS056DWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS056DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS056DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS056N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75ALS056NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75ALS057DW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS057DWE4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS057DWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS057DWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS057DWRE4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS057DWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75ALS057N ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN75ALS057NE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN75ALS056DWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
SN75ALS057DWR SOIC DW 20 2000 330.0 24.4 10.8 13.1 2.65 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN75ALS056DWR SOIC DW 20 2000 367.0 367.0 45.0
SN75ALS057DWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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