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SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
1
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DRail-To-Rail Output
DWide Bandwidth ...3 MHz
DHigh Slew Rate ...2 .4 V/µs
DSupply Voltage Range . . . 2.7 V to 16 V
DSupply Current . . . 550 µA/Channel
DInput Noise Voltage . . . 39 nV/√Hz
DInput Bias Current...1 pA
DSpecified Temperature Range
0°C to 70°C . . . Commercial Grade
−40°C to 125°C . . . Industrial Grade
DUltrasmall Packaging
− 5 Pin SOT-23 (TLV271)
− 8 Pin MSOP (TLV272)
DIdeal Upgrade for TLC27x Family
description
The TLV27x takes the minimum operating supply voltage down to 2.7 V over the extended industrial
temperature range while adding the rail-to-rail output swing feature. This makes it an ideal alternative to the
TLC27x family for applications where rail-to-rail output swings are essential. The TLV27x also provides 3-MHz
bandwidth from only 550 µA.
Like the TLC27x, the TLV27x is fully specified for 5-V and ±5-V supplies. The maximum recommended supply
voltage i s 1 6 V, which allows the devices to be operated from a variety of rechargeable cells (±8 V supplies down
to ±1.35 V).
The CMOS inputs enable use in high-impedance sensor interfaces, with the lower voltage operation making
an attractive alternative for the TLC27x in battery-powered applications.
All members are available in PDIP and SOIC with the singles in the small SOT-23 package, duals in the MSOP,
and quads in the TSSOP package.
The 2.7-V operation makes it compatible with Li-Ion powered systems and the operating supply voltage range
of many micropower microcontrollers available today including TI’s MSP430.
SELECTION OF SIGNAL AMPLIFIER PRODUCTS†
DEVICE VDD (V) VIO
(µV) Iq/Ch
(µA) IIB (pA) GBW
(MHz) SR
(V/µs) SHUTDOWN RAIL-
TO-
RAIL SINGLES/DUALS/QUADS
TLV27x 2.7−16 500 550 1 3 2.4 — O S/D/Q
TLC27x 3−16 1100 675 1 1.7 3.6 — — S/D/Q
TLV237x 2.7−16 500 550 1 3 2.4 Yes I/O S/D/Q
TLC227x 4−16 300 1100 1 2.2 3.6 — O D/Q
TLV246x 2.7−6 150 550 1300 6.4 1.6 Yes I/O S/D/Q
TLV247x 2.7−6 250 600 2 2.8 1.5 Yes I/O S/D/Q
TLV244x 2.7−10 300 725 1 1.8 1.4 — O D/Q
†Typical values measured at 5 V, 25°C
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications o
f
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
!"#$%&'#! ( )*$$+!' &( #" ,*-.)&'#! /&'+0
$#/*)'( )#!"#$% '# (,+)")&'#!( ,+$ '+ '+$%( #" +1&( !('$*%+!'(
('&!/&$/ 2&$$&!'30 $#/*)'#! ,$#)+((!4 /#+( !#' !+)+((&$.3 !).*/+
'+('!4 #" &.. ,&$&%+'+$(0
Copyright 2001−2004, Texas Instruments Incorporated
Operational Amplifier
+
−
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
2WWW.TI.COM
FAMILY PACKAGE TABLE
DEVICE
NUMBER OF
PACKAGE TYPES
SHUTDOWN
UNIVERSAL
DEVICE
NUMBER OF
CHANNELS PDIP SOIC SOT-23 TSSOP MSOP
SHUTDOWN
UNIVERSAL
EVM BOARD
TLV271 1 8 8 5 — — —
Refer to the EVM
TLV272 2 8 8 — — 8 —
Refer to the EVM
Selection Guide
(Lit# SLOU060)
TLV274 4 14 14 — 14 — —
Selection Guide
(Lit# SLOU060)
TLV271 AVAILABLE OPTIONS
VIOMAX AT
PACKAGED DEVICES
T
A
VIOMAX AT
25
°
C
SMALL OUTLINE
†
SOT-23
PLASTIC DIP
TA
25°C
SMALL OUTLINE
(D)†(DBV)‡SYMBOL
PLASTIC DIP
(P)
0°C to 70°C
5 mV
TLV271CD TLV271CDBV VBHC —
−40°C to 125°C
5 mV
TLV271ID TLV271IDBV VBHI TLV271IP
†This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV271IDR).
‡This package is only available taped and reeled. For standard quantities (3,000 pieces per reel), add an R suf fix (e.g., TLV270IDBVR). For smaller
quantities (250 pieces per mini-reel), add a T suffix to the part number (e.g., TLV270IDBVT).
TLV272 AVAILABLE OPTIONS
VIOMAX AT
PACKAGED DEVICES
T
A
VIOMAX AT
25
°
C
SMALL OUTLINE
§
MSOP
PLASTIC DIP
TA
25°C
SMALL OUTLINE
(D)§(DGK)§SYMBOL
PLASTIC DIP
(P)
0°C to 70°C
5 mV
TLV272CD TLV272CDGK AVF —
−40°C to 125°C
5 mV
TLV272ID TLV272IDGK AVG TLV272IP
§This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV272IDR).
TLV274 AVAILABLE OPTIONS
PACKAGED DEVICES
TAVIOMAX AT 25°CSMALL OUTLINE
(D)¶PLASTIC DIP
(N) TSSOP
(PW)¶
0°C to 70°C
5 mV
TLV274CD — TLV274CPW
−40°C to 125°C
5 mV
TLV274ID TLV274IN TLV274IPW
¶This package is available taped and reeled. To order this packaging option, add an R suf fix to the part number (e.g., TLV274IDR).
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TLV27x PACKAGE PINOUTS(1)
3
2
4
5
(TOP VIEW)
1
OUT
GND
IN+
VDD
IN−
TLV271
DBV PACKAGE
1
2
3
4
8
7
6
5
NC
IN−
IN+
GND
NC
VDD
OUT
NC
TLV271
D OR P PACKAGE
(TOP VIEW)
1
2
3
4
8
7
6
5
1OUT
1IN−
1IN+
GND
VDD
2OUT
2IN−
2IN+
TLV272
D, DGK, OR P PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1OUT
1IN−
1IN+
VDD
2IN+
2IN−
2OUT
4OUT
4IN−
4IN+
GND
3IN+
3IN−
3OUT
(TOP VIEW)
TLV274
D, N, OR PW PACKAGE
NC − No internal connection
(1) SOT−23 may or may not be indicated
TYPICAL PIN 1 INDICATORS
Printed or
Molded Dot Bevel Edges
Pin 1
Molded ”U” Shape
Pin 1
Stripe Pin 1 Pin 1
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SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
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absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VDD (see Note 1) 16.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential input voltage, VID ±VDD
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) −0.2 V to VDD + 0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current range, II ±10 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output current range, IO ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I suffix −40°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum junction temperature, TJ 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values, except differential voltages, are with respect to GND.
DISSIPATION RATING TABLE
PACKAGE θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING TA = 25°C
POWER RATING
D (8) 38.3 176 710 mW 396 mW
D (14) 26.9 122.3 1022 mW 531 mW
D (16) 25.7 114.7 1090 mW 567 mW
DBV (5) 55 324.1 385 mW 201 mW
DBV (6) 55 294.3 425 mW 221 mW
DGK (8) 54.23 259.96 481 mW 250 mW
DGS (10) 54.1 257.71 485 mW 252 mW
N (14, 16) 32 78 1600 mW 833 mW
P (8) 41 104 1200 mW 625 mW
PW (14) 29.3 173.6 720 mW 374 mW
PW (16) 28.7 161.4 774 mW 403 mW
recommended operating conditions
MIN MAX UNIT
Supply voltage, VDD
Single supply 2.7 16
V
Supply voltage, VDD Split supply ±1.35 ±8V
Common-mode input voltage range, VICR 0 VDD−1.35 V
Operating free-air temperature, TA
C-suffix 0 70
°C
Operating free-air temperature, T
AI-suffix −40 125 °
C
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electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless
otherwise noted)
dc performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VIO
Input offset voltage
VIC = VDD/2,
VO = VDD/2,
25°C 0.5 5
mV
VIO Input offset voltage VIC = VDD/2,
RL = 10 kΩ
VO = VDD/2,
RS = 50 Ω
Full range 7mV
VIO
Offset voltage drift
R
L
= 10 k
Ω,
RS = 50 Ω
25°C
2
V/°C
α
VIO
Offset voltage drift
RL = 10 k ,
RS = 50
25°C 2 µV/°C
VIC = 0 to VDD−1.35V,
VDD = 2.7 V
25°C 58 70
VIC = 0 to VDD−1.35V,
RS = 50 ΩVDD = 2.7 V Full range 55
CMRR
Common-mode rejection ratio
VIC = 0 to VDD−1.35V,
VDD = 5 V
25°C 65 80
dB
CMRR Common-mode rejection ratio
VIC = 0 to VDD−1.35V,
RS = 50 Ω,VDD = 5 V Full range 62 dB
VIC = −5 to VDD−1.35V,
VDD = ±5 V
25°C 69 85
VIC = −5 to VDD−1.35V,
RS = 50 Ω,VDD = ±5 V Full range 66
VDD = 2.7 V
25°C 97 106
VDD = 2.7 V Full range 76
AVD
Large-signal differential voltage
VO(PP) = VDD/2,
VDD = 5 V
25°C 100 110
dB
AVD
Large-signal differential voltage
amplification
VO(PP) = VDD/2,
RL = 10 kΩVDD = 5 V Full range 86 dB
amplification
RL = 10 k
VDD = ±5 V
25°C 100 115
VDD = ±5 V Full range 90
†Full range is 0°C to 70°C for C suffix and full range is −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
input characteristics
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
25°C 1 60
I
IO
Input offset current 70°C 100 pA
IIO
Input offset current
VDD = 5 V, VIC = VDD/2,
125°C 1000
pA
VDD = 5 V, VIC = VDD/2,
VO = VDD/2, RS = 50 Ω25°C 1 60
I
IB
Input bias current
VO = VDD/2, RS = 50
70°C 100 pA
IIB
Input bias current
125°C 1000
pA
ri(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 21 kHz 25°C 8 pF
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electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless
otherwise noted)
output characteristics
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VDD = 2.7 V
25°C 2.55 2.58
VDD = 2.7 V Full range 2.48
VIC = VDD/2, IOH = −1 mA
VDD = 5 V
25°C 4.9 4.93
VIC = VDD/2, IOH = −1 mA VDD = 5 V Full range 4.85
VDD = ±5 V
25°C 4.92 4.96
VOH
High-level output voltage
VDD = ±5 V Full range 4.9
V
VOH High-level output voltage
VDD = 2.7 V
25°C 1.9 2.1 V
VDD = 2.7 V Full range 1.5
VIC = VDD/2, IOH = −5 mA
VDD = 5 V
25°C 4.6 4.68
VIC = VDD/2, IOH = −5 mA VDD = 5 V Full range 4.5
VDD = ±5 V
25°C 4.7 4.84
VDD = ±5 V Full range 4.65
VDD = 2.7 V
25°C 0.1 0.15
VDD = 2.7 V Full range 0.22
VIC = VDD/2, IOL = 1 mA
VDD = 5 V
25°C 0.05 0.1
VIC = VDD/2, IOL = 1 mA VDD = 5 V Full range 0.15
VDD = ±5 V
25°C −4.95 −4.92
VOL
Low-level output voltage
VDD = ±5 V Full range −4.9
V
VOL Low-level output voltage
VDD = 2.7 V
25°C 0.5 0.7 V
VDD = 2.7 V Full range 1.1
VIC = VDD/2, IOL = 5 mA
VDD = 5 V
25°C 0.28 0.4
VIC = VDD/2, IOL = 5 mA VDD = 5 V Full range 0.5
VDD = ±5 V
25°C −4.84 −4.7
VDD = ±5 V Full range −4.65
VO = 0.5 V from rail, VDD = 2.7 V
Positive rail 25°C 4
V
O
= 0.5 V from rail, V
DD
= 2.7 V
Negative rail 25°C 5
IO
Output current
VO = 0.5 V from rail, VDD = 5 V
Positive rail 25°C 7
mA
I
O
Output current
V
O
= 0.5 V from rail, V
DD
= 5 V
Negative rail 25°C 8
mA
VO = 0.5 V from rail, VDD = 10 V
Positive rail 25°C 13
V
O
= 0.5 V from rail, V
DD
= 10 V
Negative rail 25°C 12
†Full range is 0°C to 70°C for C suffix and full range is −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
‡Depending on package dissipation rating
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SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
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electrical characteristics at specified free-air temperature, VDD = 2.7 V, 5 V, and ±5 V (unless
otherwise noted) (continued)
power supply
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
VDD = 2.7 V 25°C 470 560
IDD
Supply current (per channel)
VO = VDD/2
VDD = 5 V 25°C 550 660
µA
I
DD
Supply current (per channel)
V
O
= V
DD
/2
VDD = 10 V
25°C 625 800 µ
A
V
DD
= 10 V
Full range 1000
PSRR
Supply voltage rejection ratio
VDD = 2.7 V to 16 V,
VIC = VDD/2,
25°C 70 80
dB
PSRR
Supply voltage rejection ratio
(∆VDD /∆VIO)
VDD = 2.7 V to 16 V,
No load
VIC = VDD/2,
Full range 65 dB
†Full range is 0°C to 70°C for C suffix and full range is −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
dynamic performance
PARAMETER TEST CONDITIONS TA†MIN TYP MAX UNIT
UGBW
Unity gain bandwidth
RL = 2 kΩCL = 10 pF
VDD = 2.7 V 25°C 2.4
MHz
UGBW Unity gain bandwidth
R
L
= 2 k
Ω,
C
L
= 10 pF
VDD = 5 V to 10 V 25°C 3 MHz
VDD = 2.7 V
25°C1.35 2.1
V/ s
VDD = 2.7 V Full range 1V/µs
SR
Slew rate at unity gain
VO(PP) = VDD/2,
VDD = 5 V
25°C1.45 2.4
V/ s
SR Slew rate at unity gain
VO(PP) = VDD/2,
CL = 50 pF, RL = 10 kΩ,VDD = 5 V Full range 1.2 V/µs
CL = 50 pF, RL = 10 k ,
VDD = ±5 V
25°C1.8 2.6
V/ s
VDD = ±5 V Full range 1.3 V/µs
φmPhase margin RL = 2 kΩCL = 10 pF 25°C 65 °
Gain margin RL = 2 kΩCL = 10 pF 25°C 18 dB
ts
Settling time
VDD = 2.7 V,
V(STEP)PP = 1 V, AV = −1,
CL = 10 pF, RL = 2 kΩ0.1%
25°C
2.9
s
tsSettling time VDD = 5 V, ±5 V,
V(STEP)PP = 1 V, AV = −1,
CL = 47 pF, RL = 2 kΩ0.1%
25°C
2
µs
†Full range is 0°C to 70°C for C suffix and full range is −40°C to 125°C for I suffix. If not specified, full range is −40°C to 125°C.
noise/distortion performance
PARAMETER TEST CONDITIONS TAMIN TYP MAX UNIT
VDD = 2.7 V,
AV = 1 0.02%
VDD = 2.7 V,
V
O(PP)
= V
DD
/2 V,
R = 2 k , f = 10 kHz
AV = 10 25°C0.05%
THD + N
Total harmonic distortion plus noise
VO(PP) = VDD/2 V,
RL = 2 kΩ, f = 10 kHz AV = 100
25 C
0.18%
THD + N Total harmonic distortion plus noise
VDD = 5 V, ±5 V,
AV = 1 0.02%
VDD = 5 V, ±5 V,
V
O(PP)
= V
DD
/2 V,
R = 2 k , f = 10K
AV = 10 25°C0.09%
VO(PP) = VDD/2 V,
RL = 2 kΩ, f = 10K AV = 100
25 C
0.50%
Vn
Equivalent input noise voltage
f = 1 kHz
25°C
39
nV/√Hz
VnEquivalent input noise voltage f = 10 kHz 25°C35
nV/√Hz
InEquivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
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TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
CMRR Common-mode rejection ratio vs Frequency 1
Input bias and offset current vs Free-air temperature 2
VOL Low-level output voltage vs Low-level output current 3, 5, 7
VOH High-level output voltage vs High-level output current 4, 6, 8
VO(PP) Peak-to-peak output voltage vs Frequency 9
IDD Supply current vs Supply voltage 10
PSRR Power supply rejection ratio vs Frequency 11
AVD Differential voltage gain & phase vs Frequency 12
Gain-bandwidth product vs Free-air temperature 13
SR
Slew rate
vs Supply voltage 14
SR Slew rate vs Free-air temperature 15
φmPhase margin vs Capacitive load 16
VnEquivalent input noise voltage vs Frequency 17
Voltage-follower large-signal pulse response 18, 19
Voltage-follower small-signal pulse response 20
Inverting large-signal response 21, 22
Inverting small-signal response 23
Crosstalk vs Frequency 24
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TYPICAL CHARACTERISTICS
Figure 1
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M
COMMON-MODE REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
CMRR − Common-Mode Rejection Ratio − dB
VDD = 5 V, 10 V
VDD = 2.7 V
Figure 2
−50
0
50
100
150
200
250
300
−40−25−10 5 20 35 50 65 80 95 110 12
5
VDD = 2.7 V, 5 V and 10 V
VIC = VDD/2
TA − Free-Air Temperature − °C
INPUT BIAS AND OFFSET CURREN
T
vs
FREE-AIR TEMPERATURE
− Input Bias and Offset Current − pA
IIB IIO
Figure 3
0.00
0.40
0.80
1.20
1.60
2.00
2.40
2.80
0 2 4 6 8 10 12 14 16 18 20 22 24
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD = 2.7 V
OL
V − Low-Level Output Voltage − V
TA = 25 °C
TA = 125 °C
TA = 70 °C
TA = 0 °C
TA = 40 °C
Figure 4
0.00
0.40
0.80
1.20
1.60
2.00
2.40
2.80
0123456789101112
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
VDD = 2.7 V
TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
TA =−40°C
Figure 5
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
VDD = 5 V
OL
V − Low-Level Output Voltage − V
TA = 125 °C
TA = 70 °C
TA = 25 °C
TA = 0 °C
TA = −40 °C
Figure 6
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
0 5 10 15 20 25 30 35 40 45
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
VCC = 5 V
TA = −40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 125°C
Figure 7
0
2
4
6
8
10
0 20 40 60 80 100 120
TA =125°C
TA =70°C
TA =25°C
TA =0°C
TA =−40°C
VDD = 10 V
LOW-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT CURRENT
IOL − Low-Level Output Current − mA
OL
V − Low-Level Output Voltage − V
Figure 8
0
2
4
6
8
10
020 40 60 80 100 120
VDD = 10 V
TA = −40°C
TA = 0°C
TA = 25°C
TA = 70°C
TA = 125°C
HIGH-LEVEL OUTPUT VOLTAGE
vs
HIGH-LEVEL OUTPUT CURRENT
IOH − High-Level Output Current − mA
VOH − High-Level Output Voltage − V
Figure 9
0
1
2
3
4
5
6
7
8
9
10
11
10 100 1 k 10 k 100 k 1 M 10 M
PEAK-TO-PEAK OUTPUT VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
− Peak-to-Peak Output Voltage − V
VO(PP)
AV = −10
RL = 2 kΩ
CL = 10 pF
TA = 25°C
THD = 5%
VDD = 10 V
VDD = 5 V
VDD = 2.7 V
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SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
10 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 10
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SUPPLY CURRENT
vs
SUPPLY VOLTAGE
VDD − Supply Voltage − V
DD
I Supply Current − mA/ch−
AV = 1
VIC = VDD / 2 TA = 125°C
TA = 70°C
TA = 25°C
TA = 0°C
TA = −40°C
Figure 11
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M
VDD = 5 V, 10 V
TA = 25°C
VDD = 2.7 V
POWER SUPPLY REJECTION RATIO
vs
FREQUENCY
f − Frequency − Hz
PSRR − Power Supply Rejection Ratio − dB
Figure 12
−40
−20
0
20
40
60
80
100
120
10 100 1 k 10 k 100 k 1 M 10 M
−180
−135
−90
−45
0
45
90
135
180
DIFFERENTIAL VOLTAGE GAIN AND PHASE
vs
FREQUENCY
f − Frequency − Hz
− Differential Voltage Gain − dB
Phase − °
VDD=5 V
RL=2 kΩ
CL=10 pF
TA=25°C
AVD
Phase
Gain
Figure 13
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
−40−25−10 5 20 35 50 65 80 95 110 125
GAIN BANDWIDTH PRODUCT
vs
FREE-AIR TEMPERATURE
GBWP −Gain Bandwidth Product − MHz
TA − Free-Air Temperature − °C
VDD = 10 V
VDD = 2.7 V
VDD = 5 V
Figure 14
0.0
0.5
1.0
1.5
2.0
2.5
3.0
2.5 4.5 6.5 8.5 10.5 12.5 14.5
SLEW RATE
vs
SUPPLY VOLTAGE
SR − Slew Rate − V/
VCC − Supply Voltage −V
AV = 1
RL = 10 kΩ
CL = 50 pF
TA = 25°C
SR−
SR+
sµ
Figure 15
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
−40 −25−10 5 20 35 50 65 80 95 110 125
SLEW RATE
vs
FREE-AIR TEMPERATURE
TA − Free-Air Temperature − °C
SR+
SR−
SR − Slew Rate − V/
VDD = 5 V
AV = 1
RL = 10 kΩ
CL = 50 pF
VI = 3 V
sµ
Figure 16
0
10
20
30
40
50
60
70
80
90
100
10 100 1000
PHASE MARGIN
vs
CAPACITIVE LOAD
CL − Capacitive Load − pF
VDD = 5 V
RL= 2 kΩ
TA = 25°C
AV = Open Loop
Phase Margin − °
Rnull = 100
Rnull = 0
Rnull = 50
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
11
WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 17
0
10
20
30
40
50
60
70
80
90
100
10 100 1 k 10 k 100 k
EQUIVALENT INPUT NOISE VOLTAGE
vs
FREQUENCY
f − Frequency − Hz
nV/ Hz− Equivalent Input Noise Voltage −Vn
VDD = 2.7, 5, 10 V
TA = 25°C
Figure 18
0
1
2
3
4
024681012141618
0
1
2
3
VI
t − Time − µs
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
VI− Input Voltage − V
VO
VO− Output Voltage − V
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
Figure 19
0
2
4
6
8
0246810 12 14 16 18
6
4
2
0
VI
t − Time − µs
VDD = 10 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 6 VPP
TA = 25°C
VI− Input Voltage − V
VO
VO− Output Voltage − V
VOLTAGE-FOLLOWER LARGE-SIGNAL
PULSE RESPONSE
Figure 20
0.00
0.04
0.08
0.12
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8
0.00
0.04
0.08
0.12
VI
t − Time − µs
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVPP
TA = 25°C
VI− Input Voltage − mV
VO
VO− Output Voltage − mV
VOLTAGE-FOLLOWER SMALL-SIGNAL
PULSE RESPONSE
Figure 21
246810 12 14 16
VI
t − Time − µs
VDD = 5 V
AV = 1
RL = 2 kΩ
CL = 10 pF
VI = 3 VPP
TA = 25°C
VI− Input Voltage − V
VO
VO− Output Voltage − V
4
3
2
1
0
0
1
2
3
INVERTING LARGE-SIGNAL RESPONSE
20
Figure 22
0
2
4
6
8
0246810121416
6
4
2
0
t − Time − µs
INVERTING LARGE-SIGNAL RESPONSE
VDD = 10 V
AV = VI = −1
RL = 2 kΩ
CL = 10 pF
TA = 25°C
VO
− Output Voltage − VVO
VI
− Input Voltage − VVI
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
12 WWW.TI.COM
TYPICAL CHARACTERISTICS
Figure 23
0.00
0.05
0.10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
0.00
0.05
0.10
INVERTING SMALL-SIGNAL RESPONSE
VDD = 5 V
AV = VI = −1
RL = 2 kΩ
CL = 10 pF
VI = 100 mVpp
TA = 25°CVO
− Output Voltage − VVO
VI
− Input Voltage − VVI
t − Time − µs
Figure 24
−140
−120
−100
−80
−60
−40
−20
0
10 100 1 k 10 k 100 k
CROSSTALK
vs
FREQUENCY
f − Frequency − Hz
VDD = 2.7, 5, & 15 V
VI = 1 VDD/2
AV = 1
RL = 2 kΩ
TA = 25°C
Crosstalk − dB
Crosstalk
APPLICATION INFORMATION
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as shown
in Figure 25. A minimum value of 20 Ω should work well for most applications.
CLOAD
RF
Input Output
RGRNULL
+
−
VDD/2
Figure 25. Driving a Capacitive Load
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
13
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APPLICATION INFORMATION
offset voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
VOO +VIOǒ1)ǒRF
RGǓǓ"IIB)RSǒ1)ǒRF
RGǓǓ"IIB– RF
+
−
VI+
RG
RS
RF
IIB−
VO
IIB+
Figure 26. Output Offset Voltage Model
general configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into the system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see Figure 27).
VIVO
C1
+
−
RGRF
R1
f–3dB +1
2pR1C1
VO
VI+ǒ1)RF
RGǓǒ1
1)sR1C1Ǔ
VDD/2
Figure 27. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
VI
C2
R2R1
C1
RF
RG
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
(
=1
Q
2 − )
RGRF
_
+f–3dB +1
2pRC
VDD/2
Figure 28. 2-Pole Low-Pass Sallen-Key Filter
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
14 WWW.TI.COM
APPLICATION INFORMATION
circuit layout considerations
To achieve the levels of high performance of the TLV27x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
DGround planes—It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and
output, the ground plane can be removed to minimize the stray capacitance.
DProper power supply decoupling—Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic
capacitor on each supply terminal. It may be possible to share the tantalum among several amplifiers
depending on the application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal
of every amplifier. In addition, the 0.1-µF capacitor should be placed as close as possible to the supply
terminal. As this distance increases, the inductance in the connecting trace makes the capacitor less
effective. The designer should strive for distances of less than 0.1 inches between the device power
terminals and the ceramic capacitors.
DSockets—Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board
is the best implementation.
DShort trace runs/compact part placements—Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of
the amplifier . Its length should be kept as short as possible. This helps to minimize stray capacitance at the
input of the amplifier.
DSurface-mount passive components—Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be
kept as short as possible.
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
15
WWW.TI.COM
APPLICATION INFORMATION
general power dissipation considerations
For a given θJA, the maximum power dissipation is shown in Figure 29 and is calculated by the following formula:
PD+ǒTMAX–TA
qJA Ǔ
Where: PD= Maximum power dissipation of TLV27x IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-ambient air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
1
0.75
0.5
0
−55−40 −25 −10 5
Maximum Power Dissipation − W
1.25
1.5
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
1.75
20 35 50
0.25
TA − Free-Air Temperature − °C
2
65 80 95 110 125
MSOP Package
Low-K Test PCB
θJA = 260°C/W
TJ = 150°C
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOIC Package
Low-K Test PCB
θJA = 176°C/W
SOT-23 Package
Low-K Test PCB
θJA = 324°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 29. Maximum Power Dissipation vs Free-Air Temperature
µ
SLOS351D − MARCH 2001 − REVISED FEBRUAR Y 2004
16 WWW.TI.COM
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim PartsRelease 9.1, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 4) and subcircuit in Figure 30 are
generated using TLV27x typical electrical and operating characteristics at TA = 25°C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
DMaximum positive output voltage swing
DMaximum negative output voltage swing
DSlew rate
DQuiescent power dissipation
DInput bias current
DOpen-loop voltage amplification
DUnity-gain frequency
DCommon-mode rejection ratio
DPhase margin
DDC output resistance
DAC output resistance
DShort-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
*DEVICE=amp_tlv27x_highVdd,OP AMP,NJF,INT
* amp_tlv_27x_highVdd operational amplifier ”macromodel”
* subcircuit updated using Model Editor release 9.1 on 05/15/00
* at 14:40 Model Editor is an OrCAD product.
*
* connections: non-inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt amp_tlv27x_highVdd 1 2 3 4 5
*c1 11 12 457.48E−15
c2 6 7 5.0000E−12
css 10 99 1.1431E−12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
176.02E6 −1E3 1E3 180E6
−180E6
ga 6 0 11 12 16.272E−6
gcm 0 6 10 99 6.8698E−9
iss 10 4 dc 1.3371E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
J2 12 1 10 jx2
r2 6 9 100.00E3
rd1 3 11 61.456E3
rd2 3 12 61.456E3
ro1 8 5 10
ro2 7 99 10
rp 3 4 150.51E3
rss 10 99 149.58E6
vb 9 0 dc 0
vc 3 53 dc .78905
ve 54 4 dc .78905
vlim 7 8 dc 0
vlp 91 0 dc 14.200
vln 0 92 dc 14.200
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
.model jx2 NJF(Is=500.00E−15 Beta=198.03E−6 Vto=−1)
.ends
IN− G
D
S
D
S
G
rp
IN+
rd1 rd2 rss egnd fb ro2
ro1
vlim
OUT
ga
ioffgcm
vb
c1
dc
iss
dp
GND
VDD
css
c2
ve de
dlp dln
vlnhlimvlp
10
4
1
11 12
3
53
54
96
8
5
7
91 90 92
vc
99
+
+
+
+
+
+
+
−
−
−
−
−−
−
−+
r2
2
Figure 30. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV271CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271IDBVR ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271IDBVRG4 ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271IDBVT ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271IDBVTG4 ACTIVE SOT-23 DBV 5 250 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV271IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV271IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV272CD ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272CDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 2
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV272CDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272CDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272CDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272CDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272CDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272ID ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDG4 ACTIVE SOIC D 8 75 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDGK ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDGKG4 ACTIVE VSSOP DGK 8 80 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDR ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV272IP ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV272IPE4 ACTIVE PDIP P 8 50 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV274CD ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274CDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274CDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 3
Orderable Device Status (1) Package Type Package
Drawing Pins Package Qty Eco Plan (2) Lead/
Ball Finish MSL Peak Temp (3) Samples
(Requires Login)
TLV274CDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274CPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274CPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274CPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274CPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274ID ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IDG4 ACTIVE SOIC D 14 50 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IDR ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IDRG4 ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IN ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV274INE4 ACTIVE PDIP N 14 25 Pb-Free (RoHS) CU NIPDAU N / A for Pkg Type
TLV274IPW ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IPWG4 ACTIVE TSSOP PW 14 90 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IPWR ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
TLV274IPWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 16-Aug-2012
Addendum-Page 4
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLV271, TLV272, TLV274 :
•Automotive: TLV271-Q1, TLV272-Q1, TLV274-Q1
NOTE: Qualified Version Definitions:
•Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
TLV271CDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV271CDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV271CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV271IDBVR SOT-23 DBV 5 3000 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV271IDBVT SOT-23 DBV 5 250 178.0 9.0 3.23 3.17 1.37 4.0 8.0 Q3
TLV272CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV272CDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV272CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV272IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV272IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
TLV272IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
TLV274CDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV274CPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
TLV274IDR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
TLV274IPWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TLV271CDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV271CDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV271CDR SOIC D 8 2500 340.5 338.1 20.6
TLV271IDBVR SOT-23 DBV 5 3000 180.0 180.0 18.0
TLV271IDBVT SOT-23 DBV 5 250 180.0 180.0 18.0
TLV272CDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TLV272CDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
TLV272CDR SOIC D 8 2500 340.5 338.1 20.6
TLV272IDGKR VSSOP DGK 8 2500 364.0 364.0 27.0
TLV272IDGKR VSSOP DGK 8 2500 358.0 335.0 35.0
TLV272IDR SOIC D 8 2500 340.5 338.1 20.6
TLV274CDR SOIC D 14 2500 333.2 345.9 28.6
TLV274CPWR TSSOP PW 14 2000 367.0 367.0 35.0
TLV274IDR SOIC D 14 2500 333.2 345.9 28.6
TLV274IPWR TSSOP PW 14 2000 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 16-Aug-2012
Pack Materials-Page 2
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