General Description
The MAX17681/MAX17681A is a high-voltage, high-
efficiency, iso-buck DC-DC converter designed to provide
isolated power up to 5W. The device operates over a
wide 4.5V to 42V input and uses primary-side feedback
to regulate the output voltage.
The MAX17681/MAX17681A uses peak-current-mode
control. The low-resistance, on-chip MOSFETs ensure
high efficiency at full load while simplifying the PCB layout.
The MAX17681/MAX17681A devices generate a well
regulated primary side voltage which is then scaled by a
suitable transformer turns ratio to derive isolated secondary
output rails. While both MAX17681 and MAX17681A
support primary side overcurrent protection, the
MAX17681A is an enhanced design that supports robust
secondary-side overcurrent protection as well.
The MAX17681/MAX17681A is available in a compact
10-pin (3mm x 2mm) TDFN package. Simulation models
are available.
Applications
●Isolated Fieldbus Interfaces
●PLC I/O Modules
●Smart Meters
●Isolated Power Supplies in Medical Equipment
●Floating Power Supply Generation
Benets and Features
●Reduces External Components and Total Cost
• No Optocoupler
• Synchronous Primary Operation
• All-Ceramic Capacitors, Compact Layout
●Reduces Number of DC-DC Regulators to Stock
• Wide 4.5V to 42V Input
• 0.9V to 0.96 x VIN Primary Output Voltage
• Delivers Up to 5W Output Power
●Reduces Power Dissipation
• Peak Eciency > 90%
• 0.9μA (typ) Shutdown Current
●Operates Reliably in Adverse Industrial Environments
• Peak and Sink Current-Limit Protection
• ±1.7% Feedback Accuracy
• Programmable EN/UVLO Threshold
• Adjustable Soft-Start
• Overtemperature Protection
• -40°C to +125°C Operation
●Short-Circuit Protection
• MAX17681A Supports Robust Secondary-Side
Short-Circuit Protection
• MAX17681A Is Recommended for All New Designs
Ordering Information appears at end of data sheet.
19-7053; Rev 4; 3/18
Application Circuit
D1
C2
10uF
N
SEC
N
PRI
R1
105kΩ
FB
LX
MAX17681
MAX17681A
PGND
COMP
V
IN
EN/UVLO
V
CC
SS
RESET
GND
T1
1:2.4
C1
1µF
C3
1µF
C4
33nF
C7
2.2µF
C6
680pF C5
33nF
R2
10kΩ
R3
4.75kΩ
V
IN
17V TO 32V
V
OUT
24V, 100mA
R4
49.9Ω
Z1
C8
1nF
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
VIN to GND ............................................................ -0.3V to +48V
EN/UVLO to GND...................................... -0.3V to (VIN + 0.3V)
LX to PGND............................................... -0.3V to (VIN + 0.3V)
VCC, FB, RESET, COMP, SS to GND ....................-0.3V to +6V
PGND to GND ......................................................-0.3V to +0.3V
LX Total RMS Current ........................................................±1.6A
Output Short-Circuit Duration .................................... Continuous
Operating Temperature Range ......................... -40°C to +125°C
Junction Temperature ...................................................... +150°C
Storage Temperature Range ............................ -65°C to +160°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
Note 1: Continuous Power Dissipation (TA = +70°C) (derate 14.9mW/°C above +70°C) (multilayer board) 1188.7mW
PACKAGE TYPE: 10 TDFN
Package Code T1032N+1
Outline Number 21-0429
Land Pattern Number 90-0082
THERMAL RESISTANCE, FOUR-LAYER BOARD (Note 1)
Junction to Ambient (θJA) 67.3°C/W
Junction to Case (θJC) 18.2°C/W
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer board.
For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Package Information
For the latest package outline information and land patterns (footprints), go to www.maximintegrated.com/packages. Note that a “+”,
“#”, or “-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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(VIN = 24V, VGND = VPGND = 0V, CVIN = 2.2μF, CVCC = 1μF, VEN = 1.5V, CSS = 3300pF, VFB = 0.98 x VOUT, COMP = unconnected,
LX = unconnected, RESET = unconnected. TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All
voltages are referenced to GND, unless otherwise noted.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
INPUT SUPPLY (VIN)
Input Voltage Range V IN 4.5 42 V
Input Supply Current IIN-SH VEN = 0V, shutdown mode 0.9 3.5 µA
IIN-SW Normal switching mode, no load 1.95 2.8 mA
ENABLE/UVLO (EN/UVLO)
EN Threshold
VENR VEN rising 1.183 1.218 1.253
VVENF VEN falling 1.1 1.135 1.17
VEN-TRUESD VEN falling, true shutdown 0.7
EN Input Leakage Current IEN VEN = VIN = 42V, TA = +25°C 8 200 nA
LDO
VCC Output Voltage Range VCC
6V < VIN < 12V, 0mA < IVCC < 10mA,
12V < VIN < 42V, 0mA < IVCC < 2mA 4.65 5 5.35 V
VCC Current Limit IVCC-MAX VCC = 4.3V, VIN = 12V 15 40 80 mA
VCC Dropout VCC-DO VIN = 4.5V, IVCC = 5mA 4.1 V
VCC UVLO VCC-UVR VCC rising 3.85 4 4.15 V
VCC-UVF VCC falling 3.55 3.7 3.85
POWER MOSFETs
High-Side pMOS On-Resistance RDS-ONH
ILX = 0.5A
(sourcing)
TA = +25°C 0.55 0.85
Ω
TA = TJ = +125°C
(Note 3) 1.2
Low-Side nMOS On-Resistance RDS-ONL
ILX = 0.5A
(sinking)
TA = +25°C 0.2 0.35
Ω
TA = TJ = +125°C
(Note 3) 0.47
LX Leakage Current ILX_LKG
VEN = 0V, TA = +25°C, VLX = (VPGND
+ 1V) to (VIN – 1V) 1μA
SOFT-START (SS)
Charging Current ISS VSS = 0.5V 4.7 5 5.3 μA
FEEDBACK (FB)
FB Regulation Voltage VFB_REG 0.884 0.9 0.916 V
FB Input Bias Current IFB TA = +25°C 100 nA
TRANSCONDUCTANCE AMPLIFIER (COMP)
Transconductance GM ICOMP = ±2.5μA 510 590 650 μS
COMP Source Current ICOMP_SRC 19 32 55 μA
COMP Sink Current ICOMP_SINK 19 32 55 μA
Current Sense Transresistance RCS 0.45 0.5 0.55 V/A
CURRENT LIMIT
Electrical Characteristics
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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(VIN = 24V, VGND = VPGND = 0V, CVIN = 2.2μF, CVCC = 1μF, VEN = 1.5V, CSS = 3300pF, VFB = 0.98 x VOUT, COMP = unconnected,
LX = unconnected, RESET = unconnected. TA = TJ = -40°C to +125°C, unless otherwise noted. Typical values are at TA = +25°C. All
voltages are referenced to GND, unless otherwise noted.) (Note 2)
Note 2: All limits are 100% tested at +25°C. Limits over temperature are guaranteed by design.
Note 3: Guaranteed by design, not production tested.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Peak Current-Limit Threshold IPEAK-LIMIT 1.4 1.65 1.9 A
Runaway Current-Limit
Threshold
IRUNAWAY-
LIMIT
1.45 1.7 2 A
Sink Current-Limit Threshold ISINK-LIMIT 1.05 1.25 1.45 A
TIMINGS
Switching Frequency fSW 186 200 213 kHz
Events to Hiccup After Crossing
Runaway Current Limit 1
VOUT Undervoltage Trip Level
to Cause Hiccup VOUT-HICF VSS > 0.95V (soft-start is done) 67.86 70.5 73.14 %
Hiccup Timeout 32768 Cycles
Minimum On-Time tON_MIN 200 300 415 ns
Maximum Duty Cycle DMAX VFB = 0.98 x VFB-REG 96.5 97.5 98.5 %
LX Dead Time 12 ns
RESET
RESET Output Level Low IRESET = 1mA 0.02 V
RESET Output Leakage Current
High
VFB = 1.01 x VFB-REG,
TA= 25°C 0.45 μA
FB Threshold for RESET Falling VFB-OKF VFB falling 90.5 92.5 94.5 %
FB Threshold for RESET Rising VFB-OKR VFB rising 93.5 95.5 97.5 %
RESET Delay After FB Reaches
95% Regulation VFB rising 1024 Cycles
THERMAL SHUTDOWN
Thermal Shutdown Threshold Temperature rising 165 °C
Thermal Shutdown Hysteresis 10 °C
Electrical Characteristics (continued)
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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(VIN = 24V, VGND = VPGND = 0V, CVIN = 1μF, CVCC = 1μF, VEN = 1.5V, CSS = 33nF, VFB = 0.98 x VPRI, TA = +25°C, unless otherwise
noted.)
Typical Operating Characteristics
1.1
1.14
1.18
1.22
1.26
-40 -20 020 40 60 80 100 120
EN/UVLO THRESHOLD VOLTAGE (V)
TEMPERATURE (°C)
EN/UVLO THRESHOLD VOL TAGE
VS. TEMPERATURE
toc4
RISING
FALLING
-6
-4
-2
0
2
4
6
8
010 20 30 40 50 60 70 80 90 100
REGULATION (%)
LOAD CURRENT (mA)
OUTPUT VOL TAGE REGUL ATION
toc2
V
IN
= 32V
V
IN
= 24V
V
IN
= 17V
FIGURE 9
APPLICATION CIRCUIT
V
IN
= 19V
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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(VIN = 24V, VGND = VPGND = 0V, CVIN = 1μF, CVCC = 1μF, VEN = 1.5V, CSS = 33nF, VFB = 0.98 x VPRI, TA = +25°C, unless otherwise
noted.)
Typical Operating Characteristics (continued)
10V/div
100mA/div
toc12
1ms/div
V
EN/
U
VLO
VOUT 5V/div
5V/div
SOFT-START
FIGURE 9
APPLICATION CIRCUIT
VPRI
IOUT
500mV/
div
50mA/
div
toc9
400µs/div
V
OUT
(AC)
IOUT
LOAD TRANSIENT RESPONSE,
(LOAD CURRENT STEPPED
FROM 50mA to 100mA)
FIGURE6
APPLICATION
CIRCUIT
VOUT=5V
FIGURE 9
APPLICATION
CIRCUIT
IOUT
toc15
BODE PLOT
FIGURE 9 APPLICATION CIRCUIT
fCR = 6.7kHz,
PHASE MARGIN = 80°
GAIN
PHASE
GAIN (dB)
PHASE (°)
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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PIN NAME FUNCTION
1 PGND Power Ground. Connect PGND externally to the power ground plane. Connect GND and PGND pins
together at the ground return path of the VCC bypass capacitor.
2 VIN Switching Regulator Input. Connect a X7R ceramic capacitor from VIN to PGND for bypassing.
3 EN/UVLO
Active-High, Enable/Undervoltage-Detection Input. Pull EN/UVLO to GND to disable the regulator
output. Connect EN/UVLO to VIN for always-on operation. Connect a resistor-divider between VIN,
EN/UVLO, and GND to program the input voltage at which the device is enabled and turns on.
4 VCC Internal LDO Output. Bypass VCC to GND with a minimum 1μF capacitor.
5 FB Output Feedback Connection. Connect FB to a resistor-divider between VPRI and GND to set the
output voltage. See the Adjusting the Primary Output Voltage section for details.
6 SS Soft-Start Input. Connect a ceramic capacitor from SS to GND to set the soft-start time.
7 COMP Compensation Input. Connect an RC network from COMP to GND. See the External Loop
Compensation section.
8RESET
Open-Drain Reset Output. Pull up RESET to an external power supply with an external resistor.
RESET pulls low if FB voltage drops below 92.5% of its set value. RESET goes high impedance
1024 clock cycles after FB voltage rises above 95.5% of its set value.
9 GND Signal Ground.
10 LX Switching Node. Connect LX to the switching side of the transformer. LX is high impedance when the
device is in shutdown mode.
— EP Exposed Pad. Connect to the GND pin of the IC. Connect to a large copper plane below the IC to
improve heat dissipation capability.
Pin Description
Pin Conguration
MAX17681
MAX17681A
TOP VIEW
+
*EP = EXPOSED PAD, CONNECTED TO GND
EP
TDFN
3mm x 2mm
LX
10
GND
9
RESET
8
COMP
7
SS
6
5
FB
4
VCC
3
EN/
UVLO
2
VIN
1
PGND
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Block Diagram
LDO
REGULATOR
V
CC
EN/UVLO
1.218
POK
THERMAL
SHUTDOWN
CHIPEN
OSCILLATOR
FB
COMP
REF
SS REFERENCE
SWITCHOVER
CIRCUIT
REF
+
+
CS
SLOPE
HIGH-SIDE CURRENT
SENSE
CURRENT
LIMIT
LIMIT
FB
0.8595
5.12ms
DELAY
LOW-SIDE CURRENT
SENSE
HIGH-SIDE
DRIVER
LOW-SIDE
DRIVER
V
IN
LX
PGND
PWM
CONTROL
LOGIC
HICCUP
RESET
GND
SINK LIMIT
PWM
CLX
SLOPE
5µA
HICCUP
PEAK
RUNAWAY
CS
CHIPEN
V
CC
SECONDARY
OVER-
CURRENT
PROTECTION
LOGIC
*
MAX17681
MAX17681A
* SECONDARY OVER-CURRENT PROTECTION
LOGIC ONLY FOR MAX17681A
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Detailed Description
The MAX17681/MAX17681A is a high-voltage, high-
efficiency, iso-buck DC-DC converter designed to provide
isolated power up to 5W. The device operates over a
wide 4.5V to 42V input and uses primary side feedback to
regulate the output voltage.
The MAX17681/MAX17681A uses peak-current-mode
control. The low-resistance, on-chip MOSFETs ensure
high efficiency at full load while simplifying the PCB layout.
The programmable soft-start feature allows users to
reduce input inrush current. The device also incorporates
an output enable/undervoltage lockout pin (EN/UVLO)
that allows the user to turn on the part at the desired
input-voltage level. An open-drain RESET pin provides a
delayed power-good signal to the system upon achieving
successful regulation of the primary output voltage.
The device operates over the -40°C to +125°C industrial
temperature range and is available in a compact 10-pin
(3mm x 2mm) TDFN package.
Linear Regulator (VCC)
An internal linear regulator (VCC) provides a 5V nominal
supply to power the internal blocks and the low-side
MOSFET driver. The output of the VCC linear regulator
should be bypassed with a 1μF ceramic capacitor to
GND. The device employs an undervoltage-lockout circuit
that disables the internal linear regulator when VCC falls
below 3.7V (typ). The internal VCC linear regulator can
source up to 40mA (typ) to supply the device and to power
the low-side gate driver.
Enable Input (EN/UVLO) and Soft-Start (SS)
When the EN/UVLO voltage increases above 1.218V (typ),
the device initiates a soft-start sequence with the duration of
the soft-start being dependent on the value of the capacitor
connected from SS to GND. A 5μA current source charges
the capacitor and ramps up the SS pin voltage. The SS pin
voltage is used as reference for the internal error amplifier. The
reference ramp-up allows the output voltage to increase
monotonically from zero to the target value.
The EN/UVLO can be used as an input-voltage UVLO-
adjustment input. An external voltage-divider between VIN
and EN/UVLO to GND adjusts the input voltage at which
the device turns on or turns off. See the Setting the Input
Undervoltage Lockout Level section for details. If input
UVLO programming is not desired, connect the EN/UVLO
to VIN (see the Electrical Characteristics table for the EN/
UVLO rising and falling-threshold voltages). Driving the
EN/UVLO low disables both power MOSFETs as well as
other internal circuitry and reduces VIN quiescent current
to 0.9μA (typ). The SS capacitor is discharged with an
internal pulldown resistor when the EN/UVLO is low. If
the EN/UVLO pin is driven from an external signal source,
a series resistance of minimum 1kΩ is recommended to
be placed between the signal source output and the EN/
UVLO pin to reduce voltage ringing on the line.
Overcurrent Protection/HICCUP Mode
The MAX17681/MAX17681A are provided with an
overcurrent-protection scheme that protects the device
under overload and output short-circuit conditions. A cycle-
by-cycle peak current limit turns off the high-side MOSFET
whenever the switch current exceeds the internal limit of
1.65A (typ). Additionally, the sink current limit turns off
the low-side switch when the low side MOSFET negative
current exceeds 1.25A (typ). A runaway current limit on
the highside MOSFET current at 1.7A (typ) protects the
devices under high input voltage, short-circuit conditions.
The MAX17681 enters hiccup mode, either on one occurrence
of the runaway current limit or when the primary output
voltage (VPRI) drops to 70.5% (typ) of its nominal value
after the soft-start is completed. In the MAX17681, when
hiccup is triggered, the converter is protected by suspending
switching for a hiccup timeout period of 32,768 clock
cycles. Once the hiccup timeout period expires, soft-start
is attempted again. This behaviour works well for primary
output over-current events. However, when secondary-
side overcurrent events occur, additional measures are
required for the Iso-Buck topology to enter into hiccup
mode reliably, and also support robust output voltage
recovery after overcurrent removal. These measures are
not supported by MAX17681.
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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The MAX17681A provides the robust secondary overcurrent
protection, and smooth output voltage recovery after
removal of overcurrent, by entering into hiccup mode after
detecting 16 consecutive negative current limit events.
This is supported by implementing a scheme where the
primary capacitor voltage is actively discharged during the
hiccup timeout period, and soft-starting both primary and
secondary-side outputs.
The MAX17681A enters hiccup mode, either on one
occurrence of the runaway current limit, when the primary
output voltage drops to 71.14% (typ) of its nominal value
after the soft-start is completed, or when 16 consecutive
negative current limit events occur. When hiccup is
triggered, the converter enters a hiccup timeout period
of 32,768 clock cycles. During this period, the high side
switch is kept off and the low side switch is turned on each
cycle until the low side MOSFET negative current reaches
0.6A limit. This mode of operation effectively produces a
negative current in the primary capacitor and discharges
it towards zero. Once the hiccup timeout period expires,
the MAX17681A smoothly soft starts both primary and
secondary output voltages.
If the output capacitance is such that it is discharged to
zero within one hiccup timeout period, the MAX17681A
executes a normal soft-start operation upon exit from the
hiccup timeout period. For cases, where the capacitor
is sized such that it does not discharge to zero in one
hiccup timeout period, during the next soft-start attempt
the converter may re-enter the hiccup time period due to
one of the event which triggers hiccup mode. Eventually
the primary capacitor is completely discharged and the
smooth output voltage recovery is ensured.
In summary the MAX17681 provides primary side over-
current protection, whereas the MAX17681A provides
both primary and secondary side over-current protection.
RESET Output
The device includes a RESET comparator to monitor the
primary output voltage. The open-drain RESET output
requires an external pullup resistor. RESET can sink 2mA
of current while low. RESET goes high (high-impedance)
1024 switching cycles after the primary output increases
above 95.5% of the nominal regulated voltage. RESET
goes low when the primary output voltage drops to below
92.5% of the nominal regulated voltage. In MAX17681A,
when the secondary output is shorted, the primary output
voltage is discharged as well during the hiccup period. So,
in this case, even for a fault on the isolated output, the
RESET can be used as an indicator. RESET also goes
low during thermal shutdown. RESET is valid when the
device is enabled and VIN is above 4.5V.
Thermal-Overload Protection
Thermal-overload protection limits total power dissipation in
the device. When the junction temperature of the device
exceeds +165°C, an on-chip thermal sensor shuts down
the device, allowing the device to cool. The thermal
sensor turns the device on again after the junction
temperature cools by 10°C. Carefully evaluate the total
power dissipation (see the Power Dissipation section) to
avoid unwanted triggering of the thermal-overload protection
in normal operation.
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Applications Information
Operation of the Iso-Buck Converter
The iso-buck is a synchronous-buck-converter-based
topology, useful for generating isolated outputs at low
power level without using an optocoupler. Figure 1 shows
the basic circuit of an iso-buck converter, consists of a
half-bridge transformer driver and secondary side filter.
Figure 2 shows the equivalent circuit when the high-side
switch (QHS) is ON. During this time, the primary current
ramps up and stores energy in the transformer magnetizing
inductance LPRI and the primary capacitor CPRI. The
secondary side diode is reverse-biased and the load current
is supplied by the secondary-side filter capacitor COUT.
Figure 3 shows the equivalent circuit when the low-side
switch (QLS) is on. During this time, the secondary diode
gets forward-biased. The primary current ramps down and
releases stored energy in the transformer magnetizing
inductance and the primary capacitor to the load.
Operating waveforms of the converter are shown in Figure
4. Neglecting diode drop VD, transformer resistances, and
leakage inductance, the output voltage VOUT is proportional
to the primary output voltage VPRI and is regulated by the
MAX17681/MAX17681A control loop.
Figure 2. On-Period Equivalent Circuit Figure 4. Iso-Buck Operating Waveforms
Figure 1. Iso-Buck Topology Figure 3. Off-Period Equivalent Circuit
QHS
QLS
T1 D1
C
OUT
R
LOAD
V
OUT
V
IN
C
PRI
V
PRI
+
-
+
-
N
PRI
N
SEC
QHS
QLS
T1 D1
C
OUT
R
LOAD
V
OUT
V
IN
C
PRI
V
PRI
+
-
+
-
N
PRI
N
SEC
QHS
QLS
T1 D1
C
OUT
R
LOAD
V
OUT
V
IN
C
PRI
V
PRI
+
-
+
-
N
PRI
N
SEC
QHS
QLS
I
PRI
I
PK_PRI
I
NEGPK_
PRI
I
PK_SE
C
(1-D)xT
S
DxT
S
I
OUT
I
SEC
∆I
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Primary Output Voltage Selection
Primary output voltage is regulated by the MAX17681/
MAX17681A control loop. The primary output voltage can
be calculated by using the equation:
PRI MAX IN_MIN
VD V= ×
where DMAX is the maximum duty cycle of the converter
and VIN_MIN is the minimum input voltage. Maximum duty
cycle should be in the range of 0.4 to 0.6 for ideal iso-buck
operation.
Adjusting the Primary Output Voltage
The primary output voltage is set with a resistor-divider
from primary output to FB to GND (see Figure 5). Choose
R2 in the range of 10k to 49.9k and calculate R1 using
the equation:
PRI
V
R1 R2 1
0.9
=×−
Turns Ratio Selection
Neglecting diode drop VD, transformer resistances, and
leakage inductance, the iso-buck output voltage VOUT is
proportional to the primary output voltage VPRI. The turns
ratio (K) is given by the equation:
SEC OUT D
PRI PRI
SEC
PRI
N VV
NV
N
KN
+
=
=
Turns ratio can be adjusted to match with the readily
available off-the-shelf transformer turns ratio by adjusting
the primary output voltage.
Primary Inductance Selection
Primary inductance value determines the ripple current in
the transformer. The required primary inductance is given
by the equation:
PRI PRI
L 7V= ×
where LPRI is the primary inductance in μH and VPRI is
the primary output voltage.
The primary ripple current can be calculated using the
equation:
PRI
PRI IN
SW PRI
V
V1
V
IfL
×−
∆= ×
where LPRI is the primary inductance in H, fSW is the
switching frequency in Hz, VPRI is the primary output
voltage, VIN is the input voltage.
Winding Peak and RMS Currents
Windings peak and RMS current ratings should be specified
for selecting the iso-buck transformer.
Primary and secondary winding peak currents are given
by the equations:
i
i
i
n
HS_AVG PRI OUT i
i1
PK_PRI HS_AVG
OUT
PK_SEC
PRI
IN
I I IK
I
II 2
I
I(1 D)
V
DV
=
=+×
∑
∆
= +
≅−
=
where n is the total number of isolated outputs, i is the
individual isolated output, IPRI is the primary load current,
IOUTi is the individual secondary load current, Ki is the
individual secondary turns ratio, D is the duty cycle, and
ΔI is the primary ripple current.
Primary RMS current is the sum of the high-side and low-
side switch RMS currents.
High-side switch RMS current:
2
2
HS_RMS HS_AVG
I
I DI 12
∆
=×+
Figure 5. Adjusting the Primary Output Voltage
D1
C
OUT
C
PRI
+
-
+
-
N
SEC
N
PRI
R1
R2
FB
LX
MAX17681
MAX17681A
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Low-side switch RMS current:
=
−× ×
∑
−
= −×
∆∆
−+
i
n
PK_PRI OUT i
i1
LS_RMS 2
2
1
(I (I K )
(1 D)
I (1 D)
II
)
2 12
Primary winding RMS current:
22
PRI_RMS HS_RMS LS_RMS
I II= +
Secondary winding RMS current is given by the equation:
i
i
OUT
SEC_RMS
I
I(1 D)
=−
Leakage Inductance
Transformer leakage inductance (LLEAK) plays a key role
in determining the output voltage regulation. For better
output voltage regulation, leakage inductance should be
reduced to less than 1% of the primary inductance value.
Higher leakage inductance also limits the amount of
power delivered to the output.
Primary Negative Peak Current
The primary current can go negative when the low side
switch is turned on. Steady-state primary negative peak
current should be verified not to exceed -1A. The primary
negative peak current can be calculated using the equation:
i
n
NEGPK_PRI PK_PRI OUT i
i1
1
I I (I K ) I
(1 D) =
= − × × −∆
∑
−
Specifying the Iso-Buck Transformer
An off-the-shelf transformer or coupled inductor can be
used as an Iso-buck transformer. If readily not available,
use the table below to specify the Iso-buck transformer
parameters to transformer vendors.
Primary Output Capacitor Selection
X7R ceramic output capacitors are preferred due to their
stability over temperature in industrial applications. The
minimum required output capacitance is given by the
equation:
HS_AVG MAX
PRI SW PRI
PRI
MAX IN_MIN
ID
Cf 0.01 V
V
DV
×
=××
=
Where IOUT is the load current, K is the turns ratio, fSW
is the switching frequency, VPRI is the primary output
voltage, VIN_MIN is the minimum input voltage.
Secondary Output Capacitor Selection
A secondary side capacitor supplies load current when the
high-side switch is on. The required output capacitance to
support 1% steady state ripple is given by the equation:
OUT MAX
OUT SW OUT
ID
Cf 0.01 V
×
=××
It should be noted that dielectric materials used in ceramic
capacitors exhibit capacitance loss due to DC bias
levels and should be appropriately derated to ensure the
required output capacitance is obtained in the application.
Table 1. Specifying Iso-Buck Transformer
PARAMETER SYMBOL
Primary Inductance LPRI
Leakage Inductance LLEAK
Primary Ripple Current ∆I
Primary Peak Current IPK_PRI
Primary RMS Current IPRI_RMS
Secondary Peak Current IPK_SEC
Secondary RMS Current ISEC_RMS
Working Voltage VAC, VDC
Insulation Level VAC, VDC
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Input Capacitor Selection
Ceramic input capacitors are recommended for the IC.
The input capacitor reduces peak current drawn from the
power source and reduces noise and voltage ripple on
the input caused by the switching circuitry. In applications
where the source is located distant from the device input,
an electrolytic capacitor should be added in parallel to the
input ceramic capacitor to provide necessary damping for
potential oscillations caused by the longer input power
path and input ceramic capacitor. The required input
capacitance can be calculated using the equation:
( )
HS_AVG MAX MAX
IN SW IN
PRI
MAX IN_MIN
I D 1D
CfV
V
DV
× ×−
=×∆
=
ΔVIN is the input voltage ripple, normally 2% of the
minimum input voltage, DMAX is the maximum duty cycle,
and fSW is the switching frequency of operation.
Secondary Diode Selection
A secondary rectifier diode should be rated to carry peak
secondary current and to withstand reverse voltage when
the high-side switch is on. A Schottky diode with less
forward-voltage drop should be selected for better output
voltage regulation.
The peak current rating of the diode is given by:
( )
i
i
OUT
PK_DIODE
I
I1D
=−
The peak reverse voltage rating of the diode is given by:
( )
( )
DIODE IN_MAX PRI OUT
V 2 V V KV=× − ×+
Power dissipated in the diode can be calculated using the
equation:
DIODE D OUT
P VI= ×
Minimum Load Requirements
Under light-load conditions, the iso-buck converter output
voltage increases excessively due to the transformer
leakage inductance and parasitic capacitance. Normally,
a minimum load of 10% to 20% of the full load is sufficient
to keep the converter output voltage regulation within
±5%. The output voltage regulation should be verified
after testing prototype.
A resistor connected in series with a Zener diode (See R4,
Z1 in Figure 9) can be used as an overvoltage protection
circuit to limit the overvoltage under absolute no load
conditions. The Zener diode threshold can be selected
as 15% higher than the nominal regulated output voltage
VOUT. The series resistor, R1, value can be in the range
of 30Ω to 60Ω.
Soft-Start Capacitor Selection
The MAX17681/MAX17681A implements adjustable soft-
start operation to reduce inrush current. A capacitor
connected from the SS pin to GND programs the soft-start
period.
The soft-start time (tSS) is related to the capacitor con-
nected at SS (CSS) by the following equation:
SS SS
C 5.55 t= ×
where tSS is in milliseconds and CSS is in nanofarads.
Setting the Input Undervoltage Lockout Level
The device offers an adjustable input undervoltage-
lockout level. Set the voltage at which the device turns
on with a resistive voltage-divider connected from VIN
to GND (see Figure 6). Connect the center node of the
divider to EN/UVLO.
Choose R1 to be 3.3MΩ max and then calculate R2 as
follows:
( )
INU
R1 1.218
R2 V 1.218
×
=−
where VINU is the voltage at which the device is required
to turn on.
Figure 6. Adjustable EN/UVLO Network
MAX17681
MAX17681A
VIN
EN/UVLO
R1
R2
VIN
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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External Loop Compensation
The MAX17681/MAX17681A uses peak current-mode
control scheme and needs only a simple RC network to
have a stable control loop. The compensation network is
shown in Figure 7. The following equations can be used
for calculating the compensation components:
( )
OUT
COMP C PRI
2
PRI
C 1D
R 6000 f V
KC
×−
= ×× ×
×+
where RCOMP is in Ω, and the maximum limit for RCOMP
is 12kΩ. fC is bandwidth of the converter in Hz. Choose
fC in the range of 2kHz to 10kHz.
COMP C COMP
5
CfR
=π× ×
PCOMP
1
C2 50000 R
=π× ×
Power Dissipation
Ensure that the junction temperature of the device does
not exceed +125°C under the operating conditions specified
for the power supply. At a particular operating condition,
the power losses that lead to temperature rise of the
device can be estimated as follows:
()
()
( )
2
LOSS OUT PRI_RMS PRI
2
SEC_RMS SEC D OUT
1
P P -1 - I R
-I R -V I
=××
η
××
OUT OUT OUT
P VI= ×
where POUT is the output power, η is the efficiency of
power conversion, RPRI is the primary resistance of the
transformer, RSEC is the secondary resistance of the
transformer and VD is the diode drop.
The junction temperature (TJ) of the device can be esti-
mated at any ambient temperature (TA) from the following
equation:
( )
J A JA LOSS
TT P= +θ ×
where θJA is the junction-to-ambient thermal impedance
of the package.
PCB Layout Guidelines
Careful PCB layout is critical to achieve clean and stable
operation. For a sample layout that ensures first-pass
success, refer to the MAX17681/MAX17681A evaluation
kit layouts available at www.maximintegrated.com.
Follow these guidelines for good PCB layout:
1) All connections carrying pulsed currents must be very
short and as wide as possible. The loop area of these
connections must be made very small to reduce stray
inductance and radiated EMI.
2) A ceramic input lter capacitor should be placed close
to the VIN pin of the device. The bypass capacitor for
the VCC pin should also be placed close to the VCC
pin. External compensation components should be
placed close to the IC and far from the LX node. The
feedback trace should be routed as far as possible
from the LX node.
3) Signal and power grounds must be kept separate. They
should be connected together at a point where switching
noise is minimum, typically the return terminal of the
V
CC
bypass capacitor. The ground plane should be
kept continuous as much as possible.
4) Multiple thermal vias that connect to a large ground
plane should be provided under the exposed pad of
the device, for ecient heat dissipation.
Figure 8 show the recommended component placement
for the MAX17681/MAX17681A iso-buck converter.
Figure 7. External Compensation Network
COMP
RCOMP
CCOMP
CP
MAX17681
MAX17681A
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Figure 8. Recommended Component Placement
PGND PLANE
VIN PLANE
VOUT
IGND
VPRI
SGND PLANE
EN/UVLO
VCC
FB SS
COMP
RESET
VIAS TO BOTTOM SIDE GROUND PLANE
VIAS TO BOTTOM SIDE PGND TRACK
VIAS TO BOTTOM SIDE VPRI TRACK
LXPGND
VIN GND
CF
CCF
RF
CVCC
CIN
CPRI
COUT
D1
T1
U1
R1
R2
R3
R4
D1
FB
LX
MAX17681
MAX17681A
PGND
COMP
VIN
EN/UVLO
VCC
SS
RESET
GND
T1
VIN VOUT
COUT
CIN
CF
CSS
CVCC
CPRI
CCF
RF
R3
R4
R1
R2
U1
CY
CY
IGND
CSS
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Figure 9. Low-Profile 24V to 24V, 100mA Isolated Output Application Circuit
Figure 10. 24V to ±15V, 75mA Isolated Output Application Circuit
Typical Application Circuits
D1
C2
10uF
NSEC
NPRI
R1
105kΩ
FB
LX
MAX17681
MAX17681A
PGND
COMP
VIN
EN/UVLO
VCC
SS
RESET
GND
T1
1:2.4
C1
1µF
C3
1µF
C4
33nF
C7
2.2µF
C6
680pF C5
33nF
R2
10kΩ
R3
4.75kΩ
VIN
17V TO 32V
VOUT
24V, 100mA
R4
49.9Ω
Z1
C1 : MURATA 1µF/X7R/50V/1206 (GRM31MR71H105K)
C2 : MURATA 10µF/X7R/16V/1206 (GRM31CR71C106K)
C7 : MURATA 2.2µF/X7R/50V/1206 (GRM31CR71H225K)
C8 : AVX 1nF/X7R/1.5KV/1206 (1206SC102KAT3A)
D1 : DIODES INC, DFLS1200-7
Z1 : DIODES INC, MMSZ5254B-7-F
T1 : ETAL, 303993
C8
1nF
D1
C2
10uF
NSEC2
NPRI
R1
86.6kΩ
FB
LX
MAX17681
MAX17681A
PGND
COMP
VIN
EN/UVLO
VCC
SS
RESET
GND
T1
1:1.8:1.8
C1
1µF
C3
1µF
C4
33nF
C7
2.2µF
C6
680pF C5
33nF
R2
10kΩ
R3
4.75kΩ
VIN
17V TO 32V
VOUT1
+15V, 75mA
NSEC1
VOUT2
-15V, 75mA
C8
2.2µF
D2
Z1
Z2
R4
49.9Ω
R5
49.9Ω
C1 : MURATA 1µF/X7R/50V/1206 (GRM31MR71H105K)
C2 : MURATA 10µF/X7R/16V/1206 (GRM31CR71C106K)
C7, C8 : MURATA 2.2µF/X7R/25V/1206 (GRM31MR71E225K)
C9 : AVX 1nF/X7R/1.5KV/1206 (1206SC102KAT3A)
D1, D2 : DIODES INC, DFLS1200-7
Z1, Z2 : DIODES INC, DDZ17-7
T1 : WURTH, 750342557
C9
1nF
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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Figure 11. 24V to 3.3V/80mA Non-Isolated and ±16V,65mA Isolated Output Application circuit
+Denotes a lead (Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX17681ATB+ -40°C to +125°C 10L TDFN-EP*
MAX17681AATB+ -40°C to +125°C 10L TDFN-EP*
Typical Application Circuits (continued)
Ordering Information
Chip Information
PROCESS: BiCMOS
D1
C2
22uF
NSEC2
NPRI
R1
26.7kΩ
FB
LX
MAX17681
MAX17681A
PGND
COMP
VIN
EN/UVLO
VCC
SS
RESET
GND
T1
1:5.3:5.3
C1
4.7µF
C3
1µF
C4
33nF
C7
1µF
C6
470pF C5
47nF
R2
10kΩ
R3
6.8kΩ
VIN
18V TO 30V
VOUT1
+16V, 65mA
NSEC1
VOUT2
-16V, 65mA
C8
1µF
D2
R4
1.5kΩ
R5
1.5kΩ
C1 : MURATA 4.7µF/X7R/50V/1210 (GRM32ER71H475KA88)
C2 : MURATA 22µF/X7R/10V/1210 (GRM32ER71A226ME20)
C7, C8 : MURATA 1µF/X7R/50V/1206 (GRM31MR71H105KA88)
C9 : AVX 1nF/X7R/1.5KV/1206 (1206SC102KAT3A)
D1, D2 : DIODES INC, BAS521
T1 : SUMIDA,CEI-120-06340-T294
C9
1nF
VOUT2
+3.3V/80mA
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
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REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 9/14 Initial release —
1 10/15 Equation updated 12
2 1/17 Added MAX17681A to Ordering Information table 1–17
3 5/17 Updated Ordering Information footnote 1
4 3/18 Reversed Ordering Information footnote and updated Benets and Features
section. 1
Revision History
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc.
MAX17681 4.5V to 42V Input, High-Eciency,
Iso-Buck DC-DC Converter
© 2018 Maxim Integrated Products, Inc.
│
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For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
