HN27C4096AG/ACC Series
262144-word × 16-bit CMOS UV Erasable and Programmable
ROM
Description
The Hitachi HN27C4096AG/ACC is a 4-Mbit ultraviolet erasable and electrically programmable ROM,
featuring high speed and low power dissipation. Fabricated on advanced fine process and high speed circuitry
technique, the HN27C4096A makes high speed access time possible. Therefore, it is suitable for 16-bit
microcomputer systems using high speed microcomputer such as the 80286 and 68020. The HN27C4096A
offers high speed programming using page programming mode. This device has the package variation of
cerdip-40pin and JLCC-44pin.
Features
• High speed: Access time 100 ns/120 ns/150 ns (max)
• Low power dissipation:
Standby mode; 5 µW (typ)
Active mode; 35 mW/MHz (typ)
• Fast high reliability page programming and fast high-reliability programming
Programming voltage; +12.5 V D.C.
Program time; 3.5 sec (min) (Theoretical in Page programming)
• Inputs and outputs TTL compatible during both read and program modes
• Pin arrangement: 40-pin JEDEC standard
44-pin JLCC JEDEC standard
• Device identifier mode: Manufacturer code and device code
• Fully compatible with the HN27C4096G/CC Series
HN27C4096AG/ACC Series
2
Ordering Information
Type No. Access Time Package
HN27C4096AG-10
HN27C4096AG-12
HN27C4096AG-15
100 ns
120 ns
150 ns
600-mil 40-pin cerdip (DG-40A)
HN27C4096ACC-10
HN27C4096ACC-12
HN27C4096ACC-15
100 ns
120 ns
150 ns
44-pin J-bend leaded chip carrier (CC-44)
HN27C4096AG/ACC Series
3
Pin Arrangement
V
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
V
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
SS
V
A17
A16
A15
A14
A13
A12
A11
A10
A9
V
A8
A7
A6
A5
A4
A3
A2
A1
A0
SS
PP CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
A13
A12
A11
A10
A9
V
NC
A8
A7
A6
A5
I/O12
I/O11
I/O10
I/O9
I/O8
V
NC
I/O7
I/O6
I/O5
I/O4
SS
I/O13
I/O14
I/O15
CE
VCC
VPP
NC
A17
A16
A15
A14
I/O3
I/O2
I/O1
I/O0
A0
OE
NC
A1
A2
A3
A4
SS
HN27C4096AG Series HN27C4096ACC Series
(Top view) (Top view)
Pin Description
Pin Name Function
A0 – A17 Address
I/O0 – I/O15 Input/output
CE Chip enable
OE Output enable
VCC Power supply
VPP Programming power supply
VSS Ground
HN27C4096AG/ACC Series
4
Block Diagram
I/O0
:
:
:
I/O15
X-
Decoder
2,048 x 2,048
Memory Matrix
Y-Decoder
CE
OE
Input
Data
Control
Y-Gating
V
CC
V
V
SS
H
A0 A6
H : High threshold inverter
A7
:
:
:
:
:
:
:
:
:
:
:
:
A17
PP
. . . . . . . . . . . . .
H
HN27C4096AG/ACC Series
5
Mode Selection
Pin CE OE A9 VPP VCC I/O
CC-44 (3) (22) (35) (2) (44) (4 – 11, 14 – 21)
Mode DG-40A (2) (20) (31) (1) (40) (3 – 10, 12 – 19)
Read VIL VIL XV
SS – VCC VCC Dout
Output disable VIL VIH XV
SS – VCC VCC High-Z
Standby VIH XX V
SS – VCC VCC High-Z
Page program Page program set VIH VH*2 XV
PP VCC High-Z
Page data latch VIL VH*2 XV
PP VCC Din
Page program VIL VIH XV
PP VCC High-Z
Page program verify VIH VIL XV
PP VCC Dout
Page program reset VIH VIH XV
CC VCC High-Z
Word program Program VIL VIH XV
PP VCC Din
Program verify VIH VIL XV
PP VCC Dout
Optional verify VIL VIL XV
PP VCC Dout
Program inhibit VIH VIH XV
PP VCC High-Z
Identifier VIL VIL VH*2 VSS – VCC VCC Code
Notes: 1. X: Don’t care.
2. VH: 12.0 V ± 0.5 V
Absolute Maximum Ratings
Parameter Symbol Value Unit
All input and output voltages*1 Vin, Vout –0.6*2 to +7.0 V
Voltage on pin A9 and OE VID –0.6*2 to +13.0 V
VPP voltage *1 VPP –0.6 to +13.5 V
VCC voltage *1 VCC –0.6 to +7.0 V
Operating temperature range Topr 0 to +70 °C
Storage temperature range *3 Tstg –65 to +125 °C
Storage temperature under bias Tbias –20 to +80 °C
Notes: 1. Relative to VSS.
2. Vin, Vout, VID min = –2.0 V for pulse width ≤ 20 ns
3. Storage temperature range of device before programming.
HN27C4096AG/ACC Series
6
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Typ Max Unit Test Conditions
Input capacitance Cin — — 12 pF Vin = 0 V
Output capacitance Cout — — 20 pF Vout = 0 V
Read Operation
DC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 5.5 V
Output leakage current ILO ——2 µA Vout = 5.5 V/0.45 V
VPP current IPP1 —1 20µAV
PP = 5.5 V
Standby VCC current ISB1 ——1 mACE = VIH
ISB2 —1 20µACE = VCC ± 0.3 V
Operating VCC current ICC1 — — 30 mA Iout = 0 mA, f = 1 MHz
ICC2 — — 100 mA Iout = 0 mA, f = 10 MHz
Input voltage VIL –0.3*1 — 0.8 V
VIH 2.2 — VCC+1*2 V
Output voltage VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Notes: 1. VIL min = –1.0 V for pulse width ≤ 50 ns
VIL min = –2.0 V for pulse width ≤ 20 ns
2. VIH max = VCC +1.5 V for pulse width ≤ 20 ns
If VIH is over the specified maximum value, read operation cannot be guaranteed.
HN27C4096AG/ACC Series
7
AC Characteristics (VCC = 5 V ± 10%, VPP = VSS to VCC, Ta = 0 to +70°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 10 ns
• Output load: 1 TTL gate +100 pF
• Reference levels for measuring timing: 0.8 V, 2.0 V
HN27C4096A
-10 -12 -15
Parameter Symbol Min Max Min Max Min Max Unit Test Conditions
Address to output delay tACC — 100 — 120 — 150 ns CE = OE = VIL
CE to output delay tCE — 100 — 120 — 150 ns OE = VIL
OE to output delay tOE —60—60—70nsCE = VIL
OE high to output float*1tDF 035040050nsCE = VIL
Address to output hold tOH 5—5—5—nsCE = OE = VIL
Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
Read Timing Waveform
Address
CE
OE
Data Out Data Out Valid
tACC
tCE
tOE tOH
tDF
Standby mode Active mode Standby mode
HN27C4096AG/ACC Series
8
Fast High-Reliability Page Programming
This device can be applied the high performance page programming algorithm shown in the following
flowchart. This algorithm allows to obtain faster programming time without any voltage stress to the device
nor deterioration in reliability of programmed data.
Page Program Set
Apply 12 V to OE pin after applying 12.5 V to VPP to set a page program mode.
The device operates in a page program mode until reset.
HN27C4096AG/ACC Series
9
Page Program Reset
Set VPP to VCC level or less to reset a page program mode.
START
SET PAGE PROG LATCH MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
= 12.0 ± 0.5 V
PP CC
OE
Address = 0
n = 0
Latch
Address + 1 Address
→
Latch
Address + 1 Address
→
Address + 1 Address
→
Latch
Latch
n + 1 n
→
SET PAGE PROG./VERIFY MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
Address + 1 Address
→
NOGO
GO
YES
NOGO
NO NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
V = 5.0 ± 0.5 V V = V
PPCC CC
GO
Program t = 50 s ± 5%
PW µ
YES
Fast High-Reliability Page Programming Flowchart
HN27C4096AG/ACC Series
10
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 6.5 V/0.45 V
Output voltage during
verify VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Operating VCC current ICC ——50mA
Input voltage VIL –0.1*5— 0.8 V
VIH 2.2 — VCC+0.5*6V
VH11.5 12.0 12.5 V
VPP supply current IPP ——70mACE = VIL
Notes: 1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP =
12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width ≤ 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
HN27C4096AG/ACC Series
11
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Reference levels for measuring timing:
Inputs; 0.8 V, 2.0 V,
Outputs; 0.8 V, 2.0 V
Parameter Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2——µs
OE setup time tOES 2——µs
Data setup time tDS 2——µs
Address hold time tAH 0——µs
Data hold time tDH 2——µs
OE high to output float delay tDF*1 0 — 130 ns
VPP setup time tVPS 2——µs
V
CC setup time tVCS 2——µs
CE programming pulse width tPW 47.5 50.0 52.5 µs
CE setup time tCES 2——µs
Data valid from OE tOE 0 — 150 ns
CE pulse width during data latch tLW 1——µs
OE = VH setup time tOHS 2——µs
OE = VH hold time tOHH 2——µs
V
PP hold time*2 tVRS 1——µs
Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
2. Page program mode will be reset when VPP is set to VCC or less.
HN27C4096AG/ACC Series
12
Fast High-Reliability Page Programming Timing Waveform
Program data latch Page program Program verify
Data out valid
Data in
stable
Page program mode
ttt
t
tLW
VRS
OES
PW
CES
tOHH
t
VCS
t
VPS
t
OHS
t
DS
t
DH
t
OE
t
DF
t
AS
t
AH
t
AH
t
AS
A2 – A17
A0, A1
Data
V
V
CE
OE
V
V + 1.25
V
PP VPP
CC
CC
CC
CC
VIL
VH
VIH
HN27C4096AG/ACC Series
13
Fast High-Reliability Programming
This device can be applied the fast high-reliability programming algorithm shown in the following flowchart.
This algorithm allows to obtain faster programming time without any voltage stress to the device nor
deterioration in reliability of programmed data.
NOGO
START
Address = 0
n = 0
n + 1 n
SET PROG./VERIFY MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
Address + 1 Address GO
YES
NOGO
NO NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
V = 5.0 ± 0.5 V V = V
PPCC CC
GO
Program t = 50 s ± 5%
PW µ
YES
Fast High-Reliability Programming Flowchart
HN27C4096AG/ACC Series
14
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 6.5 V/0.45 V
VPP supply current IPP ——40mACE = VIL
Operating VCC current ICC ——50mA
Input voltage VIL –0.1*5 — 0.8 V
VIH 2.2 — VCC +0.5*6 V
Output voltage VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Notes: 1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed while VPP =
12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width ≤ 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
HN27C4096AG/ACC Series
15
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Reference levels for measuring timings:
Inputs: 0.8 V, 2.0 V
Outputs: 0.8 V, 2.0 V
Paramerter Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2——µs
OE setup time tOES 2——µs
Data setup time tDS 2——µs
Address hold time tAH 0——µs
Data hold time tDH 2——µs
OE to output float delay tDF*1 0 — 130 ns
VPP setup time tVPS 2——µs
V
CC setup time tVCS 2——µs
CE programming pulse width tPW 47.5 50.0 52.5 µs
Data valid from OE tOE 0 — 150 ns
Note: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
HN27C4096AG/ACC Series
16
Fast High-Reliability Programming Timing Waveform
Program Program Verify
Address
Data Data In Stable Data Out Valid
tAS
tDS
tVPS
tVCS
tDH tDF
tAH
tPW tOES tOE
VPP VCC
VPP
VCC VCC
V +1.25
CC
CE
tDS
OE
Optional Page Programming
This device can be applied the optional page programming algorithm shown in the following flowchart. This
algorithm allows to obtain faster programming time without any voltage stress to the device nor deterioration
in reliability of programmed data.
This programming algorithm is the combination of page programming and word verify. It can avoid the
increase of programming verify time when a programmer with slow machine cycle is used, and shorten the
total programming time.
Regarding the timing specifications for page programming and word verify, please refer to the specifications
for fast high-reliability page programming and fast high-reliability programming.
HN27C4096AG/ACC Series
17
START
SET PAGE PROG LATCH MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
= 12.0 ± 0.5 V
PP CC
OE
Address = 0
Latch
Address + 1 Address
Latch
Address + 1 Address
Address + 1 Address
Latch
Latch
n + 1 n
SET PAGE PROG. MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
Address + 1 Address
NOGO
GO
YES
NOGO
NO
NO
VERIFY
END FAIL
READ
all address
n = 10?
LAST
address?
SET READ MODE
V = 5.0 ± 0.5 V V = V
PPCC CC
GO
Program t = 50 s ± 5%
PW
µ
SET WORD PROG./VERIFY MODE
V = 12.5 ± 0.3 V V = 6.25 ± 0.25 V
PP CC
PAGE PROG. RESET
V = V = 6.25 ± 0.25 V
PP CC
Address = 0
n = 0
Address + 1 Address Program t = 50 s ± 5%
PW
µ
VERIFY
YES
LAST
address?
GO
NOGO
YES
Optional Page Programming Flowchart
HN27C4096AG/ACC Series
18
DC Characteristics (VCC = 6.25 V ± 0.25 V, VPP =12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Parameter Symbol Min Typ Max Unit Test Conditions
Input leakage current ILI ——2 µA Vin = 6.5 V/0.45 V
Output voltage during
verify VOL — — 0.45 V IOL = 2.1 mA
VOH 2.4 — — V IOH = –400 µA
Operating VCC current ICC ——50mA
Input voltage VIL –0.1*5 — 0.8 V
VIH 2.2 — VCC +0.5*6 V
VH11.5 12.0 12.5 V
VPP supply current IPP ——70mACE = VIL
Notes: 1. VCC must be applied before VPP and removed after VPP.
2. VPP must not exceed 13 V including overshoot.
3. An influence may be had upon device reliability if the device is installed or removed
while VPP = 12.5 V.
4. Do not alter VPP either VIL to 12.5 V or 12.5 V to VIL when CE = low.
5. VIL min = –0.6 V for pulse width ≤ 20 ns.
6. If VIH is over the specified maximum value, programming operation cannot be guaranteed.
HN27C4096AG/ACC Series
19
AC Characteristics (VCC = 6.25 V ± 0.25 V, VPP = 12.5 V ± 0.3 V, Ta = 25°C ± 5°C)
Test Conditions
• Input pulse levels: 0.45 to 2.4 V
• Input rise and fall time: ≤ 20 ns
• Reference levels for measuring timings:
Inputs; 0.8 V, 2.0 V
Outputs; 0.8 V, 2.0 V
Parameter Symbol Min Typ Max Unit Test Conditions
Address setup time tAS 2——µs
OE setup time tOES 2——µs
Data setup time tDS 2——µs
Address hold time tAH 0——µs
Data hold time tDH 2——µs
OE high to output float delay tDF*1 0 — 130 ns
VPP setup time tVPS 2——µs
V
CC setup time tVCS 2——µs
CE initial programming pulse width tPW 47.5 50.0 52.5 µs
CE setup time tCES 2——µs
Data valid from OE tOE 0 — 150 ns
CE pulse width during data latch tLW 1——µs
OE = VH setup time tOHS 2——µs
OE = VH hold time tOHH 2——µs
Page programming reset time*2 tVLW 1——µs
V
PP hold time*2 tVRS 1——µs
Notes: 1. tDF is defined as the time at which the output achieves the open circuit condition and data is no
longer driven.
2. Page program mode will be reset when VPP is set to VCC or less.
HN27C4096AG/ACC Series
20
Option Page Programming Timing Waveform
Program data latch Page program
Program verify
Page program mode
t
t
tLW OES
PW
tOHH
t
VCS
t
VPS
t
DS
t
DH
t
OE
t
DS
tt
AH
t
AH
t
AS
A2 – A17
A0, A1
Data
V
V
CE
OE
V
V + 1.25
V
PP VPP
CC
CC
CC
CC
VIL
VH
VIH
t
AH
Word program mode
Program
t
DH
t
VPS
t
DF
t
VRS
t
VLW
tCES tCES
tPW
t
OHS
Data in
stable
Data
out
valid Data in stable
AS
Erase
Erasure of the HN27C4096AG/ACC is performed by exposure to ultraviolet light of 2537 Å and all the output
data are changed to “1” after this erasure procedure. The minimum integrated dose (i.e. UV intensity X
exposure time) for erasure is 15 W · sec/cm2.
HN27C4096AG/ACC Series
21
Mode Description
Device Identifier Mode
The device identifier mode allows the reading out of binary codes that identify manufacturer and type of
device, from outputs of EPROM. By this mode, the device will be automatically matched its own
corresponding programming algorithm, using programming equipment.
HN27C4096A Identifier Code
A0 I/O8 – I/O15 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
CC-44 (24) (11 — 4) (14) (15) (16) (17) (18) (19) (20) (21)
Identifier DG-40A (21) (10 — 3) (12) (13) (14) (15) (16) (17) (18) (19) Hex Data
Manufacturer code VIL X 0000011107
Device code VIH X 10100010A2
Notes: 1. VCC = 5.0 V ± 10%
2. A9 = 12.0 V ± 0.5 V
3. A1 – A8, A10 – A17, CE, OE = VIL
4. X: Don’t care.
HN27C4096AG/ACC Series
22
Package Dimensions
HN27C4096HG Series (DG-40A) Unit: mm
0.48 ± 0.102.54 ± 0.25
0.51 Min
6.30 Max
2.54 Min
1.32
52.07
15.51 Max
40 21
120
0.25
0 – 10° + 0.11
– 0.05
15.24
53.34 Max
14.66
φ8.89
2.54 Max
HN27C4096HCC Series (CC-44) Unit: mm
17.57
16.51
39 29
717
28
6
40
1
44
18
17.57
0.89 0.73
0.46
0.18
1.27
15.75
4.80 Max
2.75 Max
15.75
1.025
+0.38
–0.22
+0.38
–0.22
+0.07
–0.13
+0.16
–0.24
+0.38
–0.22
+0.16
–0.24
M
φ8.89
0.15
