IRFIZ34E
HEXFET® Power MOSFET
PD - 9.1674A
lAdvanced Process Technology
lIsolated Package
lHigh Voltage Isolation = 2.5KVRMS
lSink to Lead Creepage Dist. = 4.8mm
lFully Avalanche Rated
TO-220 FULLPAK
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 4.1
RθJA Junction-to-Ambient ––– 65
Thermal Resistance
Fifth Generation HEXFETs from International Rectifier
utilize advanced processing techniques to achieve
extremely low on-resistance per silicon area. This benefit,
combined with the fast switching speed and ruggedized
device design that HEXFET Power MOSFETs are well
known for, provides the designer with an extremely efficient
and reliable device for use in a wide variety of applications.
The TO-220 Fullpak eliminates the need for additional
insulating hardware in commercial-industrial applications.
The moulding compound used provides a high isolation
capability and a low thermal resistance between the tab
and external heatsink. This isolation is equivalent to using
a 100 micron mica barrier with standard TO-220 product.
The Fullpak is mounted to a heatsink using a single clip or
by a single screw fixing.
9/22/97
Description
Parameter Max. Units
ID @ TC = 25°C Continuous Drain Current, VGS @ 10V 21
ID @ TC = 100°C Continuous Drain Current, VGS @ 10V 15 A
IDM Pulsed Drain Current 100
PD @TC = 25°C Power Dissipation 37 W
Linear Derating Factor 0.24 W/°C
VGS Gate-to-Source Voltage ± 20 V
EAS Single Pulse Avalanche Energy 110 mJ
IAR Avalanche Current 16 A
EAR Repetitive Avalanche Energy3.7 mJ
dv /d t Peak Diode Recovery dv/dt 5.0 V/ns
TJOperating Junction and -55 to + 175
TSTG Storage Temperature Range
Soldering Temperature, for 10 seconds 300 (1.6mm from case ) °C
Mounting torque, 6-32 or M3 screw 10 lbf•in (1.1N•m)
Absolute Maximum Ratings
°C/W
S
D
G
VDSS = 60V
RDS(on) = 0.042Ω
ID = 21A
IRFIZ34E
Parameter Min. Typ. Max. Units Conditions
V(BR)DSS Drain-to-Source Breakdown Voltage 60 – – – –– – V V GS = 0V, ID = 250µA
∆V(BR)DSS/∆TJBreakdown Voltage Temp. Coefficient ––– 0.052 ––– V/°C Reference to 25°C, I D = 1mA
RDS(on) Static Drain-to-Source On-Resistance ––– ––– 0.042 ΩVGS = 10V, ID = 11A
VGS(th) Gate Threshold Voltage 2.0 ––– 4.0 V VDS = VGS, ID = 250µA
gfs Forward Transconductance 6.5 ––– ––– S VDS = 25V, ID = 16A
––– ––– 25 µA VDS = 60V, VGS = 0V
––– ––– 250 VDS = 48V, VGS = 0V, TJ = 150°C
Gate-to-Source Forward Leakage ––– ––– 10 0 V GS = 20V
Gate-to-Source Reverse Leakage ––– ––– -100 nA VGS = -20V
QgTotal Gate Charge –– – ––– 3 4 I D = 16A
Qgs Gate-to-Source Charge ––– ––– 6.8 nC VDS = 44V
Qgd Gate-to-Drain ("Miller") Charge ––– ––– 1 4 VGS = 10V, See Fig. 6 and 13
td(on) Turn-On Delay Time ––– 7.0 ––– V DD = 28V
trRise Time ––– 49 –– – I D = 16A
td(off) Turn-Off Delay Time ––– 31 – –– R G = 18Ω
tfFall Time ––– 40 ––– R D = 1.8Ω, See Fig. 10
Between lead,
––– ––– 6mm (0.25in.)
from package
and center of die contact
Ciss Input Capacitance ––– 700 ––– VGS = 0V
Coss Output Capacitance ––– 240 ––– VDS = 25V
Crss Reverse Transfer Capacitance ––– 100 ––– ƒ = 1.0MHz, See Fig. 5
C Drain to Sink Capacitance ––– 12 – –– ƒ = 1.0MHz
nH
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
LDInternal Drain Inductance
LSInternal Source Inductance ––– –––
S
D
G
IGSS
ns
4.5
7.5
IDSS Drain-to-Source Leakage Current
pF
Notes:
Repetitive rating; pulse width limited by
max. junction temperature. ( See fig. 11 )
VDD = 25V, starting TJ = 25°C, L = 610µH
RG = 25Ω, IAS = 16A. (See Figure 12) t=60s, ƒ=60Hz
ISD ≤ 16A, di/dt ≤ 420A/µs, VDD ≤ V(BR)DSS,
TJ ≤ 175°C Uses IRFZ34N data and test conditions
Pulse width ≤ 300µs; duty cycle ≤ 2%.
S
D
G
Parameter Min. Typ. Max. Units Conditions
ISContinuous Source Current MOSFET symbol
(Body Diode) ––– ––– showing the
ISM Pulsed Source Current integral reverse
(Body Diode)
––– ––– p-n junction diode.
VSD Diode Forward Voltage ––– – –– 1.6 V TJ = 25°C, IS = 11A, VGS = 0V
trr Reverse Recovery Time ––– 57 8 6 ns TJ = 25°C, IF = 16A
Qrr Reverse RecoveryCharge ––– 13 0 200 µC di/dt = 100A/µs
ton Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
Source-Drain Ratings and Characteristics
A
21
100
IRFIZ34E
Fig 4. Normalized On-Resistance
Vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
1
10
100
45678910
T = 25°C
J
GS
V , Ga te-to-Source Voltage (V )
D
I , D rain- to-Sourc e C u rrent (A)
A
V = 25V
20µs PULSE WIDTH
T = 175°C
J
DS
0.0
0.4
0.8
1.2
1.6
2.0
2.4
-60 -40 -20 0 20 40 60 80 100 120 140 160 180
J
T , Ju nc t io n T em per atu re ( °C )
R , D rain-to-Sou rc e O n Res istan ce
DS(on)
(Normalized)
V = 10 V
GS
A
I = 2 6A
D
1
10
100
1000
0.1 1 10 100
I , Dra in-to-Source Current (A )
D
V , D rain-to-S ource V oltage (V )
DS
V G S
TO P 15 V
1 0V
8 .0V
7 .0V
6 .0V
5 .5V
5 .0V
BO TTOM 4.5 V
20µs PULSE WIDTH
T = 25 ° C
C
A
4.5V
1
10
100
1000
0.1 1 10 100
I , Dra in-to-Source Current (A )
D
V , D ra in-to-S o urc e V oltag e (V)
DS
V GS
TO P 15V
10 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
BO TTOM 4.5 V
A
4.5V
20µs PUL SE WIDTH
T = 175°C
C
IRFIZ34E
1
10
100
1000
1 10 100 1000
OPERATION IN THIS AREA LIMITED
BY RDS(on)
Single Pulse
T
T = 175 C
= 25 C
°°
J
C
V , Drain-to-Source Voltage (V)
I , Drain Current (A)I , Drain Current (A)
DS
D
10us
100us
1ms
10ms
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
Fig 8. Maximum Safe Operating Area
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
0
200
400
600
800
1000
1200
1 10 100
C, Ca pacitance (pF)
DS
V , D r ai n-to- So ur c e V olt ag e (V )
A
V = 0 V, f = 1MHz
C = C + C , C SHORTED
C = C
C = C + C
GS
iss gs gd ds
rss gd
oss ds gd
C
iss
C
oss
C
rss
0
4
8
12
16
20
0 10203040
Q , To tal Ga te Ch arg e ( nC)
G
V , G ate-to -Sou rc e Voltage (V)
GS
A
FO R TEST CIRCUIT
SEE F IGURE 1 3
V = 44 V
V = 28 V
DS
DS
I = 16 A
D
1
10
100
1000
0.4 0.8 1.2 1.6 2.0
T = 25°C
J
V = 0V
GS
V , Source-to-Drain Voltage (V)
I , Reverse Drain Current (A)
SD
SD
A
T = 175°C
J
IRFIZ34E
Fig 10a. Switching Time Test Circuit
V
DS
90%
10%
V
GS t
d(on)
t
r
t
d(off)
t
f
Fig 10b. Switching Time Waveforms
VDS
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
RD
VGS
RGD.U.T.
10V
+
-
VDD
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current Vs.
Case Temperature
25 50 75 100 125 150 175
0
4
8
12
16
20
24
T , Case Temperature ( C)
I , Drain Current (A)
°
C
D
0.01
0.1
1
10
0.00001 0.0001 0.001 0.01 0.1 1
Notes:
1. Duty factor D = t / t
2. Peak T = P x Z + T
1 2
JDM thJC C
P
t
t
DM
1
2
t , Rectangular Pulse Duration (sec)
Thermal Response (Z )
1
thJC
0.01
0.02
0.05
0.10
0.20
D = 0.50
SINGLE PULSE
(THERMAL RESPONSE)
IRFIZ34E
Q
G
Q
GS
Q
GD
V
G
Charge
D.U.T. V
DS
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
10 V
Fig 13b. Gate Charge Test Circuit
Fig 13a. Basic Gate Charge Waveform
Fig 12c. Maximum Avalanche Energy
Vs. Drain Current
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
0
50
100
150
200
250
25 50 75 100 125 150 175
J
E , S ingle Pu lse Ava lanche E nerg y (m J)
AS
A
Starting T , Junction Temperature (°C)
V = 25 V
I
T O P 6.5 A
1 1 A
BOTTOM 16A
DD
D
V
DS
L
D.U.T.
V
DD
I
AS
t
p
0.01Ω
R
G
+
-
t
p
V
DS
I
AS
V
DD
V
(BR)DSS
IRFIZ34E
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current Body Diode Forward
Current
VGS=10V
VDD
ISD
Driver Gate Drive
D.U.T. ISD Waveform
D.U.T. VDS Waveform
Inductor Curent
D = P.W.
Period
+
-
+
+
+
-
-
-
Fig 14. For N-Channel HEXFETS
* VGS = 5V for Logic Level Devices
Peak Diode Recovery dv/dt Test Circuit
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
*
IRFIZ34E
Part Marking Information
TO-220 Fullpak
Package Outline
TO-220 Fullpak Outline
Dimensions are shown in millimeters (inches)
L EA D ASS IGNMENTS
1 - G ATE
2 - DRA IN
3 - SO URCE
NOTES:
1 DIMEN SIONING & TOLERA NCING
PER AN SI Y14.5M , 1982
2 C ON TROLLIN G D IM EN SION : INCH.
D
C
AB
MINIMUM CRE EPAGE
DISTANC E BETW EEN
A-B-C-D = 4.80 (.189)
3X
2.85 (.112 )
2.65 (.104 )
2.80 (.110)
2.60 (.102)
4.80 (.189)
4.60 (.181)
7.10 (.280)
6.70 (.263)
3.40 (.133 )
3.10 (.123 )
ø
- A -
3.70 (.145)
3.20 (.126)
1.15 (.04 5)
MIN.
3.30 (.130)
3.10 (.122)
- B -
0.90 (.035)
0.70 (.028)
3X
0.25 (.010 ) MA M B
2.54 (.100)
2 X
3X
13.70 (.540)
13.50 (.530)
16.00 (.630)
15.80 (.622)
1 2 3
10.60 (.41 7)
10.40 (.40 9)
1.40 (.055)
1.05 (.042)
0.48 (.019)
0.44 (.017)
P ART NUM BE R
INTERNATIONAL
RE CTIFIER
LOG O
DATE CO DE
(YYWW)
YY = YEAR
WW = WEEK
ASSEMBL Y
LOT CODE
E401 9245
IRFI840G
E XAM P LE : TH IS IS A N IRFI840G
W IT H ASSEMBLY
LOT CODE E401
A
WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, Tel: (310) 322 3331
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http://www.irf.com/ Data and specifications subject to change without notice. 9/97
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/
