19-4817; Rev 1; 9/10 TION KIT EVALUA LE IL AVA AB High-Frequency, Low-Cost SMBus Chargers The MAX17435/MAX17535 are available in a small, 4mm x 4mm x 0.75mm, 24-pin, lead-free TQFN package. An evaluation kit is available. Applications Notebook Computers PDAs and Mobile Communicators S S S S Ordering Information PART TEMP RANGE PIN-PACKAGE MAX17435ETG+ -40NC +85NC 24 TQFN-EP* MAX17535ETG+ -40NC to +85NC 24 TQFN-EP* to +Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad. 2- to 4- Li+ Cell Battery-Powered Devices Pin Configuration IINP CC CSSP TOP VIEW 18 17 16 BATT The MAX17435 switches at an 850kHz frequency and the MAX17535 switches at 500kHz. S S S S CSSN The MAX17435/MAX17535 provide a digital output that indicates the presence of the adapter, an analog output that indicates the adapter or battery current, depending upon the presence or absence of the adapter, and a digital output that indicates when the adapter current exceeds a user-defined threshold. S S Low-Cost SMBus Charger High Switching Frequency (0.85MHz/0.5MHz) Internal Boost Switches SMBus-Programmable Charge Voltage, Input Current Limit, Charge Current, Relearn Voltage, and Digital IINP Readback Single-Point Compensation Automatic Selection of System Power Source Adapter n-Channel MOSFETs Driven by an Internal Dedicated Charge Pump Adapter Soft-Start 0.4% Accurate Charge Voltage 2.5% Accurate Input Current Limiting 3% Accurate Charge Current Monitor Outputs for AC Adapter Current (2% Accuracy) Battery Discharge Current (2% Accuracy) AC Adapter Presence AC Adapter Overvoltage Protection 11-Bit Battery Voltage Setting 6-Bit, Charge-Current Setting/Input Current Setting Improved IINP Accuracy at Low Input Current PDSL The MAX17435/MAX17535 provide up to 7A of charge current to 2, 3, or 4 lithium-ion (Li+) cells in series. The charge current, and input current-limit sense amplifiers have low offset errors and can use 10mI sense resistors. The MAX17435/MAX17535 fixed-inductor ripple architecture significantly reduces component size and circuit cost. Features S S S S 15 14 13 ACIN 19 12 CSIP ITHR 20 11 CSIN 10 ACOK VAA 21 MAX17435 MAX17535 9 DHI GND 23 8 LX EN 24 7 BST 1 2 3 4 5 6 SCL SDA DCIN LDO DLO ADAPTLIM VCC 22 SMBus is a trademark of Intel Corp. ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. MAX17435/MAX17535 General Description The MAX17435/MAX17535 integrated multichemistry battery-charger ICs simplify construction of accurate and efficient chargers. The MAX17435/MAX17535 provide SMBusK-programmable charge current, charge voltage, input current limit, relearn voltage, and digital readback of the IINP voltage. The MAX17435/MAX17535 utilize a charge pump to control the adapter selection n-channel MOSFETs when the adapter is present. When the adapter is absent, the charge pump is shut down and a p-channel MOSFET selects the battery. MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers ABSOLUTE MAXIMUM RATINGS CC, IINP to GND....................................... -0.3V to (VLDO + 0.3V) LDO Short Circuit to GND.......................................... Momentary Continuous Power Dissipation (TA = +70NC) 24-Pin TQFN (derate 20.8mW/NC above +70NC)........1666mW Operating Temperature Range........................... -40NC to +85NC Junction Temperature......................................................+150NC Storage Temperature Range............................. -65NC to +150NC Lead Temperature (soldering, 10s)..................................+300NC Soldering Temperature.....................................................+260NC DCIN, CSSP, BATT, CSIP to GND.......................... -0.3V to +28V CSIP to CSIN, CSSP to CSSN............................... -0.3V to +0.3V VCC, SCL, SDA, VAA, EN, ACIN, ITHR, ADAPTLIM, ACOK to GND................................... -0.3V to +6V PDSL to GND.......................................................... -0.3V to +37V GND to PGND....................................................... -0.3V to +0.3V DHI to LX...................................................-0.3V to (VBST + 0.3V) BST to LX.................................................................. -0.3V to +6V BST to GND............................................................ -0.3V to +34V DLO to PGND........................................... -0.3V to (VLDO + 0.3V) LX to GND................................................................. -6V to +28V Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Charging enabled, VADAPTER = 19V, VBATTERY = 16.8V 3 6 mA Charging disabled 1.5 2.2 mA INPUT SUPPLIES IDCIN + ICSSP + ICSSN Adapter Present Quiescent Current (Note 1) VBATT = 16.8V BATT + CSIP + CSIN + LX Input Current DCIN Input Current IDCIN VCC Supply Current ICC Adapter absent or charger shut down (Note 1) FA VBATT = 2V to 19V, adapter present (Note 1) 200 650 Charger disabled 0.7 1.0 mA Charger added 1.5 2.5 mA 26 V DCIN Input Voltage Range for Charger DCIN Undervoltage-Lockout Trip Point for Charger 2.0 8 VDCIN falling 7 VDCIN rising DCIN Input Voltage Range 7.2 7.7 8 7.9 26 V V CHARGE-VOLTAGE REGULATION ChargingVoltage() = 0x41A0 Battery Full-Charge Voltage and Accuracy ChargingVoltage() = 0x3130 ChargingVoltage() = 0x20D0 ChargingVoltage() = 0x1060 Battery Undervoltage-Lockout Trip Point for Trickle Charge 16.733 16.8 -0.4 12.516 12.592 -0.6 8.333 8.4 -0.8 4.15 4.192 -1.0 3 3.5 2 _______________________________________________________________________________________ 16.867 V +0.4 % 12.668 V +0.6 % 8.467 V +0.8 % 4.234 V +1.0 % 4 V High-Frequency, Low-Cost SMBus Chargers (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 78.22 80.64 83.06 mV RS2 = 10mI, Figure 1, ChargingCurrent() = 0x1f80 7.822 8.064 8.306 A +3 % RS2 = 10mI, Figure 1, ChargingCurrent() = 0x0f80 3.829 CHARGE-CURRENT REGULATION CSIP-to-CSIN Full-Scale Current-Sense Voltage Charge Current and Accuracy RS2 = 10mI, Figure 1, ChargingCurrent() = 0x0080 Based on ChargeCurrent() = 128mA and 8.064A Charge-Current Gain Error -3 3.968 -3.5 64 128 4.107 A +3.5 % 192 mA -50 +50 % -2 +2 % INPUT CURRENT REGULATION Input Current-Limit Threshold RS1 = 10mI, Figure 1, InputCurrent() = full scale 107.25 RS1 = 10mI, Figure 1, InputCurrent() = 0C80 62.08 RS1 = 10mI, Figure 1, InputCurrent() = 0780 36.86 CSSP/CSSN Input Voltage Range 110 112.75 64 65.92 38.4 39.94 -2.5 +2.5 -3 mV +3 -4 +4 8 % 26 V 20.3 V/V 0 4.2 V VCSSP - VCSSN = 110mV -5 +5 VCSSP - VCSSN = 55mV -4 +4 VCSSP - VCSSN = 5mV -10 +10 IINP Gain Error Based on VCSSP - VCSSN = 110mV and VCSSP - VCSSN = 55mV -1.5 +1.5 % IINP Offset Error Based on VCSSP - VCSSN = 110mV and VCSSP - VCSSN = 55mV -350 +350 FV IREF = 50FA 4.082 4.096 4.115 V 3.1 3.9 V 5.4 5.6 V 127 250 mV 4.1 5.0 V IINP Voltage Gain 19.7 IINP Output Voltage Range IINP Accuracy 20 % REFERENCE REF Output Voltage REF REF Undervoltage-Lockout Threshold REF falling LINEAR REGULATOR LDO Output Voltage LDO IREF = 50FA LDO Load Regulation 0 < ILDO < 40mA LDO Undervoltage-Lockout Threshold LDO falling, 500mV (typ) hysteresis 5.2 3.2 _______________________________________________________________________________________ 3 MAX17435/MAX17535 ELECTRICAL CHARACTERISTICS (continued) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL ACOK ACOK Sink Current CONDITIONS VACOK = 0.4V, VACIN = 2.5V MIN TYP MAX 1 UNITS mA 1 ACOK Leakage Current ACIN VACOK = 5.5V, VACIN = 0.5V, TA = +25NC ACIN Threshold Rising, 20mV (typ) hysteresis 1.53 V ACIN Input Bias Current TA = +25NC -1 +1 FA ITHR Leakage Current VITHR = 0V to LDO, TA = +25NC -1 +1 ADAPTLIM Sink Current VITHR > VIINP 1 1.465 1.485 FA ITHR/ADAPTLIM ADAPTLIM Leakage Current VITHR < VIINP, TA = +25NC ITHR Threshold Calculated = VITHR - VIINP FA mA -12 1 FA +12 mV 0.8 V +1 FA LOGIC LEVELS SDA/SCL Input Low Voltage SDA/SCL Input High Voltage SDA/SCL Input Bias Current 2.1 V TA = +25NC -1 VDCIN = 19V, VBATT = 10V, MAX17435 55 61 67 VDCIN = 19V, VBATT = 10V, MAX17535 93 100 107 SWITCHING REGULATOR DHI Off-Time K Factor ns/V Sense Voltage for Minimum Discontinuous Mode Ripple Current VCSIP - VCSIN 5 mV Zero-Crossing Comparator Threshold VCSIP - VCSIN 5 mV Cycle-by-Cycle Current-Limit Sense Voltage VCSIP - VCSIN DHI Resistance High IDHI = 10mA DHI Resistance Low IDHI = -10mA DLO Resistance High DLO Resistance Low 120 125 130 mV 1.5 3 I 0.8 1.6 I IDLO = 10mA 3 6 I IDLO = -10mA 3 6 I ADAPTER DETECTION Adapter Absence Detect Threshold VDCIN - VBATT, VDCIN falling 50 120 200 mV Adapter Detect Threshold VDCIN - VBATT, VDCIN rising 340 430 600 mV PDSL Gate-Driver Source Current VPDSL - VDCIN = 3V, VDCIN = 19V 40 64 FA PDSL Gate-Driver Output Voltage HIGH VDCIN = 19V, open load VDCIN + 5.3 VDCIN +8 V CHARGE-PUMP MOSFET DRIVER 4 _______________________________________________________________________________________ High-Frequency, Low-Cost SMBus Chargers (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = 0C to +85C, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 2.04 2 2.1 V ADAPTER OVERVOLTAGE PROTECTION ACOVP Threshold Rising ACOVP Threshold Hysteresis 30 mV 144 mV 16 ms 0.6 s ADAPTER OVERCURRENT PROTECTION With respect to VCSSP - VCSSN ACOCP Threshold ACOCP Blanking Time When ACOCP comparator is high and at the time the blanking time expires ACOCP Waiting Time PDSL SWITCH CONTROL PDSL Turn-Off Resistance 2.5 4 kI 100 kHz SMBus TIMING SPECIFICATIONS SMBus Frequency fSMB 10 Bus Free Time tBUF 4.7 Fs START Condition Hold Time from SCL tHD:STA 4 Fs START Condition Setup Time from SCL tSU:STA 4.7 Fs STOP Condition Setup Time from SCL tSU:STO 4 Fs Holdup Time from SCL tHD:DAT 300 ns Setup Time from SCL tSU:DAT 250 ns SCL Low Period tLOW 4.7 Fs SCL High Period tHIGH 4 Fs Maximum Charging Period Without a Charge_Voltage() or ChargeCurrent() Command 140 175 210 s ELECTRICAL CHARACTERISTICS (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Charging enabled, VADAPTER = 19V, VBATTERY = 16.8V 6 mA Charging disabled 2.2 mA INPUT SUPPLIES Adapter Present Quiescent Current IDCIN + ICSSP + ICSSN (Note 1) _______________________________________________________________________________________ 5 MAX17435/MAX17535 ELECTRICAL CHARACTERISTICS (continued) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MAX Adapter absent or charger shut down (Note 1) 1.5 VBATT = 2V to 19V, adapter present (Note 1) 650 VBATT = 16.8V BATT + CSIP + CSIN + LX Input Current MIN UNITS FA DCIN Input Current IDCIN Charger disabled 1 mA VCC Supply Current ICC Charger enabled 2.5 mA 26 V DCIN Input Voltage Range for Charger DCIN Undervoltage-Lockout Trip Point for Charger 8 VDCIN falling 7 VDCIN rising DCIN Input Voltage Range 7.9 8 26 V V CHARGE-VOLTAGE REGULATION 16.73 16.87 V -0.416 +0.416 % 12.516 12.668 V -0.6 +0.6 % 8.333 8.467 V -0.8 +0.8 % 4.15 4.234 V -1.0 +1.0 % 3 4 V 78.22 83.06 mV RS2 = 10mI, Figure 1, ChargingCurrent() = 0x1f80 7.822 8.306 A -3 +3 % RS2 = 10mI, Figure 1, ChargingCurrent() = 0x0f80 3.829 4.107 A -3.5 +3.5 % ChargingVoltage() = 0x41A0 Battery Full-Charge Voltage and Accuracy ChargingVoltage() = 0x3130 ChargingVoltage() = 0x20D0 ChargingVoltage() = 0x1060 Battery Undervoltage-Lockout Trip Point for Trickle Charge CHARGE-CURRENT REGULATION CSIP-to-CSIN Full-Scale Current-Sense Voltage Charge Current and Accuracy RS2 = 10mI, Figure 1, ChargingCurrent() = 0x0080 Charge-Current Gain Error Based on ChargeCurrent() = 128mA and 8.064A 64 192 mA -50 +50 % -2 +2 % 6 _______________________________________________________________________________________ High-Frequency, Low-Cost SMBus Chargers (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS RS1 = 10mI, Figure 1, InputCurrent() = full scale 106.7 113.3 mV -2.5 +2.5 % RS1 = 10mI, Figure 1, InputCurrent() = 0C80 62.08 65.92 mV -3 +3 % RS1 = 10mI, Figure 1, InputCurrent() = 0780 36.86 39.94 mV -4 +4 % 8 26 V 19.7 20.3 % 0 4 V -5 +5 INPUT CURRENT REGULATION Input Current-Limit Threshold CSSP/CSSN Input Voltage Range IINP Voltage Gain IINP Output Voltage Range VCSSP - VCSSN = 110mV VCSSP - VCSSN = 55mV -4 +4 VCSSP - VCSSN = 5mV -11 +11 IINP Gain Error Based on VCSSP - VCSSN = 100mV and VCSSP - VCSSN = 20mV -1.5 +1.5 % IINP Offset Error Based on VCSSP - VCSSN = 100mV and VCSSP - VCSSN = 5mV -520 +520 FV IREF = 50FA 4.075 4.115 V 3.9 V IINP Accuracy % REFERENCE REF Output Voltage REF REF Undervoltage-Lockout Threshold REF falling LINEAR REGULATOR LDO Output Voltage LDO IREF = 50FA 5.2 5.6 V 300 mV 5.0 V LDO Load Regulation 0 < ILDO < 40mA LDO Undervoltage-Lockout Threshold LDO falling, 500mV (typ) hysteresis ACOK ACOK Sink Current ACIN VACOK = 0.4V, VACIN = 1.5V 1 ACIN Threshold Rising, 20mV (typ) hysteresis 1.465 1.530 V -1 +1 FA 1 FA ACIN Input Bias Current 3.2 mA ITHR/ADAPTLIM ITHR Leakage Current VITHR = 0 to 5.4V ADAPTLIM Sink Current VITHR > VIINP ADAPTLIM Leakage Current VITHR < VIINP ITHR Threshold Calculated = VITHR - VIINP 1 -12 mA 1 FA +12 mV _______________________________________________________________________________________ 7 MAX17435/MAX17535 ELECTRICAL CHARACTERISTICS (continued) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers ELECTRICAL CHARACTERISTICS (continued) (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 0.8 V LOGIC LEVELS SDA/SCL Input Low Voltage SDA/SCL Input High Voltage 2.1 V SDA/SCL Input Bias Current -1 FA SWITCHING REGULATOR DHI Off-Time K Factor Cycle-by-Cycle Current-Limit Sense Voltage VDCIN = 19V, VBATT = 10V, MAX17435 55 67 VDCIN = 19V, VBATT = 10V, MAX17435 93 107 VCSIP - VCSIN 120 130 mV ns/V DHI Resistance High IDHI = 10mA 3 I DHI Resistance Low IDHI = -10mA 1.6 I DLO Resistance High IDLO = 10mA 6 I DLO Resistance Low IDLO = -10mA 6 I ADAPTER DETECTION Adapter Absence Detect Threshold Adapter Detect Threshold CHARGE-PUMP MOSFET DRIVER PDSL Gate-Driver Source Current VDCIN - VBATT, VDCIN falling 50 200 mV VDCIN - VBATT, VDCIN rising 270 600 mV VPDSL - VDCIN = 3V, VDCIN = 19V PDSL Gate-Driver Output Voltage High VDCIN = 19V 40 FA VDCIN + 5.3 V ADAPTER OVERVOLTAGE PROTECTION ACOVP Threshold Rising 2.04 2.1 V 4 kI 100 kHz PDSL SWITCH CONTROL PDSL Turn-Off Resistance SMBus TIMING SPECIFICATIONS SMBus Frequency fSMB 10 Bus Free Time tBUF 4.7 Fs START Condition Hold Time from SCL tHD:STA 4 Fs START Condition Setup Time from SCL tSU:STA 4.7 Fs STOP Condition Setup Time from SCL tSU:STO 4 Fs 8 _______________________________________________________________________________________ High-Frequency, Low-Cost SMBus Chargers (Circuit of Figure 1, no load on LDO, VDCIN = VCSSP = VCSSN = 19V, VLX = 0V, VBST - VLX = 5V, VBATT = VCSIP = VCSIN = 16.8V, TA = -40C to +85C, unless otherwise noted.) (Note 2) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Hold Time from SCL tHD:DAT 300 ns Setup Time from SCL tSU:DAT 250 ns SCL Low Period tLOW 4.7 Fs SCL High Period tHIGH 4 Fs Maximum Charging Period Without a Charge_Voltage() or ChargeCurrent() Command (Note 4) 140 210 s Note 1: Adapter present conditions are tested at VDCIN = 19V and VBATT = 16.8V. Adapter absent conditions are tested at VDCIN = 16V, VBATT = 16.8V. Note 2: Specifications to TA = -40C are guaranteed by design and not production tested. Typical Operating Characteristics (Circuit of Figure 1, VIN = 19V, VCC = VDD = 5V, EN = VCC, TA = +25NC, unless otherwise specified.) INPUT CURRENT-LIMIT ERROR vs. INPUT CURRENT-LIMIT SETTING 10 8 6 4 2 0 VBATT = 8.4V -1.0 -2.0 -2.5 VBATT = 12.6V -3.0 0 2 4 6 INPUT CURRENT-LIMIT SETTING (A) 8 15 10 VADAPTER = 20V VADAPTER = 0V, VBATT = 15V 5 VBATT = 16.8V 0 INPUT CURRENT LIMIT = 3.584A -5 -4.0 -4 25 20 -1.5 -3.5 -2 MAX17435 toc03 -0.5 30 IINP ERROR (%) 12 0 MAX17435 toc02 14 INPUT CURRENT-LIMIT ERROR (%) MAX17435 toc01 INPUT CURRENT-LIMIT ERROR (%) 16 IINP ERROR vs. SYSTEM CURRENT (DC SWEEP) INPUT CURRENT-LIMIT ERROR vs. SYSTEM CURRENT 0 1 2 SYSTEM CURRENT (A) 3 4 0 20 40 60 VCSSP - VCSSN (mV) _______________________________________________________________________________________ 9 MAX17435/MAX17535 ELECTRICAL CHARACTERISTICS (continued) Typical Operating Characteristics (continued) (Circuit of Figure 1, VIN = 19V, VCC = VDD = 5V, EN = VCC, TA = +25NC, unless otherwise specified.) 2.0 1.5 1.0 VBATT = 16.8V 0.5 2.0 8 ICHARGER = 5A 1.5 ICHARGER = 3A 1.0 ICHARGER = 4A 0.5 0 0 VBATT = 8.4V VBATT = 12.6V 1 2 6 5 4 3 2 1 -0.5 0 3 4 3 7 8 13 18 2 6 4 SYSTEM CURRENT (A) BATTERY VOLTAGE (V) INPUT CURRENT-LIMIT SETTING (A) CHARGE VOLTAGE ACCURACY AT 3.854A CHARGER VOLTAGE ERROR vs. CHARGER CURRENT BATTERY REMOVAL (VBATT = 3V) MAX17435 toc07 0.20 0.15 0.10 0.05 0 -0.05 0.3 0.2 -0.10 MAX17435 toc09 MAX17435 toc08 0 CHARGER VOLTAGE ERROR (%) -0.5 0.1 0 VBATT = 16.8V -0.1 VBATT = 8.4V VPDSL 5V/div VBATT 5V/div VDCIN 5V/div VBATT = 12.6V -0.2 -0.3 IL 1A/div -0.4 -0.5 -0.6 -0.15 0 5 10 15 -0.7 20 0 2 6 4 CHARGE VOLTAGE (V) CHARGER CURRENT (A) SYSTEM LOAD TRANSIENT (0A 3A 0A) CHARGE-OUTPUT SHORT CIRCUIT 100Fs/div EFFICIENCY vs. CHARGE CURRENT (2, 3, AND 4 CELLS) MAX17435 toc11 MAX17435 toc10 100 4 CELL 95 IL 1A/div 3 CELL VBATT 5V/div VCC 1V/div ISYSLD 1A/div IL 2A/div EFFICIENCY (%) 90 VBATT 200mV/div MAX17435 toc12 ERROR (%) 2.5 MAX17435 toc06 2.5 9 CHARGER-CURRENT ERROR (%) 3.0 3.0 MAX17435 toc05 MAX17435 toc04 INPUT CURRENT LIMIT = 3.584A CHARGER-CURRENT ERROR (%) 3.5 CHARGER-CURRENT ERROR vs. SMBus SETTING CHARGER-CURRENT ERROR vs. BATTERY VOLTAGE IINP ERROR vs. SYSTEM CURRENT IINP ERROR (%) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers 85 2 CELL 80 75 70 65 60 0A 55 50 1ms/div 20Fs/div 0 1 2 3 4 CHARGE CURRENT (A) 10 5 6 High-Frequency, Low-Cost SMBus Chargers (Circuit of Figure 1, VIN = 19V, VCC = VDD = 5V, EN = VCC, TA = +25NC, unless otherwise specified.) LDO VOLTAGE vs. LDO CURRENT VAA DEVIATION, SWITCHING AND NOT SWITCHING 5.44 5.42 5.40 0 SWITCHING -0.5 NOT SWITCHING 0 10 20 30 40 50 4.105 4.100 4.095 4.090 4.085 -1.5 5.34 MAX17435 toc15 MAX17435 toc14 0.5 -1.0 5.36 4.110 VAA VOLTAGE (V) 1.0 5.38 4.080 -2.0 0 5 10 15 20 25 30 -40 -20 0 20 40 60 80 LDO CURRENT (mA) DCIN (V) TEMPERATURE (NC) FREQUENCY vs. VBATT AT 4A ICHG POWER-SOURCE SELECTOR SCHEME WITH BATTERY PRESENT (ADAPTER REMOVAL) POWER-SOURCE SELECTOR SCHEME WITH BATTERY PRESENT (ADAPTER INSERTION) MAX17435 toc16 1000 900 800 FREQUENCY (kHz) 1.5 DEVIATION (mV) LDO VOLTAGE (V) 5.46 VAA vs. TEMPERATURE 2.0 MAX17435 toc13 5.48 700 MAX17435 toc18 MAX17435 toc17 VPDSL 5V/div VPDSL 5V/div VADAPTER 5V/div VSYSLD 5V/div VBATT 5V/div 600 500 400 300 100 MAX17435/MAX17535 Typical Operating Characteristics (continued) VSYSLD 5V/div VBATT 5V/div 200 VADAPTER 5V/div 100 0 0 5 10 15 20 10ms/div 40ms/div VBATT (V) ______________________________________________________________________________________ 11 MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Pin Description PIN NAME 1 SCL SMBus Clock Input. Connect to an external pullup resistor according to SMBus specifications. FUNCTION 2 SDA SMBus Data I/O. Open-drain output. Connect to an external pullup resistor according to SMBus specifications. 3 DCIN Charger Supply Input. Connect to adapter supply. For minimum input bias current connect to the center of the input/soft-start FETs. Bypass with a 1FF ceramic capacitor to PGND placed close to the pin. Add a 10 resistor to reduce input surge at adapter insertion. 4 LDO Linear Regulator Output. This is a 30mA LDO that powers the DLO driver, the BST circuit, and the internal SMBus circuitry. Bypass with a 1FF ceramic capacitor to PGND placed close to the pin. LDO is active when the Adapter Present = 1, independent of the state of EN. LDO is also active when DCIN is supply by the battery while Adapter Present = 0 and EN is high. The SMBus registers are reset by the rising LDO UVLO. 5 DLO Low-Side Power-MOSFET Driver Output. Connect to low-side n-channel MOSFET gate. 6 ADAPTLIM 7 BST 8 LX High-Side Driver Source Connection 9 DHI High-Side Power MOSFET Driver Output. Connect to high-side n-channel MOSFET gate. 10 ACOK AC Detect Output. This open-drain output is high impedance when ACIN is lower than 1.485V. The ACOK output remains high when the MAX17435/MAX17535 are powered down. For a typical application, use a 10kI pullup resistor to LDO (pin 4). 11 CSIN Output Current-Sense Negative Input. Connect this pin to the negative terminal of the sense resistor. See the Setting Charge Current section for resistor value and scaling. 12 CSIP Output Current-Sense Positive Input. Connect a current-sense resistor from CSIP to CSIN; the voltage across these two pins is interpreted by the MAX17435/MAX17535 as proportional to the charge current delivered to the battery with approximately 110mV full-scale voltage. See the Setting Charge Current section for resistor value and scaling. 13 BATT Battery Voltage Feedback Input. Connect as close as possible to the battery terminal. 14 PDSL Power-Source n-Channel MOSFET Switch Driver Output. When the adapter is not present or an overvoltage event is detected at the input, the PDSL output is pulled to GND with a 2.5kI (typ) resistor. Otherwise, it is typically 8V above the adapter voltage when the part is not using the battery. This is powered by an internal charge pump. 15 CSSN Input Current-Sense Negative Input. See the description of the CSSP pin for resistor value and scaling. Adaptive System Current-Limit Comparator Output. This open-drain output is high impedance when the voltage at the IINP pin is lower than the ITHR threshold. For a typical application, use a 10kI pullup resistor to LDO (pin 4). High-Side Driver Supply. Connect a 0.1FF capacitor from BST to LX. 12 High-Frequency, Low-Cost SMBus Chargers PIN NAME FUNCTION 16 CSSP Current Sense for Positive Input. Connect a current-sense resistor from CSSP to CSSN. The voltage across CSSP to CSSN determines the current at which the charger reduces charging current to keep from drawing more current from the adapter than is allowed. As the system current flowing in the resistor from CSSN to CSSP increases, the charger reduces charge current to keep the system current at the limit value. When the system current reaches 130% of InputCurrent() setting for more than 16ms, the PDSL pin turns off the adapter selector FET to prevent excess current from being drawn from the adapter. The adaptor selector FET is re-enabled after 0.6s. If the fault continues, the cycle is repeated three times after which the MAX17435/MAX17535 is latched off. To reset the latch, remove and reinsert the adapter. 17 CC Voltage Regulation Loop-Compensation Point. Connect a 10nF capacitor from CC to GND. 18 IINP Input Current-Monitor Output. The voltage at the IINP pin is 20 times the voltage from CSSP to CSSN. This voltage is present when charging is enabled to monitor the system current, and when the battery is discharging to monitor the battery discharge current. ACIN AC Adapter-Detect Input. ACIN is the input to a comparator with a 1.485V (typ) reference voltage. The output of the comparator is ACOK. ACOK goes low when the threshold voltage is exceeded, indicating that the AC adapter is present, and it enables the charger. When the ACIN input is above 2.0V, the MAX17435/MAX17535 interpret that as an adapter overvoltage event. The charger is then disabled and the adapter MOSFETs are turned off. If the part is charging and the ACIN voltage drops below the programmed threshold, the charger is disabled, and a ChargeCurrent() and ChargeVoltage() command have to be written over the SMBus to re-enable the charger. 20 ITHR Adaptive System Current-Limit Comparator Threshold. This pin connects to the inverting input of a comparator. The noninverting input of the comparator is the IINP input, while the output is driving the ADAPTLIM open drain. When the input to ITHR is greater than IINP, the ADAPTLIM output is high. 21 VAA 4.096V Internal Reference Voltage; No External Load Allowed. Bypass to analog ground using a 1FF or greater ceramic capacitor. VAA is active only after LDO and the internal reference are active. 22 VCC Circuitry Supply-Voltage Input. Connect to LDO through 10I and bypass with a 0.1FF capacitor to GND as close as possible to the package pin. 23 GND 24 EN -- EP 19 Analog Ground Enable/Disable Charger Operation. This disables the charger and associated circuitry when EN goes low and is in addition to the ACOK charger enable. If the adapter is absent and EN is pulled up to a voltage higher than 2.4V, LDO, VAA, the input charge current, and the battery discharge current monitor on IINP are enabled. Exposed Pad. Connect backside EP to power ground. ______________________________________________________________________________________ 13 MAX17435/MAX17535 Pin Description (continued) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Q1B R9 103kI R11 2MI RS1 10mI Q1A N3 ADAPTER R4 150kI C6 10nF R17 10I SYSTEM LOAD R18 1kI CIN N4 C10 1FF GND DCIN PDSL CSSP ACIN CSSN BST DHI R10 10kI C4 0.1FF LX DLO C1 1FF R16 10I R14 10kI L1 PGND PAD R5 10kI R13 10kI N2 ACOK ACOK LDO C IN = 2 x 4.7FF C OUT = 4.7FF L1 = 2FH N1 LDO MAX17435 MAX17535 RS2 10mI CSIP CSIN BATT VAA C3 1FF C11 1FF CC GND IINP VCC BATTERY IINP VOLTAGE C2 0.1FF LDO R7 10kI SCL SDA SMBus CONTROL COUT C5 0.01FF ADAPTER CURRENT-LIMIT FLAG ADAPTLIM ITHR EN R12 10kI LDO R6 7.06kI R8 49.9kI LDO Figure 1. Standard Application Circuit Detailed Description The MAX17435/MAX17535 charger includes all the functions necessary to charge Li+, NiMH, and NiCd smart batteries. A high-efficiency synchronous rectified stepdown DC-DC converter is used to implement a constantcurrent constant-voltage charger. The DC-DC converter drives a high-side n-channel MOSFET and provides synchronous rectification with a low-side n-channel MOSFET. The charge current and input current-sense amplifiers have low-input offset errors (200FV typ), allowing the use of small-valued sense resistors. The MAX17435/MAX17535 use an SMBus interface similar to the MAX8731A to set charge current, charge voltage, and input current limit. In addition, the MAX17435/ MAX17535 SMBus interface supports ChargeVoltage (), ChargeCurrent(), InputCurrent(), RELEARN(), and IINPVoltage() readback. 14 High-Frequency, Low-Cost SMBus Chargers LDO DHI BST DCIN PGND (PAD) LDO ADAPTER PRESENT 5.4V REGULATOR DLO LX LOW-SIDE DRIVER HIGH-SIDE DRIVER CSIN CSSP A = 20V/V CURRENTSENSE AMPLIFIER BATTERY CSSN GMS DCIN VAA GND CSIP 4.096V REFERENCE BATTERY OVP CHARGE VOLTAGE() 400mV IN_SET MAX17435 MAX17535 ZCMP AC_EN gMI CURRENTSENSE AMPLIFIER EN DC-DC CONVERTER IMAX CSI CCMP IMIN 750mA 8.064A CSIN 500mA BDIV BATT LVC AND CAP SWITCH LOGIC gMV ADAPTLIM CHG_EN IINP SCL SDA AC_EN SMBus LOGIC PDSL LOGIC 1.485V CC ACIN ACOK ITHR PDSL Figure 2. Block Diagram The MAX17435/MAX17535 control input current (CCS control loop), charge current (CCI control loop), or charge voltage (CCV control loop), depending on the operating condition. The three control loops, CCV, CCI, and CCS, are brought together internally at the lowest voltage clamp (LVC) amplifier. The output of the LVC amplifier is the feedback control signal for the DC-DC controller. The minimum voltage at the CCV, CCI, or CCS appears at the output of the LVC amplifier and clamps the other control loops to within 0.3V above the control point. Clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the Compensation section). The CCI loop is internally compensated and the CCV and CCS loops share a common compensation network at CC. The dominant control loop (CCV, CCS) drives the compensation network. ______________________________________________________________________________________ 15 MAX17435/MAX17535 IINP MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Table 1. EN Pin Function ADAPTER PRESENT EN PDSL STATUS CHARGER STATUS SYSTEM CURRENT MONITOR STATUS (IINP PATH) Yes High PDSL is pumped 8V above the DCIN voltage (charge pump on). Enabled Enabled Yes Low PDSL is pumped 8V above the DCIN voltage (charge pump on). Disabled Enabled No High Charge pump is off and PDSL is forced to 0V (typ, 27C). Disabled Enabled No Low Charge pump is off and PDSL is forced to 0V (typ, 27C). Disabled Disabled EN Pin The EN pin is a logic input. The state of the EN pin and the presence or absence of the adapter determines the state of PDSL, the IINP path, and the charger function as shown in Table 1. 30mA LDO The 5.4V LDO is powered from DCIN and is compensated for loads from 0 to 30mA with a single 1FF ceramic capacitor. The load regulation over the 30mA load is 34mV (typ), 100mV max. The LDO supplies the drive for the DLO driver and also the BST circuitry. It is shut down when the adapter is absent. Analog Input Current Monitor Output IINP monitors the system-input current sensed across the sense resistor (RS1) that connects between CSSP and CSSN. The voltage at IINP is proportional to the input current according to the following equation: IINPUT = VIINP RS1 x A where IINPUT is the DC current supplied by the AC adapter and A is the gain (20V/V typ). VIINP has a 0V to 2.2V output voltage range. Table 1 shows the charge and IINP status when the adapter is present or absent and as a function of the EN pin. When connected as shown in the standard application circuit, IINP monitors the input system current when the adapter is present or the battery discharge current when the adapter is absent. Leave IINP unconnected if not used. Table 2 is the fault protection and shutdown operation table. Table 2. Fault Protection and Shutdown Operation Table MODE CONTROLLER STATE DRIVER STATE Thermal fault (latched, reset by adapter reinsertion) Charger disabled, PDSL low, LDO, and VAA off DHI and DLO low ACOV fault or less than 3 ACOCP faults (not latched) Charger disabled, PDSL low, LDO, and VAA active DHI and DLO low More than 3 ACOCP faults (latched, reset by adapter reinsertion) Charger disabled, PDSL low, LDO, and VAA off DHI and DLO low Battery OV fault (not latched) Charger disabled, PDSL high, LDO, and VAA active DHI and DLO low SMBus Implementation The MAX17435/MAX17535 receive control inputs from the SMBus interface. The MAX17435/MAX17535 use a subset of the commands documented in the System Management Bus Specifications V1.1, which can be downloaded from www.smbus.org. The MAX17435/ MAX17535 use the SMBus read-word and write-word protocols to communicate with the system controller. The MAX17435/MAX17535 operate only as slave devices with address 0b0001001_ (0x12) and do not initiate communication on the bus. In addition, the MAX17435/ MAX17535 have two identification registers: (0xFF), a 16-bit device ID register and a 16-bit manufacturer ID register (0xFE). The SMBus implementation is similar to the MAX8731A with the addition of the RELEARN() and IINPVoltage() commands. The SMBus is not powered from an external supply, so during states that disable the charger, the SMBus register data is lost, so the register data must be rewritten when reenabled. See Figure 3. 16 High-Frequency, Low-Cost SMBus Chargers The address byte, command byte, and data bytes are transmitted between the START and STOP conditions. The SDA state is allowed to change only while SCL is low, except for the START and STOP conditions. Data is transmitted in 8-bit bytes and is sampled on the rising edge of SCL. Nine clock cycles are required to transfer each byte in or out of the MAX17435/MAX17535 because either the master or the slave acknowledges the receipt of the correct byte during the ninth clock. The MAX17435/ MAX17535 support the charger commands as described in Table 4. Communication starts when the master signals a START condition, which is a high-to-low transition on SDA, while SCL is high. When the master has finished communicating, the master issues a STOP condition, which is a low-tohigh transition on SDA, while SCL is high. The bus is then free for another transmission. Figures 4 and 5 show the timing diagrams for signals on the SMBus interface. a) Write-Word Format S SLAVE W ADDRESS 7 bits 1b MSB LSB 0 COMMAND BYTE 8 bits MSB LSB ACK 1b 0 PRESET TO 0b0001001 ACK 1b 0 Relearn() = 0x3D ChargingCurrent() = 0x14 ChargerVoltage() = 0x15 LOW DATA BYTE 8 bits MSB LSB D7 ACK 1b 0 D0 HIGH DATA BYTE 8 bits MSB LSB D15 ACK P 1b 0 D8 b) Read-Word Format S SLAVE W ADDRESS 7 bits 1b MSB LSB 0 COMMAND BYTE 8 bits MSB LSB ACK 1b 0 PRESET TO 0b0001001 ACK 1b 0 INP_Voltage() = 0x3E S SLAVE ADDRESS 7 bits MSB LSB R ACK 1b 1 1b 0 PRESET TO 0b0001001 LEGEND: S = START CONDITION OR REPEATED START CONDITION ACK = ACKNOWLEDGE (LOGIC-LOW) W = WRITE BIT (LOGIC-LOW) LOW DATA BYTE 8 bits MSB LSB D7 ACK 1b 0 HIGH DATA BYTE 8 bits MSB LSB D0 D15 H I NACK P 1b 1 D8 P = STOP CONDITION NACK = NOT ACKNOWLEDGE (LOGIC-HIGH) R = READ BIT (LOGIC-HIGH) MASTER TO SLAVE SLAVE TO MASTER Figure 3. SMBus Write-Word and Read-Word Protocols A tLOW B tHIGH C D E F G J K L M SMBCLK SMBDATA tSU:STA tHD:STA A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE E = SLAVE PULLS SMBDATA LINE LOW tSU:DAT tHD:DAT tHD:DAT F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO SLAVE H = LSB OF DATA CLOCKED INTO SLAVE I = SLAVE PULLS SMBDATA LINE LOW tSU:STO tBUF J = ACKNOWLEDGE CLOCKED INTO MASTER K = ACKNOWLEDGE CLOCK PULSE L = STOP CONDITION, DATA EXECUTED BY SLAVE M = NEW START CONDITION Figure 4. SMBus Write Timing ______________________________________________________________________________________ 17 MAX17435/MAX17535 The data (SDA) and clock (SCL) pins have Schmitttrigger inputs that can accommodate slow edges. Choose pullup resistors for SDA and SCL to achieve rise times according to the SMBus specifications. MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers A tLOW B C tHIGH D E F G H J I K SMBCLK SMBDATA tSU:STA tHD:STA tSU:DAT A = START CONDITION B = MSB OF ADDRESS CLOCKED INTO SLAVE C = LSB OF ADDRESS CLOCKED INTO SLAVE D = R/W BIT CLOCKED INTO SLAVE tHD:DAT E = SLAVE PULLS SMBDATA LINE LOW F = ACKNOWLEDGE BIT CLOCKED INTO MASTER G = MSB OF DATA CLOCKED INTO MASTER H = LSB OF DATA CLOCKED INTO MASTER tSU:STO tSU:DAT tBUF I = ACKNOWLEDGE CLOCK PULSE J = STOP CONDITION K = NEW START CONDITION Figure 5. SMBus Read Timing Battery Charger Commands The MAX17435/MAX17535 support four battery-charger commands that use either write-word or read-word protocols as summarized in Table 3. ManufacturerID() and DeviceID() can be used to identify the MAX17435/MAX17535. On the MAX17435/MAX17535, ManufacturerID() always returns 0x004D and DeviceID() always returns 0x0008. Setting Charge Voltage To set the output voltage, use the SMBus to write a 16-bit ChargeVoltage() command using the data format listed in Table 4. The ChargeVoltage() command uses the write-word and read-word protocols (see Figure 3). The command code for ChargeVoltage() is 0x15 (0b00010101). The MAX17435/MAX17535 provide a charge-voltage range of 4.095V to 19.200V, with 16mV resolution. Set ChargeVoltage() below 4.095V to terminate charging. Upon reset, the ChargeVoltage() and ChargeCurrent() values are cleared and the charger remains off until both the ChargeVoltage() and the ChargeCurrent() command are sent. Both DHI and DLO remain low until the charger is restarted. Setting Charge Current To set the charge current, use the SMBus to write a 16-bit ChargeCurrent() command using the data format listed in Table 5. The ChargeCurrent() command uses the write-word and read-word protocols (see Figure 3). The command code for ChargeCurrent() is 0x14 (0b00010100). When RS2 = 10mI, the MAX17435/MAX17535 provide a chargecurrent range of 128mA to 8.064A, with 128mA resolution. If a sense resistor other than 10mI is used, the current limit must be scaled by RS/10mI, where RS is the sense resistor value used on the circuit. Set ChargeCurrent() to 0 to terminate charging. Upon reset, the ChargeVoltage() and ChargeCurrent() values are cleared and the charger remains off until both the ChargeVoltage() and the ChargeCurrent() command are sent. Both DHI and DLO remain low until the charger is restarted. The MAX17435/MAX17535 include a fault limiter for low-battery conditions. If the battery voltage is less than 3V, the charge current is temporarily set to 128mA. The ChargeCurrent() register is preserved and becomes active again when the battery voltage is higher than 3V. This function effectively provides a foldback current limit that protects the charger during short circuit and overload. Table 3. Battery Charger Command Summary COMMAND COMMAND NAME READ/WRITE 0x14 ChargeCurrent() Read and write 0x15 ChargeVoltage() Read and write 0x3D Relearn Voltage Read and write 0x3E IINPVoltage() Read only 0x3F InputCurrent() Read and write 0xFE ManufacturerID() 0xFF DeviceID() DESCRIPTION 6-bit charge-current setting, readback (3'b0, 6'bx, 7'b0) 11-bit charge-voltage setting, readback (1'b0, 11'bx, 4'b0) 11-bit relearn voltage set and 1-bit enable/status POR STATE 0x0000 0x0000 0x4B00 Read only Digital readback of IINP voltage 6-bit input-current setting readback (3'b0, 6'bx, 7'b0) Manufacturer ID 0x004D Read only Device ID 0x0008 Note: `x' means the data is sent to the analog block. 18 NA 0x1000 High-Frequency, Low-Cost SMBus Chargers BIT BIT NAME 0 -- Not used. Normally a 1mV weight. DESCRIPTION 1 -- Not used. Normally a 2mV weight. 2 -- Not used. Normally a 4mV weight. 3 -- Not used. Normally an 8mV weight. 4 Charge Voltage, DACV 0 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 16mV of charger voltage compliance. 5 Charge Voltage, DACV 1 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 32mV of charger voltage compliance. 6 Charge Voltage, DACV 2 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 64mV of charger voltage compliance. 7 Charge Voltage, DACV 3 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 128mV of charger voltage compliance. 8 Charge Voltage, DACV 4 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 256mV of charger voltage compliance. 9 Charge Voltage, DACV 5 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 512mV of charger voltage compliance. 10 Charge Voltage, DACV 6 0 = Adds 0mA of charger voltage compliance, 4095mV min. 1 = Adds 1024mV of charger voltage compliance. 11 Charge Voltage, DACV 7 0 = Adds 0mV of charger voltage compliance, 4095mV min. 1 = Adds 2048mV of charger voltage compliance. 12 Charge Voltage, DACV 8 0 = Adds 0mV of charger voltage compliance. 1 = Adds 4096mV of charger voltage compliance. 13 Charge Voltage, DACV 9 0 = Adds 0mV of charger voltage compliance. 1 = Adds 8192mV of charger voltage compliance. 14 Charge Voltage, DACV 10 0 = Adds 0mV of charger voltage compliance. 1 = Adds 16384mV of charger voltage compliance, 19200mV max. 15 -- Not used. Normally a 32768mV weight. Table 5. ChargeCurrent() (0x14) (10mI Sense Resistor, RS2) BIT BIT NAME 0 -- Not used. Normally a 1mA weight. DESCRIPTION 1 -- Not used. Normally a 2mA weight. 2 -- Not used. Normally a 4mA weight. 3 -- Not used. Normally an 8mA weight. 4 -- Not used. Normally a 16mA weight. 5 -- Not used. Normally a 32mA weight. 6 -- Not used. Normally a 64mA weight. 7 Charge Current, DACI 0 0 = Adds 0mA of charger current compliance. 1 = Adds 128mA of charger current compliance. 8 Charge Current, DACI 1 0 = Adds 0mA of charger current compliance. 1 = Adds 256mA of charger current compliance. ______________________________________________________________________________________ 19 MAX17435/MAX17535 Table 4. ChargeVoltage() (0x15) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Table 5. ChargeCurrent() (0x14) (10mI Sense Resistor, RS2) (continued) BIT BIT NAME DESCRIPTION 9 Charge Current, DACI 2 0 = Adds 0mA of charger current compliance. 1 = Adds 512mA of charger current compliance. 10 Charge Current, DACI 3 0 = Adds 0mA of charger current compliance. 1 = Adds 1024mA of charger current compliance. 11 Charge Current, DACI 4 0 = Adds 0mA of charger current compliance. 1 = Adds 2048mA of charger current compliance. 12 Charge Current, DACI 5 0 = Adds 0mA of charger current compliance. 1 = Adds 4096mA of charger current compliance, 8064mA max 13 -- Not used. Normally a 8192mA weight. 14 -- Not used. Normally a 16386mA weight. 15 -- Not used. Normally a 32772mA weight. Setting Input-Current Limit System current normally fluctuates as portions of the system are powered up or put to sleep. By using the inputcurrent-limit circuit, the output-current requirement of the AC wall adapter can be lowered, reducing system cost. The total input current is the sum of the system supply current, the charge current flowing into the battery, and the current required by the charger. When the input current exceeds the input current limit set with the InputCurrent() command, the MAX17435/MAX17535 reduce the charge current to provide priority to system load current. As the system supply current increases, the charge current is reduced as needed to maintain the total input current at the input current limit. The MAX17435/MAX17535 decrease the charge current to zero, if necessary, to reduce the input current to the input current limit. Thereafter, if the system current continues to increase, there is nothing the MAX17435/MAX17535 can do to maintain the input current at the input current limit. If the system current continues to increase so that the input current exceeds the ACOCP threshold (130% of InputCurrent() setting) for more than 16ms (typ), the MAX17435/MAX17535 drive PDSL low, which turns off the adapter selector FETs and disconnects the adapter from the system. After waiting 0.6s, the MAX17435/MAX17535 re-enable PDSL. If the ACOCP fault occurs again, the MAX17435/MAX17535 drive PDSL low again after the 16ms (typ) delay. This cycle is repeated a maximum of three times, after which the MAX17435/MAX17535 are latched off, and need to be reset by removing and reinserting the adapter. The total input current can be estimated as follows: IINPUT = I SYSTEM + I CHARGER + where E is the efficiency of the DC-DC converter (typically 85% to 95%). To set the input current limit, use the SMBus to write a 16-bit InputCurrent() using the data format listed in Table 6. The InputCurrent() command uses the write-word and read-word protocols (see Figure 3). The command code for InputCurrent() is 0x3F (0b00111111). When RS1 = 10mI, the MAX17435/MAX17535 provide an input current-limit range of 256mA to 11.004A with 256mA resolution. If a resistor RS other than 10mI is used, the input current limit is scaled by a factor of 10mI/RS1. InputCurrent() settings from 1mA to 256mA result in a current limit of 256mA. Upon reset, the input current limit is 256mA. Setting Relearn Voltage To set the relearn voltage, use the SMBus to write a 16-bit RelearnVoltage() command using the data format listed in Table 7. The RelearnVoltage() command uses the write-word and read-word protocols (see Figure 3). The command code for RelearnVoltage() is 0x3D (0b00111101). The MAX17435/MAX17535 provide a charge-voltage range of 4.095V to 19.200V with 16mV resolution. When the relearn function is enabled by setting bit 0 to 1, the MAX17435/MAX17535 drive PDSL low, turning off the adapter selector FETs and turning on the battery selector FET. This allows the battery to discharge by powering the system while the adapter is still present. The battery voltage is monitored until the battery voltage reaches the relearn voltage corresponding to a known low state of charge. The relearn bit 0 is set to zero, and PDSL is re-enabled. [(I CHARGE x VBATTERY ) (VIN x )] 20 High-Frequency, Low-Cost SMBus Chargers BIT BIT NAME DESCRIPTION 0 -- Not used. Normally a 2mA weight. 1 -- Not used. Normally a 4mA weight. 2 -- Not used. Normally an 8mA weight. 3 -- Not used. Normally a 16mA weight. 4 -- Not used. Normally a 32mA weight. 5 -- Not used. Normally a 64mA weight. 6 -- Not used. Normally a 128mA weight. 7 Input Current, DACS 0 0 = Adds 0mA of input current compliance. 1 = Adds 256mA of input current compliance. 8 Input Current, DACS 1 0 = Adds 0mA of input current compliance. 1 = Adds 512mA of input current compliance. 9 Input Current, DACS 2 0 = Adds 0mA of input current compliance. 1 = Adds 1024mA of input current compliance. 10 Input Current, DACS 3 0 = Adds 0mA of input current compliance. 1 = Adds 2048mA of input current compliance. 11 Input Current, DACS 4 0 = Adds 0mA of input current compliance. 1 = Adds 4096mA of input current compliance. 12 Input Current, DACS 5 0 = Adds 0mA of input current compliance. 1 = Adds 8192mA of input current compliance, 11004mA max. 13 -- Not used. Normally a 16384mA weight. 14 -- Not used. Normally a 32768mA weight. 15 -- Not used. Normally a 65536mA weight. Table 7. Relearn() (0x3D) BIT 0 BIT NAME Relearn, RL 0 DESCRIPTION 0 = Disables the relearn function. 1 = Enables the relearn function. When the relearn threshold is crossed as the battery discharges, bit 0 is reset to zero by the MAX17435/MAX17535. 1 -- Not used. 2 -- Not used. 3 -- Not used. 4 Relearn, RL 1 0 = Adds 0mV of relearn threshold compliance, 1024mV min. 1 = Adds 16mV of relearn threshold compliance. 5 Relearn, RL 2 0 = Adds 0mV of relearn threshold compliance, 1024mV min. 1 = Adds 32mV of relearn threshold compliance. 6 Relearn, RL 3 0 = Adds 0mV of relearn threshold compliance, 1024mV min. 1 = Adds 64mV of relearn threshold compliance. 7 Relearn, RL 4 0 = Adds 0mV of relearn threshold compliance, 1024mV min. 1 = Adds 128mV of relearn threshold compliance. 8 Relearn, RL 5 0 = Adds 0mV of relearn threshold compliance, 1024mV min. 1 = Adds 256mV of relearn threshold compliance. ______________________________________________________________________________________ 21 MAX17435/MAX17535 Table 6. InputCurrent() (0x3F) (10mI Sense Resistor, RS1) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Table 7. Relearn() (0x3D) (continued) BIT BIT NAME DESCRIPTION 9 Relearn, RL 6 0 = Adds 0mV of relearn threshold compliance, 1024mV min. 1 = Adds 512mV of relearn threshold compliance. 10 Relearn, RL 7 0 = Adds 0mA of relearn threshold compliance. 1 = Adds 1024mV of relearn threshold compliance. 11 Relearn, RL 8 0 = Adds 0mV of relearn threshold compliance. 1 = Adds 2048mV of relearn threshold compliance. 12 Relearn, RL 9 0 = Adds 0mV of relearn threshold compliance. 1 = Adds 4096mV of relearn threshold compliance. 13 Relearn, RL 10 0 = Adds 0mV of relearn threshold compliance. 1 = Adds 8192mV of relearn threshold compliance. 14 Relearn, RL 11 0 = Adds 0mV of relearn threshold compliance. 1 = Adds 16384mV of relearn threshold compliance, 19200mV max. 15 -- Not used. Reading IINP Voltage To read the digital version of the IINP voltage, issue the SMBus command IINPVoltage() command using the 16-bit data format listed in Table 8. The command code for IINPVoltage() is 0x3E (0b00111110). The IINPVoltage() command uses the read-word protocol (see Figure 3). Charger Timeout The MAX17435/MAX17535 include a timer to terminate charging if the charger has not received a ChargeVoltage() or ChargeCurrent() command within 140s (min). If a timeout occurs, both ChargeVoltage() and ChargeCurrent() commands must be sent again to reenable charging. Table 8. IINPVoltage() (0x3E) BIT BIT NAME 0 -- Not used. Normally a 1mV weight. DESCRIPTION 1 -- Not used. Normally a 2mV weight. 2 -- Not used. Normally a 4mV weight. 3 -- Not used. Normally a 8mV weight. 4 IINP Voltage, DACV 0 0 = Adds 0mV of IINP voltage. 1 = Adds 12.8mV of IINP voltage. 5 IINP Voltage, DACV 1 0 = Adds 0mV of IINP voltage. 1 = Adds 25.6mV of IINP voltage. 6 IINP Voltage, DACV 2 0 = Adds 0mV of IINP voltage. 1 = Adds 51.2mV of IINP voltage. 7 IINP Voltage, DACV 3 0 = Adds 0mV of IINP voltage. 1 = Adds 103.6mV of IINP voltage. 8 IINP Voltage, DACV 4 0 = Adds 0mV of IINP voltage. 1 = Adds 207.2mV of IINP voltage. 9 IINP Voltage, DACV 5 0 = Adds 0mV of IINP voltage. 1 = Adds 414.4mV of IINP voltage. 22 High-Frequency, Low-Cost SMBus Chargers BIT BIT NAME DESCRIPTION 10 IINP Voltage, DACV 6 0 = Adds 0mA of IINP voltage. 1 = Adds 828.8mV of IINP voltage. 11 IINP Voltage, DACV 7 0 = Adds 0mV of IINP voltage. 1 = Adds 1.6576V of IINP voltage to a maximum of 2.20V. 12 -- Not used. Normally a 4096mV weight. 13 -- Not used. Normally a 8192mV weight. 14 -- Not used. Normally a 16384mV weight. 15 -- Not used. Normally a 32768mV weight. DC-DC Converter The MAX17435/MAX17535 employ a synchronous stepdown DC-DC converter with an n-channel, high-side MOSFET switch and an n-channel low-side synchronous rectifier. The MAX17435/MAX17535 feature a pseudofixed-frequency, current-mode control scheme with cycleby-cycle current limit. The controller's constant off-time (tOFF) is calculated based on VDCIN, VCSIN, and a time constant with a minimum value of 300ns. The MAX17435/ MAX17535 can also operate in discontinuous conduction mode for improved light-load efficiency. The operation of the DC-DC controller is determined by the following five comparators as shown in the block diagram in Figure 2: U The IMIN comparator sets the peak inductor current in discontinuous mode. IMIN compares the control signal (LVC) against 100mV (typ). When LVC voltage is less than 100mV, DHI and DLO are both low. U The CCMP comparator is used for current-mode regulation in continuous conduction mode. CCMP compares LVC against the charging current feedback signal (CSI). The comparator output is high and the high-side MOSFET on-time is terminated when the CSI voltage is higher than LVC. U The IMAX comparator provides a cycle-by-cycle current limit. IMAX compares CSI to 2V (corresponding to 10A when RS2 = 10mI). The comparator output is high and the high-side MOSFET on-time is terminated when the current-sense signal exceeds 10A. A new cycle cannot start until the IMAX comparator output goes low. U The ZCMP comparator provides zero-crossing detection during discontinuous conduction. ZCMP compares the current-sense feedback signal to 500mA (RS2 = 10mI). When the inductor current is lower than the 500mA threshold, the comparator output is high and DLO is turned off. U The OVP comparator checks for the battery voltage 400mV above the set point and, if that condition is detected, it disables charging. CCV, CCI, CCS, and LVC Control Blocks The MAX17435/MAX17535 control input current (CCS control loop), charge current (CCI control loop), or charge voltage (CCV control loop), depending on the operating condition. The three control loops, CCV, CCI, and CCS are brought together internally at the lowest voltage clamp (LVC) amplifier. The output of the LVC amplifier is the feedback control signal for the DC-DC controller. The minimum voltage at the CCV, CCI, or CCS appears at the output of the LVC amplifier and clamps the other control loops to within 0.3V above the control point. Clamping the other two control loops close to the lowest control loop ensures fast transition with minimal overshoot when switching between different control loops (see the Compensation section). Continuous Conduction Mode With sufficient charge current, the MAX17435/ MAX17535s' inductor current never crosses zero, which is defined as continuous conduction mode. The MAX17435 switches at 850kHz (nominal) and the MAX17535 switches at 500kHz (nominal) if the charger is not in dropout (VCSIN < 0.88 x VDCIN). The controller starts a new cycle by turning on the high-side MOSFET and turning off the low-side MOSFET. When the charge current feedback signal (CSI) is greater than the control point (LVC), the CCMP comparator output goes high and the controller initiates the off-time by turning off the highside MOSFET and turning on the low-side MOSFET. The operating frequency is governed by the off-time and is dependent upon VCSIN and VDCIN. At the end of the fixed off-time, the controller initiates a new cycle if the control point (LVC) is greater than 150mV, and the peak charge current is less than the cycle-bycycle current limit. Restated another way, IMIN must be high, IMAX must be low, and OVP must be low for the ______________________________________________________________________________________ 23 MAX17435/MAX17535 Table 8. IINPVoltage() (0x3E) (continued) MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers controller to initiate a new cycle. If the peak inductor current exceeds IMAX comparator threshold or the output voltage exceeds the OVP threshold, then the on-time is terminated. The cycle-by-cycle current limit effectively protects against overcurrent and short-circuit faults. Under extremely light loads, the BST capacitor may become discharged if there is no DLO pulse. After 192s (typ), the MAX17435/MAX17535 turn on DLO for 300ns and 550ns, respectively, to recharge the BST capacitor. This DLO pulse need not be followed by a DHI pulse. If, during the off-time, the inductor current goes to zero, the ZCMP comparator output pulls high, turning off the low-side MOSFET. Both the high- and low-side MOSFETs are turned off until another cycle is ready to begin. The MAX17435/ MAX17535 enter into the discontinuous conduction mode (see the Discontinuous Conduction section). The CCI loop is internally compensated. The CCV and the CCS share the external compensation capacitor. The control loop, which is dominant, uses the external compensation cap and the one that is not used uses an internal compensation capacitor. The on-time is calculated according to the following equation: t ON = L x IRIPPLE VCSSN - VBATT where: V xt IRIPPLE = BATT OFF L There is a 0.3Fs minimum off-time when the (VDCIN VBATT) differential becomes too small. If VBATT R 0.88 x VDCIN, then the threshold for minimum off-time is reached and the off-time is fixed at 0.27Fs. The switching frequency in this mode varies according to the equation: 1 f= L x IRIPPLE + t OFF VCSSN - VBATT Discontinuous Conduction The MAX17435/MAX17535 can also operate in discontinuous conduction mode to ensure that the inductor current is always positive. The MAX17435/ MAX17535 enter discontinuous conduction mode when the output of the LVC control point falls below 110mV. For RS2 = 10mI, this corresponds to 367mA: Compensation CCV Loop Compensation The simplified schematic in Figure 6 is sufficient to describe the operation of the MAX17435/MAX17535 when the voltage loop (CCV) is in control. The required compensation network is a pole-zero pair formed with CCC and RCC, which is an internal 1.7kI. The pole is necessary to roll off the voltage loop's response at low frequency; CCC = 330pF is sufficient for most applications. MOSFET Drivers The DHI and DLO outputs are optimized for driving moderate-sized power MOSFETs. The MOSFET drive capability is the same for both the low-side and highsides switches. This is consistent with the variable duty factor that occurs in the notebook computer environment where the battery voltage changes over a wide range. There must be a low-resistance, low-inductance path from the DLO driver to the MOSFET gate to prevent shootthrough. Otherwise, the sense circuitry in the MAX17435/ MAX17535 interprets the MOSFET gate as off while there is still charge left on the gate. Use very short, wide traces measuring 10 squares to 20 squares or less (1.25mm to 2.5mm wide if the MOSFET is 25mm from the device). Unlike the DLO output, the DHI output uses a 50ns (typ) delay time to prevent the low-side MOSFET from turning on until DHI is fully off. The same considerations should be used for routing the DHI signal to the high-side MOSFET. 110mV IDIS = 1 x = 367mA 2 15 x RS2 In discontinuous mode, a new cycle is not started until the LVC voltage rises above 150mV. Discontinuous mode operation can occur during conditioning charge of overdischarged battery packs, when the charge current has been reduced sufficiently by the CCS control loop, or when the charger is in constant-voltage mode with a nearly full battery pack. BATT GM(OUT) where IDIS is the current level for discontinuous conduction. RESR COUT CC gMV RCC ROGMV CCC REF Figure 6. CC Loop Diagram 24 RL High-Frequency, Low-Cost SMBus Chargers Design Procedure MOSFET Selection Choose the n-channel MOSFETs according to the maximum required charge current. Low-current applications usually require less attention. The high-side MOSFET (N1) must be able to dissipate the resistive losses plus the switching losses at both VDCI(MIN) and VDCIN(MAX). Calculate both these sums. Ideally, the losses at VDCIN(MIN) should be roughly equal to losses at VDCIN(MAX) with lower losses in between. If the losses at VDCIN(MIN) are significantly higher than the losses at VDCIN(MAX), consider increasing the size of N1. Conversely, if the losses at VDCIN(MAX) are significantly higher than the losses at VIN(MIN), consider reducing the size of N1. If DCIN does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. Choose a low-side MOSFET that has the lowest possible on-resistance (RDS(ON)), comes in a moderate-sized package (i.e., one or two 8-pin SO, DPAK, or D2 PAK), and is reasonably priced. Make sure that the DLO gate driver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to-drain capacitor caused by the high-side MOSFET turning on; otherwise, cross-conduction problems can occur. Select devices that have short turn-off times, and make sure that: N2(tDOFF(MAX)) - N1(tDON(MIN)) < 40ns, and N1(tDOFF(MAX)) - N2(tDON(MIN)) < 40ns Failure to do so could result in efficiency-reducing shootthrough currents. MOSFET Power Dissipation Worst-case conduction losses occur at the duty factor extremes. For the high-side MOSFET, the worst-case power dissipation (PD) due to resistance occurs at the minimum supply voltage: 2 V I PD(High - side) = BATT LOAD x R DS(ON) V 2 DCIN Generally, a small high-side MOSFET is desired to reduce switching losses at high input voltages. However, the RDS(ON) required to stay within package powerdissipation limits often limits how small the MOSFET can be. The optimum occurs when the switching (AC) losses equal the conduction (RDS(ON)) losses. Switching losses in the high-side MOSFET can become an insidious heat problem when maximum AC adapter voltages are applied, due to the squared term in the CV2 f switchingloss equation. If the high-side MOSFET that was chosen for adequate RDS(ON) at low supply voltages becomes extraordinarily hot when subjected to VIN(MAX), then choose a MOSFET with lower losses. Calculating the power dissipation in N1 due to switching losses is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn-off times. These factors include the internal gate resistance, gate charge, threshold voltage, source inductance, and PCB layout characteristics. The following switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including a verification using a thermocouple mounted on N1: PD(HS_Switching) = VDCIN(MAX) 2 x C RSS x fSW x ILOAD 2 x IGATE where CRSS is the reverse transfer capacitance of N1 and IGATE is the peak gate-drive source/sink current (3.3A sourcing and 5A sinking). For the low-side MOSFET (N2), the worst-case power dissipation always occurs at maximum input voltage: 2 V I PD(Low - side) = 1- BATT LOAD x R DS(ON) VDCIN 2 Inductor Selection The charge current, ripple, and operating frequency (off-time) determine the inductor characteristics. For optimum efficiency, choose the inductance according to the following equation: L = VBATT O tOFF/(0.3 x ICHG) This sets the ripple current to 1/3 the charge current and results in a good balance between inductor size and efficiency. Higher inductor values decrease the ripple current. Smaller inductor values require high saturation current capabilities and degrade efficiency. Due to the minimum tOFF blanking effect upon zerocrossing detection, higher inductor values are desired for proper operation for a design with low input voltage and high output voltage, especially for MAX17535. ______________________________________________________________________________________ 25 MAX17435/MAX17535 The high-side driver (DHI) swings from LX to 5V above LX (BST) and has a typical impedance of 1.5I sourcing and 0.8I sinking. The low-side driver (DLO) swings from DLOV to ground and has a typical impedance of 3I sinking and 3I sourcing. This helps prevent DLO from being pulled up when the high-side switch turns on due to capacitive coupling from the drain to the gate of the low-side MOSFET. This places some restrictions on the MOSFETs that can be used. Using a low-side MOSFET with smaller gate-to-drain capacitance can prevent these problems. MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Inductor L1 must have a saturation current rating of at least the maximum charge current plus 1/2 the ripple current (DIL): ISAT = ICHG + (1/2) DIL The ripple current is determined by: DIL = VBATT O tOFF/L where: tOFF = 2.5Fs (VDCIN - VBATT)/ VDCIN for VBATT < 0.88 VDCIN or: tOFF = 0.3Fs for VBATT > 0.88 VDCIN Input Capacitor Selection The input capacitor must meet the ripple current requirement (IRMS) imposed by the switching currents. Nontantalum chemistries (ceramic, aluminum, or OS-CON) are preferred due to their resilience to powerup surge currents: V BATT (VDCIN - VBATT ) IRMS = I CHG VDCIN The input capacitors should be sized so that the temperature rise due to ripple current in continuous conduction does not exceed approximately 10NC. The maximum ripple current occurs at 50% duty factor or VDCIN = 2 x VBATT, which equates to 0.5 x ICHG. If the application of interest does not achieve the maximum value, size the input capacitors according to the worstcase conditions. Output Capacitor Selection The output capacitor absorbs the inductor ripple current and must tolerate the surge current delivered from the battery when it is initially plugged into the charger. As such, both capacitance and ESR are important parameters in specifying the output capacitor as a filter and to the ensure stability of the DC-DC converter. See the Compensation section. Beyond the stability requirements, it is often sufficient to make sure that the output capacitor's ESR is much lower than the battery's ESR. Either tantalum or ceramic capacitors can be used on the output. Ceramic devices are preferable because of their good voltage ratings and resilience to surge currents. For most applications the output capacitance can be as low as 4.7FF. If the output voltage is low and the input voltage is high, the output capacitance may need to be increased. Applications Information Layout and Bypassing Bypass DCIN with a 0.1FF ceramic to ground (Figure 1). N3 and Q1A protect the MAX17435/MAX17535 when the DC power source input is reversed. Bypass VCC, DCIN, LDO, and VAA, as shown in Figure 1. Good PCB layout is required to achieve specified noise immunity, efficiency, and stable performance. The PCB layout artist must be given explicit instructions-- preferably, a sketch showing the placement of the power switching components and high current routing. Refer to the PCB layout in the MAX17435 and MAX17535 Evaluation Kits for examples. A ground plane is essential for optimum performance. In most applications, the circuit is located on a multilayer board, and full use of the four or more copper layers is recommended. Use the top layer for high current connections, the bottom layer for quiet connections, and the inner layers for an uninterrupted ground plane. Use the following step-by-step guide: 1) Place the high-power connections first, with their grounds adjacent: U Minimize the current-sense resistor trace lengths, and ensure accurate current sensing with Kelvin connections. U Minimize ground trace lengths in the high-current paths. U Minimize other trace lengths in the high-current paths. U Use > 5mm wide traces in the high-current paths. U Connect C1 and C2 to high-side MOSFET (10mm max length). U Minimize the LX node (MOSFETs, rectifier cathode, inductor (15mm max length). Keep LX on one side of the PCB to reduce EMI radiation. 26 High-Frequency, Low-Cost SMBus Chargers 2) Place the IC and signal components. Keep the main switching node (LX node) away from sensitive analog components (current-sense traces and VAA capacitor). Important: The IC must be no further than 10mm from the current-sense resistors. Quiet connections to VAA, CC, ACIN, and DCIN should be returned to a separate ground (GND) island. The appropriate traces are marked on the schematic with the () ground symbol. There is very little current flowing in these traces, so the ground island need not be very large. When placed on an inner layer, a sizable ground island can help simplify the layout because the low current connections can be made through vias. The ground pad on the backside of the package should also be connected to this quiet ground island. 3) Keep the gate drive traces (DHI and DLO) as short as possible (L < 20mm), and route them away from the current-sense lines and REF. These traces should also be relatively wide (W > 1.25mm). 4) Place ceramic bypass capacitors close to the IC. The bulk capacitors can be placed further away. Place the current-sense input filter capacitors under the part, connected directly to the GND pin. 5) Use a single-point star ground placed directly below the part at the PGND pin. Connect the power ground (ground plane) and the quiet ground island at this location. Refer to the MAX17435 and MAX17535 Evaluation Kit layouts for a layout example. Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE No. LAND PATTERN No. 24 TQFN-EP T2444+3 21-0139 90-0021 ______________________________________________________________________________________ 27 MAX17435/MAX17535 Ideally, surface-mount power components are flush against one another with their ground terminals almost touching. These high-current grounds are then connected to each other with a wide, filled zone of top-layer copper, so they do not go through vias. The resulting top-layer subground plane is connected to the normal inner-layer ground plane at the paddle. Other high-current paths should also be minimized, but focusing primarily on short ground and currentsense connections eliminates about 90% of all PCB layout problems. MAX17435/MAX17535 High-Frequency, Low-Cost SMBus Chargers Revision History REVISION NUMBER REVISION DATE 0 7/09 Initial release 1 9/10 Removed the MAX17035 from the data sheet. DESCRIPTION PAGES CHANGED -- 1-28 Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 28 (c) Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.