SSN1N45BTA - Fairchild Semiconductor

SSN1N45B

450V N-Ch annel MOSFET

General Description

These N-Channel enhancement mode power field effect

transistors are produced using Fairchild’s proprietary,

planar, DMOS technology.

This advanced technology has been especially tailored to

minimize on-state resistance, provide superior switching

performance, and withstand high energy pulse in the

avalanche and commutation mode. These devices are well

suited for electronic ballasts based on half bridge

configuration.

Features

• 0.5A, 450V, RDS(on) = 4.25Ω @VGS = 10 V

• Low gate charge ( typical 6.5 nC)

• Low Crss ( typical 6.5 pF)

• 100% avalanche tested

• Improved dv/dt capability

• Gate-Source Voltage ± 50V guaranteed

Absolute Maximum Ratings TC = 25°C unless otherwise noted

Thermal Characteristics

Symbol Parameter SSN1N45B Units

VDSS Drain-Source Voltage 450 V

IDDrain Current - Continuous (TC = 25°C) 0.5 A

- Continuous (TC = 100°C) 0.32 A

IDM Drain Current - Pulsed (Note 1) 4.0 A

VGSS Gate-Source Voltage ± 50 V

EAS Single Pulsed Avalanche Energy (Note 2) 108 mJ

IAR Avalanche Current (Note 1) 0.5 A

EAR Repetitive Avalanche Energy (Note 1) 0.25 mJ

dv/dt Peak Diode Recovery dv/dt (Note 3) 5.5 V/ns

PDPower Dissipation (TA = 25°C) 0.9 W

Power Dissipation (TL = 25°C) 2.5 W

- Derate above 25°C 0.02 W/°C

TJ, Tstg Operating and Storage Temperature Range -55 to +150 °C

TLMaximum lead temperature for soldering purposes,

1/8" from case for 5 seconds 300 °C

Symbol Parameter Typ Max Units

RθJL Thermal Resistance, Junction-to-Lead (Note 6a) -- 50 °C/W

RθJA Thermal Resistance, Junction-to-Ambient (Note 6b) -- 140 °C/W

TO-92

SSN Series

SDG

Rev. A, November 2002

SSN1N45B

Electrical Characteristics TC = 25°C unless otherwise noted

Notes:

1. Repetitive Rating : Pulse width limited by maximum junction temperature

2. L = 75mH, IAS = 1.6A, VDD = 50V, RG = 25 Ω, Starting TJ = 25°C

3. ISD ≤ 0.5A, di/dt ≤ 300A/µs, VDD ≤ BVDSS, Starting TJ = 25°C

4. Pulse Test : Pulse width ≤300µs, Duty cycle ≤2%

5. Essentially independent of operating temperature

6. a) Reference point of the RθJL is the drain lead

b) When mounted on 3”x4.5” FR-4 PCB without any pad copper in a still air environment

(RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance. RθCA is determined by the user’s board design)

Symbol Parame ter Test Condition s Min Typ Max Units

Off Characteristics

BVDSS Drain-S ource Breakdown Voltage VGS = 0 V, ID = 250 µA450 -- -- V

∆BVDSS

/ ∆TJ

Breakdown Voltage Temperature

Coefficient ID = 250 µA, Referenced to 25°C -- 0.5 -- V/°C

IDSS Zero Gate Voltage Drain Current VDS = 450 V, VGS = 0 V -- -- 10 µA

VDS = 360 V, TC = 125°C -- -- 100 µA

IGSSF Gate-Body Leakage Current, Forward VGS = 50 V, VDS = 0 V -- -- 100 nA

IGSSR Gate-Body Leakage Current, Reverse VGS = -50 V, VDS = 0 V -- -- -100 nA

On Characteri st ics

VGS(th) G ate Threshold Voltage VDS = VGS, ID = 250 µA2.3 3.0 3.7 V

VDS = VGS, ID = 250 mA 3.5 4.2 4.9 V

RDS(on) Static Drain-Source

On-Resistance VGS = 10 V, ID = 0.25 A -- 3.4 4.25 Ω

gFS Forward Transconductance VDS = 50 V, ID = 0.25 A -- 0.7 -- S

Dynamic Characteristics

Ciss Input Capacitance VDS = 25 V, VGS = 0 V,

f = 1.0 MHz

-- 185 240 pF

Coss Output Capacitance -- 29 40 pF

Crss Reverse Transfer Capacitance -- 6.5 8.5 pF

Switching Characteristics

td(on) Turn-On Delay Time VDD = 225 V, ID = 0.5 A,

RG = 25 Ω

(Note 4,5)

-- 7.5 25 ns

trTurn-On Rise Time -- 21 50 ns

td(off) Turn-Off De l a y Time -- 23 55 ns

tfTurn -Off Fall Time -- 3 6 80 ns

QgTotal Gate Charge VDS = 360 V, ID = 0.5 A,

VGS = 10 V

(Note 4,5)

-- 6.5 8.5 nC

Qgs Gate-Source Charge -- 0.9 -- nC

Qgd Gate-Drain Charge -- 3.2 -- nC

Drain-Source Di ode Characteristics and Maximum Ratings

ISMaximum Continuous Drain-Source Diode Forward Current -- -- 0.5 A

ISM Maximum Pulsed Drain-Source Diode Forward Current -- -- 4.0 A

VSD Drain-Source Diode Forward Voltage VGS = 0 V, IS = 0.5 A -- -- 1.4 V

trr Reverse Recovery Time VGS = 0 V, IS = 0.5 A,

dIF / dt = 100 A/µs (Note 4)

-- 102 -- ns

Qrr Reverse Recovery Charge -- 0.26 - - µC

Rev. A, November 2002

SSN1N45B

10-1 100101

100

200

300

400 Ciss = Cgs + Cgd (Cds = shorted)

Coss = Cds + Cgd

Crss = Cgd

$ N o te ;

1 . V GS = 0 V

2 . f = 1 MHz

Crss

Coss

Ciss

Capacitance [pF]

VDS, Drain-Source Voltage [V] 01234567

VDS = 225 V

VDS = 90V

VDS = 360 V

$ N o te : ID = 0.5 A

VGS, Gate-Source Voltage [V]

QG, To ta l Gate Cha rg e [n C]

0.2 0.4 0.6 0.8 1.0 1.2 1.4

10-1

100

150%

$ N otes :

1. VGS = 0V

2. 250 &s Pulse Test

25%

IDR, Reverse Drain Current [A]

VSD, S o u rc e -D r ain v olta g e [V ]

012345

VGS = 20V

VGS = 10V

N o te : TJ = 25%

RDS(ON) ['],

Drain-Source On-Resistance

ID, Drain Current [A]

246810

10-1

100

N o te s :

1 . V DS = 50V

2. 250&s Pulse Test

-55%

150%

25%

ID , D ra in C u rre n t [A ]

VGS , Gate -S o u rc e V o ltag e [V ]

10-1 100101

10-1

100

V GS

T op : 1 5 .0 V

10 .0 V

8.0 V

6.0 V

5.5 V

5.0 V

B otto m : 4.5 V

$ N o te s :

1. 250&s Pulse T es t

2. TC = 25%

ID, D ra in C u rr en t [A ]

VDS, Drain-Source Voltage [V]

Typical Characteristics

Figure 5. Capacitance C haracterist ics Figure 6. Gate Charge Characteris tics

Figu re 3. On-Res istance Variation vs.

Drain Current and Gate Voltage Figure 4. Body Diode Fo rwa rd Voltage

Va riation with Source Cur r ent

and Temperature

Figure 2. Transfer CharacteristicsFigure 1. On- R egi on Character ist ic s

SSN1N45B

100101102103

10-3

10-2

10-1

100

101

10 ms

100 ms

1 s

100 µs

1 ms

Operation in This Area

is Limited by R DS(on)

$ Notes :

1. T C = 25 oC

2. T J = 150 oC

3. Single Pulse

ID, D ra in Cu rre n t [A ]

VDS, Drain-Source Voltage [V]

10-5 10-4 10-3 10-2 10-1 100101102103

10-1

100

101

102

$ Notes :

1 . Z (JL(t) = 5 0 %/W Ma x.

2 . Du ty Fa c t o r, D=t1/t2

3 . T JM - TL = P DM * Z(JL(t)

single puls e

D=0.5

0.02

0.2

0.05

0.1

0.01

ZθJL

(t), Therm al R esponse

t1, S quare Wave Pulse D uration [sec]

25 50 75 100 125 150

0.0

0.1

0.2

0.3

0.4

0.5

0.6

ID, D ra in Curre n t [A ]

TC, Case Tem perature [%

]

-100 -50 0 50 100 150 200

0.0

0.5

1.0

1.5

2.0

2.5

3.0

$ Notes :

1 . V GS = 1 0 V

2 . ID = 0.25 A

RDS(ON) , (N o r malize d )

Drain-Source On-Resistance

TJ, Junction Temperature [oC]

-100 -50 0 50 100 150 200

0.8

0.9

1.0

1.1

1.2

N o te s :

1 . V GS = 0 V

2 . ID = 250 &A

BV DSS , (No r ma liz e d )

D rain-Source Breakdow n Voltage

TJ, Junction Tem perature [oC]

Typical Characteristics (Continued)

Figure 9. Maximum Safe Operating Area Figure 10. Maximum Drain Current

vs. Case Temperature

Figu re 7. Breakdo w n Voltage Variation

vs. Temperature Figure 8. On-Resistance Va riation

vs. Temperature

Figure 11. Trans ient Therm al Res ponse Curve

PDM

Rev. A, November 2002

SSN1N45B

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K)

200nF

12V

Same Type

as DUT

Charge

VGS

10V Qg

Qgs Qgd

3mA

VGS

DUT

VDS

300nF

50K)

200nF

12V

Same Type

as DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

VDS

10%

90%

td(on) tr

ton toff

td(off) tf

VDD

10V

VDS RL

DUT

VGS

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

EAS =LI

AS2

----

EAS =LI

AS2

----

1--------------------

BVDSS -V

BVDSS

VDD

VDS

BVDSS

t p

VDD

IAS

VDS (t)

ID (t)

Time

10V DUT

t p

Gate Charge Test Circuit & Waveform

Resistive Switching Test Circuit & Waveforms

Unclamped Inductive Switching Test Circuit & Waveforms

SSN1N45B

Peak Diode Recovery dv/dt Test Circ ui t & Waveform s

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD con troll ed by pulse peri od

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

DUT

VDS

Driver

RGSame Type

as DUT

VGS • dv/dt controlled by RG

•I

SD con troll ed by pulse peri od

VDD

ISD

10V

VGS

( Driver )

ISD

( DUT )

VDS

( DUT )

VDD

Body Diode

Forward Voltage Drop

VSD

IFM , Body Diode Forward Current

Body Diode Reverse Current

IRM

Body Diode Recovery dv/dt

di/dt

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

D = Gate Pulse Width

Gate Pu lse P eri od

--------------------------

SSN1N45B

Dimensions in Millimeters

Package Dimensions

0.46 ±0.10

1.27TYP

(R2.29)

3.86MAX

[1.27 ±0.20]1.27TYP

[1.27 ±0.20]

3.60 ±0.20

14.47 ±0.40

1.02 ±0.10

(0.25) 4.58 ±0.20

4.58 +0.25

–0.15

0.38 +0.10

–0.05

0.38 +0.10

–0.05

TO-92

Dimensions in Millimeters

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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY

PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY

LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN;

NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR

CORPORATION.

As used herein:

1. Life support devices or systems are devic es or syst em s

which, (a) ar e intended for surgical implant into the body,

or (b) support or sustain life, or (c) whose failure to perform

when properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to

result in significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be

reasonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

PRODUCT STATUS DEFINITIONS

Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or In

Design This datasheet contains the design specifications for

product development. Specifications may change in

any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.

Fairchild Semiconduct or reserv es the right to make

changes at any time without notice in order to improve

design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild

Semiconductor reserves the right to make changes at

any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.

The datasheet is printed for reference information only.

Rev. I1

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