National Semiconductor ADC0852/ADC0854 Multiplexed Comparator with 8-Bit Reference Divider General Description The ADCO852 and ADC0854 are CMOS devices that com- bine a versatile analog input multiplexer, voltage compara- tor, and an 8-bit DAC which provides the comparators threshold voltage (VT). The comparator provides a 1-bit output as a result of a comparison between the analog input and the DACs output. This allows for easy implementation of set-point, on-off or bang-bang control systems with several advantages over previous devices. The ADC0854 has a 4 input multiplexer that can be software configured for single ended, pseudo-differential, and full-dif- ferential modes of operation. In addition the DAC's refer- ence input is brought out to aliow for reduction of the span. The ADCO852 has a two input multiplexer that can be con- figured as 2 single-ended or 1 differential input pair. The DAC reference input is internally tied 10 Voc. The multiplexer and 8-bit DAC are programmed via a serial data input word. Once programmed the output is updated once each clock cycle up to a maximum clock rate of 400 kHz. Features @ 2 or 4 channel multiplexer @ Differential or Single-ended input, software controlled @ Serial digital data interface @ 256 programmable reference voltage levels @ Continuous comparison after programming @ Fixed, ratiometric, or reduced span referenca capability (ADC 0854) Key Specifications @ Accuracy, + 14 LSB or + 1 LSB of Reference (0.2%) m Single 5V power supply m Low Power, 15 mW CLK Vacr 8-8IT VTH DAC ~ bo acnD ____ COMPARATOR + vyt Oo m | vn + Vin Vee i INPUT MUX DGND CHO CHT =CH2 CH3 COM TL/H/5521-1 FIGURE 1, ADC0854 Simplified Block Diagram (ADC0852 has 2 Input channels, COM tied to GND, Ver tied to Voc, V+ omitted, and one GND connection) 2 Channel and ADC0852 2-CHANNEL MUX Dual-In-Line Package si 8 Ver. (Veer) CcHOq2 77 CK ADC0852 CHim43 6FD0 GND (COM) 44 5FD! TL/H/5521-10 Top View AGND and COM internally connected to GND Vaer internally connected to Voc Order Number ADC0852 See NS Package Number JO8A or NOSE 4 Channel Pin Out ADC0854 4-CHANNEL MUX Dual-In-Line Package c-i 14} Vog cHo42 13,y* cHi43 12-0 CH274 = ADC0854 11 CLK cH345 10/00 COM46 SF Veer DGND 47 8}aGND TL/H/5521~11 Top View Order Number ADC0854 See NS Package Number Ji4A or N14A 3-187 ps8090Vv/zs8000VADC0852/ADC0854 Absolute Maximum Ratings (notes 1 and 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications. Current into V+ (Note 3) 15mA Supply Voltage, Vcc (Note 3) 6.5V Voltage Logic and Analog Inputs 0.3V to Voc + 0.3V Input Current per Pin +5mA Input Current per Package +20mA Storage Temperature 65C to + 150C Package Dissipation atT, = 25C (Board Mount) 0.8W Lead Temp. (Soldering, 10 seconds) Dual-In-Line Package (plastic) 260C Dual-In-Line Package (ceramic) 300C ESD Susceptibility (Note 14) 2000V Operating Conditions Supply Voltage, Voc 4.5Vpc to 6.3Voc Temperature Range ADCO854BU, ADCO854CJ ADC08528J, ADCO852CJ ADCO0854BCJ, ADCO854CCJ ADC0852BCJ, ADCO852CCJ ADC0854BCN, ADCO854CCN ADC0852BCN, ADC0S52CCN Tain = Ta S Tmax 55C < Ta < 125C 40C < Ta < 85C orc < Ta < 70C Electrical Characteristics the folowing specifications apply for Voc = V+ = 5V (no V+ on ADCO852), Vrer < Voc + 0.1V, fork = 250 kHz unless otherwise specified. Botdface limits apply from Tyn to Twax; all other limits Ta = Ty = 26C. ADC0852BCJ/CCJ/Bu/CJ ADC0852BCN/CCN ADC0854BCJ/CCJ/BJ/CJ ADC0854BCN/CCN Parameter Conditions r Tested Design| Tested Design _| Units (Note 4)| _Lient Limit (ote 4)| Limit _ Limit (Note 5) =| (Note 6) {Note 5) (Note 6) CONVERTER AND MULTIPLEXER CHARACTERISTICS Total Unadjusted Vrer Forced to Error (Note 7) 5.000 Voc ADC0852/4/BCN t% +% LSB ADC0852/4/BJ/BCJ t% LSB ADG0852/4/CCN +1 1 LSB ADC0852/4/CJ/CCJ +4 LSB Comparator Offset ADC0852/4/BCN 25 25 10 mV ADC0852/4/BJ/BCJ 25 10 2.5 mV ADC0852/4/CCN 25 2.5 20 mv ADC0852/4/CCJ 2.5 20 2.5 mV Minimum Total Ladder ADC0854 Resistance (Note 15) 3.5 1.3 3.5 1.3 1.3 ko Maximum Total Ladder ADC0854 Resistance (Note 15) 3.5 5.9 3.5 5.4 5.9 ko Minimum Common-Mode | All MUX Inputs Input (Note 8) and COM Input GND-0.05 GND-0.05 | GND-0.05 | V Maximum Gommon-Mode | Ali MUX Inputs Input (Note 8) and GOM Input Vec + 0.05 Veco + 0.051 Vee + 0.05] V DC Common-Mode Error + Ve % te tY% +t% LSB Power Supply Sensitivity | Voc = 5V +5% te t% +e. tM +4 LSB Vz, Internal 15 mA into V+ diode MIN 6.3 6.3 Vv breakdown MAX 8.5 8.5 Vv at V+ (Note 3) loc, Off Channel Leakage | On Channel = 5V, ~1 1 pA Current (Note 9) Off Channel = OV ~ 200 200 nA On Ghannel = OV, +4 +1 pA Off Channel = 5V + 200 +200 nA 3-188Electrical Characteristics (continued) The following specifications apply for Voc = V+ = 5V (no V+ on ADC0852), foLk = 250 kHz unless otherwise specified. Boldface limits apply trom Ty to Twax; all other limits Ta = Ty = 25C. ySs0D0V/zs8000V ADC0852BCJ/CCJ/BJ/CJ ADC0852BCN/CCN ADCO854BCJ/CCJ/BJ/CU ADC0854BCN/CCN Parameter Conditions r Tested | Design | |. Tested | Design | Units Note a | Limit | Limit (Note 4) | Limit | Limit (Note 5} | (Note 6) (Note 5} | (Note 6) CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued) lon, On Channe! Leakage On Channel = 5V, +4 +4 pA Current (Note 8) Off Channel = oV +200 +200 nA On Channel = OV, -1 -1 pA Off Channel = 5V 200 200 nA DIGITAL AND DC CHARACTERISTICS Vinct) Logical 1 Input Voc = .25V 2.0 2.0 2.0 Vv Voltage Vingo) Logical 0 Input Voc = 4.75V 0.8 0.8 0.8 v Voltage linc1): Logical 1" Input Vin = Voc 0.005 1 0.005 1 1 pA Current lino. Logical 0 Input Vin = OV 0.005 4 ~0.005 -1 -1 pA Current Vout) Logical 1 Output | Vog = 4.75V Voltage louT = 360 pA 2.4 2.4 2.4 Vv louT = 10 pA 4.5 4.5 4.5 Vv Voutiop Logical 0 Output | lout = 1.6 mA, Voltage Voo = 4.75V 0.4 0.4 0.4 Vv - lout, TRI-STATE Output | CS = Logical 1 Current (DO) Vout = 0.4V 0.1 -3 ~0.1 -3 -3 pA Vout = 5V 0.1 a 0.1 3 3 BA ISOURCE Vour Short to GND -14 -6.5 14 ~7.5 -6.8 | mA isink Vout Short to Voc 16 8.0 16 9.0 8.0 mA loc Supply Current Includes DAC ADC0852 Ladder Current 2.7 6.5 2.7 6.5 6.5 mA loc Supply Current Does not Include DAC ADC0854 (Note 3) Ladder Current 0.9 2.5 0.9 25 2.5 mA 3-189ADC0852/ADC0854 AC Characteristics :, = | = 20ns, tT, = 25C T Tested Design Symbol Parameter Conditions (ote 4 | Limit Limit Units (Note 5) {Note 6) folk Clock Frequency MIN 10 kHz (Note 12) MAX 400 kHz toi Rising Edge of Ciock OL = 100 pF 650 1000 ns to DO Enabled & Comparator Response Not Including 2+ 12s 1/foik Time (Note 13) Addressing Time Clock Duty Cycle MIN 40 % (Note 10) MAX 60 % tsET-UP CS Falling Edge or MAX 250 ns Data Input Valid to CLK Rising Edge tHoOLD Data Input Valid after MIN 90 ns CLK Rising Edge tod1: tpao | GLK Falling Edge to MAX | CG. = 100 pF 650 1000 ns Output Data Valid (Note 11) ten, ton Rising Edge of CS to MAX | Cy. = 10pF, RA, = 10k 125 250 ns Data Output Hi-Z GC. = 100 pF, RL = 2k 500 500 ns (see TRI-STATE Test Circuits) Cin Capacitance of Logic 5 pF Input Cout Capacitance of Logic 5 pF Outputs Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating the device bayond its specified operating conditions. Note 2: Ali voltages are measured with respect to ground. Note 3: Internal zener diodes (approx. 7V) are connected from V+ to GND and Voc to GND. The zener at V+ can operate as a shunt regulator and is connected to Voc via a conventional diade. Since the zener voltage equals the A/Ds breakdown voltage, the diode ensures that Voc will be below breakdown when the device is powered from V+. Functionality is therefore guaranteed for V+ operation even though the resultant voltage at Vcc may exceed the specified Absolute Max of 6.5. it is recommended that a resistor ba used to limit the max current into V+. Note 4: Typicals are at 25C and represent most likely parametric norm. Note 5: Tasted and guaranteed to National ACQL (Average Outgoing Quality Level). Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels. Note 7: Total unadjusted error includes comparator offset, DAC linearity, and multiplexer arror. It is expressed in LSBs of the threshold DACs input cade. Note B: For Vin()2Vin(+) the output will be 0. Two on-chip diodes are tied to each analog input (see Biock Diagram) which will forward conduct for analog input voltages one diode drop below ground or ona diode drop greater than the Voc supply. Be careful, during testing at low Voc levels (4.5), as high level analog inputs (5V) can cause this input diode to conductespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mY forward bias of either diode. This means that as long as the analog Vin or Vaer does not excaed the supply voltage by more than 50 mV, the output code will be correct. To achieve an absolute 0 Voc to 5 Vpc input voltage range will therefore require a minimum supply voltage of 4.950 Vp over temperature variations, initial tolerance and loading. Note 8: Leakage current ie measured with the clock not switching. Note 10: A 40% to 60% clock duty cycle ranga ensures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these limite then 1.6 pS < CLK Low < 60 nS and 1.6 uS < CLK HIGH < %, Note 11: With CS low and programming complete, DC is updated on each falling CLK edge. However, each new output is based on the comparison completed 0.5 clock cycles prior (see Figure 5). Note 12: Error specs are not guaranteed at 400 kHz (see graph: Comparator Error vs. foi). Note 13: See text, section 1.2. Note 14: Human body model, 100 pF discharged through a 1.5 kf resistor. Note 15: Because the reference ladder of the ADCOB52 is intemally connected to Vcc, ladder resistance cannot be directly tested for the ADCO852. Ladder current ig included in the ADCO852s supply current specification. 3-190Typical Performance Characteristics Internal DAC Linearity 5 Error vs Vaer Voltage ec =5V 1.25 fern = 250 kHz Ta=25C _ ea LINEARITY ERROR (LSB) x & 0 1 2 3 4 5 Veer (Voc) Output Current vs Temperature ; Vcc = 5V 20 5 | Isink Voc = 5 i MS source Voc = OV ty T v Isounce Voc = 2.4 5 ee | | OUTPUT CURRENT (mA} Isinx Voc = 0.4 i L 0 ~100 50 0 50 100 = 150 TEMPERATURE (C) lec, Power Supply Current vs. Temperature, ADC0854* 15 Vee= POWER SUPPLY CURRENT (mA) foun = 250 kHz Cari" 0 7T5-S0~25 0 25 50 75 100 125 TEMPERATURE (C) *For ADCO852 add Ine COMPARATOR OFFSET (mW) LINEARITY ERROR (LSB) POWER SUPPLY CURRENT (mA) Internal DAC Linearity 50 Error vs Temperature \ ML o a Vrer = 5.0 foLw = 250 kHz 0 ~108 50 0 50 100 6150 TEMPERATURE {C} Comparator Offset vs 5 Temperature DN LAA \ 50-25 0 25 SO 75 100 125 TEMPERATURE (C) lec, Power Supply Current vs. fo_x, ADC0854* _ an Veo =5 @ 25C _ o aa Oo 100 200 300) 6400 (500 fLx(kHz) ERROA (mV) Ss 8 8&8 & REFERENCE CURRENT (mA) 8 15 1.0 Comparator Error ve 0 Current vs, Temp. ADC0854 Vacr = 5V 25C G 100 200 300 400 500 600 feux (kHz) Incr, Reference Vec = 5.0 Voc J -50-25 0 25 50 75 100 125 TEMPERATURE (C) TL/H/521+2 3-191 yS80D0V/zss000VADC0852/ADC0854 Timing Diagrams Data Input Timing cx f \ sXe tser-up DATA IN (Di) TL/H/5521-3 Data Output Timing TRI-STATE Test Circuits and Waveforms TEt Vec 10k _ DATA os OUTPUT C, Leakage Test Circuit ov DATA OUTPUT DATA OUT (00) TL/H/5521-4 v ce 50% ts 50% ton Vec po v 10% ot TL/H/5521-5 ton CHO (ON) ADCOBS4 CH1 CH2 p (OFF) chug TL/H/5521-6 3-192ADC0852/ADC0854 Wwes6eIq 4OOIg PaeIeq 2 AUNDIA L-lesS/H/ IL - SLNANI 91901 TWNOLLITONd LAAN { ao yno yyBnoug exe EHO pu ZHO AjuO 20, 0} pen zl T Alreuseyul 61 JHA no yyBnoug 61 29, Ajo ONDq oy peg Ayeu _ il JOU ex WOO pue ONDy ,,4,, 8 0} paaidy $1 39868 NEIS/GGO sunauia NOE Ad \ USNAZ AL JO Indu; Q ey} OF ANoeKp Indu Ss! 1G ZSB0D0y 404 *b SION TWNUALNI new _ mh aNsv 300030 ONY H3007 ol = 1 200N ; ay WANZ AL AWLINGUID > (0 0 '0 3009 xnw) WHHL OL ; vt xO" SOWNY acs OL BX HOLWT 8-2 U 1a u 303 YALSISIH LIS LIS-@ Q HI a 2H | a10N ssaugdy xnw 4WWLS) sf ddg/ 198 | NOS/0C0 m3 3-193wes6eiq Gujwil, SHNDIA Zb-bessyH/TL Sk rh L el Lh "W119 JO eBpg Buljez uo Aju eBueys wea yndyno pyeA 7a0N SIVLS-WL CFTIWAN! LNG G31GYNI 00 HLA MICHS3HHL WYHOOUd - XN WWHOOUd >] zsg030y SERS 309 1.NOd coo J sec | soo J rao | cao | cao | sac gf ogc |nasracofsna/19s] svi ESS > 1d 1) = mow L iNd1N0 OWA ETCTCRTT oa OITWANI Lng G3 7evNa 00 HLA CIOHSIUHL WWHSOUd }+XfW WvH90ud - voaooay ERT <a ego} gea sao | rao | ca | zo | tao | ogo | toss [wssron0] ssi /vas it RSX | monf La. m0 | dN 135, w LL w19 a St rl lL a tL OL 6 8 Z 9 s 5 E 2 L pSs0Ddv/2zS8000V 3-194Functional Description 1. 1 The Sampled-data Comparator The ADC0852 and ADC0854 utilize a sampled-data com- parator structure to compare the analog difference between a selected + and input to an 8-bit programmable threshold. This comparator consists of a CMOS inverter with a capaci- tively coupled input (Figure 4). Analog switches connect the two comparator inputs to the input capacitor and also con- nect the inverters input and output. This device in effect now has one differential input pair. A comparison requires two cycles, one for zeroing the comparator and another for making the comparison. In the first cycle (Figure 4a), one input switch and the invert- ers feedback switch are closed. In this interval, the input capacitor (C) is charged to the connected input (V1) less the inverter's bias voltage (Vp, approx. 1.2 volts). In the second cycle (Figure 4b) these two switches are opened and the other (V2) inputs switch is closed. The input capacitor now subtracts its stored voltage from the second input and the differance is amplified by the inverter's open loop gain. The and C+Cg the output will go high or low depending on the sign of Vp- Ve. inverter input (Vp"} becomes Vg (V1 V2) FIGURE 4. Sampied-Data Comparator V1 o_O v=o s TL/H/5521-8 Vo = VB Vonc = Vy-Vg Cg = Stray Input Node Cap. * Vg = Inverter Input Bias Voltage FIGURE 4a. Zeroing Phase a v2 TL/H/5521-9 Cc Va Vp = (V2-V4) C+O5 *Vo= G+ Srglve- CV; ] * Vois dependent on V2V, FIGURE 4b. Compare Phase Ya(+) 1 =. * vl +) oe Vo == V4) + Cp (V4 - V. 0 Gy + Gp + Gy 1 V2 1) + Co (V4 V3)] =4 _ aac, + aacyl C1 + Co + Cg 1 2 * Comparator Reads V7 from Internal DAC Differentially TL/H/5521-14 FIGURE 4c. Multiple Differential Inputs 3-195 pss0Ddy/zss0DdvADC0852/ADC0854 Functional Description (continued) In actual practice, the devices used in the ADC0852/4 are a simple but important expansion of the basic comparator de- scribed above. As shown in Figure 4c, multiple differential comparisons can be made. In this circuit, the feedback switch and one input switch on each capacitor (A switches) are closed in the first cycle. Then the other input on each capacitor is connected while all of the first switches are opened. The change in voltage at the inverters input, as a result of the change in charge on each input capacitor (C1, C2), will now depend on both input signal differences. 1.2 Input Sampling and Response Time The input phases of the comparator relate to the device clock (CLK) as shown in Figure & Bacause the comparator is a sampling device, its response characteristics are some- what different from those of linear comparators. The Vin(+) input is sampied first (CLK high) followed by Viq() (CLK low). The output responds to those inputs, one half cycle later, on CLKs falling edge. The comparators response time to an input step is depen- dent on the steps phase relation to the CLK signal. If an input step occurs too late to influence the most imminent comparator decision, on more CLK cycle will pass before the output is correct. In effect, the response time for the Vin(+) input has a minimum of 1 CLK cycle + 1 pS anda maximum of 2 CLK cycles + 1 nS. The Vin() inputs delay will range from 1/2 GLK cycle + 1 4S to 1.5 CLK cycles + 1 uS since it is sampled after Vijn(+). The sampied inputs also affect the devices response to pulsed signals. As shown in the shaded areas in Figure 5, pulses that rise and/or fall near the latter part of a CLK half- cycle may be ignored. 1.3 Input Multiplexer A unique input multiplexing scheme has been utilized to pro- vide multiple analog channels with software-configurable single-ended, differential, or pseudo-differential operation. The analog signal conditioning required in transducer-input and other types of data acquisition systems is significantly simplified with this type of input flexibility. One device pack- age can now handle ground referenced inputs as well as signals with some arbitrary reference voltage. On the ADG0854, the common pin (pin 6) is used as the " input for all channels in single-ended mode. Since this input need not be at analog ground, it can be used as the common line for pseudo-differential operation. It may be tied to a reference potential that is common to all inputs and within the input range of the comparator. This feature is especially useful in singie-supply applications where the an- alog circuitry is biased to a potential other than ground. A particular input configuration is assigned during the MUX addressing sequence which occurs prior to the start of a comparison. The MUX address selects which of the analog channels is to be enabled, what the input mode will be, and the input channel! polarity. One limitation is that differential inputs are restricted to adjacent channel pairs. For example, channei 0 and 1 may be selected as a differential pair but they cannot act differentially with any other channel. The channel and polarity selection is done serially via the DI input. A complete listing of the input configurations and cor- responding MUX addresses for the ADCO852 and ADCO854 is shown in tables | and Il. Figure 6 illustrates the analog connections for the various input options. The analog input voltage for each channel can range from 50 mV below ground to 50 mV above Voc (typically 5V) without degrading accuracy. A inj+) AND Vrpy) SAMPLED (ZEROING) B Vin(-) AND Vru+) SAMPLED C ec+) AND Wrxj_) FOR NEXT COMPARISON O OUTPUT UPOATED [ BASED ON AAND 6 E Ving ) AND Vrnys) FOR | NEXT COMPARISON F OUTPUT BASED ONC ANDE sel bal eo SAMPLING UNCERTAINTY FOR TRANSIENTS ON ey+) INPUT DURING THIS TIME SAMPLING UNCERTAINTY FOR TRANSIENTS ON Ving) INPUT DURING THIS TIME TL/H/8521=13 FIGURE 5. Analog Input Timing> Functional Description (continued) S oa TABLE |. MUX Addressing: ADC0854 TABLE jl. MUX Addressing: ADC0652 2 Single-Ended MUX Mode Single Ended MUX Mode > MUX Address Channel MUX Address Channel g SGL/ | ODD/ SGL/ ODD/ DIF | SIGN SELECT | 0 | 1/| 2/3 | COM BIE SIGN 0 1 g 1 0 0 + - 1 0 + 1 0 4 + - 1 1 + 1 1 0 + = COM is internally tied to A GND 1 1 1 + Differential MUX Mode MUX Address Channel Differential MUX Mode SGL/ ODD/ DIF SIGN 0 1 MUX Address Channel 0 0 + - SGL/ | ODD/ DIF SIGN SELECT 0 1 2 3 0 ' _ + 0 G + ~ 0 0 1 + - 0 1 0 -|+ 0 1 1 | + 4 Single-Ended 4 Pseudo-Differential 0 + Oy 1 + 1d + 2 + 2 + gf 3 + COM {- 1 COM (} Le] | = Vous =. 2 Differential = Mixed Mode mes > 0 Hf a1 ) tt) tommy t +{-) 2,3 ay -- (+) gay Fe Vous Lt - TL/H/5521-15 FIGURE 6. Analog input Multiplexer Options for the ADC0854 3-197ADC0852/ADC0854 Functional Description (continued) 2.0 THE DIGITAL INTERFACE An important characteristic of the ADCO852 and ADC0854 is their serial data link with the controlling processor. A seri- al communication format eliminates the transmission of low level analog signals by locating the comparator close to the signal source. Thus only highly noise immune digital signals need to be transmitted back to the host processer. To understand the operation of these devices it is best to refer to the timing diagrams (Figure 3) and functional block diagram (Figure 2) while following a complete comparison sequence. 1. A comparison is initiated by first pulling the CS (chip se- lect) line low. This line must be held low for the entire ad- dressing sequence and comparison. The comparator then waits for a start bit, its MUX assignment word, and an 8-bit code to set the internal DAC which supplies the compara- tors threshold voltage (Vt). 2. An external clock is applied to the CLK input. This clock can be applied continuously and need not be gated on and off. 3. On each rising edge of the clock, the level present on the DI line is clocked into the MUX address shift register. The start bit is the first logic 1" that appears on this line. All leading zeroes are ignored. After the start bit, the ADCO852 expects the next 2 bits to be the MUX assignment word while the ADCO854, with more MUX configurations, looks for 3 bits. 4, Immediately after the MUX assignment word has been clocked in, the shift register then reads the next eight bits as the input code to the internal DAC. This eight bit ward is read LSB first and is used to set the voltage applied to the comparators threshold input {internal). 5. After the rising edge of the 11th or 12th clock (ADCO852 or ADC0854 respectively) following the start bit, the com- parator and DAC programming is complete. At this point the DI line is disabled and ignores further inputs. Also at this time the data out (DO) line comes out of TRI-STATE and enters a dont care state (undefined output) for 1.5 clock cycles. 6. Tha result of the comparison between the programmed threshold voltage and the difference between the two se- fected inputs (Vi (+)Vin ()) is output to the DO line on each subsequent high to low clock transition. 7. After programming, continuous comparison on the same selected channel with the same programmed threshold can Vv a) Ratiometric be done indefinitely, without reprogramming the device, as long as CS remains low. Each new comparator decision will be shifted to the output on the falling edge of the clock. However, the output will, in effect, lag the analog input by 0.5 to 1.5 clock cycles because of the time required to make the comparison and latch the output (see Figure 4). 8. All internal registers are cleared when the CS line is brought high. If another comparison is desired CS must make a high to low transition followed by new address and threshold programming. 3.0 REFERENCE CONSIDERATIONS / RATIOMETRIC OPERATION The voltage applied to the Vref input of the DAC defines the voltage span that can be programmed to appear at the threshold input of the comparator. The ADCO854 can be used in either ratiometric applications or in systems with absolute references. The Vaer pin must be connected to a source capable of driving the DAC ladder resistance (typ. 2.4 kf) with a stable voltage. In ratiometric systems, the analog input voltage is normally a proportion of the DAC's or A/Ds reference voltage. For example, a mechanical position serve using a potentiometer to indicate rotation, could use the sarne voltage to drive the reference as well as the potentiometer. Changes in the val- ue of VReF would not affect system accuracy since only the relative value of these signals to each other is important. This technique relaxes the stability requirements of the sys- tem reference since the analog input and DAC reference move together, thus maintaining the same comparator out- put for a given input condition. In the absolute case, the VreF input can be driven with a stable voltage source whose output is insensitive to time and temperature changes. The LM385 and LM336 are good low current devices for this purpose. The maximum value of Vme_r is limited to the Voc supply voltage. The minimum value can be quite small (see typical performance curves) allowing the effective resolution of the comparator threshold DAC to also be small (VRer = 0.5V, DAG resclution = 2.0 mV). This in turn lets the designer have finer control over the comparator trip point. In such instances however, more care must be taken with regard to noise pickup, grounding, and system error sources. TRANSOUCER OV-1.25 = TL/H/5521-16 b) Absolute with a Reduced Span FIGURE 7. Referencing Examples 3-198Functional Description (continued) 4.0 ANALOG INPUTS 4. 1 Differential Inputs The serial interface of the ADCO852 and ADC0854 allows them to be located right at the analog signal source and to communicate with a controlling processor via a few fairly noise immune digital lines. This feature in itself greatly re- duces the analog front end circuitry often needed to main- tain signal integrity. Nevertheless, a few words are in order with regard to the analog inputs should the input be noisy to begin with or pessibly riding on a large common mode volt- age. The differential input of the comparator actually reduces the effect of common-mode input noise, i.e. signals common to both selacted + and inputs such as 60 Hz line noise. The time interval between sampling the + input and then the input is 4% of a clock period (see Figure 5). The change in the common-mode voltage during this short time interval can cause comparator errors. For a sinusoidal common-mode signal this error is: VERROR (MAX) = Vpgak (27 fow/2 tox) where fom is the frequency of the common-mode signal, Vpeak is its peak voltage value, and foLK is the DAC clock frequency. For example, 1 Vpp 60 Hz noise superimposed on both sides of a differential input signal would cause an error (re- ferred to the input) of 0.75 mV. This amounts to less than Yes of an LSB referred to the threshold DAC, (assuming Vrer = 5V and fcLtk = 250 kHz). 4. 2 Input Currents and Filtering Due to the sampling nature of the analog inputs, short spikes of current enter the + input and leave the "' at the clock edges during a comparison. These currents decay rapidly and do not cause errors as the comparator is strobed at the end of the clock period (see Figure 5). The source resistance of the analog input is important with regard to the DC leakage currents of the input multiplexer. The worst-case leakage currents of +1 A over tempera- ture will create a 1 mV input error with a 1 kQ source Typical Applications 1s Nee GNO ADCO854 TL/H/5621-17 FIGURE 8. An On-Chip Shunt Reguiator Diode resistance. An op-amp RC active low pass filter can provide both impedance buffering and noise filtering should a high impedance source be required. 4. 3 Arbitrary Analog Input/Reterence Range The total span of the DAC output and hence the compara- tors threshold voltage is determined by the DAC reference. For example, if Vagr is set to 1 volt then the comparators threshold can be programmed over a 0 to 1 volt range with 8 bits of resolution. From the analog inputs point of view, this span can aiso be shifted by applying an offset potential to one of the comparators selected analog input lines (usu- ally ). This gives the designer greater contro! of the ADC0852/4s input range and resolution and can help sim- plify or eliminate expensive signal conditioning electronics. An example of this capability is shown in the Load Cell Limit Comparator of Figure 75. In this circuit, the ADCO852 allows the load-cell signal conditioning to be done with only one dual op-amp and without complex, multiple resistor matching. 5.0 POWER SUPPLY A unique feature of the ADCO854 is the inclusion of a 7 volt zener diode connected from the V+ terminal to ground (Figures 2 and & V+ also connects to Vcc via a silicon diode. The zener is intended for use as a shunt voltage regulator to eliminate the need for additional regulating components. This is especially useful if the ADC0854 is to be remotely located from the system power source. An important use of the interconnecting diode between V + and Vcc is shown in Figures 10 and 77. Here this diode is used as a rectifier to allow the Voc supply for the converter to be derived from the comparator clock. The low device current requirements and the relatively high clock frequen- cies used {10 kHz-400 kHz) allows use of the small value filter capacitor shown. The shunt zener regulator can also be used in this mode however this requires a clock voltage swing in excess of 7 volts. Current limiting for the zener is also needed, either built into the clock generator or through a resistor connected from the clock to V+. ADCOS54 CMOS OA NMOS CIRCUITS ANALOG CIRCUITS te t Lt TL/H/5521-18 FIGURE 9. Using the ADC0854 as the System Supply Regulator 3-199 pss00dv/css00dVvADC0852/ADC0854 Typical Applications (continued) IL > >I CLK 1 man Eos Ft TL/H/5521-18 FIGURE 10. Generating Vcc from the Comparator Clock TRANSDUCER TL/H/5521-20 FIGURE 11. Remote SensingClock and Power on One Wire I Va(~-} 10 pF TL/H/5521-21 FIGURE 12. Protecting the Analog Input TO wP Is ji |7 : ol ow CLK By Bf cc Vm Vrer pO ADCOBS2 ty" = GHO CHT z 73 nye! ANALOG INPUT TL/H/5521 -22 FIGURE 13. One Component Window Comparator Requires no additional parts. Window comparisons can be accomplished by inputting the upper and lower window limits into Dt on successive compari- sons and observing the two outputs: Fwo high outputs > input > window Two low outputs input < window One low and one high input is within window 3-200Typical Applications (continued) 110 Vac 5v Ht Is jz DIGITAL CONTROL 7 1 Jaz ji fu of fay CLK 1 9 Ver Vm : 47k 2 ; DO gtd AAA 2N2222 a 4 3h > 67k FUSE avd Ver 3 1 pena 8 f = = anew 110 Vac HEATER 1/2 LM358 sy 1.25 tk 110 Vac Ww > Su ng ? OFFSET S > 2k q Su. Ee ] SCALE $% ad q TL/H/5521-23 FIGURE 14. Serial Input Temperature Controller Note 1: ADC0854 does not require constant service from computer. Self controlled after one write to Dt if CS remains low. Note 2: U,: Solid State Relay, Potter Brumfield #EOM1DB22 Nate 3: Set Temp via. Dl. Range: 0 to 125C 330 10 Wy B.8k laz i Jin ne af : ot cs CLK $ i ac oan $<] * Spies > =j- poll 10 LFa12 + DUAL 2S 2 oawo AL aDcoas4 l BY kena cHO [CH 2 3 WA AK STRAIN GAUGE + LOAD CELL Luray? 3000/30 my FS. DUAL + , = 20k $' 10v 10k OFFSET 20k FIGURE 15. Load Cell Limit Comparator Differential Input eliminates need for instrumentation ampiifier * A total of 4 load calis can be monitored by ADCO854 TL/H/5521-24 3-201 S8090V/2580900VADC0852/ADC0854 Typical Applications (continued) 5 + \7 Is + i wv ol CLK ee ol CLK 6 1ec vw 8 Vm - pols - oors Vaer -- Wer . = Q | : - anceesz - anceet2 4 <|" oy = CHO pot = cHo [cm 2 fa 1mm 7+ alt jm in 3 > th a] YY vv" q TL/H/5821-28 = TL/H/5521-29 * Qy used in inverted mode for low Vgar Hysteresis band = 50 mV FIGURE 16. Adding Comparator Hysteresis 250 kHz 5 i jz 5V ol ts CLK ag cc oe a. pols W Vrer po aneree + 6 0 gee TRIGGER ov + INPUT 4Na148 4 ' ADCO852 1k C1 O GND CHO [CHI am tee DO Lwase Wr 1Ne148 \ 5v = Kew Ov TL/H/5521-27 FIGURE 17. Pulse-Width Modulator Range of pulse-widths controlled via Ry, C; 3-202Typical Applications (continued 250 kHz |7 ov IK. CLA 89 Vcc Vin Ver + + ADcoeS2 BNO cHo | cH 2 {3 = tk hh rvy 1N4148 5v OUTPUT OV-5 TL/H/5521 -28 FIGURE 18. Serial Input 8-Bit DAC Ordering Information Part Number Channels Unedhusted Error Package henge ADC0852B,) JOBA 55C to + 125C ADC0852BCJ +% 40C to + 85C ADC0852BCN 2 NOSE OC to 70C ADCO0852CCJ +4 JOBA 40C to + 86C ADGC0852CCN NOSE OC to 70C ADCO0854BU) J14A 55C to + 125C ADCO0854BCJ t% 40C to + 85C ADCO0854BCN 4 N14A OC to 70C ADCO0854CCJ +4 J14A 40C to + 85C ADC0854CCN N14A OC to 70C 3-203 yssoody/zse0ody