IDT70V657S10BCG8 - Integrated Device Technology

MARCH 2004

DSC-4869/5

128/64/32K x 36

MEMORY

ARRAY

Address

Decoder A

16R(1)

Address

Decoder

Dout0-8_L

Dout9-17_L

Dout18-26_L

Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R

Dout27-35_R

I/O

0L-

I/O

35L

16 L(1)

I/O

0R-

I/O

35R

Di n_L

ADDR_L

Di n_R

ADDR_R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEM

INT

L(3)

BUSY

L(2,3)

M/S

R/W

BUSY

R(2,3)

SEM

INT

R(3)

TMS

TCK

TRST

TDI

TDO JTAG

4869 drw 01

Functional Block Diagram

◆◆

◆Full on-chip hardware support of semaphore signaling

between ports

◆◆

◆Fully asynchronous operation from either port

◆Separate byte controls for multiplexed bus and bus

matching compatibility

◆◆

◆Supports JTAG features compliant to IEEE 1149.1

◆◆

◆LVTTL-compatible, single 3.3V (±150mV) power supply for

core

◆◆

◆LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

◆◆

◆Available in a 208-pin Plastic Quad Flatpack, 208-ball fine

pitch Ball Grid Array, and 256-ball Ball Grid Array

◆◆

◆Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Features

◆◆

◆True Dual-Port memory cells which allow simultaneous

access of the same memory location

◆◆

◆High-speed access

– Commercial: 10/12/15ns (max.)

– Industrial: 12/15ns (max.)

◆◆

◆Dual chip enables allow for depth expansion without

external logic

◆◆

◆IDT70V659/58/57 easily expands data bus width to 72 bits

or more using the Master/Slave select when cascading

more than one device

◆◆

◆M/S = VIH for BUSY output flag on Master,

M/S = VIL for BUSY input on Slave

◆◆

◆Busy and Interrupt Flags

◆◆

◆On-chip port arbitration logic

HIGH-SPEED 3.3V

128/64/32K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

IDT70V659/58/57S

1. A16 is a NC for IDT70V658. Also, Addresses A16 and A15 are NC's for IDT70V657.

2. BUSY is an input as a Slave (M/S=VIL) and an output when it is a Master (M/S=VIH).

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).

NOTES:

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70V659/58/57 is a high-speed 128/64/32K x 36 Asynchro-

nous Dual-Port Static RAM. The IDT70V659/58/57 is designed to be used

as a stand-alone 4/2/1Mbit Dual-Port RAM or as a combination MASTER/

SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the IDT

MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider memory

system applications results in full-speed, error-free operation without the

need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down

feature controlled by the chip enables (either CE0 or CE1) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The 70V659/58/57 can support an operating voltage of either 3.3V

or 2.5V on one or both ports, controlled by the OPT pins. The power supply

for the core of the device (VDD) remains at 3.3V.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations(3,4,5,6,7,8)

100

101

102

103

104

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

208

207

206

205

204

203

202

201

200

199

198

197

196

195

194

193

192

191

190

189

188

187

186

185

184

183

182

181

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

70V659/58/57DR

DR-208

(7)

208-Pin PQFP

Top View

(8)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

DDQL

I/O

35R

I/O

35L

TMS

TCK

TRST

16R(1)

15R(2)

14R

13R

12R

11R

10R

SEM

R/W

BUSY

INT

M/S

OPT

I/O

DDQL

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

DDQR

I/O

18R

I/O

18L

TDI

TDO

16L(1)

15L(2)

14L

13L

12L

11L

10L

SEM

R/W

BUSY

INT

OPT

I/O

17L

I/O

17R

DDQR

4869 drw 02a

03/19/04

NOTES:

1. Pin is a NC for IDT70V658 and IDT70V657.

2. Pin is a NC for IDT70V657.

3. All VDD pins must be connected to 3.3V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground.

6. Package body is approximately 28mm x 28mm x 3.5mm.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations(3,4,5,6,7,8,5,6,7,8

,5,6,7,8,5,6,7,8

,5,6,7,8) (con't.)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

6L C14

OPT

B14

A14

A12

B12

C11

BUSY

D12

DDQR

D11

DDQR

C10

SEM

B11

A11

INT

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

13L

DDQL

16L(1)

TDO

I/O

20L

I/O

19R

I/O

19L

TDI

I/O

18L

I/O

18R

I/O

20R

I/O

21R

I/O

21L

I/O

22L

DDQL

I/O

23L F2

I/O

22R F3

I/O

23R F4

DDQL

I/O

24R G2

I/O

24L G3

I/O

25L

DDQR

I/O

26L

I/O

25R

I/O

26R

DDQR

I/O

27L J2

I/O

28R J3

I/O

27R J4

DDQL

I/O

29R

I/O

29L K3

I/O

28L

DDQL

I/O

30L L2

I/O

31R

I/O

30R L4

DDQR

I/O

32R M2

I/O

32L M3

I/O

31L M4

DDQR

I/O

33L

I/O

34R

I/O

33R

I/O

35R P2

I/O

34L P3

TMS

16R(1)

I/O

35L

TRST

TCK

13R

15R(2)

P12

1R P9

P10

SEM

T11

INT

P11

BUSY

R12

T12

P13

R13

T13

12R

14R T14

R14

OPT

P14

I/O

0L P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R F15

I/O

13R

R11

M/S

11R

11L

B10

R/W

C13

10R

R10

R/W

T10

DD E6

DD E7

SS E8

SS E9

SS E10

SS E11

DD E12

DD E13

DDQR

DD F6

SS F8

SS F10

SS F12

F13

DDQR

SS G6

SS G7

SS G9

SS G10

SS G11

G12

SS G13

DDQL

SS H8

SS H9

SS H10

H11

SS H12

SS H13

DDQL

SS J6

SS J7

SS J8

SS J9

SS J10

SS J11

SS J12

SS J13

DDQR

SS K7

DD M6

DD M7

SS M8

DDQR

DDQL

K10

SS K11

K12

L10

L11

L12

SS M10

SS M11

DD M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

SS F11

4869 drw 02c

03/19/04

15L(2)

NOTES:

1. Pin is a NC for IDT70V658 and IDT70V657.

2. Pin is a NC for IDT70V657.

3. All VDD pins must be connected to 3.3V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V), and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground supply.

6. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

70V659/58/57BC

BC-256(7)

256-Pin BGA

Top View (8)

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration(3,4,5,6,7,8) (con't.)

1716

1412 13

9876543

21 11

I/O

19L

I/O

18L

INT

SEM

12L

16L(1)

I/O

17L

OPT

I/O

20R

I/O

18R

BUSY

13L

NC I/O16L

DDQR

DDQL

I/O

19R

DDQR

10L

14L

NC I/O

15L

I/O

16R

I/O

22L

I/O

21L

I/O

20L

I/O

23L

I/O

22R

DDQR

I/O

21R

DDQL

I/O

23R

I/O

24L

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DDQR

I/O

25R

DDQL

I/O

29R

I/O

28L

DDQR

DDQL

I/O

29L

I/O

30R

I/O

14R

DDQL

I/O

14L

15L(2)

11L

I/O

12L

I/O

13R

I/O

13L

I/O

12R

I/O

11L

I/O

DDQL

I/O

10L

I/O

11R

I/O

10R

DDQR

I/O

DDQL

I/O8R V

I/O

31L

I/O

31R

I/O

30L

16R(1 )

12R

SEM

INT

DDQR

I/O

33L

I/O

34R

NC A

13R

BUSY

DDQL

I/O

DDQR

I/O

33R

I/O

34L

DDQL

NC A

14R

10R

I/O

35L

15R(2)

11R

DDQL

I/O

OPT

I/O

70V659/58/57BF

BF-208

(7)

208-Ball BGA

Top View

(8)

4869 drw 02b

I/O

27L

I/O

28R

I/O

27R

I/O

32R

I/O

32L

DDQR

I/O

35R

I/O

17R

DDQR

I/O

15R

TDO

TDI

TCK

TMS

TRST

03/19/04

NOTES:

1. Pin is a NC for IDT70V658 and IDT70V657.

2. Pin is a NC for IDT70V657.

3. All VDD pins must be connected to 3.3V power supply.

4. All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VDD (3.3V) and 2.5V if OPT pin for that port is

set to VSS (0V).

5. All VSS pins must be connected to ground.

6. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.

7. This package code is used to reference the package diagram.

8. This text does not indicate orientation of the actual part-marking.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:

1. VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to

applying inputs on I/OX.

2. OPTX selects the operating voltage levels for the I/Os and controls on that port.

If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that

port's I/Os and controls will operate at 2.5V levels and VDDQX must be supplied

at 2.5V. The OPT pins are independent of one another—both ports can operate

at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V

with the other at 2.5V.

3. Addresses A16x is a NC for IDT70V658. Also, Addresses A16x and A15x are

NC's for IDT70V657.

4. BUSY is an input as a slave (M/S = VIL).

Left Port Right Port Names

Chip Enables - (Input)

R/W

Read/Write Enable - (Input)

Output Enable - (Input)

- A

16L

(3)

- A

16R

(3)

Address - (Input)

I/O

- I/O

35L

I/O

- I/O

35R

Data Input/Output

SEM

Semaphore Enable - (Input)

INT

Interrupt Flag - (Output)

BUSY

Busy Flag - (Output)

(4)

- BE

Byte Enables (9-bit bytes) - (Input)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

- (Input)

(1)

OPT

Option for selecting V

DDQX

- (Input)

(1,2)

M/SMaster or Slave Select - (Input)

Power (3.3V) - (Input)

(1)

Ground (0V) - (Input)

TDI Test Data Inp ut

TDO Test Data Output

TCK Test Logic Clock (10MHz)

TMS Test Mode Select

TRST Reset (Initialize TAP Controller)

4869 tbl 01

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. "H" = VIH, "L" = VIL, "X" = Don't Care.

2. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table I—Read/Write and Enable Control(1,2)

OE SEM CE

R/W

Byte 3

I/O

27-3 5

Byte 2

I/O

18-26

Byte 1

I/O

9-17

Byte 0

I/O

0-8

MODE

X H H X X X X X X High-Z High-Z High-Z High-Z Deselected–Power Down

X H X L X X X X X High-Z High-Z High-Z High-Z Deselected–Power Down

X H L H H H H H X High-Z High-Z High-Z High-Z All Bytes Deselected

X H L H H H H L L High-Z High-Z High-Z D

Write to Byte 0 Only

X H L H H H L H L High-Z High-Z D

High-Z Write to Byte 1 Only

XHLHHLHHLHigh-Z D

High-Z High-Z Write to Byte 2 Only

XHLHLHHHL D

High-Z High-Z High-Z Write to Byte 3 Only

X H L H H H L L L High-Z High-Z D

Write to Lowe r 2 Bytes Only

XHLHLLHHL D

High-Z High-Z Write to Upper 2 bytes Only

XHLHLLLLL D

Write to All Bytes

L H L H H H H L H High-Z High-Z High-Z D

OUT

Read Byte 0 Only

LHLHHHLHHHigh-ZHigh-Z D

OUT

High-Z Read By te 1 Only

LHLHHLHHHHigh-Z D

OUT

High-Z High-Z Read Byte 2 Only

LHLHLHHHH D

OUT

High-Z High-Z High-Z Read Byte 3 Only

L H L H H H L L H High-Z High-Z D

OUT

Read Lower 2 Bytes Only

LHLHLLHHH D

OUT

High-Z High-Z Read Upper 2 Bytes Only

LHLHLLLLH D

OUT

Read All Bytes

H H L H L L L L X High-Z High-Z High-Z High-Z Outputs Disab led

4869 tb l 0 2

Truth Table II – Semaphore Read/Write Control(1)

NOTES:

1. There are eight semaphore flags written to I/O0 and read from all the I/Os (I/O0-I/O35). These eight semaphore flags are addressed by A0-A2.

2. CE = L occurs when CE0 = VIL and CE1 = VIH.

3. Each byte is controlled by the respective BEn. To read data BEn = VIL.

Inputs

(1)

Outputs

Mode

(2)

R/WOE BE

SEM I/O

1-3 5

I/O

HHLLLLL LDATA

OUT

DATA

OUT

Read Data in Semaphore Flag

(3)

H↑XXXXL L X DATA

Write I/O

into Semaphore Flag

LXXXXXX L

______ ______

Not Allowed

4869 tbl 03

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Absolute Maximum Ratings(1)

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

2. VTERM must not exceed VDD + 150mV for more than 25% of the cycle time

or 4ns maximum, and is limited to < 20mA for the period of VTERM > VDD

+ 150mV.

3. Ambient Temperature under DC Bias. No AC Conditions. Chip Deselected.

Symbol Rating Commercial

& Industrial

Unit

TERM

(2)

)

Terminal Voltage

with Respect to GND

-0.5 to + 4.6 V

BIAS

(3)

Temperature Under Bias -55 to +125

STG

Storage Temperature -65 to +150

Junction Temperature +150

OUT

(For V

DDQ

3.3V) DC Output Current 50 mA

OUT

(For V

DDQ

2.5V) DC Output Current 40 mA

4869 tbl 05

Recommended DC Operating

Conditions with VDDQ at 3.3V

NOTES:

1. VIL > -1.5V for pulse width less than 10 ns.

2. VTERM must not exceed VDDQ + 150mV.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VDD (3.3V), and VDDQX for that port must be

supplied as indicated above.

Symbol Parameter Min. Typ. Max. Unit

Core Supply Voltage 3.15 3.3 3.45 V

DDQ

I/O Supply Voltage

(3)

3.15 3.3 3.45 V

Ground 0 0 0 V

Inp ut High Voltage

(Address & Control Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

Input High Vo ltage - I/O

(3)

2.0

____

DDQ

+ 150mV

(2)

Input Low Voltage -0.3

(1)

____

0.8 V

48 69 tb l 07

Recommended DC Operating

Conditions with VDDQ at 2.5V

NOTES:

1. VIL > -1.5V for pulse width less than 10 ns.

2. VTERM must not exceed VDDQ + 100mV.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to VSS (0V), and VDDQX for that port must be

supplied as indicated above.

Symbol Parameter Min. Typ. Max. Unit

Core Supply Voltage 3.15 3.3 3.45 V

DDQ

I/O Supply Voltage

(3)

2.4 2.5 2.6 V

Ground 0 0 0 V

Inp ut High Voltage

(3)

(Address & Control Inputs)

1.7

____

DDQ

+ 100mV

(2)

Inp ut High Voltage - I/O

(3 )

1.7

____

DDQ

+ 100mV

(2)

Input Low Voltage -0.5

(1)

____

0.7 V

4869 tbl 06

Maximum Operating

Temperature and Supply Voltage(1)

NOTE:

1. This is the parameter TA. This is the "instant on" case temperature.

Grade

Ambient

Temperature GND V

Commercial 0

C to +70

C0V3.3V

150mV

Industrial -40

C to +85

C0V3.3V

150mV

4869 tbl 04

NOTES:

1. These parameters are determined by device characterization, but are not

production tested.

2. COUT also references CI/O.

Capacitance(1)

(TA = +25°C, F = 1.0MHZ) PQFP ONLY

Symbol Parameter Conditions Max. Unit

Input Capacitance V

= 0V 8 pF

OUT

(2)

Output Capacitance V

OUT

= 0V 10.5 pF

4869 tbl 08

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range (VDD = 3.3V ± 150mV)

NOTE:

1. At VDD < - 2.0V input leakages are undefined.

2. VDDQ is selectable (3.3V/2.5V) via OPT pins. Refer to p.6 for details.

Symbol Parameter Test Conditions

70V659/58/57S

UnitMin. Max.

| Input Leakage Current

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

10 µA

| Output Leakage Current CE

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

10 µA

(3.3V) Output Low Voltage

(2)

= +4mA, V

DDQ

= Min.

___

0.4 V

(3.3V) Output High Voltage

(2)

= -4mA, V

DDQ

= Min. 2.4

___

(2.5V) Output Low Voltage

(2)

= +2mA, V

DDQ

= Min.

___

0.4 V

(2.5V) Output High Voltage

(2)

= -2mA, V

DDQ

= Min. 2.0

___

4869 tbl 09

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(3) (VDD = 3.3V ± 150mV)

NOTES:

1. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address or control lines change. Applies only to input at CMOS level standby.

3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

4. VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 120mA (Typ).

5. CEX = VIL means CE0X = VIL and CE1X = VIH

CEX = VIH means CE0X = VIH or CE1X = VIL

CEX < 0.2V means CE0X < 0.2V and CE1X > VCC - 0.2V

CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X - 0.2V

"X" represents "L" for left port or "R" for right port.

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

& Ind

70V659/58/57S15

Com'l

& Ind

Symbol Parameter Test Condition Version Typ.

(4)

Max. Typ.

(4)

Max. Typ.

(4)

Max. Unit

Dynamic Operating

Current (Both

Ports Active)

and CE

= V

Outputs Disabled

f = f

MAX

(1)

COM'L S 340 500 315 465 300 440 mA

IND S

____ ____

365 515 350 490

SB1

Standby Current

(Both Ports - TTL

Level Inputs)

= CE

= V

f = f

MAX

(1)

COM'L S 115 165 90 125 75 100 mA

IND S

____ ____

115 150 100 125

SB2

Standby Current

(One Port - TTL

Level Inputs)

"A"

= V

and CE

"B"

= V

(5)

Active Port Outputs Disabled,

f=f

MAX

(1)

COM'L S 225 340 200 325 175 315 mA

IND S

____ ____

225 365 200 350

SB3

Full Standby Current

(Both Ports - CMOS

Level Inputs)

Both Ports CE

and

> V

- 0.2V, V

> V

- 0.2V

or V

< 0.2V, f = 0

(2)

COM'LS315315315

IND S

____ ____

615615

SB4

Full Standby Current

(One Port - CMOS

Level Inputs)

"A"

< 0.2V and CE

"B"

> V

- 0.2V

(5)

> V

- 0.2V or V

< 0.2V, Active

Port, Outputs Disabled, f = f

MAX

(1)

COM'L S 220 335 195 320 170 310 mA

IND S

____ ____

220 360 195 345

4869 tbl 10

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions (VDDQ - 3.3V/2.5V)

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For tCKLZ, tCKHZ, tOLZ, and tOHZ).

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V / GND to 2.5V

2ns Max.

1.5V/1.25V

Figures 1 and 2

4869 tbl 11

1.5V/1.25

50Ω

4869 drw 03

10pF

(Tester)

DATA

OUT

4869 drw 04

590Ω

5pF*

435Ω

3.3V

DATA

OUT

833Ω

5pF*

770Ω

2.5V

DATA

OUT

-1

20.5 30 50 80 100 200

10.5pF is the I/O capacitance of this

device, and 10pF is the AC Test Load

Capacitance.

Capacitance (pF)

∆tAA

(Typical, ns)

4869 drw 05

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range(5)

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).

2. This parameter is guaranted by device characterization, but is not production tested.

3. To access RAM, CE= VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage

and temperature, the actual tDH will always be smaller than the actual tOW.

5. These values are valid regardless of the power supply level selected for I/O and control signals (3.3V/2.5V). See page 6 for details.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage(5)

Symbol Parameter

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

& Ind

70V659/58/57S15

Com'l

& Ind

UnitMin. Max. Min. Max. Min. Max.

READ CYCLE

Read Cycle Time 10

____

Address Access Time

____

15 ns

ACE

Chip Enable Access Time

(3)

____

15 ns

ABE

Byte Enable Access Time

(3)

____

7ns

AOE

Output Enable Access Time

____

7ns

Output Hold from Address Change 3

____

Output Low-Z Time

(1,2)

____

Output High-Z Time

(1, 2)

040608ns

Chip Enable to Power Up Time

(2)

____

Chip Disable to Powe r Down Time

(2)

____

15 ns

SOP

Semaphore Flag Update Pulse (OE or SEM)

____

8ns

SAA

Semaphore Address Access Time 3 10 3 12 3 20 ns

4869 tbl 12

Symbol Parameter

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

& Ind

70V659/58/57S15

Com'l

& Ind

UnitMin. Max. Min. Max. Min. Max.

WRI TE CYCL E

Write Cycle Time 10

____

Chip Enable to End-of-Write

(3)

____

Address Valid to End-of-Write 8

____

Address Set-up Time

(3)

____

Write Pulse Width 8

____

Write Rec ove ry Time 0

____

Data Valid to End-of-Write 6

____

Data Hold Time

(4)

____

Write Enable to Output in High-Z

(1,2)

____

4ns

Output Active from End-of-Write

(1,2,4)

____

SWRD

SEM Flag Write to Read Time 5

____

SPS

SEM Flag Contention Wind ow 5

____

4869 tbl 13

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing of Power-Up Power-Down

Waveform of Read Cycles(5)

NOTES:

1. Timing depends on which signal is asserted last, OE, CE or BEn.

2. Timing depends on which signal is de-asserted first CE, OE or BEn.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

R/W

ADDR

BEn

4869 drw 06

(4)

ACE

(4)

AOE

(4)

ABE

(4)

(1)

(2)

(3,4)

BDD

DATA

OUT

BUSY

OUT

VALID DATA

(4)

(6)

4869 drw 07

50% 50%

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing(1,5,8)

Timing Waveform of Write Cycle No. 2, CE Controlled Timing(1,5)

NOTES:

1. R/W or CE or BEn = VIH during all address transitions.

2. A write occurs during the overlap (tEW or tWP) of a CE = VIL and a R/W = VIL for memory array writing cycle.

3. tWR is measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM = VIL transition occurs simultaneously with or after the R/W = VIL transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 2).

8. If OE = VIL during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required tDW. If OE = VIH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified tWP.

9. To access RAM, CE = VIL and SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

R/W

DATA

OUT

(2)

ADDRESS

DATA

(6)

(4) (4)

(7)

BEn

4869 drw 08

(9)

CE or SEM

(9)

(7)

(3)

4869 drw 09

ADDRESS

DATA

R/W

BEn

(3)

(2)

(6)

CE or SEM

(9)

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side(1)

NOTES:

1. DOR = DOL = VIL, CEL = CER = VIH. Refer to Truth Table II for appropriate BE controls.

2. All timing is the same for left and right ports. Port "A" may be either left or right port. "B" is the opposite from port "A".

3. This parameter is measured from R/W"A" or SEM"A" going HIGH to R/W"B" or SEM"B" going HIGH.

4. If tSPS is not satisfied,the semaphore will fall positively to one side or the other, but there is no guarantee which side will be granted the semaphore flag.

Timing Waveform of Semaphore Write Contention(1,3,4)

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle) (Refer to Chip Enable Truth Table). Refer also to Truth Table II for appropriate BE controls.

2. "DATAOUT VALID" represents all I/O's (I/O0 - I/O35) equal to the semaphore value.

SEM/BEn

(1)

4869 drw 10

I/O

VALID ADDRESS

SAA

R/W

ACE

VALID ADDRESS

DATA VALID

DATA

OUT

SWRD

AOE

Read Cycle

Write Cycle

-A

VALID

(2)

SOP

SEM

"A"

4869 drw 11

SPS

MATCH

R/W

"A"

MATCH

0"A"

-A

2"A"

SIDE "A"

(2)

SEM

"B"

R/W

"B"

0"B"

-A

2"B"

SIDE "B"

(2)

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)".

2. To ensure that the earlier of the two ports wins.

3. tBDD is a calculated parameter and is the greater of the Max. spec, tWDD – tWP (actual), or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".

5. To ensure that a write cycle is completed on port "B" after contention on port "A".

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

Symbol Parameter

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

& Ind

70V659/58/57S15

Com'l

& Ind

Unit

Min. Max. Min. Max. Min. Max.

BUSY TIMING (M/S=V

)

BAA

BUSY Access Time from Address Match

____

15 ns

BDA

BUSY Disable Time from Address Not Matched

____

15 ns

BAC

BUSY Access Time from Chip Enable Low

____

15 ns

BDC

BUSY Disable Time from Chip Enable High

____

15 ns

APS

Arbitration Priority Set-up Time

(2)

____

BDD

BUSY Disable to Valid Data

(3)

____

15 ns

Write Hold After BUSY

(5)

____

BUSY TIMING (M/S=V

)

BUSY Input to Write

(4)

____

Write Hold After BUSY

(5)

____

PORT-TO-PORT DELAY TIMING

WDD

Write Pulse to Data Delay

(1)

____

30 ns

DDD

Write Data Valid to Read Data Delay

(1)

____

25 ns

4869 tbl 14

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Port-to-Port Read and BUSY (M/S = VIH)(2,4,5)

Timing Waveform of Write with BUSY (M/S = VIL)

NOTES:

1. tWH must be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W"B", until BUSY"B" goes HIGH.

3. tWB is only for the 'slave' version.

NOTES:

1. To ensure that the earlier of the two ports wins. tAPS is ignored for M/S = VIL (SLAVE).

2. CEL = CER = VIL.

3. OE = VIL for the reading port.

4. If M/S = VIL (slave), BUSY is an input. Then for this example BUSY"A" = VIH and BUSY"B" input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".

4869 drw 12

APS

ADDR

"A"

DATA

OUT "B"

MATCH

R/W

"A"

DATA

IN "A"

ADDR

"B"

VALID

(1)

MATCH

BUSY

"B"

BDA

VALID

BDD

DDD

(3)

WDD

BAA

4869 drw 13

R/W

"A"

BUSY

"B"

(3)

R/W

"B"

(1)

(2)

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

Waveform of BUSY Arbitration Controlled by CE Timing (M/S = VIH)(1)

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing (M/S = VIH)(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. If tAPS is not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

4869 drw 14

ADDR

"A"

and

"B"

ADDRESSES MATCH

"A"

"B"

BUSY

"B"

APS

BAC

BDC

(2)

4869 drw 15

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

70V659/58/57S10

Com'l Only

70V659/58/57S12

Com'l

& Ind

70V659/58/57S15

Com'l

& Ind

Symbol Parameter Min.Max.Min.Max.Min.Max.Unit

INTERRUPT TIMING

Address Set-up Time 0

____

Write Recovery Time 0

____

INS

Inte rrupt Se t Time

____

15 ns

INR

Inte rrupt Reset Time

____

15 ns

4869 tbl 15

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Truth Table III — Interrupt Flag(1,4)

Waveform of Interrupt Timing(1)

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.

2. Refer to Interrupt Truth Table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

NOTES:

1. Assumes BUSYL = BUSYR =VIH.

2. If BUSYL = VIL, then no change.

3. If BUSYR = VIL, then no change.

4. INTL and INTR must be initialized at power-up.

5. A16x is a NC for IDT70V658, therefore Interrupt Addresses are FFFF and FFFE.

6. A16x and A15x are NC's for IDT70V657, therefore Interrupt Addresses are 7FFF and 7FFE.

4869 drw 16

ADDR

"A"

INTERRUPT SET ADDRESS

"A"

R/W

"A"

(3) (4)

INS

(3)

INT

"B"

(2)

4869 drw 17

ADDR

"B"

INTERRUPT CLEAR ADDRESS

"B"

(3)

INR

(3)

INT

"B"

(2)

Left Port Right Port

FunctionR/W

16L

-A

(5,6) INT

R/W

16R

-A

(5,6) INT

L L X 1FFFF XXXX X L

(2) Set Right INT

Flag

XXXXXXLL1FFFFH

(3) Reset Right INT

Flag

XXX X L

(3) L L X 1FFFE X Set Left INT

Flag

X L L 1FFFE H(2) X X X X X Reset Left INT

Flag

4869 tb l 16

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V659/58/57 provides two ports with separate control,

address and I/O pins that permit independent access for reads or writes

to any location in memory. The IDT70V659/58/57 has an automatic power

down feature controlled by CE. The CE0 and CE1 control the on-chip

power down circuitry that permits the respective port to go into a standby

mode when not selected (CE = HIGH). When a port is enabled, access

to the entire memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag

(INTL) is asserted when the right port writes to memory location 1FFFE

(HEX) (FFFE for IDT70V658 and 7FFE for IDT70V657), where a write

is defined as CER = R/WR = VIL per the Truth Table III. The left port clears

the interrupt through access of address location 1FFFE (FFFE for

IDT70V658 and 7FFE for IDT70V657) when CEL = OEL = VIL, R/W is

Truth Table IV —

Address BUSY Arbitration

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSY outputs on the

IDT70V659/58/57 are push-pull, not open drain outputs. On slaves the BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSYR outputs are driving LOW regardless of actual logic level on the pin.

4. A16X is a NC for IDT70V658, therefore Address comparison will be for A0 - A15. Also, A16X and A15X are NC's for IDT70V657, therefore Address comparison will

be for A0 - A14.

Inputs Outputs

Function

-A

16L

(4)

-A

16R

BUSY

(1)

BUSY

(1)

X X NO MATCH H H Normal

HXMATCHH HNormal

XHMATCHH HNormal

LL MATCH (2) (2) Write Inhibit

(3)

4869 tbl 17

Truth Table V — Example of Semaphore Procurement Sequence(1,2,3)

NOTES:

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V659/58/57.

2. There are eight semaphore flags written to via I/O0 and read from all I/O's (I/O0-I/O35). These eight semaphores are addressed by A0 - A2.

3. CE = VIH, SEM = VIL to access the semaphores. Refer to the Semaphore Read/Write Control Truth Table.

Functions D

- D

Left D

- D

Right Status

No Action 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Right Port Writes "0" to Semaphore 0 1 No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore 1 0 Right port obtains semaphore token

Left Port Writes "0" to Semaphore 1 0 No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore 0 1 Left port obtains semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

Right Port Writes "0" to Semaphore 1 0 Right port has semaphore token

Right Port Writes "1" to Semaphore 1 1 Semaphore free

Left Port Writes "0" to Semaphore 0 1 Left port has semaphore token

Left Port Writes "1" to Semaphore 1 1 Semaphore free

4869 tbl 18

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the

two accesses to proceed and signals the other side that the RAM is “Busy”.

The BUSY pin can then be used to stall the access until the operation on

the other side is completed. If a write operation has been attempted from

the side that receives a BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the BUSY outputs together

and use any BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of BUSY logic is

not desirable, the BUSY logic can be disabled by placing the part in slave

mode with the M/S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying

the BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70V659/58/57 RAM in master mode,

are push-pull type outputs and do not require pull up resistors to operate.

If these RAMs are being expanded in depth, then the BUSY indication

for the resulting array requires the use of an external AND gate.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating BUSY on one side of the

array and another master indicating BUSY on one other side of

the array. This would inhibit the write operations from one port for part of

a word and inhibit the write operations from the other port for the other part

of the word.

The BUSY arbitration on a master is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In

a master/slave array, both address and chip enable must be valid long

enough for a BUSY flag to be output from the master before the actual write

pulse can be initiated with the R/W signal. Failure to observe this timing

can result in a glitched internal write inhibit signal and corrupted data in the

slave.

Semaphores

The IDT70V659/58/57 is an extremely fast Dual-Port 128/64/32K x

36 CMOS Static RAM with an additional 8 address locations dedicated to

binary semaphore flags. These flags allow either processor on the left or

right side of the Dual-Port RAM to claim a privilege over the other processor

for functions defined by the system designer’s software. As an example,

the semaphore can be used by one processor to inhibit the other from

accessing a portion of the Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, with both ports being

completely independent of each other. This means that the activity on the

left port in no way slows the access time of the right port. Both ports are

identical in function to standard CMOS Static RAM and can be read from

or written to at the same time with the only possible conflict arising from the

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphore location. Semaphores are protected against such ambiguous

situations and may be used by the system program to avoid any conflicts

in the non-semaphore portion of the Dual-Port RAM. These devices have

an automatic power-down feature controlled by CE, the Dual-Port RAM

enable, and SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into

standby mode when not selected.

Systems which can best use the IDT70V659/58/57 contain multiple

processors or controllers and are typically very high-speed systems

which are software controlled or software intensive. These systems

can benefit from a performance increase offered by the IDT70V659/58/

57s hardware semaphores, which provide a lockout mechanism without

requiring complex programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying

configurations. The IDT70V659/58/57 does not use its semaphore

flags to control any resources through hardware, thus allowing the system

designer total flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred in

either processor. This can prove to be a major advantage in very high-

speed systems.

4869 drw 18

MASTER

Dual Port RAM

BUSY

MASTER

Dual Port RAM

BUSY

SLAVE

Dual Port RAM

BUSY

SLAVE

Dual Port RAM

BUSY

17(1,2)

BUSY

a "don't care". Likewise, the right port interrupt flag (INTR) is asserted when

the left port writes to memory location 1FFFF (HEX) (FFFF for IDT70V658

and 7FFF for IDT70V657) and to clear the interrupt flag (INTR), the right

port must read the memory location 1FFFF (FFFF for IDT70V658 and

7FFF for IDT70V657). The message (36 bits) at 1FFFE (FFFE for

IDT70V658 and 7FFE for IDT70V657)or 1FFFF (FFFF for IDT70V658

and 7FFF for IDT70V657) is user-defined since it is an addressable

SRAM location. If the interrupt function is not used, address locations

1FFFE (FFFE for IDT70V658 and 7FFE for IDT70V657) and 1FFFF

(FFFF for IDT70V658 and 7FFF for IDT70V657) are not used as mail

boxes, but as part of the random access memory. Refer to Truth Table III

for the interrupt operation.

Width Expansion with Busy Logic

Master/Slave Arrays

When expanding an IDT70V659/58/57 RAM array in width while

using BUSY logic, one master part is used to decide which side of the RAMs

array will receive a BUSY indication, and to output that indication. Any

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70V659/58/57 RAMs.

number of slaves to be addressed in the same address range as the master

use the BUSY signal as a write inhibit signal. Thus on the IDT70V659/58/

57 RAM the BUSY pin is an output if the part is used as a master (M/S pin

= VIH), and the BUSY pin is an input if the part used as a slave (M/S pin

= VIL) as shown in Figure 3.

NOTES:

1. A16 for IDT70V658.

2. A15 for IDT70V657.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

The semaphore flags are active LOW. A token is requested by writing

a zero into a semaphore latch and is released when the same side writes

a one to that latch.

The eight semaphore flags reside within the IDT70V659/58/57 in a

separate memory space from the Dual-Port RAM. This address space is

accessed by placing a low input on the SEM pin (which acts as a chip select

for the semaphore flags) and using the other control pins (Address, CE,

R/W and BEo) as they would be used in accessing a standard Static RAM.

Each of the flags has a unique address which can be accessed by either

side through address pins A0 – A2. When accessing the semaphores, none

of the other address pins has any effect.

When writing to a semaphore, only data pin D0 is used. If a low level

is written into an unused semaphore location, that flag will be set to a zero

on that side and a one on the other side (see Truth Table V). That

semaphore can now only be modified by the side showing the zero. When

a one is written into the same location from the same side, the flag will be

set to a one for both sides (unless a semaphore request from the other side

is pending) and then can be written to by both sides. The fact that the side

which is able to write a zero into a semaphore subsequently locks out writes

from the other side is what makes semaphore flags useful in interprocessor

communications. (A thorough discussion on the use of this feature follows

shortly.) A zero written into the same location from the other side will be

stored in the semaphore request latch for that side until the semaphore is

freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing

a zero reads as all zeros. The read value is latched into one side’s output

(OE) signals go active. This serves to disallow the semaphore from

changing state in the middle of a read cycle due to a write cycle from the

other side. Because of this latch, a repeated read of a semaphore in a test

loop must cause either signal (SEM or OE) to go inactive or the output will

never change. However, during reads BEn functions only as an output

for semaphore. It does not have any influence on the semaphore control

logic.

A sequence WRITE/READ must be used by the semaphore in order

to guarantee that no system level contention will occur. A processor

requests access to shared resources by attempting to write a zero into a

semaphore location. If the semaphore is already in use, the semaphore

reason for this is easily understood by looking at the simple logic diagram

of the semaphore flag in Figure 4. Two semaphore request latches feed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphore flag will force its side of the semaphore flag LOW and the other

side HIGH. This condition will continue until a one is written to the same

semaphore request latch. Should the other side’s semaphore request latch

have been written to a zero in the meantime, the semaphore flag will flip

over to the other side as soon as a one is written into the first side’s request

latch. The second side’s flag will now stay LOW until its semaphore request

latch is written to a one. From this it is easy to understand that, if a semaphore

is requested and the processor which requested it no longer needs the

resource, the entire system can hang up until a one is written into that

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The

semaphore logic is specially designed to resolve this problem. If simulta-

neous requests are made, the logic guarantees that only one side receives

the token. If one side is earlier than the other in making the request, the first

side to make the request will receive the token. If both requests arrive at

the same time, the assignment will be arbitrarily made to one port or the

other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is secure.

As with any powerful programming technique, if semaphores are misused

or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request

flag which contains a zero must be reset to a one, all semaphores on both

sides should have a one written into them at initialization from both sides

to assure that they will be free when needed.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,

from one port to the other to indicate that a shared resource

is in use. The semaphores provide a hardware assist for a use assignment

method called “Token Passing Allocation.” In this method, the state of a

semaphore latch is used as a token indicating that a shared resource is

in use. If the left processor wants to use this resource, it requests the token

by setting the latch. This processor then verifies its success in setting the

latch by reading it. If it was successful, it proceeds to assume control over

the shared resource. If it was not successful in setting the latch, it determines

that the right side processorhas set the latch first, has the token and is using

the shared resource. The left processor can then either repeatedly request

that semaphore’s status or remove its request for that semaphore to

perform another task and occasionally attempt again to gain control of the

token via the set and test sequence. Once the right side has relinquished

the token, the left side should succeed in gaining control.

Figure 4. IDT70V659/58/57 Semaphore Logic

4869 drw 19

0DQ

WRITE D

WRITE

SEMAPHORE

REQUEST FLIP FLOP SEMAPHORE

REQUEST FLIP FLOP

LPORT RPORT

SEMAPHORE

READ SEMAPHORE

READ

request latch will contain a zero, yet the semaphore flag will appear as one,

a fact which the processor will verify by the subsequent read (see Table

V). As an example, assume a processor writes a zero to the left port at a

free semaphore location. On used instead, system contention problems

could have occurred during the gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The

semaphore request latch.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

JTAG AC Electrical

Characteristics(1,2,3,4)

Symbol Parameter Min. Max. Units

JCYC

JTAG Clock Input Period 100

____

JCH

JTAG Clock HIGH 40

____

JCL

JTAG Clock Low 40

____

JTAG Clock Rise Time

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Reset 50

____

JRSR

JTAG Reset Recovery 50

____

JCD

JTAG Data Output

____

25 ns

JDC

JTAG Data Output Hold 0

____

JTAG Setup 15

____

JTAG Hold 15

____

4869 tbl 19

NOTES:

1. Guaranteed by design.

2. 30pF loading on external output signals.

3. Refer to AC Electrical Test Conditions stated earlier in this document.

4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

JTAG Timing Specifications

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

4869 drw 20

NOTES:

1. Device inputs = All device inputs except TDI, TMS, and TRST.

2. Device outputs = All device outputs except TDO.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field Value Description

Revision Number (31:28) 0x0 Reserved for version number

IDT Device ID (27:12) 0x303

(1)

Defines IDT part number

IDT JEDEC ID (11:1) 0x33 Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0) 1 Indicates the presence of an ID register

4869 tbl 20

Scan Register Sizes

Instruction (IR) 4

Bypass (BYR) 1

Identificatio n (IDR) 32

Boundary Scan (BSR) Note (3)

4869 tbl 21

System Interface Parameters

Instruction Code Description

EXTEST 0000 Forces contents of the boundary scan cells onto the device outputs

(1)

Places the boundary scan register (BSR) between TDI and TDO.

BYPASS 1111 Places the bypass register (BYR) between TDI and TDO.

IDCODE 0010 Loads the ID register (IDR) with the vendor ID code and places the

HIGHZ 0100 Places the bypass register (BYR) between TDI and TDO. Forces all

device output drivers to a High-Z state.

CLAMP 0011 Uses BYR. Forces contents of the boundary scan cells onto the device

outputs. Places the bypass register (BYR) between TDI and TDO.

SAMPLE/PRELOAD 0001 Places the boundary scan register (BSR) between TDI and TDO.

SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD

allows data to be input serially into the b oundary scan cells via the TDI.

RESERVED All other codes Several combinations are reserved. Do not use codes other than those

identified above.

4869 tbl 22

NOTES:

1. Device outputs = All device outputs except TDO.

2. Device inputs = All device inputs except TDI, TMS, and TRST.

3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

NOTE:

1. Device ID for IDT70V658 is 0x30B. Device ID for IDT70V657 is 0x323.

IDT70V659/58/57S

High-Speed 3.3V 128/64/32K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

4869 drw 21

Commercial (0°Cto+70°C)

Industrial (-40°Cto+85°C)

208-ball fpBGA (BF-208)

208-pin PQFP (DR-208)

256-ball BGA (BC-256)

Standard Power

Speed in nanoseconds

Commercial Only

Commercial & Industrial

4Mbit (128K x 36) 3.3V Asynchronous Dual-Port RAM

2Mbit (64K x 36) 3.3V Asynchronous Dual-Port RAM

1Mbit (32K x 36) 3.3V Asynchronous Dual-Port RAM

Power

999

Speed

Package

Process/

Temperature

Range

Blank

(1)

70V659

70V658

70V657

XXXXX

Device

Type

IDT

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History:

6/2/00: Initial Public Offering

8/11/00: Page 6, 13 & 20 Inserted additional BEn information

6/20/01: Page 14 Increased BUSY TIMING parameters tBDA, tBAC, tBDC and tBDD for all speeds

Page 21 Changed maximum value for JTAG AC Electrical Characteristics for tJCD from 20ns to 25ns

12/17/01: Page 2, 3 & 4 Added date revision for pin configurations

Page 8, 10, 14 & 16 Removed I-temp 15ns speed from DC & AC Electrical Characteristics

Page 23 Removed I-temp 15ns speed from ordering information

Added I-temp footnote

Page 1 & 23 Replaced TM logo with ® logo

03/19/04: Consolidated multiple devices into one data sheet

Removed "Preliminary" Status

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 831-754-4613

Santa Clara, CA 95054 fax: 408-492-8674 DualPortHelp@idt.com

www.idt.com

NOTE:

1. Contact your local sales office for industrial temp range for other speeds, packages and powers.