16-Bit Lower Power
PulSAR ADCs in MSOP/LFCSP (QFN)
Data Sheet
AD7988-1/AD7988-5
Rev. D Document Feedback
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FEATURES
Low power dissipation
AD7988-1
400 µW at 100 kSPS (VDD only)
700 µW at 100 kSPS (total)
AD7988-5
2 mW at 500 kSPS (VDD only)
3.5 mW at 500 kSPS (total)
16-bit resolution with no missing codes
Throughput: 100 kSPS/500 kSPS options
INL: ±0.6 LSB typical, ±1.25 LSB maximum
SINAD: 91.5 dB at 10 kHz
THD: −114 dB at 10 kHz
Pseudo differential analog input range
0 V to VREF with VREF from 2.5 V to 5.5 V
Any input range and easy to drive with the ADA4841-1
No pipeline delay
Single-supply 2.5 V operation with 1.8 V/2.5 V/3 V/5 V logic
interface
SPI-/QSPI-/MICROWIRE™-/DSP-compatible serial interface
Daisy-chain multiple ADCs
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP (QFN), same
space as SOT-23
Wide operating temperature range: −40°C to +125°C
APPLICATIONS
Battery-powered equipment
Low power data acquisition systems
Portable medical instruments
ATE equipment
Data acquisitions
Communications
GENERAL DESCRIPTION
The AD7988-1/AD7988-5 are 16-bit, successive approximation,
analog-to-digital converters (ADC) that operate from a single
power supply, VDD. The AD7988-1 offers a 100 kSPS throughput,
and the AD7988-5 offers a 500 kSPS throughput. They are low
power, 16-bit sampling ADCs with a versatile serial interface
port. On the CNV rising edge, they sample an analog input,
IN+, between 0 V to VREF with respect to a ground sense, IN−.
The reference voltage, REF, is applied externally and can be set
independent of the supply voltage, VDD.
The SPI-compatible serial interface also features the ability to
daisy-chain several ADCs on a single 3-wire bus using the SDI
input. It is compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic using
the separate supply, VIO.
The AD7988-1/AD7988-5 generics are housed in a 10-lead
MSOP or a 10-lead LFCSP (QFN) with operation specified
from −40°C to +125°C.
Table 1. MSOP, LFCSP (QFN) 14-/16-/18-Bit PulSAR® ADCs
Bits 100 kSPS 250 kSPS
400 kSPS to
500 kSPS
≥1000
kSPS ADC Driver
181 AD76912 AD76902 AD79822 ADA4941-1
AD79842 ADA4841-1
16
1
AD7684 AD7687
2
AD7688
2
ADA4941-1
AD7693
2
ADA4841-1
163 AD7680 AD76852 AD76862 AD79802 ADA4841-1
AD7683 AD7694 AD7988-52
AD7988-12
143 AD7940 AD79422 AD79462 ADA4841-1
1 True differential.
2 Pin-for-pin compatible.
3 Pseudo differential.
TYPICAL APPLICATION DIAGRAM
REF
GND
VDD
IN+
IN–
VIO
SDI
SCK
SDO
CNV
1.8V TO 5.5V
3- O R 4- WIRE INT E RFACE
(SPI, DAISY CHAIN, CS)
2.5V TO 5V 2.5V
0V TO V
REF
10231-001
AD7988-1/
AD7988-5
Figure 1.
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 2 of 24
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Typical Application Diagram .......................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configurations and Function Descriptions ........................... 8
Terminology ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 14
Circuit Information .................................................................... 14
Converter Operation .................................................................. 14
Typical Connection Diagram ................................................... 15
Analog Inputs ............................................................................. 16
Driver Amplifier Choice ........................................................... 16
Voltage Reference Input ............................................................ 17
Power Supply ............................................................................... 17
Digital Interface .......................................................................... 17
CS Mode, 3-Wire ........................................................................ 18
CS Mode 4-Wire ......................................................................... 19
Chain Mode ................................................................................ 20
Applications Information .............................................................. 21
Interfacing to Blackfin® DSP ..................................................... 21
Layout .......................................................................................... 21
Evaluating the Performance of the AD7988-x ........................ 21
Outline Dimensions ....................................................................... 22
Ordering Guide .......................................................................... 23
REVISION HISTORY
8/13—Rev. C to Rev. D
Changes to Features Section............................................................ 1
Changes to Table 3 ............................................................................ 4
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 23
8/12—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 23
5/12—Rev. A to Rev. B
Changes to Table 3 ............................................................................ 4
Updated Outline Dimensions ....................................................... 22
2/12—Rev. 0 to Rev. A
Added LFCSP Thermal Impedance Values ................................... 7
Updated Outline Dimensions ....................................................... 23
Changes to Ordering Guide .......................................................... 23
2/12—Revision 0: Initial Versi on
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 3 of 24
SPECIFICATIONS
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, V REF = 5 V, TA = –40°C to +125°C, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
RESOLUTION 16 Bits
ANALOG INPUT
Voltage Range IN+ − IN− 0 VREF V
Absolute Input Voltage
IN+
−0.1
V
REF
+ 0.1
V
IN− −0.1 +0.1 V
Analog Input CMRR fIN = 1 kHz 60 dB
Leakage Current at 25°C Acquisition phase 1 nA
Input Impedance See the Analog Inputs section
ACCURACY
No Missing Codes 16 Bits
Differential Linearity Error VREF = 5 V −0.9 ±0.4 +0.9 LSB1
VREF = 2.5 V ±0.55 LSB1
Integral Linearity Error
V
REF
= 5 V
−1.25
±0.6
+1.25
LSB
1
VREF = 2.5 V ±0.65 LSB1
Transition Noise VREF = 5 V 0.6 LSB1
VREF = 2.5 V 1.0 LSB1
Gain Error, TMIN to TMAX 2 ±2 LSB1
Gain Error Temperature Drift
±0.35
ppm/°C
Zero Error, TMIN to TMAX2 −0.5 ±0.08 +0.5 mV
Zero Temperature Drift 0.54 ppm/°C
Power Supply Sensitivity VDD = 2.5 V ± 5% ±0.1 LSB1
THROUGHPUT
AD7988-1
Conversion Rate VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C up to
125°C
0 100 kSPS
Transient Response Full-scale step 500 ns
AD7988-5
Conversion Rate VIO ≥ 2.3 V up to 85°C, VIO ≥ 3.3 V above 85°C up to
125°C
0 500 kSPS
Transient Response Full-scale step 400 ns
AC ACCURACY
Dynamic Range VREF = 5 V 92 dB3
VREF = 2.5 V 87 dB3
Oversampled Dynamic Range fO = 10 kSPS 111 dB3
Signal-to-Noise Ratio, SNR fIN = 10 kHz, VREF = 5 V 90 91 dB3
fIN = 10 kHz, VREF = 2.5 V 86.5 dB3
Spurious-Free Dynamic Range, SFDR fIN = 10 kHz −110 dB3
Total Harmonic Distortion, THD fIN = 10 kHz −114 dB3
Signal-to-(Noise + Distortion), SINAD fIN = 10 kHz, VREF = 5 V 91.5 dB3
fIN = 10 kHz, VREF = 2.5 V 87.0 dB3
1 LSB means least significant bit. With the 5 V input range, 1 LSB is 76.3 µV.
2 See the Terminology section. These specifications include full temperature range variation, but not the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 4 of 24
VDD = 2.5 V, VIO = 2.3 V to 5.5 V, V REF = 5 V, TA = –40°C to +125°C, unless otherwise noted.
Table 3.
Parameter Test Conditions/Comments Min Typ Max Unit
REFERENCE
Voltage Range 2.4 5.1 V
Load Current VREF = 5 V 250 µA
SAMPLING DYNAMICS
−3 dB Input Bandwidth 10 MHz
Aperture Delay VDD = 2.5 V 2.0 ns
DIGITAL INPUTS
Logic Levels
VIL VIO > 3 V –0.3 0.3 × VIO V
VIH VIO > 3 V 0.7 × VIO VIO + 0.3 V
VIL VIO ≤ 3 V –0.3 0.1 × VIO V
VIH VIO ≤ 3 V 0.9 × VIO VIO + 0.3 V
IIL −1 +1 µA
IIH −1 +1 µA
DIGITAL OUTPUTS
Data Format Serial 16 bits straight binary
Pipeline Delay Conversion results available immediately
after completed conversion
VOL ISINK = 500 µA 0.4 V
VOH ISOURCE = −500 µA VIO − 0.3 V
POWER SUPPLIES
VDD 2.375 2.5 2.625 V
VIO Specified performance 2.3 5.5 V
VIO Range 1.8 5.5 V
Standby Current1, 2 VDD and VIO = 2.5 V, 25°C 0.35 nA
AD7988-1 Power Dissipation
VDD = 2.625 V, V
REF
= 5 V, VIO = 3 V
Total 10 kSPS throughput 70 µW
100 kSPS throughput 700 µW
1 mW
VDD Only 400 µW
REF Only 170 µW
VIO Only
130
µW
AD7988-5 Power Dissipation VDD = 2.625 V, VREF = 5 V, VIO = 3 V
Total 500 kSPS throughput 3.5 5 mW
VDD Only 2 mW
REF Only 0.85 mW
VIO Only 0.65 mW
Energy per Conversion 7.0 nJ/sample
TEMPERATURE RANGE
Specified Performance
T
MIN
to T
MAX
−40
+125
°C
1 With all digital inputs forced to VIO or GND as required.
2 During the acquisition phase.
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 5 of 24
TIMING SPECIFICATIONS
VDD = 2.37 V to 2.63 V, VIO = 3.3 V to 5.5 V, −40°C to +125°C unless otherwise stated. See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter Symbol Min Typ Max Unit
AD7988-1
Throughput Rate 100 kHz
Conversion Time: CNV Rising Edge to Data Available tCONV 9.5 μs
Acquisition Time tACQ 500 ns
Time Between Conversions tCYC 10 μs
AD7988-5
Throughput Rate 500 kHz
Conversion Time: CNV Rising Edge to Data Available tCONV 1.6 μs
Acquisition Time tACQ 400 ns
Time Between Conversions tCYC 2 μs
CNV Pulse Width (CS Mode) tCNVH 500 ns
SCK Period (CS Mode) tSCK
VIO Above 4.5 V 10.5 ns
VIO Above 3 V 12 ns
VIO Above 2.7 V 13 ns
VIO Above 2.3 V 15 ns
SCK Period (Chain Mode)
t
SCK
VIO Above 4.5 V 11.5 ns
VIO Above 3 V 13 ns
VIO Above 2.7 V 14 ns
VIO Above 2.3 V 16 ns
SCK Low Time tSCKL 4.5 ns
SCK High Time
t
SCKH
4.5
ns
SCK Falling Edge to Data Remains Valid tHSDO 3 ns
SCK Falling Edge to Data Valid Delay tDSDO
VIO Above 4.5 V 9.5 ns
VIO Above 3 V 11 ns
VIO Above 2.7 V 12 ns
VIO Above 2.3 V 14 ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode) tEN
VIO Above 3 V 10 ns
VIO Above 2.3V 15 ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode) tDIS 20 ns
SDI Valid Setup Time from CNV Rising Edge
t
SSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode) tHSDICNV 2 ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode) tHSDICNV 0 ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode) tSSCKCNV 5 ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode) tHSCKCNV 5 ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode) tSSDISCK 2 ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode) tHSDISCK 3 ns
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 6 of 24
500µA I
OL
500µA I
OH
1.4V
TO SDO C
L
20pF
10231-002
Figure 2. Load Circuit for Digital Interface Timing
X% VIO
1
Y% VIO
1
V
IH2
V
IL2
V
IL2
V
IH2
t
DELAY
t
DELAY
1
FOR VIO ≤ 3.0V, X = 90 AND Y = 10; FOR VIO > 3.0V X = 70, AND Y = 30.
2
MINIMUM V
IH
AND MAXIMUM V
IL
USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
10231-003
Figure 3. Voltage Levels for Timing
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 7 of 24
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating
Analog Inputs
IN+,1 IN−1 to GND
−0.3 V to V
REF
+ 0.3 V or ±130 mA
Supply Voltage
REF, VIO to GND −0.3 V to +6 V
VDD to GND −0.3 V to +3 V
VDD to VIO +3 V to −6 V
Digital Inputs to GND −0.3 V to VIO + 0.3 V
Digital Outputs to GND
−0.3 V to VIO + 0.3 V
Storage Temperature Range −65°C to +125°C
Junction Temperature 150°C
θJA Thermal Impedance
10-Lead MSOP 200°C/W
10-Lead LFCSP 80°C/W
θ
JC
Thermal Impedance
10-Lead MSOP 44°C/W
10-Lead LFCSP 15°C/W
Reflow Soldering JEDEC Standard (J-STD-020)
1 See the Analog Inputs section.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 8 of 24
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
1
VDD
2
IN+
3
IN–
4
GND
5
VIO
10
SDI
9
SCK
8
SDO
7
CNV
6
10231-004
AD7988-1/
AD7988-5
TOP VIEW
(Not to Scale)
Figure 4. 10-Lead MSOP Pin Configuration
NOTES
1. THE EXPOSED PAD CAN BE CONNECTED TO GND.
1REF
2VDD
3IN+
4IN–
5GND
10 VIO
9SDI
8SCK
7SDO
6CNV
10231-005
AD7988-1/
AD7988-5
TOPVIEW
(Notto Scale)
Figure 5. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No. Mnemonic Type 1 Description
1 REF AI Reference Input Voltage. The VREF range is from 2.4 V to 5.1 V. It is referred to the GND pin. The GND pin
should be decoupled closely to the REF pin with a 10 µF capacitor.
2 VDD P Power Supply.
3 IN+ AI Analog Input. It is referred to IN−. The voltage range, for example, the difference between IN+ and IN−, is
0 V to VREF.
4 IN− AI Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
5 GND P Power Supply Ground.
6
CNV
DI
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode of the part: chain mode or CS mode. In CS mode, the SDO pin is enabled when
CNV is low. In chain mode, the data should be read when CNV is high.
7 SDO DO Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
8 SCK DI Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
9
SDI
DI
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC as
follows:
Chain mode is selected if this pin is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital data
level on SDI is output on SDO with a delay of 16 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can enable
the serial output signals when low.
10 VIO P Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V, 3 V,
or 5 V).
EP Exposed Pad. The exposed pad can be connected to GND.
1AI = analog input, DI = digital input, DO = digital output, and P = power.
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 9 of 24
TERMINOLOGY
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 30).
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (38.1 µV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Gain Error
The last transition (from 111 … 10 to 111 … 11) should
occur for an analog voltage 1½ LSB below the nominal full
scale (4.999886 V for the 0 V to 5 V range). The gain error is
the deviation of the actual level of the last transition from the
ideal level after the offset is adjusted out.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which
it is impossible to distinctly resolve individual codes. It is
calculated as
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
and is expressed in bits.
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in dB. It is measured
with a signal at −60 dBFS to include all noise sources and DNL
artifacts.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
Aperture Delay
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the ADC to
accurately acquire its input after a full-scale step function is
applied.
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 10 of 24
TYPICAL PERFORMANCE CHARACTERISTICS
VDD = 2.5 V, VREF = 5.0 V, VIO = 3.3 V, unless otherwise noted.
0
–180
FREQUENCY (kHz)
–20
–40
–60
–80
–100
–120
–140
–160
fS = 500kSPS
fIN = 10kHz
SNR = 91. 17dB
THD = –113.63d B
SF DR = 110.30d B
SI NAD = 91.15d B
AMPLITUDE (dB of FULL SCALE)
050 100 150 200 250
10231-046
Figure 6. AD7988-5 FFT Plot, VREF = 5 V
0
–180
FREQUENCY (kHz)
–20
–40
–60
–80
–100
–120
–140
–160
fS = 500kSPS
fIN = 10kHz
SNR = 86. 8dB
THD = –111.4d B
SF DR = 105.9d B
SI NAD = 86.8d B
AMPLITUDE (dB of FULL SCALE)
050 100 150 200 250
10231-047
Figure 7. AD7988-5 FFT Plot, VREF = 2.5 V
0
–180
FREQUENCY (kHz)
–20
–40
–60
–80
–100
–120
–140
–160
fS = 100kSPS
fIN = 10kHz
SNR = 91. 09dB
THD = –113.12d B
SF DR = 110.30d B
SI NAD = 91.05d B
AMPLITUDE (dB of FULL SCALE)
010 20 30 40 50
10231-048
Figure 8. AD7988-1 FFT Plot, VREF = 5 V
0
–180
FREQUENCY (kHz)
–20
–40
–60
–80
–100
–120
–140
–160
fS = 100kSPS
fIN = 10kHz
SNR = 86. 7dB
THD = –110.4d B
SF DR = 103.9d B
SI NAD = 86.6d B
AMPLITUDE (dB of FULL SCALE)
010 20 30 40 50
10231-049
Figure 9. AD7988-1 FFT Plot, VREF = 2.5 V
1.25
–1.25
CODE
INL (LSB)
1.00
0.75
0.50
0.25
–0.25
–0.75
0
–0.50
–1.00
POSITIVE INL: +0.40 LSB
NEGATIVEINL:–0.35LSB
016384 32768 49152 65536
10231-010
Figure 10. Integral Nonlinearity vs. Code, VREF = 5 V
1.25
1.00
–1.25
–1.00
INL (LSB)
0.75
0.50
0.25
–0.25
–0.75
0
–0.50
POSITIVE INL: +0.45 LSB
NEGATIVE INL: –0.29 LSB
CODE
016384 32768 49152 65536
10231-011
Figure 11. Integral Nonlinearity vs. Code, VREF = 2.5 V
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 11 of 24
CODE
016384 32768 49152 65536
1.00
–1.00
DNL (LSB)
0.75
0.50
0.25
–0.25
–0.75
0
–0.50
POSITIVE INL:+0.18LSB
NEGATIVE INL: –0.21 LSB
10231-012
Figure 12. Differential Nonlinearity vs. Code, VREF = 5 V
CODE
016384 32768 49152 65536
1.00
–1.00
DNL (LSB)
0.75
0.50
0.25
–0.25
–0.75
0
–0.50
POSITIVE INL: +0.25 LSB
NEGATIVE INL: –0.22 LSB
10231-013
Figure 13. Differential Nonlinearity vs. Code, VREF = 2.5 V
180k
0
000 0022
CODE IN HEX
COUNTS
8003 8004 8005 8006 8007 8008 8009 800A 800B 800C 800D 800E 800F
1291 852 29 2
10231-050
160k
140k
120k
100k
80k
60k
40k
20k
52720
162595
42731
Figure 14. Histogram of a DC Input at the Code Center, VREF = 5 V
60k
00
0
00
9430
1
CODE IN HEX
COUNTS
50k
30k
10k
40k
20k
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
2290
18848
50970
45198
12424
1217
10231-015
Figure 15. Histogram of a DC Input at the Code Transition, VREF = 2.5 V
100
80
85
90
95
REFERENCE VOLTAGE (V)
SNR, SINAD (dB)
16
12
13
14
15
ENOB (Bits)
SNR
SINAD
ENOB
2.25 2.75 3.25 3.75 4.25 4.75 5.25
10231-016
Figure 16. SNR, SINAD, and ENOB vs. Reference Voltage
60k
0000 0
590 11
19
CODE IN HEX
COUNTS
50k
30k
10k
40k
20k
7FFA 7FFB 7FFC 7FFD 7FFE 7FFF 8000 8001 8002 8003 8004 8005 8006
7285
37417
53412
31540
5807
512
10231-051
Figure 17. Histogram of a DC Input at the Code Center, VREF = 2.5 V
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 12 of 24
95
85
87
89
92
91
93
94
86
88
90
INPUT LEVEL (dB OF FULLSCALE)
SNR (dB)
–10 –9 –8 –7 –6 –5 –4 –3 –2 –1 0
10231-018
Figure 18. SNR vs. Input Level
–95
–125
–110
–115
–105
–100
–120
115
85
100
95
105
110
90
REFERENCE VOLTAGE (V)
THD (dB)
SFDR (dB)
THD
SFDR
2.25 2.75 3.25 3.75 4.25 4.75 5.25
10231-019
Figure 19. THD, SFDR vs. Reference Voltage
100
8010 1k
FRE QUENCY ( kHz )
SI NAD ( dB)
95
90
85
100
10231-052
Figure 20. SINAD vs. Frequency
10231-053
95
85
89
87
91
93
–55 125
TEMPERATURE (°C)
SNR (dB)
–35 –15 525 65 85
45 105
Figure 21. SNR vs. Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
VDD VOLTAGE (V)
IVDD
I
REF
I
VIO
CURRENT ( mA)
2.375 2.425 2.475 2.525 2.575 2.625
10231-023
Figure 22. Operating Currents vs. Supply (AD7988-5)
0.14
0.12
0.10
0.08
0.06
0.04
0.02
0
VDD VOLTAGE (V)
I
VDD
I
REF
I
VIO
CURRENT ( mA)
2.375 2.425 2.475 2.525 2.575 2.625
10231-024
Figure 23. Operating Currents vs. Supply (AD7988-1)
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 13 of 24
10231-054
–85
–12510 1k
FRE QUENCY ( kHz )
THD ( dB)
100
–90
–95
–100
–105
–110
–115
–120
Figure 24. THD vs. Frequency
–110
–120
THD (dB)
TEMPERATURE (°C)
–112
–114
–116
–118
–55 –35 –15 525 45 65 85 105 125
10231-026
Figure 25. THD vs. Temperature
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
CURRENT ( mA)
I
VDD
I
REF
I
VIO
TEMPERATURE (°C)
–55 –35 –15 525 45 65 85 105 125
10231-027
Figure 26. Operating Currents vs. Temperature (AD7988-5)
0.14
0.12
0.10
008
0.06
0.04
0.02
0
CURRENT ( mA)
IVDD
I
REF
I
VIO
TEMPERATURE (°C)
–55 –35 –15 525 45 65 85 105 125
10231-028
Figure 27. Operating Currents vs. Temperature (AD7988-1)
8
7
6
5
4
3
2
1
0
CURRENT ( µ A)
TEMPERATURE (°C)
I
VDD
+ I
VIO
–55 –35 –15 525 45 65 85 105 125
10231-029
Figure 28. Power-Down Currents vs. Temperature
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 14 of 24
THEORY OF OPERATION
COMP
SW ITCHE S CONT ROL
BUSY
OUTPUT CODE
CNV
CONTROL
LOGIC
SW+LSB
SW–LSB
IN+
REF
GND
IN–
MSB
MSB
CC4C 2C16,384C
32,768C
CC4C 2C16,384C32,768C
10231-030
Figure 29. ADC Simplified Schematic
CIRCUIT INFORMATION
The AD7988-1/AD7988-5 devices are fast, low power, single-
supply, precise 16-bit ADCs that use a successive approximation
architecture.
The AD7988-1 is capable of converting 100,000 samples per
second (100 kSPS), whereas the AD7988-5 is capable of a
throughput of 500 kSPS, and they power down between
conversions. When operating at 10 kSPS, for example, the
ADC consumes 70 µW typically, ideal for battery-powered
applications.
The AD7988-x provides the user with on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The AD7988-x can be interfaced to any 1.8 V to 5 V digital logic
family. It is housed in a 10-lead MSOP or a tiny 10-lead LFCSP
(QFN) that combines space savings and allows flexible
configurations.
CONVERTER OPERATION
The AD7988-x is a successive approximation ADC based on a
charge redistribution DAC. Figure 29 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 16 binary weighted capacitors, which are
connected to the two comparator inputs.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Therefore, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is completed and the CNV input goes high, a
conversion phase is initiated. When the conversion phase begins,
SW+ and SW− are opened first. The two capacitor arrays are then
disconnected from the inputs and connected to the GND input.
Therefore, the differential voltage between the IN+ and IN−
inputs captured at the end of the acquisition phase are applied
to the comparator inputs, causing the comparator to become
unbalanced. By switching each element of the capacitor array
between GND and REF, the comparator input varies by binary
weighted voltage steps (VREF/2, VREF/4 … VREF/65,536). The
control logic toggles these switches, starting with the MSB, to
bring the comparator back into a balanced condition. After the
completion of this process, the part returns to the acquisition phase
and the control logic generates the ADC output code.
Because the AD7988-x has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 15 of 24
Transfer Functions
The ideal transfer characteristic for the AD7988-x is shown in
Figure 30 and Table 7.
000 .. . 000
000 .. . 001
000 .. . 010
111 ... 101
111 ... 110
111 ... 111
–FSR –FSR + 1LSB
–FSR + 0.5L S B +FS R – 1 LSB
+FS R – 1.5 L S B
ANALO G I NP UT
ADC CODE ( S TRAI GHT BINARY)
10231-031
Figure 30. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Analog Input
Description VREF = 5 V Digital Output Code (Hex)
FSR – 1 LSB 4.999924 V FFFF1
Midscale + 1 LSB 2.500076 V 8001
Midscale 2.5 V 8000
Midscale – 1 LSB 2.499924 V 7FFF
–FSR + 1 LSB 76.3 µV 0001
–FSR 0 V 00002
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
Figure 31 shows an example of the recommended connection
diagram for the AD7988-x when multiple supplies are available.
AD7988-1/
AD7988-5
2.5VV+
20Ω
V+
V–
0V TO VREF
1.8V TO 5.5V
100nF
10µF2
2.7nF
4
3
100nF
REF
IN+
IN–
VDD VIO
GND
3- O R 4- WIRE INT E RFACE5
REF1
1SEE THE VOLT AGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2CREF IS US UALL Y A 10µ F CERAM IC CAPACITOR (X 5R) .
3SEE THE DRIVER AMPLI F I ER CHOICE SECTION.
4OPTIONAL FILTER. SEE THE ANALOG INPUTS SECTION.
5SEE THE DIGITAL INTERFACE SECTION FOR THE MOST CONVENIENT INTERFACE MODE.
10231-032
CNV
SCK
SDO
SDI
Figure 31. Typical Application Diagram with Multiple Supplies
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 16 of 24
ANALOG INPUTS
Figure 32 shows an equivalent circuit of the input structure of
the AD7988-x.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V, because this causes these diodes to become forward-
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance,
these conditions may eventually occur when the input buffer’s
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.
REF
R
IN
C
IN
IN+
OR IN–
GND
D2C
PIN
D1
10231-033
Figure 32. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination of
Capacitor CPIN and the network formed by the series connection of
RIN and CIN. CPIN is primarily the pin capacitance. RIN is typically
400 Ω and is a lumped component made up of serial resistors
and the on resistance of the switches. CIN is typically 30 pF and
is mainly the ADC sampling capacitor. During the conversion
phase, when the switches are opened, the input impedance is
limited to CPIN. RIN and CIN make a one-pole, low-pass filter that
reduces undesirable aliasing effects and limits the noise.
When the source impedance of the driving circuit is low, the
AD7988-x can be driven directly. Large source impedances
significantly affect the ac performance, especially THD. The dc
performances are less sensitive to the input impedance. The
maximum source impedance depends on the amount of THD
that can be tolerated. The THD degrades as a function of the
source impedance and the maximum input frequency.
DRIVER AMPLIFIER CHOICE
Although the AD7988-x is easy to drive, the driver amplifier
needs to meet the following requirements:
• The noise generated by the driver amplifier must be kept as
low as possible to preserve the SNR and transition noise
performance of the AD7988-x. The noise coming from the
driver is filtered by the AD7988-x analog input circuit’s
one-pole, low-pass filter made by RIN and CIN or by the
external filter, if one is used. Because the typical noise of
the AD7988-x is 47.3 µV rms, the SNR degradation due to
the amplifier is
+
=
−
2
3dB
2)
(
2
π
47.3
47.3
log20
N
LOSS
Nef
SNR
where:
f–3dB is the input bandwidth in MHz of the AD7988-x
(10 MHz) or the cutoff frequency of the input filter, if
one is used.
N is the noise gain of the amplifier (for example, 1 in buffer
configuration).
eN is the equivalent input noise voltage of the op amp,
in nV/√Hz.
• For ac applications, the driver should have a THD
performance commensurate with the AD7988-x.
• For multichannel multiplexed applications, the driver ampli-
fier and the AD7988-x analog input circuit must settle for
a full-scale step onto the capacitor array at a 16-bit level
(0.0015%, 15 ppm). In the amplifier data sheet, settling at
0.1% to 0.01% is more commonly specified. This may
differ significantly from the settling time at a 16-bit level
and should be verified prior to driver selection.
Table 8. Recommended Driver Amplifiers
Amplifier Typical Application
ADA4841-1 Very low noise, small size, and low power
AD8021 Very low noise and high frequency
AD8022 Low noise and high frequency
OP184 Low power, low noise, and low frequency
AD8655 5 V single-supply, low noise
AD8605, AD8615
5 V single-supply, low power
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 17 of 24
VOLTAGE REFERENCE INPUT
The AD7988-x voltage reference input, REF, has a dynamic
input impedance and should therefore be driven by a low
impedance source with efficient decoupling between the REF
and GND pins, as explained in the Layout section.
When REF is driven by a very low impedance source, for example,
a reference buffer using the AD8031 or the AD8605, a ceramic
chip capacitor is appropriate for optimum performance.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For example, a 22 µF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
If desired, a reference-decoupling capacitor value as small as
2.2 µF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
POWER SUPPLY
The AD7988-x uses two power supply pins: a core supply, VDD,
and a digital input/output interface supply, VIO. VIO allows
direct interface with any logic between 1.8 V and 5.0 V. To
reduce the number of supplies needed, VIO and VDD can be
tied together. The AD7988-x is independent of power supply
sequencing between VIO and VDD. Additionally, it is very
insensitive to power supply variations over a wide frequency
range, as shown in Figure 33.
80
5511k
FRE QUENCY ( kHz )
PSRR ( dB)
10 100
75
70
65
60
10231-034
Figure 33. PSRR vs. Frequency
To ensure optimum performance, VDD should be roughly half
of REF, the voltage reference input. For example, if REF is 5.0 V,
VDD should be set to 2.5 V (±5%). If REF = 2.5V, and VDD =
2.5 V, performance is degraded as can be seen in Table 2.
The AD7988-x powers down automatically at the end of each
conversion phase.
DIGITAL INTERFACE
Although the AD7988-x has a reduced number of pins, it offers
flexibility in its serial interface modes.
The AD7988-x, when in CS mode, is compatible with SPI, QSPI™,
and digital hosts. This interface can use either a 3-wire or 4-wire
interface. A 3-wire interface using the CNV, SCK, and SDO
signals minimizes wiring connections and is useful, for
instance, in isolated applications. A 4-wire interface using the
SDI, CNV, SCK, and SDO signals allows CNV, which initiates
the conversions, to be independent of the readback timing
(SDI). This is useful in low jitter sampling or simultaneous
sampling applications.
The AD7988-x, when in chain mode, provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line, similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. CS mode is selected if SDI is
high, and chain mode is selected if SDI is low. The SDI hold
time is such that when SDI and CNV are connected together,
the chain mode is selected.
The user must time out the maximum conversion time prior to
readback.
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 18 of 24
CS MODE, 3-WIRE
This mode is typically used when a single AD7988-x is
connected to an SPI-compatible digital host. The connection
diagram is shown in Figure 34, and the corresponding timing is
given in Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a conver-
sion, selects the CS mode, and forces SDO to high impedance.
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down.
When CNV goes low, the MSB is output onto SDO. The remaining
data bits are then clocked by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided that it has an acceptable
hold time. After the 16th SCK falling edge or when CNV goes
high, whichever is earlier, SDO returns to high impedance.
AD7988-1/
AD7988-5
SDO DAT A IN
DIGITAL HOST
CONVERT
CLK
VIO CNV
SCK
SDI
10231-035
Figure 34. 3-Wire CS Mode Connection Diagram
t
CONV
t
CYC
CNV
ACQUISITION ACQUISITION
t
ACQ
t
SCK
t
SCKL
CONVERSION
SCK
SDO D15 D14 D13 D1 D0
t
EN
t
HSDO
1 2 3 14 15 16
t
DSDO
t
DIS
t
SCKH
t
CNVH
SDI = 1
10231-036
Figure 35. 3-Wire CS Mode Serial Interface Timing (SDI High)
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 19 of 24
CS MODE 4-WIRE
This mode is typically used when multiple AD7988-x devices
are connected to an SPI-compatible digital host.
A connection diagram example using two AD7988-x devices is
shown in Figure 36, and the corresponding timing is given in
Figure 37.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
time elapses and then held high for the maximum conversion time.
When the conversion is complete, the AD7988-x enters the
acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are then
clocked by subsequent SCK falling edges. The data is valid on
both SCK edges. Although the rising edge can be used to capture
the data, a digital host using the SCK falling edge allows a faster
reading rate, provided that it has an acceptable hold time. After
the 16th SCK falling edge or when SDI goes high, whichever is
earlier, SDO returns to high impedance and another AD7988-x
can be read.
DIGITAL HOST
CONVERT
CLK
DATA IN
AD7988-1/
AD7988-5
SDO
CNV
SCK
AD7988-1/
AD7988-5
SDO
CNV
SCK
CS1
CS2
SDI SDI
10231-037
Figure 36. 4-Wire CS Mode Connection Diagram
t
CONV
t
CYC
ACQUISITION ACQUISITION
t
ACQ
t
SCK
t
SCKH
t
SCKL
CONVERSION
SCK
CNV
t
SSDICNV
t
HSDICNV
SDO D15 D13D14 D1 D0 D15 D14 D1 D0
t
HSDO
t
EN
123 14 15 16 17 18 30 31 32
t
DSDO
t
DIS
SDI ( CS 1)
SDI ( CS 2)
10231-038
Figure 37. 4-Wire CS Mode Serial Interface Timing
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 20 of 24
CHAIN MODE
This mode can be used to daisy-chain multiple AD7988-x
devices on a 3-wire serial interface. This feature is useful for
reducing component count and wiring connections, for example,
in isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7988-x devices is
shown in Figure 38, and the corresponding timing is given in
Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion and selects the chain
mode. In this mode, CNV is held high during the conversion
phase and the subsequent data readback. When the conversion
is complete, the MSB is output onto SDO and the AD7988-x
enters the acquisition phase and powers down. The remaining
data bits stored in the internal shift register are clocked by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 16 × N clocks are required to read back the N ADCs. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate and, consequently, more
AD7988-x devices in the chain, provided that the digital host
has an acceptable hold time. The maximum conversion rate
may be reduced due to the total readback time.
DIGITAL HOST
CONVERT
CLK
DATA IN
AD7988-1/
AD7988-5
SDO
CNV
A
SCK
AD7988-1/
AD7988-5
SDO
CNV
B
SCK
10231-039
SDISDI
Figure 38. Chain Mode Connection Diagram
t
CONV
t
CYC
t
SSDISCK
t
SCKL
t
SCK
t
HSDISCK
t
ACQ
ACQUISITION
t
SSCKCNV
ACQUISITION
t
SCKH
CONVERSION
t
HSCKCNV
SCK
CNV
SDO
B
t
EN
D
A
15 D
A
14 D
A
13
D
B
15 D
B
14 D
B
13 D
B
1 D
B
0 D
A
15 D
A
14 D
A
0D
A
1
D
A
1 D
A
0
t
HSDO
1 2 3 15 16 1714 18 30 31 32
t
DSDO
10231-040
SDI
A
= 0
SDO
A
= SDI
B
Figure 39. Chain Mode Serial Interface Timing
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 21 of 24
APPLICATIONS INFORMATION
INTERFACING TO BLACKFIN® DSP
The AD7988-x can easily connect to a DSP SPI or SPORT. The
SPI configuration is straightforward, using the standard SPI
interface as shown in Figure 40.
AD7988-1/
AD7988-5
SCK
SDO
CNV
SPI_CLK
SPI_MISO
SPI_MOSI
10231-041
BLACKFIN
DSP
Figure 40. Typical Connection to Blackfin SPI Interface
Similarly, the SPORT interface can be used to interface to this
ADC. The SPORT interface has some benefits in that it can use
direct memory access (DMA) and provides a lower jitter CNV
signal generated from a hardware counter.
Some glue logic may be required between SPORT and the
AD7988-x interface. The evaluation board for the AD7988-x
interfaces directly to the SPORT of the Blackfin-based (ADSP-
BF-527) SDP board. The configuration used for the SPORT
interface requires the addition of some glue logic as shown in
Figure 41. The SCK input to the ADC was gated off when CNV
was high to keep the SCK line static while converting the data,
thereby ensuring the best integrity of the result. This approach
uses an AND gate and a NOT gate for the SCK path. The other
logic gates used on the RSCLK and RFS paths are for delay
matching purposes and may not be necessary where path
lengths are short.
This is one approach to using the SPORT interface for this ADC;
there may be other solutions equal to this approach.
SCK
SDO
CNV
TSCLK
DR
TFS
RFS
RSCLK
VDRIVE
AD7988-1/
AD7988-5
10231-045
BLACKFIN
DSP
Figure 41. Evaluation Board Connection to Blackfin Sport Interface
LAYOUT
Design the printed circuit board (PCB) that houses the AD7988-x
so that the analog and digital sections are separated and confined
to certain areas of the board. The pinout of the AD7988-x, with all
the analog signals on the left side and all the digital signals on
the right side, eases this task.
Avoid running digital lines under the device because these couple
noise onto the die, unless a ground plane under the AD7988-x is
used as a shield. Fast switching signals, such as CNV or clocks,
should never run near analog signal paths. Avoid crossover of
digital and analog signals.
Using at least one ground plane is recommended. It can be
common or split between the digital and analog section. In the
latter case, join the planes underneath the AD7988-x devices.
The AD7988-x voltage reference input, REF, has a dynamic input
impedance. Decouple REF with minimal parasitic inductances
by placing the reference decoupling ceramic capacitor close to,
but ideally right up against, the REF and GND pins and connect-
ing them with wide, low impedance traces.
Finally, decouple the power supplies of the AD7988-x, VDD and
VIO, with ceramic capacitors, typically 100 nF, placed close to
the AD7988-x and connected using short and wide traces to
provide low impedance paths and to reduce the effect of glitches
on the power supply lines.
An example of a layout following these rules is shown in Figure 42
and Figure 43.
EVALUATING THE PERFORMANCE OF THE
AD7988-x
The evaluation board package for the AD7988-x (EVAL-AD7988-
5SDZ) includes a fully assembled and tested evaluation board,
documentation, and software for controlling the board from a
PC via the EVAL-SDP-CB1Z.
AD7988-1/
AD7988-5
10231-043
Figure 42. Example Layout of the AD7988-x (Top Layer)
10231-044
Figure 43. Example Layout of the AD7988-x (Bottom Layer)
AD7988-1/AD7988-5 Data Sheet
Rev. D | Page 22 of 24
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 44.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
0.50
0.40
0.30
10
1
6
5
0.30
0.25
0.20
PI N 1 INDEX
AREA
SEATING
PLANE
0.80
0.75
0.70
1.74
1.64
1.49
0.20 RE F
0.05 M AX
0.02 NOM
0.50 BS C
EXPOSED
PAD
3.10
3.00 S Q
2.90
PI N 1
INDICATOR
(R 0. 15)
FOR PRO P E R CONNECTI ON OF
THE EXPOSED PAD, REFER TO
THE P IN CONFI GURAT ION AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
02-05-2013-C
TOP VIEW BOTTOM VIEW
0.20 M IN
Figure 45. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
Data Sheet AD7988-1/AD7988-5
Rev. D | Page 23 of 24
ORDERING GUIDE
Model1 Notes
Integral
Nonlinearity
Temperature
Range
Ordering
Quantity Package Description
Package
Option Branding
AD7988-1BRMZ ±1.25 LSB max −40°C to +125°C Tube, 50 10-Lead MSOP RM-10 C7E
AD7988-1BRMZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,000 10-Lead MSOP RM-10 C7E
AD7988-1BCPZ-RL ±1.25 LSB max −40°C to +125°C Reel, 5,000 10-Lead QFN (LFCSP_WD) CP-10-9 C7X
AD7988-1BCPZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,500 10-Lead QFN (LFCSP_WD) CP-10-9 C7X
AD7988-5BRMZ ±1.25 LSB max −40°C to +125°C Tube, 50 10-Lead MSOP RM-10 C7Q
AD7988-5BRMZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,000 10-Lead MSOP RM-10 C7Q
AD7988-5BCPZ-RL ±1.25 LSB max −40°C to +125°C Reel, 5,000 10-Lead QFN (LFCSP_WD) CP-10-9 C7Z
AD7988-5BCPZ-RL7 ±1.25 LSB max −40°C to +125°C Reel, 1,500 10-Lead QFN (LFCSP_WD) CP-10-9 C7Z
EVAL-AD7988-5SDZ
2
Evaluation Board with AD7988-5
Populated; Use for Evaluation of Both
AD7988-1 and AD7988-5
EVAL-SDP-CB1Z 3 System Demonstration Board, Used as a
Controller Board for Data Transfer via
USB Interface to PC
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-SDZ-CB1Z for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices, Inc., evaluation boards ending in the SD designator.
