General Description
The MAX12529 is a dual, 96Msps, 12-bit analog-to-digi-
tal converter (ADC) featuring fully differential wideband
track-and-hold (T/H) inputs, driving internal quantizers.
The MAX12529 is optimized for low power, small size,
and high dynamic performance in intermediate frequen-
cy (IF) and baseband sampling applications. This dual
ADC operates from a single 3.3V supply, consuming
only 980mW while delivering a typical 69.7dB signal-to-
noise ratio (SNR) performance at a 175MHz input fre-
quency. The T/H input stages accept single-ended or
differential inputs up to 350MHz. In addition to low oper-
ating power, the MAX12529 features a 0.66mW power-
down mode to conserve power during idle periods.
A flexible reference structure allows the MAX12529 to
use the internal 2.048V bandgap reference or accept
an externally applied reference and allows the refer-
ence to be shared between the two ADCs. The refer-
ence structure allows the full-scale analog input range
to be adjusted from ±0.35V to ±1.15V. The MAX12529
provides a common-mode reference to simplify design
and reduce external component count in differential
analog input circuits.
The MAX12529 supports either a single-ended or differ-
ential input clock. User-selectable divide-by-two (DIV2)
and divide-by-four (DIV4) modes allow for design flexibil-
ity and help eliminate the negative effects of clock jitter.
Wide variations in the clock duty cycle are compensated
with the ADC’s internal duty-cycle equalizer (DCE).
The MAX12529 features two parallel, 12-bit-wide,
CMOS-compatible outputs. The digital output format is
pin-selectable to be either two’s complement or Gray
code. A separate power-supply input for the digital out-
puts accepts a 1.7V to 3.6V voltage for flexible interfac-
ing with various logic levels. The MAX12529 is available
in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package
with exposed paddle (EP), and is specified for the
extended (-40°C to +85°C) temperature range.
Applications
IF and Baseband Communication Receivers
Cellular, LMDS, Point-to-Point Microwave,
MMDS, HFC, WLAN
I/Q Receivers
Medical Imaging
Portable Instrumentation
Digital Set-Top Boxes
Low-Power Data Acquisition
Features
♦Direct IF Sampling Up to 350MHz
♦Excellent Dynamic Performance
70.1dB/69.7dB SNR at fIN = 70MHz/175MHz
83.2dBc/78.9dBc SFDR at fIN = 70MHz/175MHz
♦3.3V Low-Power Operation
980mW (Differential Clock Mode)
952mW (Single-Ended Clock Mode)
♦Fully Differential or Single-Ended Analog Input
♦Adjustable Differential Analog Input Voltage
♦750MHz Input Bandwidth
♦Internal, External, or Shared Reference
♦Differential or Single-Ended Clock
♦Accepts 25% to 75% Clock Duty Cycle
♦User-Selectable DIV2 and DIV4 Clock Modes
♦Power-Down Mode
♦CMOS Outputs in Two’s Complement or Gray
Code
♦Out-of-Range and Data-Valid Indicators
♦Compact, 68-Pin Thin QFN Package (10mm x
10mm x 0.8mm)
♦Evaluation Kit Available (Order MAX12529EVKIT)
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-3927; Rev 1; 5/07
EVALUATION KIT
AVAILABLE
PART TEMP RANGE PIN-PACKAGE PKG
CODE
M AX 12529E TK- D - 40° C to + 85° C 68 Thi n QFN - E P * T6800- 4
M AX 12529E TK+ D - 40° C to + 85° C 68 Thi n QFN - E P * T6800- 4
Pin Configuration appears at end of data sheet.
Selector Guide
PART
SAMPLING RATE
(Msps)
RESOLUTION
(Bits)
MAX12559 96 14
MAX12558 80 14
MAX12557 65 14
MAX12529 96 12
MAX12528 80 12
MAX12527 65 12
*EP = Exposed paddle.
+Denotes lead-free package.
D = Dry pack.
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim's website at www.maxim-ic.com.
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, AIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA=
-40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND ................................................................-0.3V to +3.6V
OVDD to GND............-0.3V to the lower of (VDD + 0.3V) and +3.6V
INAP, INAN to GND....-0.3V to the lower of (VDD + 0.3V) and +3.6V
INBP, INBN to GND....-0.3V to the lower of (VDD + 0.3V) and +3.6V
CLKP, CLKN to
GND ........................-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFIN, REFOUT
to GND ..................-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFAP, REFAN,
COMA to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V
REFBP, REFBN,
COMB to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V
DIFFCLK/SECLK, G/T, PD, SHREF, DIV2,
DIV4 to GND .........-0.3V to the lower of (VDD + 0.3V) and +3.6V
D0A–D11A, D0B–D11B, DAV,
DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA= +70°C)
68-Pin Thin QFN 10mm x 10mm x 0.8mm
(derate 70mW/°C above +70°C) ....................................4000mW
Thermal Resistance θjc........................................................0.4°C/W
Operating Temperature Range................................-40°C to +85°C
Junction Temperature ...........................................................+150°C
Storage Temperature Range .................................-65°C to +150°C
Lead Temperature (soldering, 10s)......................................+300°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
DC ACCURACY
Resolution 12 Bits
Integral Nonlinearity INL fIN = 3MHz ±0.65 ±3.4 LSB
Differential Nonlinearity DNL fIN = 3MHz, no missing codes
over temperature ±0.4 ±0.8 LSB
Offset Error ±0.04 ±0.7 %FSR
Gain Error External reference, VREFIN = 2.048V ±0.4 ±4.7 %FSR
ANALOG INPUTS (INAP, INAN, INBP, INBN)
Differential Input Voltage Range VDIFF Differential or single-ended inputs ±1.024 V
Common-Mode Input Voltage VDD / 2 V
Analog Input Resistance RIN Each input, Figure 3 2.3 kΩ
CPAR Fixed capacitance to ground,
each input, Figure 3 2
Analog Input Capacitance
CSAMPLE Switched capacitance,
each input, Figure 3 4.5
pF
CONVERSION RATE
Maximum Clock Frequency fCLK 96 MHz
Minimum Clock Frequency 5 MHz
Data Latency Figure 5 8 Clock
Cycles
DYNAMIC CHARACTERISTICS (VIN = -1dBFS)
Small-Signal Noise Floor SSNF Input at -35dBFS 70.9 72.2 dBFS
fIN = 3MHz 68.6 70.8
fIN = 48MHz 70.6
fIN = 70MHz 70.1
Signal-to-Noise Ratio SNR
fIN = 175MHz 67.4 69.7
dB
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, AIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA=
-40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN = 3MHz 67.2 70.5
fIN = 48MHz 69.9
fIN = 70MHz 69.7
Signal-to-Noise Plus Distortion SINAD
fIN = 175MHz 64.9 69.1
dB
fIN = 3MHz 71.9 84.5
fIN = 48MHz 81.7
fIN = 70MHz 83.2
Spurious-Free Dynamic Range SFDR
fIN = 175MHz 68.8 78.9
dBc
fIN = 3MHz -82.1 -70
fIN = 48MHz -78.7
fIN = 70MHz -80.2
Total Harmonic Distortion THD
fIN = 175MHz -77.9 -66.7
dBc
fIN = 3MHz -85.7
fIN = 48MHz -82.4
fIN = 70MHz -86.3
Second Harmonic HD2
fIN = 175MHz -78.9
dBc
fIN = 3MHz -89.6
fIN = 48MHz -86.9
fIN = 70MHz -84
Third Harmonic HD3
fIN = 175MHz -88.6
dBc
fIN1 = 69MHz at AIN1 = -7dBFS,
fIN2 = 72MHz at AIN2 = -7dBFS -82
3rd-Order Intermodulation
Distortion IM3
fIN1 = 173MHz at AIN1 = -7dBFS,
fIN2 = 177MHz at AIN2 = -7dBFS -87
dBc
Full-Power Bandwidth FPBW Input at -0.2dBFS, -3dB rolloff 750 MHz
Aperture Delay tAD Figure 5 1.2 ns
Aperture Jitter tAJ < 0.1 psRMS
Output Noise nOUT INAP = INAN = COMA,
INBP = INBN = COMB 0.44 LSBRMS
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, AIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA=
-40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Overdrive Recovery Time ±10% beyond full scale 1 Clock
cycle
INTERCHANNEL CHARACTERISTICS
fINA or fINB = 70MHz at -1dBFS 92
Crosstalk Rejection fINA or fINB = 175MHz at -1dBFS 85 dB
Gain Matching ±0.02 ±0.12 dB
Offset Matching ±0.05 %FSR
INTERNAL REFERENCE (REFOUT)
REFOUT Output Voltage VREFOUT 2.000 2.048 2.080 V
REFOUT Load Regulation -1mA < IREFOUT < +1mA 35 mV/mA
REFOUT Temperature Coefficient TCREF 55 ppm/°C
Short to VDD—sinking 0.24
REFOUT Short-Circuit Current Short to GND—sourcing 2.1 mA
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source;
VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are generated internally)
REFIN Input Voltage VREFIN 2.048 V
REFIN Input Resistance RREFIN > 50 MΩ
COM_ Output Voltage VCOMA
VCOMB VCOM_ = VDD / 2 1.60 1.65 1.70 V
REF_P Output Voltage VREFAP
VREFBP VREF_P = VDD / 2 + (VREFIN x 3/8) 2.418 V
REF_N Output Voltage VREFAN
VREFBN VREF_N = VDD / 2 - (VREFIN x 3/8) 0.882 V
Differential Reference Voltage VREFA
VREFB
VREFA = VREFAP - VREFAN
VREFB = VREFBP - VREFBN 1.450 1.536 1.590 V
Differential Reference
Temperature Coefficient TCREF 30 ppm/°C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are applied
externally, VCOMA = VCOMB = VDD / 2)
REF_P Input Voltage VREFAP
VREFBP VREF_P - VCOM +0.768 V
REF_N Input Voltage VREFAN
VREFBN VREF_N - VCOM -0.768 V
COM_ Input Voltage VCOM VCOM_ = VDD / 2 1.65 V
Differential Reference Voltage VREFA
VREFB VREF_ = VREF_P - VREF_N = VREFIN x 3/4 1.536 V
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, AIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA=
-40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
REF_P Sink Current IREFAP
IREFBP VREF_P = 2.418V 1.2 mA
REF_N Source Current IREFAN
IREFBN VREF_N = 0.882V 0.85 mA
COM_ Sink Current ICOMA
ICOMB VCOM_ = 1.65V 0.85 mA
REF_P, REF_N Capacitance CREF_P,
CREF_N 13 pF
COM_ Capacitance CCOM_ 6pF
CLOCK INPUTS (CLKP, CLKN)
Single-Ended Input High
Threshold VIH DIFFCLK/SECLK = GND, CLKN = GND 0.8 x
VDD V
Single-Ended Input Low
Threshold VIL DIFFCLK/SECLK = GND, CLKN = GND 0.2 x
VDD V
Minimum Differential Clock Input
Voltage Swing DIFFCLK/SECLK = OVDD 0.2 VP-P
Differential Input Common-Mode
Voltage DIFFCLK/SECLK = OVDD VDD / 2 V
CLK_ Input Resistance RCLK Each input, Figure 4 5 kΩ
CLK_ Input Capacitance CCLK Each input 2 pF
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4)
Input High Threshold VIH 0.8 x
OVDD V
Input Low Threshold VIL 0.2 x
OVDD V
OVDD applied to input ±5
Input Leakage Current Input connected to ground ±5 µA
Digital Input Capacitance CDIN 5pF
DIGITAL OUTPUTS (D0A–D11A, D0B–D11B, DORA, DORB, DAV)
D0A–D11A, D0B–D11B, DORA, DORB:
ISINK = 200µA 0.2
Output-Voltage Low VOL
DAV: ISINK = 600µA 0.2
V
D0A–D11A, D0B–D11B, DORA, DORB:
ISOURCE = 200µA
OVDD -
0.2
Output-Voltage High VOH
DAV: ISOURCE = 600µA OVDD -
0.2
V
OVDD applied to input ±5
Tri-State Leakage Current
(Note 2) ILEAK Input connected to ground ±5 µA
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, AIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA=
-40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
D 0A–D 11A, D O RA,
D 0B–D 11B and D ORB Tr i - S tate
O utp ut C ap aci tance ( N ote 2)
COUT 3pF
DAV Tri-State Output
Capacitance (Note 2) CDAV 6pF
POWER REQUIREMENTS
Analog Supply Voltage VDD 3.15 3.30 3.60 V
Digital Output Supply Voltage OVDD 1.70 2.0 VDD V
Normal operating mode
fIN = 175MHz,
single-ended clock
(DIFFCLK/SECLK = GND)
288.5
Normal operating mode
fIN = 175MHz,
differential clock
(DIFFCLK/SECLK = OVDD)
297 322
Analog Supply Current IVDD
Power-down mode (PD = OVDD)
clock idle 0.2
mA
Normal operating mode
fIN = 175MHz,
single-ended clock
(DIFFCLK/SECLK = GND)
952
Normal operating mode
fIN = 175MHz,
differential clock
(DIFFCLK/SECLK = OVDD)
980 1063
Analog Power Dissipation PVDD
Power-down mode (PD = OVDD)
clock idle 0.66
mW
Normal operating mode
fIN = 175MHz, CL ≈ 10pF 24
Digital Output Supply Current IOVDD Power-down mode (PD = OVDD)
clock idle 0.001
mA
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
_______________________________________________________________________________________ 7
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL≈10pF at digital outputs, AIN = -1dBFS (differential),
DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA=
-40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
TIMING CHARACTERISTICS (Figure 5)
Clock Pulse-Width High tCH 5.1 ns
Clock Pulse-Width Low tCL 5.1 ns
Data-Valid Delay tDAV (Notes 3, 4) 3.15 5.8 6.65 ns
Data Setup Time Before Rising
Edge of DAV tSETUP (Notes 3, 4) 3.6 ns
Data Hold Time After Rising Edge
of DAV tHOLD (Notes 3, 4) 3.55 ns
Data Setup Time Before Falling
Edge of Clock tD AT AS E TU P (Notes 3, 4) 2.25 ns
Data Hold Time After Falling
Edge of Clock tDATAHOLD (Notes 3, 4) 3.25 ns
Wake-Up Time from Power-Down tWAKE VREFIN = 2.048V 10 ms
Note 1: Specifications ≥+25°C guaranteed by production test, < +25°C guaranteed by design and characterization.
Note 2: During power-down, D0A–D11A, D0B–D11B, DORA, DORB, and DAV are high impedance.
Note 3: Data outputs settle to VIH or VIL.
Note 4: Guaranteed by design and characterization.
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, AIN = -1dBFS (differen-
tial), DIFFCLK/SECLK = OVDD, PD = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
-120
-60
-80
-100
-40
-20
0
020155 10 2530354045
FFT PLOT (65,536-POINT DATA RECORD)
MAX12529 toc01
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
HD2 HD3
fCLK = 96Msps
fIN = 2.99919MHz
AIN = -1.00dBFS
SNR = 70.9dB
SINAD = 70.5dB
THD = -81.1dBc
SFDR = 85dBc
HD2 = -86.2dBc
HD3 = -91.5dBc
-120
-60
-80
-100
-40
-20
0
020155 10 2530354045
FFT PLOT (65,536-POINT DATA RECORD)
MAX12529 toc02
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
HD2
HD3
fCLK = 96Msps
fIN = 47.89893MHz
AIN = -0.98dBFS
SNR = 70.7dB
SINAD = 69.6dB
THD = -76.1dBc
SFDR = 79.8dBc
HD2 = -79.7dBc
HD3 = -85.2dBc
-120
-60
-80
-100
-40
-20
0
020155 10 2530354045
FFT PLOT (65,536-POINT DATA RECORD)
MAX12529 toc03
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
HD2
HD3
fCLK = 96Msps
fIN = 70.1001MHz
AIN = -0.98dBFS
SNR = 70.2dB
SINAD = 69.8dB
THD = -80.6dBc
SFDR = 84.3dBc
HD2 = -93.2dBc
HD3 = -85.5dBc
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
8 _______________________________________________________________________________________
-1.00
-0.50
-0.75
0
-0.25
0.25
0.50
0.75
1.00
0 1024 1536512 2048 2560 3072 3584 4096
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX12529 toc07
DIGITAL OUTPUT CODE
INL (LSB)
fIN = 2.99908MHz
-1.00
-0.50
-0.75
0
-0.25
0.25
0.50
0.75
1.00
0 1025 1537513 2049 2561 3073 3585 4096
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
MAX12529 toc08
DIGITAL OUTPUT CODE
DNL (LSB)
fIN = 2.99908MHz
50
55
65
60
70
75
0 10050 150 200 250 300 350
SNR, SINAD vs. ANALOG INPUT FREQUENCY
(fCLK = 96MHz, AIN = -1dBFS)
MAX12529 toc09
fIN (MHz)
SNR, SINAD (dB)
SNR
SINAD
50
60
55
70
65
85
80
75
90
0 10050 150 200 250 300 350
-THD, SFDR vs. ANALOG INPUT FREQUENC
Y
(fCLK = 96MHz, AIN = -1dBFS)
MAX12529 toc10
fIN (MHz)
-THD, SFDR (dBc)
SFDR
-THD
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 70MHz)
MAX12529 toc11
AIN (dBFS)
SNR, SINAD (dB)
-5-10-20 -15-50 -45 -40 -35 -30 -25-55
15
20
25
30
35
40
45
50
55
60
65
70
75
10
-60 0
SNR
SINAD
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 70MHz)
MAX12529 toc12
AIN (dBFS)
-THD, SFDR (dBc)
-5-10-20 -15-50 -45 -40 -35 -30 -25-55
30
35
40
45
50
55
60
65
70
75
80
85
90
25
-60 0
SFDR
-THD
-120
-60
-80
-100
-40
-20
0
020155 10 2530354045
FFT PLOT (65,536-POINT DATA RECORD)
MAX12529 toc04
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
HD2 HD3
fCLK = 96Msps
fIN = 175.00049MHz
AIN = -1.00dBFS
SNR = 69.8dB
SINAD = 69.3dB
THD = -78.3dBc
SFDR = 80.3dBc
HD2 = -80.2dBc
HD3 = -89.3dBc
-120
-60
-80
-100
-40
-20
0
020155 10 2530354045
TWO-TONE IMD (65,536-POINT DATA RECORD)
MAX12529 toc05
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 96Msps
fIN1 = 68.50049MHz
AIN1 = -7dBFS
fIN2 = 71.50049MHz
AIN2 = -7.04dBFS
IM3 = -84.5dBc
fIN1
2fIN1 - fIN2
2fIN2 - fIN1
fIN2
-120
-60
-80
-100
-40
-20
0
020155 10 2530354045
TWO-TONE IMD PLOT
(65,536-POINT DATA RECORD)
MAX12529 toc06
ANALOG INPUT FREQUENCY (MHz)
AMPLITUDE (dBFS)
fCLK = 96Msps
fIN1 = 172.50146MHz
AIN1 = -6.97dBFS
fIN2 = 177.50244MHz
AIN2 = -7.01dBFS
IM3 = -84.7dBc
fIN2 fIN1
2fIN1 - fIN2
2fIN2 - fIN1
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, AIN = -1dBFS (differen-
tial), DIFFCLK/SECLK = OVDD, PD = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
_______________________________________________________________________________________ 9
SNR, SINAD vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc13
AIN (dBFS)
SNR, SINAD (dB)
-5-10-20 -15-50 -45 -40 -35 -30 -25-55
15
20
25
30
35
40
45
50
55
60
65
70
75
10
-60 0
SNR
SINAD
-THD, SFDR vs. ANALOG INPUT AMPLITUDE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc14
AIN (dBFS)
-THD, SFDR (dBc)
-5-10-20 -15-50 -45 -40 -35 -30 -25-55
30
35
40
45
50
55
60
65
70
75
80
85
90
25
-60 0
SFDR
-THD
SNR, SINAD vs. CLOCK SPEED
(fIN = 70MHz, AIN = -1dBFS)
MAX12529 toc15
fCLK (MHz)
SNR, SINAD (dB)
90807060504030
55
60
65
70
75
50
20 100
SNR
SINAD
DIV4 = 0VDD
DIV2 = GND
-THD, SFDR vs. CLOCK SPEED
(fIN = 70MHz, AIN = -1dBFS)
MAX12529 toc16
fCLK (MHz)
-THD, SFDR (dBc)
908030 40 50 60 70
65
70
75
80
85
90
95
100
60
20 100
-THD
SFDR
DIV4 = 0VDD
DIV2 = GND
SNR, SINAD vs. CLOCK SPEED
(fIN = 175MHz, AIN = -1dBFS)
MAX12529 toc17
fCLK (MHz)
SNR, SINAD (dB)
90807060504030
55
60
65
70
75
50
20 100
DIV4 = 0VDD
DIV2 = GND
SINAD
SNR
-THD, SFDR vs. CLOCK SPEED
(fIN = 175MHz, AIN = -1dBFS)
MAX12529 toc18
fCLK (MHz)
-THD, SFDR (dBc)
908030 40 50 60 70
55
60
65
70
75
80
85
90
50
20 100
-THD
SFDR
DIV4 = 0VDD
DIV2 = GND
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
MAX12529 toc19
VDD (V)
SNR, SINAD (dB)
3.53.43.33.2
66
68
70
72
74
64
3.1 3.6
SINAD
SNR
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
MAX12529 toc20
VDD (V)
-THD, SFDR (dBc)
3.53.43.33.2
50
60
70
80
90
100
40
3.1 3.6
SFDR
-THD
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc21
VDD (V)
SNR, SINAD (dB)
3.53.43.33.2
62
64
66
68
70
72
60
3.1 3.6
SNR
SINAD
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, AIN = -1dBFS (differen-
tial), DIFFCLK/SECLK = OVDD, PD = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
10 ______________________________________________________________________________________
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc22
VDD (V)
-THD, SFDR (dBc)
3.53.43.33.2
60
65
70
75
80
85
55
3.1 3.6
-THD
SFDR
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
MAX12529 toc23
OVDD (V)
SNR, SINAD (dB)
3.43.23.02.82.62.42.22.01.8
66
68
70
72
74
64
1.6 3.6
SNR
SINAD
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 70MHz)
MAX12529 toc24
OVDD (V)
-THD, SFDR (dBc)
3.43.21.8 2.0 2.2 2.6 2.82.4 3.0
55
60
65
70
75
80
85
90
50
1.6 3.6
SFDR
-THD
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc25
OVDD (V)
SNR, SINAD (dB)
3.43.23.02.82.62.42.22.01.8
55
60
65
70
75
50
1.6 3.6
SNR
SINAD
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc26
OVDD (V)
-THD, SFDR (dBc)
3.43.23.02.82.62.42.22.01.8
60
65
70
75
80
85
90
55
1.6 3.6
SFDR
-THD
100
500
300
900
700
1100
1300
3.1 3.6
PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc27
VDD (V)
PDISS, IVDD (mW, mA)
3.33.2 3.4 3.5
PDISS (ANALOG)
IVDD
0
20
10
40
30
50
60
80
70
90
1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7
PDISS, IOVDD (DIGITAL) vs. DIGITAL SUPPLY VOLTAGE
(fCLK = 96MHz, fIN = 175MHz)
MAX12529 toc28
OVDD (V)
PDISS, IOVDD (mW, mA)
PDISS (DIGITAL)
IOVDD
SNR, SINAD vs. CLOCK DUTY CYCLE
(fIN = 70MHz, AIN = -1dBFS)
MAX12529 toc29
CLOCK DUTY CYCLE (%)
SNR, SINAD (dB)
55
60
65
70
75
50
25 70
30 35 40 45 50 55 60 65
SINGLE-ENDED CLOCK DRIVE
SNR
SINAD
-THD, SFDR vs. CLOCK DUTY CYCLE
(fIN = 70MHz, AIN = -1dBFS)
MAX12529 toc30
CLOCK DUTY CYCLE (%)
-THD, SFDR (dBc)
70
65
75
80
85
90
60
25 70
30 35 40 45 50 55 60 65
SINGLE-ENDED CLOCK DRIVE
SFDR
-THD
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, AIN = -1dBFS (differen-
tial), DIFFCLK/SECLK = OVDD, PD = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 11
SNR, SINAD vs. TEMPERATURE
(fIN = 175MHz, AIN = -1dBFS)
MAX12529 toc31
TEMPERATURE (°C)
SNR, SINAD (dB)
603510-15
62
64
66
68
70
72
60
-40 85
SNR
SINAD
-THD, SFDR vs. TEMPERATURE
(fIN = 175MHz, AIN = -1dBFS)
MAX12529 toc32
TEMPERATURE (°C)
-THD, SFDR (dBc)
603510-15
65
70
75
80
85
90
60
-40 85
SFDR
-THD
GAIN ERROR vs. TEMPERATURE
(VREFIN = 2.048V)
MAX12529 toc33
TEMPERATURE (°C)
GAIN ERROR (%FSR)
603510-15
-2
-1
0
1
2
3
-3
-40 85
OFFSET ERROR vs. TEMPERATURE
MAX12529 toc34
TEMPERATURE (°C)
OFFSET ERROR (%FSR)
603510-15
-0.2
-0.1
0
0.1
0.2
0.3
-0.3
-40 85
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL≈5pF at digital outputs, AIN = -1dBFS (differen-
tial), DIFFCLK/SECLK = OVDD, PD = GND, G/T= GND, fCLK = 96MHz (50% duty cycle), TA= +25°C, unless otherwise noted.)
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
12 ______________________________________________________________________________________
PIN NAME FUNCTION
1, 4, 5, 9,
13, 14, 17 GND Converter Ground. Connect all ground pins and the exposed paddle (EP) together.
2 INAP Channel A Positive Analog Input
3 INAN Channel A Negative Analog Input
6 COMA Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1µF capacitor.
7 REFAP
Channel A Positive Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass
REFAP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
8 REFAN
Channel A Negative Reference I/O. Channel A conversion range is ±2/3 x (VREFAP - VREFAN). Bypass
REFAN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFAP
and REFAN. Place the 1µF REFAP-to-REFAN capacitor as close to the device as possible on the
same side of the PC board.
10 REFBN
Channel B Negative Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass
REFBN with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
11 REFBP
Channel B Positive Reference I/O. Channel B conversion range is ±2/3 x (VREFBP - VREFBN). Bypass
REFBP with a 0.1µF capacitor to GND. Connect a 10µF and a 1µF bypass capacitor between REFBP
and REFBN. Place the 1µF REFBP-to-REFBN capacitor as close to the device as possible on the
same side of the PC board.
12 COMB Channel B Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1µF capacitor.
15 INBN Channel B Negative Analog Input
16 INBP Channel B Positive Analog Input
18 DIFFCLK/
SECLK
Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock
input drives.
DIFFCLK/SECLK = GND: Selects single-ended clock input drive.
DIFFCLK/SECLK = OVDD: Selects differential clock input drive.
19 CLKN
Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the clock signal to CLKP and connect CLKN to GND.
20 CLKP
Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential
clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply
the single-ended clock signal to CLKP and connect CLKN to GND.
21 DIV2 Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details.
22 DIV4 Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details.
23–26, 61,
62, 63 VDD Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel
capacitor combination of ≥ 10µF and 0.1µF. Connect all VDD pins to the same potential.
27, 43, 60 OVDD Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a
parallel capacitor combination of ≥ 10µF and 0.1µF.
28, 29, 45,
46 N.C. No Connection
Pin Description
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 13
PIN NAME FUNCTION
30 D0B Channel B CMOS Digital Output, Bit 0 (LSB)
31 D1B Channel B CMOS Digital Output, Bit 1
32 D2B Channel B CMOS Digital Output, Bit 2
33 D3B Channel B CMOS Digital Output, Bit 3
34 D4B Channel B CMOS Digital Output, Bit 4
35 D5B Channel B CMOS Digital Output, Bit 5
36 D6B Channel B CMOS Digital Output, Bit 6
37 D7B Channel B CMOS Digital Output, Bit 7
38 D8B Channel B CMOS Digital Output, Bit 8
39 D9B Channel B CMOS Digital Output, Bit 9
40 D10B Channel B CMOS Digital Output, Bit 10
41 D11B Channel B CMOS Digital Output, Bit 11 (MSB)
42 DORB
Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog
input voltage is out of range.
DORB = 1: Digital outputs exceed full-scale range.
DORB = 0: Digital outputs are within full-scale range.
44 DAV Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs.
The MAX12529 evaluation kit utilizes DAV to latch data into any external back-end digital logic.
47 D0A Channel A CMOS Digital Output, Bit 0 (LSB)
48 D1A Channel A CMOS Digital Output, Bit 1
49 D2A Channel A CMOS Digital Output, Bit 2
50 D3A Channel A CMOS Digital Output, Bit 3
51 D4A Channel A CMOS Digital Output, Bit 4
52 D5A Channel A CMOS Digital Output, Bit 5
53 D6A Channel A CMOS Digital Output, Bit 6
54 D7A Channel A CMOS Digital Output, Bit 7
55 D8A Channel A CMOS Digital Output, Bit 8
56 D9A Channel A CMOS Digital Output, Bit 9
57 D10A Channel A CMOS Digital Output, Bit 10
58 D11A Channel A CMOS Digital Output, Bit 11 (MSB)
59 DORA
Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog
input voltage is out of range.
DORA = 1: Digital outputs exceed full-scale range.
DORA = 0: Digital outputs are within full-scale range.
64 G/T
Output Format Select Digital Input.
G/T = GND: Two’s-complement output format selected.
G/T = OVDD: Gray-code output format selected.
65 PD
Power-Down Digital Input.
PD = GND: ADCs are fully operational.
PD = OVDD: ADCs are powered down.
Pin Description (continued)
MAX12529
Detailed Description
The MAX12529 uses a 10-stage, fully differential,
pipelined architecture (Figure 1) that allows for high-
speed conversion while minimizing power consump-
tion. Samples taken at the inputs move progressively
through the pipeline stages every half clock cycle.
From input to output the total latency is 8 clock cycles.
Each pipeline converter stage converts its input voltage
to a digital output code. At every stage, except the last,
the error between the input voltage and the digital out-
put code is multiplied and passed along to the next
pipeline stage. Digital error correction compensates for
ADC comparator offsets in each pipeline stage and
ensures no missing codes. Figure 2 shows the
MAX12529 functional diagram.
Dual, 96Msps, 12-Bit, IF/Baseband ADC
14 ______________________________________________________________________________________
PIN NAME FUNCTION
66 SHREF
Shared Reference Digital Input.
SHREF = VDD: Shared reference enabled.
SHREF = GND: Shared reference disabled.
When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP
equals VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to
ensure that VREFAN = VREFBN.
67 REFOUT
Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA.
For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from
REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a ≥ 0.1µF capacitor.
For external reference operation, REFOUT is not required and must be bypassed to GND with a ≥ 0.1µF
capacitor.
68 REFIN
Single-Ended Reference Analog Input. For internal reference and buffered external reference operation,
apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7µF capacitor.
Within its specified operating voltage, REFIN has a > 50MΩ input impedance, and the differential
reference voltage (VREF_P - VREF_N) is generated from REFIN. For unbuffered external reference
operation, connect REFIN to GND. In this mode REF_P, REF_N, and COM_ are high-impedance inputs
that accept the external reference voltages.
—EP
Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified
dynamic performance.
Pin Description (continued)
MAX12529 Σ
+
−
DIGITAL ERROR CORRECTION
FLASH
ADC
x2
DAC
STAGE 2
IN_P
IN_N
STAGE 1 STAGE 9 STAGE 10
END OF PIPELINE
D0_ THROUGH D11_
Figure 1. Pipeline Architecture—Stage Blocks
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 15
INBP
12-BIT
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
CHANNEL A
REFERENCE
SYSTEM
COMA
REFAN
REFAP
OVDD
DAV
OUTPUT
DRIVERS DORA
CLOCK
DIVIDER
DATA
FORMAT
12-BIT
PIPELINE
ADC
DIGITAL
ERROR
CORRECTION
OUTPUT
DRIVERS
DATA
FORMAT
DIV2
DIV4
INBN
D0B TO D11B
DORB
CHANNEL B
REFERENCE
SYSTEM
COMB
REFBN
REFBP
INAP
INAN
CLKP
CLKN
DUTY-CYCLE
EQUALIZER
CLOCK
CLOCK
POWER
CONTROL
AND
BIAS CIRCUITS
PD
VDD
GND
CLOCK
REFIN INTERNAL
REFERENCE
GENERATOR
REFOUT
SHREF
DIFFCLK/SECLK
D0A TO D11A
G/T
MAX12529
Figure 2. Functional Diagram
MAX12529
Analog Inputs and Input Track-and-Hold
(T/H) Amplifier
Figure 3 displays a simplified functional diagram of the
input T/H circuit. This input T/H circuit allows for high
analog input frequencies of 175MHz and beyond and
supports a VDD / 2 common-mode input voltage.
The MAX12529 sampling clock controls the switched-
capacitor input T/H architecture (Figure 3) allowing the
analog input signals to be stored as charge on the
sampling capacitors. These switches are closed (track
mode) when the sampling clock is high and open (hold
mode) when the sampling clock is low (Figure 4). The
analog input signal source must be able to provide the
dynamic currents necessary to charge and discharge
the sampling capacitors. To avoid signal degradation,
these capacitors must be charged to one-half LSB
accuracy within one-half of a clock cycle. The analog
input of the MAX12529 supports differential or single-
ended input drive. For optimum performance with differ-
ential inputs, balance the input impedance of IN_P and
IN_N and set the common-mode voltage to mid-supply
(VDD / 2). The MAX12529 provides the optimum com-
mon-mode voltage of VDD / 2 through the COM output
when operating in internal reference mode and
buffered external reference mode. This COM output
voltage can be used to bias the input network as shown
in Figures 9, 10, and 11.
Reference Output
An internal bandgap reference is the basis for all the
internal voltages and bias currents used in the
MAX12529. The power-down logic input (PD) enables
and disables the reference circuit. REFOUT has approxi-
mately 17kΩto GND when the MAX12529 is powered
down. The reference circuit requires 10ms to power up
and settle to its final value when power is applied to the
MAX12529 or when PD transitions from high to low.
The internal bandgap reference produces a buffered
reference voltage of 2.048V ±1% at the REFOUT pin
with a ±50ppm/°C temperature coefficient. Connect an
external ≥ 0.1µF bypass capacitor from REFOUT to
GND for stability. REFOUT sources up to 1mA and
sinks up to 0.1mA for external circuits with a 35mV/mA
load regulation. Short-circuit protection limits IREFOUT
to a 2.1mA source current when shorted to GND and a
0.24mA sink current when shorted to VDD. Similar to
REFOUT, REFIN should be bypassed with a 4.7µF
capacitor to GND.
Reference Configurations
The MAX12529 full-scale analog input range is ±2/3 x
VREF with a VDD / 2 ±0.5V common-mode input range.
VREF is the voltage difference between REFAP (REFBP)
and REFAN (REFBN). The MAX12529 provides three
modes of reference operation. The voltage at REFIN
(VREFIN) selects the reference operation mode (Table 1).
Connect REFOUT to REFIN either with a direct short or
through a resistive divider to enter internal reference
mode. COM_, REF_P, and REF_N are low-impedance
outputs with VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x
VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.
Dual, 96Msps, 12-Bit, IF/Baseband ADC
16 ______________________________________________________________________________________
VREFIN REFERENCE MODE
35% VREFOUT
to 100%
VREFOUT
Internal Reference Mode.
REFIN is driven by REFOUT either through a
direct short or a resistive divider.
VCOM_ = VDD / 2
VREF_P = VDD / 2 + 3/8 x VREFIN
VREF_N = VDD / 2 - 3/8 x VREFIN
0.7V to 2.3V
Buffered External Reference Mode.
An external 0.7V to 2.3V reference voltage is
applied to REFIN.
VCOM_ = VDD / 2
VREF_P = VDD / 2 + 3/8 x VREFIN
VREF_N = VDD / 2 - 3/8 x VREFIN
< 0.5V
U nb uffer ed E xter nal Refer ence M od e.
RE F_P , RE F_N , and C O M _ ar e d r i ven b y
exter nal r efer ence sour ces. The ful l - scal e
anal og i np ut r ang e i s ± ( V
R E F _P
- V
R E F _N
) x 2/3.
Table 1. Reference Modes
MAX12529
CPAR
2pF
VDD
BOND WIRE
INDUCTANCE
1.5nH
IN_P
SAMPLING
CLOCK
*THE EFFECTIVE RESISTANCE OF THE
SWITCHED SAMPLING CAPACITORS IS:
*CSAMPLE
4.5pF
CPAR
2pF
VDD
BOND WIRE
INDUCTANCE
1.5nH
IN_N
*CSAMPLE
4.5pF
RIN = 1
fCLK x CSAMPLE
Figure 3. Internal T/H Circuit
Bypass REFIN and REFOUT to GND with a 0.1µF capac-
itor. The REFIN input impedance is very large (> 50MΩ).
When driving REFIN through a resistive divider, use
resistances ≥ 10kΩto avoid loading REFOUT.
Buffered external reference mode is virtually identical to
the internal reference mode except that the reference
source is derived from an external reference and not the
MAX12529’s internal bandgap reference. In buffered
external reference mode, apply a stable reference volt-
age source between 0.7V to 2.3V at REFIN. Pins COM_,
REF_P, and REF_N are low-impedance outputs with
VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, and
VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N,
and COM_ each with a 0.1µF capacitor to GND. Bypass
REF_P to REF_N with a 10µF capacitor.
Connect REFIN to GND to enter unbuffered external ref-
erence mode. Connecting REFIN to GND deactivates
the on-chip reference buffers for COM_, REF_P, and
REF_N. With their buffers deactivated, COM_, REF_P,
and REF_N become high-impedance inputs and must
be driven with separate, external reference sources.
Drive VCOM_ to VDD / 2 ±5%, and drive REF_P and
REF_N so VCOM_ = (VREF_P_ + VREF_N_) / 2. The analog
input range is ±(VREF_P_ - VREF_N) x 2/3. Bypass
REF_P, REF_N, and COM_ each with a 0.1µF capacitor
to GND. Bypass REF_P to REF_N with a 10µF capacitor.
For all reference modes, bypass REFOUT with a 0.1µF
and REFIN with a 4.7µF capacitor to GND.
The MAX12529 also features a shared reference mode,
in which the user can achieve better channel-to-chan-
nel matching. When sharing the reference (SHREF =
VDD), externally connect REFAP and REFBP together to
ensure that VREFAP = VREFBP. Similarly, when sharing
the reference, externally connect REFAN to REFBN
together to ensure that VREFAN = VREFBN.
Connect SHREF to GND to disable the shared refer-
ence mode of the MAX12529. In this independent refer-
ence mode, a better channel-to-channel isolation is
achieved.
For detailed circuit suggestions and how to drive the
ADC in buffered/unbuffered external reference mode,
see the Applications Information section.
Clock Duty-Cycle Equalizer
The MAX12529 has an internal clock duty-cycle equaliz-
er, which makes the converter insensitive to the duty
cycle of the signal applied to CLKP and CLKN. The con-
verters allow clock duty-cycle variations from 25% to 75%
without negatively impacting the dynamic performance.
The clock duty-cycle equalizer uses a delay-locked
loop (DLL) to create internal timing signals that are
duty-cycle independent. Due to this DLL, the
MAX12529 requires approximately 100 clock cycles to
acquire and lock to new clock frequencies.
Clock Input and Clock Control Lines
The MAX12529 accepts both differential and single-
ended clock inputs with a wide 25% to 75% input clock
duty cycle. For single-ended clock input operation,
connect DIFFCLK/SECLK and CLKN to GND. Apply an
external single-ended clock signal to CLKP. To reduce
clock jitter, the external single-ended clock must have
sharp falling edges. For differential clock input opera-
tion, connect DIFFCLK/SECLK to OVDD. Apply an
external differential clock signal to CLKP and CLKN.
Consider the clock input as an analog input and route it
away from any other analog inputs and digital signal
lines. CLKP and CLKN enter high impedance when the
MAX12529 is powered down (Figure 4).
Low clock jitter is required for the specified SNR perfor-
mance of the MAX12529. The analog inputs are sam-
pled on the falling (rising) edge of CLKP (CLKN),
requiring this edge to have the lowest possible jitter.
Jitter limits the maximum SNR performance of any ADC
according to the following relationship:
where fIN represents the analog input frequency and tJ
is the total system clock jitter. Clock jitter is especially
critical for undersampling applications. For instance,
assuming that clock jitter is the only noise source, to
obtain the specified 69.5dB of SNR with an input fre-
quency of 175MHz, the system must have less than
0.31ps of clock jitter. However, in reality there are other
noise sources such as thermal noise and quantization
noise that contribute to the system noise requiring the
clock jitter to be less than 0.2ps to obtain the specified
69.5dB of SNR at 175MHz.
Clock-Divider Control Inputs (DIV2, DIV4)
The MAX12529 features three different modes of sam-
pling/clock operation (see Table 2). Pulling both control
lines low, the clock-divider function is disabled and the
converters sample at full clock speed. Pulling DIV4 low
and DIV2 high enables the divide-by-two feature, which
sets the sampling speed to one-half the selected clock
frequency. In divide-by-four mode, the converter sam-
pling speed is set to one-fourth the clock speed of the
MAX12529. Divide-by-four mode is achieved by applying
a high level to DIV4 and a low level to DIV2. The option to
select either one-half or one-fourth of the clock speed for
SNR ft
IN J
log
=× ×× ×
⎛
⎝
⎜⎞
⎠
⎟
20 1
2π
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 17
MAX12529
sampling provides design flexibility, relaxes clock
requirements, and can minimize clock jitter.
System Timing Requirements
Figure 5 shows the timing relationship between the
clock, analog inputs, DAV indicator, DOR_ indicators,
and the resulting output data. The analog input is sam-
pled on the falling (rising) edge of CLKP (CLKN) and
the resulting data appears at the digital outputs 8 clock
cycles later.
The DAV indicator is synchronized with the digital out-
put and optimized for use in latching data into digital
back-end circuitry. Alternatively, digital back-end cir-
cuitry can be latched with the rising edge of the con-
version clock (CLKP - CLKN).
Data-Valid Output
DAV is a single-ended version of the input clock that is
compensated to correct for any input clock duty-cycle
variations. The MAX12529 output data changes on the
falling edge of DAV, and DAV rises once the output data
is valid. The falling edge of DAV is synchronized to have
a 5.8ns delay from the falling edge of the input clock.
Output data at D0A/B–D11A/B and DORA/B are valid
from 3.6ns before the rising edge of DAV to 3.55ns after
the rising edge of DAV.
DAV enters high impedance when the MAX12529 is
powered down (PD = OVDD). DAV enters its high-
impedance state 10ns after the rising edge of PD and
becomes active again 10ns after PD transitions low.
DAV can sink and source 600µA and has three times the
driving capabilities of D0A/B–D11A/B and DORA/B. DAV
is typically used to latch the MAX12529 output data into
an external digital back-end circuit. Keep the capacitive
load on DAV as low as possible (< 15pF) to avoid large
digital currents feeding back into the analog portion of
the MAX12529, thereby degrading its dynamic perfor-
mance. Buffering DAV externally isolates it from heavy
Dual, 96Msps, 12-Bit, IF/Baseband ADC
18 ______________________________________________________________________________________
MAX12529
CLKP
CLKN
VDD
GND
10kΩ
10kΩ
10kΩ
10kΩ
DUTY-CYCLE
EQUALIZER
S1H
S2H
S2L
S1L
SWITCHES S1_ AND S2_ ARE OPEN
DURING POWER-DOWN MAKING
CLKP AND CLKN HIGH IMPEDANCE.
SWITCHES S2_ ARE OPEN IN
SINGLE-ENDED CLOCK MODE.
Figure 4. Simplified Clock Input Circuit
DIV4 DIV2 FUNCTION
00
Clock Divider Disabled
fSAMPLE = fCLK
01
Divide-by-Two Clock Divider
fSAMPLE = fCLK / 2
10
Divide-by-Four Clock Divider
fSAMPLE = fCLK / 4
1 1 Not Allowed
Table 2. Clock-Divider Control Inputs
DAV
NN + 1 N +2
N + 3
N + 4 N + 5
N + 6
N + 7
N + 8
N + 9
tDAV
tSETUP
tAD
N - 1
N - 2
N - 3
tHOLD
tCL tCH
DIFFERENTIAL ANALOG INPUT (IN_P–IN_N)
CLKN
CLKP
(VREF_P - VREF_N) x 2/3
(VREF_N - VREF_P) x 2/3
D0_–D13_
DOR 8.0 CLOCK-CYCLE DATA LATENCY tDATASETUP
tDATAHOLD
N - 2 N N + 1 N + 3 N + 4 N + 5 N + 6 N + 7 N + 8 N + 9
N - 3 N - 1 N + 2
Figure 5. System Timing Diagram
capacitive loads. Refer to the MAX12529 EV kit schemat-
ic for recommendations of how to drive the DAV signal
through an external buffer.
Data Out-of-Range Indicator
The DORA and DORB digital outputs indicate when the
analog input voltage is out of range. When DOR_ is high,
the analog input is out of range. When DOR_ is low, the
analog input is within range. The valid differential input
range is from (VREF_P - VREF_N) x 2/3 to (VREF_N -
VREF_P) x 2/3. Signals outside of this valid differential
range cause DOR_ to assert high as shown in Table 1.
DOR is synchronized with DAV and transitions along
with the output data D11_–D0_. There is an 8 clock-
cycle latency in the DOR function as is with the output
data (Figure 5). DOR_ is high impedance when the
MAX12529 is in power-down (PD = high). DOR_ enters
a high-impedance state within 10ns after the rising edge
of PD and becomes active 10ns after PD’s falling edge.
Digital Output Data and Output Format Selection
The MAX12529 provides two 12-bit, parallel, tri-state
output buses. D0A/B–D11A/B and DORA/B update on
the falling edge of DAV and are valid on the rising edge
of DAV.
The MAX12529 output data format is either Gray code
or two’s complement depending on the logic input G/T.
With G/Thigh, the output data format is Gray code.
With G/Tlow, the output data format is set to two’s com-
plement. See Figure 8 for a binary-to-Gray and Gray-to-
binary code conversion example.
The following equations, Table 3, Figure 6, and Figure 7
define the relationship between the digital output and
the analog input.
Gray Code (G/T= 1):
VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x
(CODE10 - 2048) / 4096
Two’s Complement (G/T= 0):
VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x
CODE10 / 4096
where CODE10 is the decimal equivalent of the digital
output code as shown in Table 3.
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 19
GRAY-CODE OUTPUT CODE
(G/T = 1)
TWO’S-COMPLEMENT OUTPUT CODE
(G/T = 0)
BINARY
D11A–D0A
D11B–D0B
DOR
H EXA D ECIM A L
EQUIVALENT
OF
D11A–D0A
D11B–D0B
DECIMAL
EQUIVALENT
OF
D11A–D0A
D11B–D0B
(CODE10)
BINARY
D11A–D0A
D11B–D0B
DOR
HEXADECIMAL
EQUIVALENT
OF
D11A–D0A
D11B–D0B
DECIMAL
EQUIVALENT
OF
D11A–D0A
D11B–D0B
(CODE10)
VIN_P - VIN_N
VREF
_
P = 2.418V
VREF
_
N = 0.882V
1000 0000 0000 10x800 +4095 0111 1111 1111 10x7FF +2047
> +1.0235V
(DATA OUT OF
RANGE)
1000 0000 0000 0 0x800 +4095 0111 1111 1111 0 0x7FF +2047 +1.0235V
1000 0000 0001 0 0x801 +4094 0111 1111 1110 0 0x7FE +2046 +1.0230V
1100 0000 0011 0 0xC03 +2050 0000 0000 0010 0 0x002 +2 +0.0010V
1100 0000 0001 0 0xC01 +2049 0000 0000 0001 0 0x001 +1 +0.0005V
1100 0000 0000 0 0xC00 +2048 0000 0000 0000 0 0x000 0 +0.0000V
0100 0000 0000 0 0x400 +2047 1111 1111 1111 0 0xFFF -1 -0.0005V
0100 0000 0001 0 0x401 +2046 1111 1111 1110 0 0xFFE -2 -0.0010V
0000 0000 0001 0 0x001 +1 1000 0000 0001 0 0x801 -2047 -1.0235V
0000 0000 0000 0 0x000 0 1000 0000 0000 0 0x800 -2048 -1.0240V
0000 0000 0000 10x000 0 1000 0000 0000 10x800 -2048
< -1.0240V
(DATA OUT OF
RANGE)
Table 3. Output Codes vs. Input Voltage
MAX12529
The digital outputs D0A/B–D11A/B are high impedance
when the MAX12529 is in power-down (PD = 1) mode.
D0A/B–D11A/B enter this state 10ns after the rising
edge of PD and become active again 10ns after PD
transitions low.
Keep the capacitive load on the MAX12529 digital out-
puts D0A/B–D11A/B as low as possible (< 15pF) to
avoid large digital currents feeding back into the ana-
log portion of the MAX12529 and degrading its dynam-
ic performance. Adding external digital buffers on the
digital outputs helps isolate the MAX12529 from heavy
capacitive loads. To improve the dynamic performance
of the MAX12529, add 220Ωresistors in series with the
digital outputs close to the MAX12529. Refer to the
MAX12529 EV kit schematic for guidelines of how to
drive the digital outputs through 220Ωseries resistors
and external digital output buffers.
Power-Down Input
The MAX12529 has two power modes that are con-
trolled with a power-down digital input (PD). With PD
low, the MAX12529 is in its normal operating mode.
With PD high, the MAX12529 is in power-down mode.
The power-down mode allows the MAX12529 to effi-
ciently use power by transitioning to a low-power state
when conversions are not required. Additionally, the
MAX12529 parallel output bus goes high-impedance in
power-down mode, allowing other devices on the bus
to be accessed.
In power-down mode all internal circuits are off, the
analog supply current reduces to less than 100µA, and
the digital supply current reduces to less than 1µA. The
following list shows the state of the analog inputs and
digital outputs in power-down mode:
1) INAP/B and INAN/B analog inputs are disconnect-
ed from the internal input amplifier (Figure 3).
2) REFOUT has approximately 17kΩto GND.
3) REFAP/B, COMA/B, and REFAN/B enter a high-
impedance state with respect to VDD and GND, but
there is an internal 4kΩresistor between REFAP/B
and COMA/B, as well as an internal 4kΩresistor
between REFAN/B and COMA/B.
4) D0A–D11A, D0B–D11B, DORA, and DORB enter a
high-impedance state.
5) DAV enters a high-impedance state.
6) CLKP and CLKN clock inputs enter a high-imped-
ance state (Figure 4).
The wake-up time from power-down mode is dominated
by the time required to charge the capacitors at REF_P,
REF_N, and COM. In internal reference mode and
buffered external reference mode the wake-up time is
typically 10ms. When operating in the unbuffered exter-
nal reference mode the wake-up time is dependent on
the external reference drivers.
Dual, 96Msps, 12-Bit, IF/Baseband ADC
20 ______________________________________________________________________________________
DIFFERENTIAL INPUT VOLTAGE (LSB)
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
-2045 +2047+2045-1 0 +1-2047
0x800
0x801
0x802
0x803
0x7FF
0x7FE
0x7FD
0xFFF
0x000
0x001
2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN)
1 LSB = 4/3 x (VREFP - VREFN) / 4096
Figure 6. Two’s-Complement Transfer Function (G/
T
= 0)
DIFFERENTIAL INPUT VOLTAGE (LSB)
GRAY OUTPUT CODE (LSB)
-2045 +2047+2045-1 0 +1-2047
0x000
0x001
0x003
0x002
0x800
0x801
0x803
0xC00
0xC00
0xC01
2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN)
1 LSB = 4/3 x (VREFP - VREFN) / 4096
Figure 7. Gray-Code Transfer Function (G/
T
= 1)
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 21
BINARY-TO-GRAY CODE CONVERSION
1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME
AS THE MOST SIGNIFICANT BINARY BIT.
0111 0100 1100 BINARY
GRAY CODE0
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING
TO THE FOLLOWING EQUATION:
D11 D7 D3 D0
GRAYX = BINARYX +BINARYX + 1
BIT POSITION
0 111 0100 1100 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
GRAY10 = BINARY10 BINARY11
GRAY10 = 1 0
GRAY10 = 1
1
3) REPEAT STEP 2 UNTIL COMPLETE:
01 11 0100 1100 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
GRAY9 = BINARY9BINARY10
GRAY9 = 1 1
GRAY9 = 0
10
4) THE FINAL GRAY-CODE CONVERSION IS:
0111 0100 1100 BINARY
GRAY CODE0
D11 D7 D3 D0 BIT POSITION
1001101 1010
GRAY-TO-BINARY CODE CONVERSION
1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE
MOST SIGNIFICANT GRAY-CODE BIT.
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO
THE FOLLOWING EQUATION:
D11 D7 D3 D0
BINARYX = BINARYX+1
BIT POSITION
BINARY10 = BINARY11 GRAY10
BINARY10 = 0 1
BINARY10 = 1
3) REPEAT STEP 2 UNTIL COMPLETE:
4) THE FINAL BINARY CONVERSION IS:
0100 1110 1010
BINARY
GRAY CODE
D11 D7 D3 D0 BIT POSITION
0 BINARY
GRAY CODE0100 11 011010
BINARY9 = BINARY10 GRAY9
BINARY9 = 1 0
BINARY9 = 1
GRAYX
0 100 1110 1010
BINARY
GRAY CODE
0
D11 D7 D3 D0 BIT POSITION
1
01 00 1110 1010
BINARY
GRAY CODE
0
D11 D7 D3 D0 BIT POSITION
11
0111 0100 1100
AB Y=AB
00
01
10
11
0
1
1
0
EXCLUSIVE OR TRUTH TABLE
WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+WHERE IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH
TABLE BELOW) AND X IS THE BIT POSITION:
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY
CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT
FORMAT OF THE MAX12529 IS TWO'S-COMPLEMENT BINARY,
HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE
MUST BE INVERTED TO REFLECT TRUE OFFSET BINARY FORMAT.
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion
MAX12529
Applications Information
Using Transformer Coupling
In general, the MAX12529 provides better SFDR and
THD with fully differential input signals than single-
ended input drive, especially for input frequencies
above 125MHz. In differential input mode, even-order
harmonics are lower as both inputs are balanced, and
each of the ADC inputs only requires half the signal
swing compared to single-ended input mode.
An RF transformer (Figure 9) provides an excellent
solution to convert a single-ended input source signal
to a fully differential signal, required by the MAX12529
for optimum performance. Connecting the center tap of
the transformer to COM provides a VDD / 2 DC level
shift to the input. Although a 1:1 transformer is shown, a
step-up transformer can be selected to reduce the
drive requirements. A reduced signal swing from the
input driver, such as an op amp, can also improve the
overall distortion. The configuration of Figure 9 is good
for frequencies up to Nyquist (fCLK / 2).
The circuit of Figure 10 converts a single-ended input
signal to fully differential just as Figure 9. However,
Figure 10 utilizes an additional transformer to improve
the common-mode rejection allowing high-frequency
signals beyond the Nyquist frequency. A set of 75Ω
Dual, 96Msps, 12-Bit, IF/Baseband ADC
22 ______________________________________________________________________________________
MAX12529
1
5
3
6
2
4
N.C. N.C.
VIN
0.1μF
T1
MINI-CIRCUITS
ADT1-1WT
24.9Ω
24.9Ω
49.9Ω
0.5%
49.9Ω
0.5%
5.6pF
5.6pF
0.1μF
IN_P
COM_
IN_N
Figure 9. Transformer-Coupled Input Drive for Input Frequencies
Up to Nyquist
1
5
3
6
2
4
N.C.
VIN
0.1μF
T1
MINI-CIRCUITS
ADT1-1WT
IN_P
COM_
IN_N
*0Ω RESISTORS CAN BE REPLACED WITH
LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH.
N.C.
1
5
3
6
2
4
N.C.
T2
MINI-CIRCUITS
ADT1-1WT
N.C.
75Ω
0.5%
75Ω
0.5%
110Ω
0.5%
110Ω
0.5%
0.1μF
0Ω*
0Ω*
MAX12529
CIN
RIN
CIN
RIN
Figure 10. Transformer-Coupled Input Drive for Input Frequencies Beyond Nyquist
MAX12529
MAX4108
0.1μF
0.1μF
0Ω
5.6pF
IN_P
COM_
IN_N
100Ω
100Ω
VIN
24.9Ω
24.9Ω
5.6pF
Figure 11. Single-Ended, AC-Coupled Input Drive
and 110Ωtermination resistors provide an equivalent
50Ωtermination to the signal source. The second set of
termination resistors connects to COM_ providing the
correct input common-mode voltage. Two 0Ωresistors
in series with the analog inputs allow high IF input fre-
quencies. These 0Ωresistors can be replaced with low-
value resistors to limit the input bandwidth.
The input network in Figure 10 can be modified to
enhance the frequency-range specific AC performance
of the MAX12529 by simply replacing the input capaci-
tance with a series network of resistor (RIN) and capacitor
(CIN). Table 4 displays a selection of resistors and capac-
itors that are recommended to help improve the already
excellent performance of this ADC for specific applica-
tions requiring only a certain range of input frequencies.
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input
application. The MAX4108 provides high speed, high
bandwidth, low noise, and low distortion to maintain the
input signal integrity.
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________________________ 23
MAX4230
0.1μF
1μF
5
2
3
4
1
1
5
2
REFIN
VDD
GND
0.1μF
47Ω
3.3V
2.048V
16.2kΩ
REFOUT
0.1μF
REF_P
REF_N
COM_
0.1μF
0.1μF
0.1μF
2.2μF
0.1μF
3.3V
1.47kΩ
300μF
6V
NOTE: ONE FRONT-END REFERENCE CIRCUIT IS
CAPABLE OF SOURCING UP TO 15mA AND
SINKING UP TO 30mA OF OUTPUT CURRENT.
10μF0.1μF
REFIN
VDD
GND
REFOUT
0.1μF
REF_P
REF_N
COM_
0.1μF
0.1μF
0.1μF
2.2μF
0.1μF
10μF0.1μF
MAX12529
MAX6029
(EUK21)
MAX12529
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
MAX12529
Buffered External Reference Drives
Multiple ADCs
The buffered external reference mode allows for more
control over the MAX12529 reference voltage and
allows multiple converters to use a common reference.
The REFIN input impedance is > 50MΩ.
Figure 12 shows the MAX6029 precision 2.048V bandgap
reference used as a common reference for multiple con-
verters. The 2.048V output of the MAX6029 passes
through a single-pole 10Hz LP filter to the MAX4230.
The MAX4250 buffers the 2.048V reference and pro-
vides additional 10Hz LP filtering before its output is
applied to the REFIN input of the MAX12529.
Dual, 96Msps, 12-Bit, IF/Baseband ADC
24 ______________________________________________________________________________________
MAX12529
MAX4230
MAX6029
(EUK30)
0.1μF1
5
2
0.47μF10μF
6V
47Ω
1.47kΩ
2.413V
3V
4
1
3330μF
6V
MAX4230
10μF
6V
47Ω
1.47kΩ
1.647V
4
1
3330μF
6V
MAX4230
10μF
6V
47Ω
1.47kΩ
0.880V
4
1
3330μF
6V
REF_P
REF_N
COM_
VDD
GND REFIN
3.3V
3.3V
REFOUT
0.1μF
0.1μF
0.1μF
10μF
0.1μF
2.2μF
0.1μF
20kΩ
1%
20kΩ
1%
20kΩ
1%
20kΩ
1%
20kΩ
1%
52.3kΩ
1%
52.3kΩ
1%
0.1μF
MAX12529
REF_P
REF_N
COM_
VDD
GND REFIN
REFOUT
0.1μF
0.1μF
0.1μF
10μF
0.1μF
2.2μF
0.1μF
0.1μF
Figure 13. External Unbuffered Reference Driving Multiple ADCs
INPUT
FREQUENCY
RANGE
CIN
COMPONENT
VALUES (pF)
RIN
COMPONENT
VALUES (Ω)
< 10MHz 12 to 22 0
10MHz to 125MHz 12 50
> 125MHz 5.6 0
Table 4. Component Selection to
Enhance the Frequency-Range Specific
AC Performance
Unbuffered External Reference Drives
Multiple ADCs
The unbuffered external reference mode allows for pre-
cise control over the MAX12529 reference and allows
multiple converters to use a common reference.
Connecting REFIN to GND disables the internal reference,
allowing REF_P, REF_N, and COM_ to be driven directly
by a set of external reference sources.
Figure 13 uses a MAX6029 precision 3.000V bandgap
reference as a common reference for multiple convert-
ers. A seven-component resistive divider chain follows
the MAX6029 voltage reference. The 0.47µF capacitor
along this chain creates a 10Hz LP filter. Three
MAX4230 amplifiers buffer taps along this resistor chain
providing 2.413V, 1.647V, and 0.880V to the MAX12529
REF_P, REF_N, and COM_ reference inputs. The feed-
back around the MAX4230 op amps provides addition-
al 10Hz LP filtering. Reference voltages 2.413V and
0.880V set the full-scale analog input range for the con-
verter to ±1.022V (±[VREF_P - VREF_N] x 2/3).
Note that one single power supply for all active circuit
components removes any concern regarding power-
supply sequencing when powering up or down.
Grounding, Bypassing, and
Board Layout
The MAX12529 requires high-speed board layout
design techniques. Refer to the MAX12527/MAX12528/
MAX12529/MAX12557/MAX12558/MAX12559 EV kit
data sheet for a board layout reference. Locate all
bypass capacitors as close to the device as possible,
preferably on the same side as the ADC, using surface-
mount devices for minimum inductance. Bypass VDD to
GND with a 220µF ceramic capacitor in parallel with at
least one 10µF, one 4.7µF, and one 0.1µF ceramic
capacitor. Bypass OVDD to GND with a 220µF ceramic
capacitor in parallel with at least one 10µF, one 4.7µF,
and one 0.1µF ceramic capacitor. High-frequency
bypassing/decoupling capacitors should be located as
close as possible to the converter supply pins.
Multilayer boards with ample ground and power planes
produce the highest level of signal integrity. All grounds
and the exposed backside paddle of the MAX12529
package (package code: T6800-2) must be connected
to the same ground plane. The MAX12529 relies on the
exposed backside paddle connection for a low-induc-
tance ground connection. Isolate the ground plane
from any noisy digital system ground planes such as a
DSP or output buffer ground.
Route high-speed digital signal traces away from the
sensitive analog traces. Keep all signal lines short and
free of 90°turns.
Ensure that the differential, analog input network layout
is symmetric and that all parasitic components are
balanced equally. Refer to the MAX12529 EV kit data
sheet for an example of symmetric input layout.
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer
function from a straight line. For the MAX12529, this
straight line is between the endpoints of the transfer
function, once offset and gain errors have been nulli-
fied. INL deviations are measured at every step of the
transfer function and the worst-case deviation is report-
ed in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and
the ideal value of 1 LSB. A DNL error specification of
less than 1 LSB guarantees no missing codes and a
monotonic transfer function. For the MAX12529, DNL
deviations are measured at every step of the transfer
function and the worst-case deviation is reported in the
Electrical Characteristics table.
Offset Error
Offset error is a figure of merit that indicates how well
the actual transfer function matches the ideal transfer
function at a single point. Ideally, the midscale
MAX12529 transition occurs at 0.5 LSB above mid-
scale. The offset error is the amount of deviation
between the measured midscale transition point and
the ideal midscale transition point.
Gain Error
Gain error is a figure of merit that indicates how well the
slope of the actual transfer function matches the slope of
the ideal transfer function. The slope of the actual trans-
fer function is measured between two data points: posi-
tive full scale and negative full scale. Ideally, the positive
full-scale MAX12529 transition occurs at 1.5 LSBs below
positive full scale, and the negative full-scale transition
occurs at 0.5 LSB above negative full scale. The gain
error is the difference of the measured transition points
minus the difference of the ideal transition points.
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the
Nyquist band for small-signal inputs. The DC offset is
excluded from this noise calculation. For this converter,
a small signal is defined as a single tone with an ampli-
tude of -35dBFS. This parameter captures the thermal
and quantization noise characteristics of the data con-
verter and can be used to help calculate the overall
noise figure of a digital receiver signal path.
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 25
MAX12529
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital
samples, the theoretical maximum SNR is the ratio of
the full-scale analog input (RMS value) to the RMS
quantization error (residual error). The ideal, theoretical
minimum analog-to-digital noise is caused by quantiza-
tion error only and results directly from the ADC’s reso-
lution (N bits):
SNR[max] = 6.02 ×N + 1.76
In reality, there are other noise sources besides quanti-
zation noise: thermal noise, reference noise, clock jitter,
etc. SNR is computed by taking the ratio of the RMS
signal to the RMS noise. RMS noise includes all spec-
tral components to the Nyquist frequency excluding the
fundamental, the first six harmonics (HD2 through
HD7), and the DC offset.
SNR = 20 x log (SIGNALRMS / NOISERMS)
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS sig-
nal to the RMS noise plus distortion. RMS noise plus
distortion includes all spectral components to the
Nyquist frequency excluding the fundamental and the
DC offset.
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmon-
ics of the input signal to the fundamental itself. This is
expressed as:
where V1is the fundamental amplitude, and V2through
V7are the amplitudes of the 2nd- through 7th-order
harmonics (HD2 through HD7).
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS
amplitude of the fundamental (maximum signal compo-
nent) to the RMS value of the next largest spurious
component, excluding DC offset.
3rd-Order Intermodulation (IM3)
IM3 is the power of the 3rd-order intermodulation product
relative to the input power of either of the two input tones
fIN1 and fIN2. The individual input tone power levels are
set to -7dBFS for the MAX12529. The 3rd-order inter-
modulation products are 2 x fIN1 - fIN2 and 2 x fIN2 - fIN1.
Aperture Jitter
Figure 14 shows the aperture jitter (tAJ), which is the
sample-to-sample variation in the aperture delay.
Aperture Delay
Aperture delay (tAD) is the time defined between the
rising edge of the sampling clock and the instant when
an actual sample is taken (Figure 14).
Full-Power Bandwidth
A large -0.2dBFS analog input signal is applied to an
ADC and the input frequency is swept up to the point
where the amplitude of the digitized conversion result
has decreased by -3dB. This point is defined as full-
power input bandwidth frequency.
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to thermal
plus quantization noise and is an indication of the con-
verter’s overall noise performance.
No fundamental input tone is used to test for nOUT.
IN_P, IN_N, and COM_ are connected together and
1024k data points are collected. nOUT is computed by
taking the RMS value of the collected data points after
the mean is removed.
Overdrive Recovery Time
Overdrive recovery time is the time required for the
ADC to recover from an input transient that exceeds the
full-scale limits. The MAX12529 specifies overdrive
recovery time using an input transient that exceeds the
full-scale limits by ±10%. The MAX12529 requires one
clock cycle to recover from an overdrive condition.
Crosstalk
Crosstalk is coupling onto one channel being driven by
a (-1dBFS) signal when the adjacent interfering channel
is driven by a full-scale signal. Measurement includes
all spurs resulting from both direct coupling and mixing
components.
THD VVVVVV
V
log
=× +++++
⎛
⎝
⎜
⎜
⎞
⎠
⎟
⎟
20 223242526272
1
Dual, 96Msps, 12-Bit, IF/Baseband ADC
26 ______________________________________________________________________________________
tAD
tAJ
T/H TRACKHOLD HOLD
CLKN
CLKP
ANALOG
INPUT
SAMPLED
DATA
Figure 14. T/H Aperture Timing
Gain Matching
Gain matching is a figure of merit that indicates how
well the gains between the two channels are matched
to each other. The same input signal is applied to both
channels and the maximum deviation in gain is report-
ed (typically in dB) as gain matching.
Offset Matching
Like gain matching, offset matching is a figure of merit
that indicates how well the offsets between the two chan-
nels are matched to each other. The same input signal is
applied to both channels and the maximum deviation in
offset is reported (typically in %FSR) as offset matching.
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
______________________________________________________________________________________ 27
4142434445 3738394046
21
22
23
24
25
26
27
28
29
30
VDD
INAP
N.C.
THIN QFN
TOP VIEW
N.C.
DAV
OVDD
DORB
D11B
D10B
D9B
D8B
D7B
3536
D6B
D5B
GND
INAN
COMA
GND
REFAN
REFAP
REFBN
GND
COMB
REFBP
GND
GND
INBN
D0B
N.C.
N.C.
OVDD
VDD
VDD
VDD
VDD
DIV4
DIV2
18
19
20 CLKP
CLKN
EXPOSED PADDLE (GND)
VDD
OVDD
DORA
D11A
D10A
REFOUT
SHREF
PD
VDD
D9A
D8A
D7A
D6A
31 D1B
D5A
47
D0A
484950
D3A
D2A
D1A
51
D4A
654321098711211 151413
INBP
GND
1716
32
33 D3B
D2B
34 D4B
62
61
60
59
58
57
56
55
54
53
67
66
65
64
63
52
REFIN 68
MAX12529
GND
DIFFCLK/SECLK
G/T
Pin Configuration
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
28 ______________________________________________________________________________________
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
68L QFN THIN.EPS
PACKAGE OUTLINE
21-0142
2
1
E
68L THIN QFN, 10x10x0.8mm
MAX12529
Dual, 96Msps, 12-Bit, IF/Baseband ADC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 29
© 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE
21-0142
2
2
E
68L THIN QFN, 10x10x0.8mm
Boblet
Revision History
Pages changed at Rev 1: 1–4, 7–11, 28, 29
