 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
DDesigned for TIA/EIA-485, TIA/EIA-422,
and ISO 8482 Applications
DSignaling Rates up to 30 Mbps
DPropagation Delay Times <11 ns
DLow Standby Power Consumption
1.5 mA Max
DOutput ESD Protection 12 kV
DDriver Positive- and Negative-Current
Limiting
DPower-Up and Power-Down Glitch-Free for
Live Insertion Applications
DThermal Shutdown Protection
DIndustry Standard Pin-Out, Compatible
With SN75172, AM26LS31, DS96172,
LTC486, and MAX3045
description
The SN65LBC172A and SN75LBC172A are quadruple differential line drivers with 3-state outputs, designed
for TIA/EIA-485 (RS-485), TIA/EIA-422 (RS-422), and ISO 8482 applications.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
G
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
G
3Z
3Y
3A
N PACKAGE
(TOP VIEW)
logic diagram (positive logic)
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A 1
7
9
15
G
G12
4
2
3
6
5
10
11
14
13
4Z
4Y
3Z
3Y
2Z
2Y
1Z
1Y
4A
3A
2A
1A 1
9
11
19
G
G15
5
2
4
8
6
12
14
18
16
logic diagram (positive logic)
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1A
1Y
1Z
G
2Z
2Y
2A
GND
VCC
4A
4Y
4Z
G
3Z
3Y
3A
16-DW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1A
1Y
NC
1Z
G
2Z
NC
2Y
2A
GND
VCC
4A
4Y
NC
4Z
G
3Z
NC
3Y
3A
20-DW PACKAGE
(TOP VIEW)
Copyright 2008 − 2003, Texas Instruments Incorporated
  !"# $ %&'# "$  (&)*%"# +"#',
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LinBiCMOS is a trademark of Texas Instruments.
The signaling rate of a line is the number of voltage transitions that are made per second expressed in the units bps (bits per second).
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
These devices are optimized for balanced multipoint bus transmission at signalling rates up to 30 million bits
per second. The transmission media may be printed-circuit board traces, backplanes, or cables. The ultimate
rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise
coupling to the environment.
Each driver features current limiting and thermal-shutdown circuitry making it suitable for high-speed mulitpoint
data transmission applications in noisy environments. These devices are designed using LinBiCMOSt,
facilitating low power consumption and robustness.
The G and G inputs provide driver enable control using either positive or negative logic. When disabled or
powered off, the driver outputs present a high-impedance to the bus for reduced system loading.
The SN75LBC172A is characterized for operation over the temperature range of 0°C to 70°C. The
SN65LBC172A is characterized over the temperature range from –40°C to 85°C.
AVAILABLE OPTIONS
PACKAGE
TA16-PIN PLASTIC
SMALL OUTLINE
(JEDEC MS-013)
20-PIN PLASTIC
SMALL OUTLINE
(JEDEC MS-013)
16-PIN PLASTIC
THROUGH-HOLE
(JEDEC MS-001)
0°C to 70°C
SN75LBC172A16DW SN75LBC172ADW SN75LBC172AN
0°C to 70°CMarked as 75LBC172A
−40°C to 85°C
SN65LBC172A16DW SN65LBC172ADW SN65LBC172AN
−40°C to 85°CMarked as 65LBC172A
Add R suffix for taped and reeled version.
FUNCTION TABLE
(EACH DRIVER)
INPUT ENABLES OUTPUTS
A G G Y Z
L H X L H
L X L L H
H H X H L
H X L H L
OPEN H X H L
OPEN X L H L
H OPEN X H L
L OPEN X L H
X L H Z Z
X L OPEN Z Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
equivalent input and output schematic diagrams
VCC
A, G, or G Input
1 k
9 V
Input
100 k
VCC
Output
16 V
Y or Z Output
16 V
20 V
17 V
16 V
16 V
absolute maximum ratings
Supply voltage range, VCC (see Note 1) −0.3 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO, at any bus (steady state) −10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO, at any bus (transient pulse through 100 , see Figu re 8) −30 V to 30 V. . . . . . . . . . .
Input voltage range, VI, at any A, G, or G terminal −0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Electrostatic discharge: Human body model (see Note 2) Y, Z, and GND 12 kV. . . . . . . . . . . . . . . . . . . . .
All pins 5 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Charged-device model (see Note 3) All pins 1 kV. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg −65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values, except differential I/O bus voltages, are with respect to GND.
2. Tested in accordance with JEDEC standard 22, Test Method A114−A.
3. Tested in accordance with JEDEC standard 22, Test Method C101.
DISSIPATION RATING TABLE
PACKAGE JEDEC
BOARD
MODEL
TA 25°C
POWER RATING DERATING FACTOR
ABOVE TA = 25°CTA = 70°C
POWER RATING TA = 85°C
POWER RATING
16-PIN DW
Low K 1200 mW 9.6 mW/°C769 mW 625 mW
16-PIN DW High K 2240 mW 17.9 mW/°C1434 mW 1165 mW
20-PIN DW
Low K 1483 mW 11.86 mW/°C949 mW 771 mW
20-PIN DW High K 2753 mW 22 mW/°C1762 mW 1432 mW
16-PIN N Low K 1150 mW 9.2 mW/°C736 mW 598 mW
This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow.
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
Voltage at any bus terminal Y, Z −7 12 V
High-level input voltage, VIH
A, G, G
2 VCC
V
Low-level input voltage, VIL A, G, G 0 0.8 V
Output current −60 60 mA
Operating free-air temperature, TA
SN75LBC172A 0 70
°C
Operating free-air temperature, TASN65LBC172A −40 85 °C
electrical characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
VIK Input clamp voltage II = −18 mA −1.5 −0.77 V
VOOpen-circuit output voltage Y or Z, No load 0 VCC V
Steady-state differential output voltage
No load (open circuit) 3 VCC
VOD(SS)
Steady-state differential output voltage
1
1.6
2.5
V
V
OD(SS)
Steady-state differential output voltage
magnitude
R
= 54 , see Figure 1 1 1.6 2.5 V
VOD(SS)
magnitude
1
1.6
2.5
V
magnitude
With common-mode loading, see Figure 2 1 1.6 2.5
VOD(SS) Change in steady-state differential output
voltage between logic states See Figure 1 −0.1 0.1 V
VOC(SS) Steady-state common-mode output
voltage See Figure 3 2 2.4 2.8 V
VOC(SS) Change in steady-state common-mode
output voltage between logic states See Figure 3 −0.02 0.02 V
IIInput current A, G, G −50 50 µA
IOS
Short-circuit output current
VI = 0 V
−200
200
mA
IOS Short-circuit output current
VTEST = −7 V to 12 V,
VI = VCC −20
0
200 mA
IOZ High-impedance-state output current
V
TEST
= −7 V to 12 V,
See Figure 7
G at 0 V, G at VCC −50 50
A
IO(OFF) Output current with power off
See Figure 7
VCC = 0 V −10 10 µA
ICC
Supply current
VI = 0 V or VCC,
All drivers enabled 23
mA
ICC Supply current
VI = 0 V or VCC,
No load All drivers disabled 1.5 mA
All typical values are at VCC = 5 V and 25°C.
The minimum VOD may not fully comply with TIA/EIA-485-A at operating temperatures below 0°C. System designers should take the possibly
of lower output signal into account in determining the maximum signal transmission distance.
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
switching characteristics over recommended operating conditions
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low-to-high level output 5.5 8 11 ns
tPHL Propagation delay time, high-to-low level output 5.5 8 11 ns
trDifferential output voltage rise time
R = 54 , C = 50 pF,
3 7.5 11 ns
tfDifferential output voltage fall time RL = 54 , CL = 50 pF,
see Figure 4
3 7.5 11 ns
tsk(p) Pulse skew |tPLH – tPHL|
see Figure 4
0.6 2 ns
tsk(o) Output skew2 ns
tsk(pp) Part-to-part skew3 ns
tPZH Propagation delay time, high-impedance-to-high-level output See Figure 5 25 ns
tPHZ Propagation delay time, high-level-output-to-high impedance 25 ns
tPZL Propagation delay time, high-impedance-to-low-level output See Figure 6 30 ns
tPLZ Propagation delay time, low-level-output-to-high impedance 20 ns
Output skew (tsk(o)) is the magnitude of the time delay difference between the outputs of a single device with all of the inputs connected together.
Part-to-part skew (tsk(pp)) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when
both devices operate with the same input signals, the same supply voltages, at the same temperature, and have identical packages and test
circuits.
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
GND
VI
AIOZ
IOY
Y
ZVOD VOY
II
VOZ
54
Figure 1. Test Circuit, VOD Without Common-Mode Loading
375
VTEST = −7 V to 12 V
Y
ZVOD
Input 60 375
VI
A
VTEST
Figure 2. Test Circuit, VOD With Common-Mode Loading
Y
ZVOC
27
A
50
Signal
GeneratorCL = 50 pF
27
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50
Includes probe and jig capacitance
Figure 3. VOC Test Circuit
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Y
ZVOD
RL = 54
A
50
Signal
Generator
CL = 50 pF
90%
Output
0 V
10%
tf
−1.5 V
1.5 V
tr
Input 0 V
3 V
tPHL
1.5 V
tPLH
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50
Includes probe and jig capacitance
Figure 4. Output Switching Test Circuit and Waveforms
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
S1
A
50
Signal
Generator
Output
2.3 V
Input 0 V
3 V
1.5 V
tPZH 0.5 V
0 V
VOH
tPHZ
0 V or 3 V w
Input
G
G
RL = 110 CL = 50 pF
Output
3 V
Y
Z
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50
Includes probe and jig capacitance
§3-V if testing Y output, 0 V if testing Z output
Figure 5. Enable Timing Test Circuit and Waveforms, tPZH and tPHZ
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
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POST OFFICE BOX 655303 DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
S1
A
50
Signal
Generator
Output
2.3 V
Input 0 V
3 V
1.5 V
tPZL
0.5 V
5 V
VOL
tPLZ
0 V or 3 V w
Input
G
G
RL = 110
CL = 50 pF
Output
3 V
5 V
Y
Z
PRR = 1 MHz, 50% duty cycle, tr < 6 ns, tf < 6 ns, ZO = 50
Includes probe and jig capacitance
§3-V if testing Y output, 0 V if testing Z output
Figure 6. Enable Timing Test Circuit and Waveforms, tPZL and tPLZ
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Voltage Source
VTEST = −7 V to 12 V
Slew Rate 1.2 V/µs
VI
VTEST
IO
Y
Z
Figure 7. Test Circuit, Short-Circuit Output Current
VTEST
Pulse Generator
15 µs Duration,
1% Duty Cycle
100
Y
Z
−VTEST
15 µs1.5 ms
0 V
Figure 8. Test Circuit and Waveform, Transient Over-Voltage
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
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TYPICAL CHARACTERISTICS
Figure 9
0
0.5
1
1.5
2
2.5
3
3.5
4
0 20406080100
VCC = 5.25 V VCC = 5 V
VCC = 4.75 V
− Differential Output Voltage − V
DIFFERENTIAL OUTPUT VOLTAGE
vs
OUTPUT CURRENT
IO − Output Current − mA
VOD
Figure 10
0
0.5
1
1.5
2
2.5
−60 −40 −20 0 20 40 60 80 100
VCC = 5.25 V
VCC = 5 V
VCC = 4.75 V
− Differential Output Voltage − V
DIFFERENTIAL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
VOD
TA − Free-Air Temperature − °C
Figure 11
5
5.5
6
6.5
7
7.5
8
8.5
−40 −20 0 20 40 60 80
VCC = 5.25 V
VCC = 4.75 V
Propigation Delay Time − ns
PROPAGATION DELAY TIME
vs
TEMPERATURE
T − Temperature − °C
Figure 12
128
130
132
134
136
138
140
142
144
1 10 100
− Supply Current (Four Channels) − mA
Signaling Rate − Mbps
SUPPLY CURRENT (FOUR CHANNELS)
vs
SIGNALING RATE
ICC
RL = 54
CL = 50 pF
(Each Channel)
 
    
SLLS447C − O CTOBER 2000 − REVISED AUGUST 2008
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
RL = 54
CL = 50 pF
Figure 13. Eye Pattern, Pseudorandom Data at 30 Mbps
APPLICATION INFORMATION
TMS320F243
DSP
(Controller)
SPISIMO
SN65LBC172A SN65LBC175A TMS320F241
DSP
(Embedded
Application)
SPISIMO
IOPA1
SPISTE SPISTE
IOPA0
(Handshake
/Status)
SPICLK
IOPA0
IOPA1
(Enable)
SPICLK
SPISOMI SPISOMI
IOPA2
Figure 14. Typical Application Circuit, DSP-to-DSP Link via Serial Peripheral Interface
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN65LBC172A16DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172A16DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172A16DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172A16DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172ADW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172ADWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN65LBC172AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
SN65LBC172ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
SN75LBC172A16DW ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172A16DWG4 ACTIVE SOIC DW 16 40 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172A16DWR ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172A16DWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172ADW ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172ADWG4 ACTIVE SOIC DW 20 25 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172ADWR ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172ADWRG4 ACTIVE SOIC DW 20 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN75LBC172AN ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
SN75LBC172ANE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPD N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2008
Addendum-Page 1
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 10-Jul-2008
Addendum-Page 2
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
SN65LBC172A16DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
SN65LBC172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
SN75LBC172A16DWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
SN75LBC172ADWR SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN65LBC172A16DWR SOIC DW 16 2000 367.0 367.0 38.0
SN65LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0
SN75LBC172A16DWR SOIC DW 16 2000 367.0 367.0 38.0
SN75LBC172ADWR SOIC DW 20 2000 367.0 367.0 45.0
PACKAGE MATERIALS INFORMATION
www.ti.com 14-Jul-2012
Pack Materials-Page 2
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