Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 10 1Publication Order Number:
MC10EP016/D
MC10EP016, MC100EP016
3.3V / 5VECL 8-Bit
Synchronous Binary
Up Counter
The MC10/100EP016 is a high–speed synchronous, presettable,
cascadeable 8–bit binary counter. Architecture and operation are the
same as the MC10E016 in the ECLinPS family.
The counter features internal feedback to TC gated by the TCLD
(Terminal Count Load) pin. When TCLD is LOW (or left open, in
which case it is pulled LOW by the internal pulldowns), the TC
feedback is disabled, and counting proceeds continuously, with TC
going LOW to indicate an all–one state. When TCLD is HIGH, the TC
feedback causes the counter to automatically reload upon TC = LOW,
thus functioning as a programmable counter. The Qn outputs do not
need to be terminated for the count function to operate properly. To
minimize noise and power, unused Q outputs should be left
unterminated.
COUT and COUT provide differential outputs from a single,
non–cascaded counter or divider application. COUT and COUT
should not be used in cascade configuration. Only TC should be used
for a counter or divider cascade chain output.
A differential clock input has also been added to improve
performance.
The 100 Series contains temperature compensation.
•500 ps Typical Propagation Delay
•PECL Mode Operating Range: VCC = 3.0 V to 5.5 V
with VEE = 0 V
•NECL Mode Operating Range: VCC = 0 V
with VEE = –3.0 V to –5.5 V
•Open Input Default State
•Safety Clamp on Inputs
•Internal TC Feedback (Gated)
•Addition of COUT and COUT
•8–Bit
•Differential Clock Input
•VBB Output
•Fully Synchronous Counting and TC Generation
•Asynchronous Master Reset
Device Package Shipping
ORDERING INFORMATION
MC10EP016FA LQFP–32 250 Units/Tray
MC10EP016FAR2 LQFP–32 2000 Tape & Reel
LQFP–32
FA SUFFIX
CASE 873A
MARKING
DIAGRAM*
MCxxx
AWLYYWW
1
32
xxx = 10 OR 100
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
*For additional information, see Application Note
AND8002/D
EP016
MC100EP016FA LQFP–32 250 Units/Tray
MC100EP016FAR2 LQFP–32 2000 Tape & Reel
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VEE
25
26
27
28
29
30
31
32
15
14
13
12
11
10
9
12345678
24 23 22 21 20 19 18 17
16
MC10EP016
MC100EP016
COUT
COUT
TC
VCC
P7
P6
P5
VCC
Q2
Q1
Q0
VEE
MR
CE
PE
VCC
TCLDQ7Q6Q5Q4VCC
P4P3P2P1P0CLKVBB CLK
Figure 1. 32–Lead LQFP Pinout (Top View)
Q3
Warning: All VCC and VEE pins must be externally connected to
Power Supply to guarantee proper operation.
PIN DESCRIPTION
PIN
P0–P7*
Q0–Q7 ECL Data Outputs
FUNCTION
ECL Parallel Data (Preset) Inputs
CE*
PE* ECL Parallel Load Enable Control Input
ECL Count Enable Control Input
MR*
CLK*, CLK* ECL Differential Clock
ECL Master Reset
TC
TCLD* ECL TC–Load Control Input
ECL Terminal Count Output
COUT, COUT
VCC Positive Supply
ECL Differential Output
VEE
VBB Reference Voltage Output
Negative Supply
* Pins will default LOW when left open.
ZZ = Clock Pulse (High–to–Low)
Z = Clock Pulse (Low–to–High)
CE FUNCTION
X
L
L
H
X
X
Load Parallel (Pn to Qn)
Continuous Count
Count; Load Parallel on TC = LOW
Hold
Masters Respond, Slaves Hold
Reset (Qn : = LOW, TC : = HIGH)
FUNCTION TABLES
PE
L
H
H
H
X
X
TCLD
X
L
H
X
X
X
MR
L
L
L
L
L
H
CLK
Z
Z
Z
Z
ZZ
X
FUNCTION TABLE
Function PE CE MR TCLD CLK P7–P4 P3 P2 P1 P0 Q7–Q4 Q3 Q2 Q1 Q0 TC COUT COUT
Load Count L
H
H
H
H
X
L
L
L
L
L
L
L
L
L
X
L
L
L
L
Z
Z
Z
Z
Z
H
X
X
X
X
H
X
X
X
X
H
X
X
X
X
L
X
X
X
X
L
X
X
X
X
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
L
L
H
H
L
L
H
L
H
L
H
H
H
L
H
H
H
H
L
H
L
L
L
H
L
Load Hold L
H
H
X
H
H
L
L
L
X
X
X
Z
Z
Z
H
X
X
H
X
X
H
X
X
L
X
X
L
X
X
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
L
L
L
Load on
Terminal
Count
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
Z
Z
Z
Z
Z
Z
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
L
L
H
H
H
H
H
H
L
L
H
H
H
H
L
H
L
H
L
H
L
H
H
L
H
H
H
H
H
L
H
H
H
L
L
H
L
L
L
Reset X X H X X X X X X X L L L L L H H L
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Figure 2. 8-BIT Binary Counter Logic Diagram
Note that this diagram is provided for understanding of logic operation only.
It should not be used for propagation delays as many gate functions are achieved internally without incurring a full gate delay.
P1
SLAVEMASTER
5TC
Q1
Q0
P7
Q6
Q5Q4
Q3Q2
Q1
CEQ0
BIT 1
CE
Q0
Q0M
Q0M
PE
TCLD
CE
P0
MR
CLK
BIT 7
BITS 2–6
Q7
CLK
COUT
COUT
BIT 0
VBB
VEE
ATTRIBUTES
Characteristics Value
Internal Input Pulldown Resistor 75 k
Internal Input Pullup Resistor N/A
ESD Protection Human Body Model
Machine Model
Charged Device Model
> 2 kV
> 100 V
> 2 kV
Moisture Sensitivity (Note 1) Level 2
Flammability Rating Oxygen Index: 28 to 34 UL 94 V–0 @ 0.125 in
Transistor Count 897 Devices
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
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MAXIMUM RATINGS (Note 2)
Symbol Parameter Condition 1 Condition 2 Rating Units
VCC PECL Mode Power Supply VEE = 0 V 6 V
VEE NECL Mode Power Supply VCC = 0 V –6 V
VIPECL Mode Input Volta
g
e VEE = 0 V VI V
CC
6 V
VI
PECL
Mode
In ut
Voltage
NECL Mode Input Voltage
VEE
=
0
V
VCC = 0 V
VI
VCC
VI VEE
6
–6
V
V
Iout Output Current Continuous
Surge 50
100 mA
mA
IBB VBB Sink/Source ± 0.5 mA
TA Operating Temperature Range –40 to +85 °C
Tstg Storage Temperature Range –65 to +150 °C
θJA Thermal Resistance (Junction–to–Ambient) 0 LFPM
500 LFPM 32 LQFP
32 LQFP 80
55 °C/W
°C/W
θJC Thermal Resistance (Junction–to–Case) std bd 32 LQFP 12 to 17 °C/W
Tsol Wave Solder <2 to 3 sec @ 248°C 265 °C
2. Maximum Ratings are those values beyond which device damage may occur .
10EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 3)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 120 160 200 120 160 200 120 160 200 mA
VOH Output HIGH Voltage (Note 4) 2165 2290 2415 2230 2355 2480 2290 2415 2540 mV
VOL Output LOW Voltage (Note 4) 1365 1490 1615 1430 1555 1680 1490 1615 1740 mV
VIH Input HIGH Voltage (Single–Ended) 2090 2415 2155 2480 2215 2540 mV
VIL Input LOW Voltage (Single–Ended) 1365 1690 1460 1755 1490 1815 mV
VBB Output Voltage Reference 1790 1890 1990 1855 1955 2055 1915 2015 2115 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 5) 2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
3. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
4. All loading with 50 to VCC–2.0 volts.
5. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
10EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 6)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current (Note 7) 120 160 200 120 160 200 120 160 200 mA
VOH Output HIGH Voltage (Note 8) 3865 3990 4115 3930 4055 4180 3990 4115 4240 mV
VOL Output LOW Voltage (Note 8) 3065 3190 3315 3130 3255 3380 3190 3315 3440 mV
VIH Input HIGH Voltage (Single–Ended) 3790 4115 3855 4180 3915 4240 mV
VIL Input LOW Voltage (Single–Ended) 3065 3390 3130 3455 3190 3515 mV
VBB Output Voltage Reference 3490 3590 3690 3555 3655 3755 3615 3715 3815 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 9) 2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
6. Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
7. Required 500 lfpm air flow when using +5 V power supply. For (V CC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V.
8. All loading with 50 to VCC–2.0 volts.
9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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10EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 10)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current (Note 11) 120 160 200 120 160 200 120 160 200 mA
VOH Output HIGH Voltage (Note 12) –1135 –1010 –885 –1070 –945 –820 –1010 –885 –760 mV
VOL Output LOW Voltage (Note 12) –1935 –1810 –1685 –1870 –1745 –1620 –1810 –1685 –1560 mV
VIH Input HIGH Voltage (Single–Ended) –1210 –885 –1145 –820 –1085 –760 mV
VIL Input LOW Voltage (Single–Ended) –1935 –1610 –1870 –1545 –1810 –1485 mV
VBB Output Voltage Reference –1510 –1410 –1310 –1445 –1345 –1245 –1385 –1285 –1185 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 13) VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
10.Input and output parameters vary 1:1 with VCC.
11.Required 500 lfpm air flow when using –5 V power supply. For (V CC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V.
12.All loading with 50 to VCC–2.0 volts.
13.VIHCMR min varies 1:1 with V EE, VIHCMR max varies 1:1 with V CC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 14)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current 120 160 200 120 160 200 120 160 200 mA
VOH Output HIGH Voltage (Note 15) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mV
VOL Output LOW Voltage (Note 15) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mV
VIH Input HIGH Voltage (Single–Ended) 2075 2420 2075 2420 2075 2420 mV
VIL Input LOW Voltage (Single–Ended) 1355 1675 1355 1675 1355 1675 mV
VBB Output Voltage Reference 1775 1875 1975 1775 1875 1975 1775 1875 1975 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 16) 2.0 3.3 2.0 3.3 2.0 3.3 V
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
14.Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to –2.2 V.
15.All loading with 50 to VCC–2.0 volts.
16.VIHCMR min varies 1:1 with V EE, VIHCMR max varies 1:1 with V CC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
100EP DC CHARACTERISTICS, PECL VCC = 5.0 V, VEE = 0 V (Note 17)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current (Note 18) 120 160 200 120 160 200 120 160 200 mA
VOH Output HIGH Voltage (Note 19) 3855 3980 4105 3855 3980 4105 3855 3980 4105 mV
VOL Output LOW Voltage (Note 19) 3055 3180 3305 3055 3180 3305 3055 3180 3305 mV
VIH Input HIGH Voltage (Single–Ended) 3775 4120 3775 4120 3775 4120 mV
VIL Input LOW Voltage (Single–Ended) 3055 3375 3055 3375 3055 3375 mV
VBB Output Voltage Reference 3475 3575 3675 3475 3575 3675 3475 3575 3675 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 20) 2.0 5.0 2.0 5.0 2.0 5.0 V
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
17.Input and output parameters vary 1:1 with VCC. VEE can vary +2.0 V to –0.5 V.
18.Required 500 lfpm air flow when using +5 V power supply. For (V CC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V.
19.All loading with 50 to VCC–2.0 volts.
20.VIHCMR min varies 1:1 with V EE, VIHCMR max varies 1:1 with V CC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
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100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = –5.5 V to –3.0 V (Note 21)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
IEE Power Supply Current (Note 22) 120 160 200 120 160 200 120 160 200 mA
VOH Output HIGH Voltage (Note 23) –1145 –1020 –895 –1145 –1020 –895 –1145 –1020 –895 mV
VOL Output LOW Voltage (Note 23) –1945 –1820 –1695 –1945 –1820 –1695 –1945 –1820 –1695 mV
VIH Input HIGH Voltage (Single–Ended) –1225 –880 –1225 –880 –1225 –880 mV
VIL Input LOW Voltage (Single–Ended) –1945 –1625 –1945 –1625 –1945 –1625 mV
VBB Output Voltage Reference –1525 –1425 –1325 –1525 –1425 –1325 –1525 –1425 –1325 mV
VIHCMR Input HIGH Voltage Common Mode
Range (Differential) (Note 24) VEE+2.0 0.0 VEE+2.0 0.0 VEE+2.0 0.0 V
IIH Input HIGH Current 150 150 150 µA
IIL Input LOW Current 0.5 0.5 0.5 µA
NOTE: EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The
circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintained.
21.Input and output parameters vary 1:1 with VCC.
22.Required 500 lfpm air flow when using –5 V power supply. For (V CC – VEE) >3.3 V, 5 to 10 in line with VEE required for maximum thermal
protection at elevated temperatures. Recommend VCC–VEE operation at 3.3 V.
23.All loading with 50 to VCC–2.0 volts.
24.VIHCMR min varies 1:1 with V EE, VIHCMR max varies 1:1 with V CC. The VIHCMR range is referenced to the most positive side of the differential
input signal.
AC CHARACTERISTICS VEE = –3.0 V to –5.5 V; VCC = 0 V or VCC = 3.0 V to 5.5 V; VEE = 0 V (Note 25)
–40°C 25°C 85°C
Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit
fCOUNT Maximum Frequency Q, TC
COUT/COUT > 1
> 800 > 1
> 800 > 1
> 800 GHz
MHz
tPLH
tPHL Propagation Delay (10) CLK to Q
(10) MR to Q
(10) CLK to TC
(10) MR to TC
(10) CLK to COUT
(10) MR to COUT
(100) CLK to Q
(100) MR to Q
(100) CLK to TC
(100) MR to TC
(100) CLK to COUT
(100) MR to COUT
300
300
350
250
400
300
350
400
350
400
400
450
460
400
420
350
470
400
500
550
500
550
550
600
600
500
550
450
650
550
650
700
650
700
750
800
350
400
400
350
450
400
400
450
400
450
450
500
500
500
500
450
550
500
550
590
550
590
600
640
650
600
600
550
700
650
700
750
700
750
800
850
400
450
400
400
450
450
480
520
480
520
530
570
560
580
550
510
600
560
630
670
630
670
680
720
700
700
700
600
800
700
780
820
780
820
880
920
ps
tSSetup Time Pn
CE
PE
TCLD
100
500
500
500
–50
300
300
300
100
500
500
500
–50
300
300
300
100
500
500
500
–50
300
300
300
ps
tHHold Time Pn
CE
PE
TCLD
100
500
500
500
–50
300
300
300
100
500
500
500
–50
300
300
300
100
500
500
500
–50
300
300
300
ps
tJITTER Clock Random Jitter
(RMS >1000 Waveforms) 2.6 8.5 2.5 8.0 2.5 8.0 ps
tRR Reset Recovery Time 200 80 200 80 200 80 ps
tPW Minimum Pulse Width CLK, MR 550 300 550 300 550 300 ps
tr
tfOutput Rise/Fall Times
20% – 80% 120 210 320 120 220 320 150 250 450 ps
25.Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 to VCC–2.0 V.
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Applications Information
Cascading Multiple EP016 Devices
For applications which call for larger than 8-bit counters
multiple EP016s can be tied together to achieve very wide
bit width counters. The active low terminal count (TC)
output and count enable input (CE) greatly facilitate the
cascading of EP016 devices. Two EP016s can be cascaded
without the need for external gating, however for counters
wider than 16 bits external OR gates are necessary for
cascade implementations.
Figure 3 below pictorially illustrates the cascading of 4
EP016s to build a 32-bit high frequency counter. Note the
EP01 gates used to OR the terminal count outputs of the
lower order EP016s to control the counting operation of the
higher order bits. When the terminal count of the preceding
device (or devices) goes low (the counter reaches an all 1s
state) the more significant EP016 is set in its count mode and
will count one binary digit upon the next positive clock
transition. In addition, the preceding devices will also count
one bit thus sending their terminal count outputs back to a
high state disabling the count operation of the more
significant counters and placing them back into hold modes.
Therefore, for an EP016 in the chain to count, all of the lower
order terminal count outputs must be in the low state. The bit
width of the counter can be increased or decreased by simply
adding or subtracting EP016 devices from Figure 3 and
maintaining the logic pattern illustrated in the same figure.
The maximum frequency of operation for a cascaded
counter c hain i s s et b y t he p ropagation d elay o f t he T C o utput,
the necessary setup t ime of t he CE i nput, a nd t he p ropagation
delay through the O R g ate c ontrolling i t ( for 1 6–bit c ounters
the limitation is only the TC propagation delay and the CE
setup time). Figure 3 shows EP01 gates used to control the
count e nable i nputs, h owever, if t he f requency o f o peration i s
slow e nough, a LVECL O R g ate c an b e u s ed. U sing t he w orst
case guarantees for these parameters.
Figure 3. 32-Bit Cascaded EP016 Counter
CLK
P0 to P7
TC
CLK
P0 to P7
TC
CLK
EP01 P0 to P7 P0 to P7
MSB
EP016
Q0 to Q7Q0 to Q7 Q0 to Q7
EP016
Q0 to Q7
EP016
PE
CE
LSB
EP016
PECE
LOAD
LO
CLK CLK
CLK
EP01
TC
CLK
PE
CE
CLK TC
CLK
PE
CE
CLK
Note that this assumes the trace delay between the TC
outputs and the CE inputs are negligible. If this is not the
case estimates of these delays need to be added to the
calculations.
Programmable Divider
The EP016 has been designed with a control pin which
makes it ideal for use as an 8 -bit p rogrammable d ivider. The
TCLD p in ( load o n t erminal count) w hen a sserted r eloads t he
data present at the parallel input pin (Pn’s) upon reaching
terminal count (an all 1s state on the outputs). Because this
feedback is built internal to the chip, the programmable
division operation w ill run a t v ery nearly t he same f requency
as the maximum counting frequency of the device. Figure 4
below illustrates the input conditions necessary for utilizing
the E P016 a s a p rogrammable d ivider s et up t o d ivide b y 113.
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Applications Information (continued)
H
L
H
HLLLHHHH
TC
PE
CE
TCLD
CLK
P7 P6 P4 P3 P2 P1 P0P5
Q7 Q6 Q4 Q3 Q2 Q1 Q0Q5
Figure 4. Mod 2 to 256 Programmable Divider
CLK
COUT
COUT
To determine what value to load into the device to
accomplish the desired division, the designer simply
subtracts the binary equivalent of the desired divide ratio
from the binary value for 256. As an example for a divide
ratio of 113:
Pn’s = 256 – 113 = 8F16 = 1000 1111
where:
P0 = LSB and P7 = MSB
Forcing this input condition as per the setup in Figure 4
will result in the waveforms of Figure 5. Note that the TC
output is used as the divide output and the pulse duration is
equal to a full clock period. For even divide ratios, twice the
desired divide ratio can be loaded into the EP016 and the TC
output can feed the clock input of a toggle flip flop to create
a signal divided as desired with a 50% duty cycle.
Table 1. Preset Values for Various Divide Ratios
Divide Preset Data Inputs
de
Ratio P7 P6 P5 P4 P3 P2 P1 P0
2 H H H H H H H L
3 H HHHHHLH
4 H HHHHHLL
5 H HHHHLHH
• • •••••••
• • •••••••
112 HLLHLLLL
113 HLLLHHHH
114 HLLLHHHL
• • •••••••
• • •••••••
254 L LLLLLHL
255 L LLLLLLH
256 L L L L L L L L
A single EP016 can be used to divide by any ratio from 2
to 256 inclusive. If divide ratios of greater than 256 are
needed m ultiple EP016s can be cascaded in a manner similar
to that already discussed. When EP016s are cascaded to
build lar ger dividers the TCLD pin will no longer provide a
means for loading on terminal count. Because one does not
want to reload the counters until all of the devices in the
chain have reached terminal count, external gating of the TC
pins must be used for multiple EP016 divider chains.
•••
PE
•••
•••
CLK
TC
Load
DIVIDE BY 113
Load1001 0000 1001 0001 1111 1100 1111 1101 1111 1110 1111 1111
Figure 5. Divide by 113 EP016 Programmable Divider Waveforms
MC10EP016, MC100EP016
http://onsemi.com
9
Applications Information (continued)
EP01
Q0 to Q7
P0 to P7
CLK TC
PECE
Figure 6. 32-Bit Cascaded EP016 Programmable Divider
LO
CLK
CLK
CLK
MSB
LSB
EP016
EP01 EP01
Q0 to Q7 Q0 to Q7 Q0 to Q7 Q0 to Q7
P0 to P7 P0 to P7 P0 to P7
EP016 EP016 EP016
CLK TC
PECE
CLK CLK TC
PECE
CLK CLK TC
PECE
CLK
Figure 6 shows a typical block diagram of a 32-bit divider
chain. Once again to maximize the frequency of operation
EP01 OR gates were used. For lower frequency applications
a slower OR gate could replace the EP01. Note that for a
16-bit divider the OR function feeding the PE (program
enable) input CANNOT be replaced by a wire OR tie as the
TC output of the least significant EP016 must also feed the
CE input of the most significant EP016. If the two TC
outputs were OR tied the cascaded count operation would
not operate properly. Because in the cascaded form the PE
feedback is external and requires external gating, the
maximum frequency of operation will be significantly less
than the same operation in a single device.
Maximizing EP016 Count Frequency
The EP016 device produces 9 fast transitioning
single–ended outputs, thus VCC noise can become
significant in situations where all of the outputs switch
simultaneously in the same direction. This VCC noise can
negatively impact the maximum frequency of operation of
the device. Since the device does not need to have the Q
outputs terminated to count properly, i t is recommended that
if the outputs are not going to be used in the rest of the system
they should be left unterminated. In addition, if only a subset
of the Q outputs are used in the system only those outputs
should be terminated. Not terminating the unused outputs
will not only cut down the VCC noise generated but will also
save in total system power dissipation. Following these
guidelines will allow designers to either be more aggressive
in their designs or provide them with an extra margin to the
published data book specifications.
MC10EP016, MC100EP016
http://onsemi.com
10
Figure 7. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020 – Termination of ECL Logic Devices.)
Driver
Device Receiver
Device
QD
50
50
Q D
VTT
VTT = VCC – 2.0 V
Resource Reference of Application Notes
AN1404 –ECLinPS Circuit Performance at Non–Standard VIH Levels
AN1405 –ECL Clock Distribution Techniques
AN1406 –Designing with PECL (ECL at +5.0 V)
AN1504 –Metastability and the ECLinPS Family
AN1568 –Interfacing Between LVDS and ECL
AN1650 –Using Wire–OR Ties in ECLinPS Designs
AN1672 –The ECL Translator Guide
AND8001 –Odd Number Counters Design
AND8002 –Marking and Date Codes
AND8009 –ECLinPS Plus Spice I/O Model Kit
AND8020 –Termination of ECL Logic Devices
For an updated list of Application Notes, please see our website at http://onsemi.com.
MC10EP016, MC100EP016
http://onsemi.com
11
PACKAGE DIMENSIONS
ÉÉ
ÉÉ
ÉÉ
ÉÉ
DETAIL Y
A
S1
VB
1
8
9
17
25
32
AE
AE
P
DETAIL Y
BASE
N
J
DF
METAL
SECTION AE–AE
G
SEATING
PLANE
R
Q
WK
X
0.250 (0.010)
GAUGE PLANE
E
C
H
DETAIL AD
DIM
A
MIN MAX MIN MAX
INCHES
7.000 BSC 0.276 BSC
MILLIMETERS
B7.000 BSC 0.276 BSC
C1.400 1.600 0.055 0.063
D0.300 0.450 0.012 0.018
E1.350 1.450 0.053 0.057
F0.300 0.400 0.012 0.016
G0.800 BSC 0.031 BSC
H0.050 0.150 0.002 0.006
J0.090 0.200 0.004 0.008
K0.500 0.700 0.020 0.028
M12 REF 12 REF
N0.090 0.160 0.004 0.006
P0.400 BSC 0.016 BSC
Q1 5 1 5
R0.150 0.250 0.006 0.010
V9.000 BSC 0.354 BSC
V1 4.500 BSC 0.177 BSC


DETAIL AD
A1
B1 V1
4X
S
4X
B1 3.500 BSC 0.138 BSC
A1 3.500 BSC 0.138 BSC
S9.000 BSC 0.354 BSC
S1 4.500 BSC 0.177 BSC
W0.200 REF 0.008 REF
X1.000 REF 0.039 REF
9
–T–
–Z–
–U–
T-U0.20 (0.008) Z
AC
T-U0.20 (0.008) ZAB
0.10 (0.004) AC
–AC–
–AB–
M
8X
–T–, –U–, –Z–
T-U
M
0.20 (0.008) ZAC
LQFP
FA SUFFIX
32–LEAD PLASTIC PACKAGE
CASE 873A–02
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED
AT DATUM PLANE -AB-.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE -AC-.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE -AB-.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
MC10EP016, MC100EP016
http://onsemi.com
12
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