DRAM MODULE M364C040(8)4BT0-C Buffered 4Mx64 DIMM (4Mx16 base) Revision 0.1 June 1998 DRAM MODULE M364C040(8)4BT0-C Revision History Version 0.0 (Sept. 1997) * Removed two AC parameters tCACP(access time from CAS) and tAAP (access time from col. addr.) in AC CHARACTERISTICS. * Changed the parameter tCAC(access time from CAS) from 18ns to 20ns @ -5 in AC CHARACTERISTICS. Version 0.1 (June 1998) * The 3rd generation of 64M DRAM components are applied for this module. DRAM MODULE M364C040(8)4BT0-C M364C040(8)4BT0-C Fast Page Mode 4M x 64 DRAM DIMM Using 4Mx16, 4K & 8K Refresh, 5V GENERAL DESCRIPTION FEATURES The Samsung M364C040(8)4BT0-C is a 4Mx64bits Dynamic RAM high density memory module. The Samsung M364C040(8)4BT0-C consists of four CMOS 4Mx16bits DRAMs in TSOP-II 400mil packages and two 16 bits driver IC in TSSOP package mounted on a 168-pin glass-epoxy substrate. A 0.1 or 0.22uF decoupling capacitor is mounted on the printed circuit board for each DRAM. The M364C040(8)4BT0C is a Dual In-line Memory Module and is intended for mounting into 168 pin edge connector sockets. * Part Identification PERFORMANCE RANGE Speed tRAC tCAC tRC tPC -C50 50ns 18ns 90ns 35ns -C60 60ns 20ns 110ns 40ns Part number PKG Ref. M364C0404BT0-C TSOPll 4K M364C0484BT0-C TSOPll 8K * * * * * * * * 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 *DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 DQ16 *DQ17 VSS RSVD RSVD VCC W0 CAS0 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front CAS2 RAS0 OE0 VSS A0 A2 A4 A6 A8 A10 A12 VCC RFU RFU VSS OE2 RAS2 CAS4 CAS6 W2 VCC RSVD RSVD DQ18 DQ19 VSS DQ20 DQ21 Pin ROR Ref. 4K/64ms 4K/64ms 8K/64ms Fast Page Mode Operation CAS-before-RAS Refresh capability RAS-only and Hidden refresh capability TTL compatible inputs and outputs Single 5V10% power supply JEDEC standard pinout & Buffered PDpin Buffered input except RAS and DQ PCB : Height(1000mil), single sided component PIN CONFIGURATIONS Pin Front Pin CBR Ref. PIN NAMES Front Pin Back Pin Back Pin Back 57 DQ22 85 VSS 113 CAS3 141 58 DQ23 86 DQ36 114 *RAS1 142 59 87 DQ37 115 RFU 143 VCC 60 DQ24 88 DQ38 116 VSS 144 61 RFU 89 DQ39 117 A1 145 62 RFU 90 VCC 118 A3 146 63 RFU 91 DQ40 119 A5 147 64 RFU 92 DQ41 120 A7 148 65 DQ25 93 DQ42 121 A9 149 66 *DQ26 94 DQ43 122 A11 150 67 DQ27 95 *DQ44 123 *A13 151 68 VSS 124 VCC 152 96 VSS 69 DQ28 97 DQ45 125 RFU 153 70 DQ29 98 DQ46 126 B0 154 71 DQ30 99 DQ47 127 VSS 155 72 DQ31 100 DQ48 128 RFU 156 73 VCC 101 DQ49 129 *RAS3 157 74 DQ32 102 VCC 130 CAS5 158 75 DQ33 103 DQ50 131 CAS7 159 76 DQ34 104 DQ51 132 PDE 160 77 *DQ35 105 DQ52 133 VCC 161 78 VSS 106 *DQ53 134 RSVD 162 79 PD1 107 VSS 135 RSVD 163 80 PD3 108 RSVD 136 DQ54 164 81 PD5 109 RSVD 137 DQ55 165 82 PD7 110 VCC 138 VSS 166 83 ID0 111 RFU 139 DQ56 167 84 VCC 112 CAS1 140 DQ57 168 NOTE : A12 is used for only M364C0484BT0-C (8K Ref.) DQ58 DQ59 VCC DQ60 RFU RFU RFU RFU DQ61 *DQ62 DQ63 VSS DQ64 DQ65 DQ66 DQ67 VCC DQ68 DQ69 DQ70 *DQ71 VSS PD2 PD4 PD6 PD8 ID1 VCC Pin Names Function A0, B0, A1 - A11 Address Input(4K ref.) A0, B0, A1 - A12 Address Input(8K ref.) DQ0 - DQ71 Data In/Out W0, W2 Read/Write Enable OE0, OE2 Output Enable RAS0, RAS2 Row Address Strobe CAS0 - CAS7 Column Address Strobe VCC Power(+5V) VSS Ground NC No Connection PDE Presence Detect Enable PD1 - 8 Presence Detect ID0 - 1 ID bit RSVD Reserved Use RFU Reserved for Future Use Pins marked * are not used in this module. PD & ID Table Pin 50NS 60NS PD1 PD2 PD3 PD4 PD5 PD6 PD7 PD8 1 1 0 1 0 0 0 1 1 1 0 1 0 1 1 1 ID0 0 0 0 ID1 0 PD Note :PD & ID Terminals must each be pulled up through a resistor to V CC at the next higher level assembly. PDs will be either open (NC) or driven to V SS via on-board buffer circuits. PD : 0 for Vol of Drive IC & 1 for N.C ID Note : IDs will be either open (NC) or connected directly to VSS without a buffer. ID : 0 for Vss & 1 for N.C DRAM MODULE M364C040(8)4BT0-C FUNCTIONAL BLOCK DIAGRAM RAS0 W0 OE0 A0 A1-A11(A12) CAS0 RAS2 W2 OE2 B0 A1-A11(A12) U0 CAS1 CAS2 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ27 DQ28 DQ29 DQ30 DQ31 DQ32 DQ33 DQ34 CAS6 LCAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ36 DQ37 DQ38 DQ39 DQ40 DQ41 DQ42 DQ43 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ45 DQ46 DQ47 DQ48 DQ49 DQ50 DQ51 DQ52 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ54 DQ55 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ63 DQ64 DQ65 DQ66 DQ67 DQ68 DQ69 DQ70 UCAS LCAS U3 CAS7 UCAS LCAS U2 CAS5 UCAS U1 CAS3 CAS4 LCAS UCAS Note : A12 is used for only M364C0484BT0 (8K ref.) Vcc 0.1 or 0.22uF Capacitor under each DRAM Vss To all DRAMs A0 B0 A1-A11(A12) W0, OE0 W2, OE2 U0-U1 U2-U3 U0-U3 U0-U1 U2-U3 DRAM MODULE M364C040(8)4BT0-C ABSOLUTE MAXIMUM RATINGS * Item Voltage on any pin relative V SS Voltage on V CC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Output Current Symbol Rating Unit VIN, VOUT VCC Tstg PD IOS -1 to +7.0 -1 to +7.0 -55 to +125 4 50 V V C W mA * Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for intended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS (Voltage referenced to VSS, TA = 0 to 70C) Item Supply Voltage Ground Input High Voltage Input Low Voltage Symbol Min Typ Max Unit VCC VSS VIH VIL 4.5 0 2.4 5.0 0 - 5.5 0 V V V V -1.0*2 VCC*1 0.8 *1 : VCC+2.0V at pulse width20ns, which is measured at VCC. *2 : -2.0V at pulse width20ns, which is measured at VSS. DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted) Symbol Speed ICC1 M364C0404BT0 M364C0484BT0 Unit Min Max Min Max -50 -60 - 480 440 - 360 320 mA mA ICC2 Dont care - 100 - 100 mA ICC3 -50 -60 - 480 440 - 360 320 mA mA ICC4 -50 -60 - 280 240 - 240 200 mA mA ICC5 Dont care - 30 - 30 mA ICC6 -50 -60 - 480 440 - 360 320 mA mA II(L) IO(L) Dont care -10 -5 10 5 -10 -5 10 5 uA uA VOH VOL Dont care 2.4 - 0.4 2.4 - 0.4 V V ICC1 * : Operating Current * (RAS, CAS, Address cycling @tRC=min) ICC2 : Standby Current (RAS=CAS=W=VIH ) ICC3 * : RAS Only Refresh Current * (CAS=VIH , RAS cycling @tRC=min) ICC4 * : Fast Page Mode Current * (RAS=VIL, CAS cycling : tPC=min) ICC5 : Standby Current (RAS=CAS=W=Vcc-0.2V) ICC6 * : CAS-Before-RAS Refresh Current * (RAS and CAS cycling @ tRC=min) I(IL) : Input Leakage Current (Any input 0VINVcc+0.5V, all other pins not under test=0 V) I(OL) : Output Leakage Current(Data Out is disabled, 0VVOUT Vcc) VOH : Output High Voltage Level (IOH = -5mA) VOL : Output Low Voltage Level (IOL = 4.2mA) * NOTE : ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In I CC1 and I CC3, address can be changed maximum once while RAS=VIL. In I CC4, address can be changed maximum once within one Fast page mode cycle time, tPC. DRAM MODULE M364C040(8)4BT0-C CAPACITANCE (TA = 25C, f = 1MHz) Item Symbol Input capacitance[A0, B0, A1 - A12] Input capacitance[W0, W2, OE0, OE2] Input capacitance[RAS0, RAS2] Input capacitance[CAS0 - CAS7] Input/Output capacitance[DQ0 - 71] CIN1 CIN2 CIN3 CIN4 CDQ Min Max Unit - 20 20 24 20 17 pF pF pF pF pF AC CHARACTERISTICS (0CTA70C, V CC=5.0V10%. See notes 1,2.) Test condition : Vih/Vil=2.6/0.8V, Voh/Vol=2.4/0.4V, output loading CL=100pF Parameter Random read or write cycle time Read-modify-write cycle time Access time from RAS Access time from CAS Access time from column address CAS to output in Low-Z Output buffer turn-off delay Transition time(rise and fall) RAS precharge time RAS pulse width RAS hold time CAS hold time CAS pulse width RAS to CAS delay time RAS to column address delay time CAS to RAS precharge time Row address set-up time Row address hold time Column address set-up time Column address hold time Column address to RAS lead time Read command set-up time Read command hold referencde to CAS Read command hold referenced to RAS Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data in set-up time Data in hold time Refresh period Write command set-up time CAS to W delay time Column address to W delay time CAS prechange to W delay time Symbol tRC tRWC tRAC tCAC tAA tCLZ tOFF tT tRP tRAS tRSH tCSH tCAS tRCD tRAD tCRP tASR tRAH tASC tCAH tRAL tRCS tRCH tRRH tWCH tWP tRWL tCWL tDS tDH tREF tWCS tCWD tAWD tCPWD -50 Min -60 Max Min 90 110 133 155 Max Unit Note ns ns 50 60 ns 3,4 18 20 ns 3,4,5,11 30 35 ns 3,10,11 5 ns 3,11 5 18 5 5 20 ns 6,11 1 50 1 50 ns 2 30 50 40 10K 60 ns 10K ns 18 20 ns 11 45 55 ns 11 13 10K 15 10K ns 18 32 18 40 ns 4,11 13 20 13 25 ns 10,11 10 10 ns 11 5 5 ns 11 8 8 ns 11 0 0 ns 12 10 10 ns 12 30 35 ns 11 0 0 ns 0 0 ns 8 -2 -2 ns 8,11 10 10 ns 10 10 ns 20 20 ns 13 15 ns 15 -2 -2 ns 9,11 ns 9,11 15 15 64 64 11 ms 0 0 ns 7 36 40 ns 7,15 48 55 ns 7 53 60 ns 7 DRAM MODULE M364C040(8)4BT0-C AC CHARACTERISTICS (0CTA70C, VCC=5.0V10%. See notes 1,2.) Parameter RAS ro W delay time CAS setup time(CAS-before-RAS refresh) CAS hold time(CAS-before-RAS refresh) RAS to CAS precharge time Access time from CAS precharge Fast page mode cycle time Fast page mode read-modify-write cycle time CAS precharge time(Fast page cycle) RAS pulse width(Fast page cycle) RAS hold time from CAS precharge W to RAS precharge time(C-B-R refresh) W to RAS hold time(C-B-R refresh) OE access time OE to data delay Output buffer turn off delay time from OE OE command hold time Symbol tRWD tCSR tCHR tRPC tCPA tPC tPRWC tCP tRASP tRHCP tWRP tWRH tOEA tOED tOEZ tOEH -50 Min -60 Max Min Max Unit 73 85 ns 7,11 10 10 ns 11,16 8 8 ns 11 3 3 ns 11 ns 3,11 35 40 35 40 ns 76 85 ns 10 10 50 ns PDE to Valid PD bit tPD tPDOFF 13 18 20 ns 30 35 ns 11 ns 11 35 200K 60 40 ns 11 15 15 ns 11 8 8 ns 11 ns 11 18 18 200K 20 20 ns Present Detect Read Cycle PDE to PD bit Inactive Note 10 2 7 2 10 ns 7 ns DRAM MODULE M364C040(8)4BT0-C NOTES 1. An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before proper device operation is achieved. 2. Input voltage levels are V ih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between V IH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3. Measured with a load equivalent to 2 TTL loads and 100pF. 4. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5. Assumes that tRCDtRCD(max). 6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V OH or VOL. 7. tWCS, tRWD, tCWD, tAWD and tCPWD are not restrictive operating parameter. They are included in the data sheet as electrical characteristics only. If tWCStWCS (min) the cycle is an early write cycle and the data out pin will remain high impedance for the duration of the cycle. If tRWDtRWD(min), tCWDtCWD(min), tAWD tAWD(min) and tCPWDtCPWD(min). The cycle is a read-modify-write cycle and the data out will contain data read from the selected cell. If neither of the above sets of conditions is satisfied, the condition of data out(at access time) is indeterminate. 8. Either tRCH or tRRH must be satisfied for a read cycle. 9. These parameters are referenced to the CAS leading edge in early write cycles. 10. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD (max) is specified as reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. 11. The timing skew from the DRAM to the DIMM resulted from the addition of buffers. 12. tASC, tCAH are referenced to the earlier CAS falling edge. 13. tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle. 14. tCWD is referenced to the later CAS falling edge at word readmodify-write cycle. 15. tCWL is specified from W falling edge to the earlier CAS rising edge. 16. tCSR is referenced to earlier CAS falling low before RAS transition low. DRAM MODULE M364C040(8)4BT0-C READ CYCLE tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS tRCD tCRP tRSH tCAS VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tRCH tRCS W tRRH VIH VIL - tOFF tAA OE VIH - tOEZ tOEA VIL - tCAC DQ VOH VOL - tRAC OPEN tCLZ DATA-OUT Dont care Undefined DRAM MODULE M364C040(8)4BT0-C WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRAS RAS tRC tRP VIH VIL - tCSH tCRP CAS tRCD tRSH tCAS VIH VIL - tRAD tASR A tCRP VIH VIL - tRAH tASC ROW ADDRESS tRAL tCAH COLUMN ADDRESS tCWL tRWL tWCS W OE tWP VIL - VIH VIL - tDS DQ tWCH VIH - VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C WRITE CYCLE ( OE CONTROLLED WRITE ) NOTE : DOUT = OPEN tRC tRAS RAS tRP VIH VIL - tCSH tCRP CAS VIL - tRSH tCAS VIH VIL - tCRP tRAD tASR A tRCD VIH - tRAH tRAL tASC ROW ADDRESS tCAH COLUMN ADDRESS tCWL tRWL W OE VIH - tWP VIL - VIH VIL - tOED tOEH tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C READ - MODIFY - WRTIE CYCLE tRWC tRP tRAS VIH - RAS VIL - tCRP tRCD tRSH tCAS VIH - CAS VIL - tASR tRAD tRAH tASC tCAH tCSH VIH - A VIL - ROW ADDR COLUMN ADDRESS tRWL tAWD tCWD W OE tCWL VIH - tWP VIL - tRWD tOEA VIH VIL - tCLZ tCAC tAA DQ VI/OH VI/OL - tOED tOEZ tRAC VALID DATA-OUT tDS tDH VALID DATA-IN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C FAST PAGE READ CYCLE NOTE : D OUT = OPEN tRP tRASP RAS VIH - tRHCP VIL - o tCRP CAS VIH - tRAD tASC VIL - VIH VIL - tCP tCAS tCAS tASR A tPC tCP tRCD tRSH tCAS o tCSH tRAH tCAH ROW ADDR tASC COLUMN ADDRESS tCAH COLUMN ADDRESS tASC o tCAH COLUMN ADDRESS o tRRH tRCS W tRCH tRCS VIH - tCAC tOEA VIH VIL - VOH VOL - tCAC tOEA o o tAA tAA DQ o tRCH VIL - tCAC tOEA OE tRCS tRAC tCLZ tOEZ VALID DATA-OUT tOFF tCLZ tOEZ VALID DATA-OUT tAA tOFF tCLZ tOFF tOEZ VALID DATA-OUT Dont care Undefined DRAM MODULE M364C040(8)4BT0-C FAST PAGE WRITE CYCLE ( EARLY WRITE ) NOTE : DOUT = OPEN tRP tRASP RAS tRHCP VIH VIL - o tPC tCRP CAS VIH - tCAS tASR A VIL - tCSH tCAH tRAH tASC COLUMN ADDRESS ROW ADDR VIH - tWCH tCAH tASC o tWCS tWP o tWCH tWP tCAH COLUMN ADDRESS tWCS o tWCH tWP VIL - o VIL - VIH VIL - tCWL tRWL tCWL VIH - o tDS DQ tCAS COLUMN ADDRESS tCWL OE tRSH o tWCS W tCP tCAS tRAD tASC VIL - VIH - tPC tCP tRCD tDH VALID DATA-IN tDS tDH VALID DATA-IN tDS tDH o VALID DATA-IN o Dont care Undefined DRAM MODULE M364C040(8)4BT0-C FAST PAGE READ - MODIFY - WRITE CYCLE tRP tRASP RAS VIH - tCSH VIL - tRSH tRCD CAS tCP VIH - tCRP tCAS tCAS VIL - tRAD tPRWC tRAH tASR A VIH VIL - tCAH tASC COL. ADDR ROW ADDR COL. ADDR tRWL tRCS W tRAL tCAH tASC tCWL VIH - tCWL tWP VIL - tWP tCWD tCWD tAWD OE tAWD tCPWD tRWD tOEA VIH - tOEA VIL - tOED tCAC tCAC tAA tRAC DQ tOEZ tDH tOED tDH tAA tDS tDS tOEZ VI/OH VI/OL - tCLZ tCLZ VALID DATA-OUT VALID DATA-IN VALID DATA-OUT VALID DATA-IN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C RAS - ONLY REFRESH CYCLE NOTE : W, OE, DIN = Dont care D OUT = OPEN tRAS RAS tRC tRP VIH VIL - tRPC tCRP CAS VIH VIL - tASR A tCRP VIH VIL - tRAH ROW ADDR CAS - BEFORE - RAS REFRESH CYCLE NOTE : OE, A = Dont care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC tCSR VIH - tWRP W tCHR VIL - tWRH VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C HIDDEN REFRESH CYCLE ( READ ) tRC tRC tRP tRAS RAS VIH VIL - tCRP CAS tRP tRAS tRCD tRSH tCHR VIH VIL - tRAD tASR A VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tRCS W tRRH tWRP VIH VIL - tAA OE VIH - tOEA VIL - tOFF tCAC tRAC DQ VOH VOL - OPEN tCLZ tOEZ DATA-OUT Dont care Undefined DRAM MODULE M364C040(8)4BT0-C HIDDEN REFRESH CYCLE ( WRITE ) NOTE : DOUT = OPEN tRC tRC RAS VIH - tRP tRCD tRSH tCHR VIH VIL - tRAD tASR A tRAS VIL - tCRP CAS tRP tRAS VIH VIL - tRAH tASC ROW ADDRESS tCAH COLUMN ADDRESS tWRH tWRP W OE VIH - tWCS tWCH tWP VIL - VIH VIL - tDS DQ VIH VIL - tDH DATA-IN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C CAS-BEFORE-RAS REFRESH COUNTER TEST CYCLE tRP VIH - RAS tRAS VIL VIH - CAS tCPT tCSR tRSH tCAS tCHR VIL - tRAL tASC VIH - A COLUMN ADDRESS VIL - READ CYCLE tWRP tWRH tRRH tAA tRCS tRCH tCAC VIH - W VIL VIH - OE VIL - tOEA tCLZ VOH - DQ tCAH tOEZ DATA-OUT VOL - WRITE CYCLE W tOFF tWRP tRWL tWRH tCWL tWCS VIH - tWCH VIL - tWP OE VIH VIL - tDS DQ tDH VIH DATA-IN VIL - READ-MODIFY-WRITE tWRP W tWRH tAWD tRCS tCWL tCWD VIH - tRWL tWP tCAC VIL - tAA tOEA OE VIH - tOED VIL - tCLZ DQ tOEZ tDH tDS VI/OH VI/OL VALID DATA-OUT VALID DATA-IN Dont care NOTE : This timing diagram is applied to all devices besides 16M DRAM 4th & 64M DRAM. Undefined DRAM MODULE M364C040(8)4BT0-C CAS - BEFORE - RAS SELF REFRESH CYCLE NOTE : OE, A = Dont care tRP RAS tRASS tRPS VIH VIL - tRPC tRPC tCP CAS tCHS VIH - tCSR VIL - tOFF DQ VOH - OPEN VOL - tWRP W tWRH VIH VIL - TEST MODE IN CYCLE NOTE : OE, A = Dont care tRC tRP RAS tRAS tRP VIH VIL - tRPC tCP CAS tRPC VIH - tCSR tWTS W tCHR VIL - tWTH VIH VIL - tOFF DQ VOH VOL - OPEN Dont care Undefined DRAM MODULE M364C040(8)4BT0-C PACKAGE DIMENSIONS Units : Inches (millimeters) 5.250 (133.350) 0.054 (1.372) 5.014 (127.350) R 0.079 (R 2.000) 0.700 (17.780) 0.1570.004 (4.0000.100) 0.118 (3.000) B A .118DIA.004 (3.000DIA.100) 0.250 (6.350) 0.250 (6.350) 0.350 (8.890) .450 (11.430) C 0.100Min (2.540Min) 1.000 (25.40) 0.118 (3.000) 1.450 (36.830) 2.150 (54.61) 4.550 (115.57) ( Front view ) 0.165 Min (4.19 Min) 0.100 Max (2.54 Max) 0.0500.0039 (1.2700.10) 0.100 Min 0.250 (6.350) 0.250 (6.350) 0.1230.0050 (3.125.125) 0.039.002 (1.000.050) 0.1230.0050 (3.125.125) 0.079.0040 (2.000.100) Detail A (2.540 Min) ( Back view ) 0.079.0040 (2.000.100) Detail B Tolerances : .005(.13) unless otherwise specified The used device is 4Mx16 DRAM with Fast page mode, TSOP II. DRAM Part No. : M364C0404BT0 - K4F641611B M364C0484BT0 - K4F661611B 0.01Max (0.25 Max) 0.050 (1.270) Detail C