Classic EPLD Family Features Altera Corporation A-DS-CLASSIC-04 Complete device family with logic densities of 300 to 900 usable gates (see Fable 1) Device erasure and reprogramming with advanced, non-volatile EPROM configuration elements Fast pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz 24 to 68 pins available in dual in-line package (DIP), ceramic and plastic J-lead chip carrier (JLCC and PLCC), pin-grid array (PGA), and small-outline integrated circuit (SOIC) packages Programmable security bit for protection of proprietary designs 100% generically tested to provide 100% programming yield Programmable registers providing D, T, JK, and SR flipflops with individual clear and clock controls Software design support featuring the Altera MAX+PLUS II development system on 486- and Pentium-based PCs, and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System /6000 workstations, and third-party development systems Programming support with Alteras Master Programming Unit (MPU); programming hardware from Data I/O, BP Microsystems, and other third-party programming vendors Additional design entry and simulation support provided by EDIF, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, Synplicity, and VeriBest Table 1. Classic Device Features Feature EP610 EP910 EP1810 EP6101 EP910I Usable gates 300 450 900 Macrocells 16 24 48 Maximum user I/O pins 22 38 64 tpp (ns) 10 12 20 font (MHz) 100 76.9 50 419Classic EPLD Family Data Sheet General Description 420 The Altera Classic device family offers a solution to high-speed, low- power logic integration. Fabricated on advanced CMOS technology, Classic devices also have a Turbo-only version, which is described in this data sheet. Classic devices support 100% TTL emulation and can easily integrate multiple PAL- and GAL-type devices with densities ranging from 300 to 900 usable gates. The Classic family provides pin-to-pin logic delays as low as 10 ns and counter frequencies as high as 100 MHz. Classic devices are available in a wide range of packages, including CerDIP, PDIP, PLCC, PGA, and SOIC packages. EPROM-based Classic devices can reduce active power consumption without sacrificing performance. This reduced power consumption makes the Classic family well suited for a wide range of low-power applications. Classic devices are 100% generically tested and can be erased with ultra-violet (UV) light, allowing design changes to be implemented quickly. Classic devices use sum-of-products logic and a programmable register. The sum-of-products logic provides a programmable-AND/fixed-OR structure that can implement logic with up to eight product terms. The programmable register can be individually programmed for D, T, SR, or JK flipflop operation or can be bypassed for combinatorial operation. In addition, macrocell registers can be individually clocked either by a global clock or by any input or feedback path to the AND array. Alteras proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to implement a variety of logic functions simultaneously. Classic devices are supported by Alteras MAX+PLUS II development system, a single, integrated package that offers schematic, textincluding VHDL, Verilog HDL, and the Altera Hardware Description Language (AHDL)and waveform design entry; compilation and logic synthesis; simulation and timing analysis; and device programming. The MAX+PLUS II software provides EDIF 2 0 0 and 3.0 0, LPM, VHDL, Verilog HDL, and other interfaces for additional design entry and simulation support from other industry-standard PC- and workstation- based EDA tools. The MAX+PLUS II software runs on 486- and Pentium- based PCs, and Sun SPARCstation, HP 9000 Series 700/800, and IBM RISC System /6000 workstations. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. For more information, go to the MANX+PLUS i Programmable Logic Development System & Software Data Sheet in this data book. Altera CorporationClassic EPLD Family Data Sheet Functional Description Altera Corporation The Classic architecture includes the following elements: # Macrocells @ Programmable registers @ Output enable/clock select #@ Feedback select Macrocells Classic macrocells, shown in Figure 1, can be individually configured for both sequential and combinatorial logic operation. Eight product terms form a programmable-AND array that feeds an OR gate for combinatorial logic implementation. An additional product term is used for asynchronous clear control of the internal register; another product term implements either an output enable or a logic-array-generated clock. Inputs to the programmable-AND array come from both the true and complement signals of the dedicated inputs; feedbacks from I/O pins that are configured as inputs; and feedbacks from macrocell outputs. Signals from dedicated inputs are globally routed and can feed the inputs of all device macrocells. The feedback multiplexer controls the routing of feedback signals from macrocells and from I/O pins. For additional information on feedback select configurations, see Figure 3 on page 423. Figure 1. Classic Device Macrocell Logic Array Global YCC Output Enable/Clock Select Programmable Register Feedback Select Input, I/O, and to Logic Array Macrocell Feedbacks = Asynchronous Clear 421Classic EPLD Family Data Sheet 422 The eight product terms of the programmable-AND array feed the 8-input OR gate, which then feeds one input to an XOR gate. The other input to the XOR gate is connected to a programmable bit that allows the array output to be inverted. Alteras MAX+PLUS II software uses the XOR gate to implement either active-high or active-low logic, or De Morgans inversion to reduce the number of product terms needed to implement a function. Programmable Registers To implement registered functions, each macrocell register can be individually programmed for D, T, JK, or SR operation. If necessary, the register can be bypassed for combinatorial operation. During design compilation, the MAX+PLUS II software selects the most efficient register operation for each registered function to minimize the logic resources needed by the design. Registers have an individual asynchronous clear function that is controlled by a dedicated product term. These registers are cleared automatically during power-up. In addition, macrocell registers can be individually clocked by either a global clock or any input or feedback path to the AND array. Alteras proprietary programmable I/O architecture allows the designer to program output and feedback paths for combinatorial or registered operation in both active-high and active-low modes. These features make it possible to simultaneously implement a variety of logic functions. Output Enable/Clock Select Figure 2 shows the two operating modes (Modes 0 and 1) provided by the output enable/clock (OE/CLK) select. The OE /CLK select, which is controlled by a single programmable bit, can be individually configured for each macrocell. In Mode 0, the tri-state output buffer is controlled by a single product term. If the output enable is high, the output buffer is enabled. If the output enable is low, the output has a high-impedance value. In Mode 0, the macrocell flipflop is clocked by its global clock input signal. In Mode 1, the output enable buffer is always enabled, and the macrocell register can be triggered by an array clock signal generated by a product term. This mode allows registers to be individually clocked by any signal on the AND array. With both true and complement signals in the AND array, the register can be configured to trigger on a rising or falling edge. This product-term-controlled clock configuration also supports gated clock structures. Altera CorporationClassic EPLD Family Data Sheet Figure 2. Classic Output Enable/Clock Select Mode 0 vec Output Enable/Clock Global Select In Mode 0, the register Clock peefonsssnaneesess a is clocked by the global AND T) clock signal. The Array ouiput is enabled by the logic from the produc term. OE = Product Term CLK = Global cLR Macrocell Output Buffer Mode 1 Output Enable/Clock Global VCC elect In Mode 1, the output Clock is permanently enabled AND ) and the register is Array clocked by the product term, which allows gated clocks to be generated. OE = Enabled CLK = Product Term Macrocell Output Buffer Feedback Select Each macrocell in a Classic device provides feedback selection that is controlled by the feedback multiplexer. This feedback selection allows the designer to feed either the macrocell output or the I/O pin input associated with the macrocell back into the AND array. The macrocell output can be either the Q output of the programmable register or the combinatorial output of the macrocell. Different devices have different feedback multiplexer configurations. See Figure 3. Figure 3. Classic Feedback Multiplexer Configurations Global Feedback Multiplexer Quadrant Feedback Multiplexer Dual Feedback Multiplexer <4 0 j#+Q Quadrant ~@ 4Q Global@ 7 _ be v0 Quadrant ta vo Global 4-1/0 EP610 EP1810 EP1810 EP6101 EP1810T EPi810T EP910 EP9i0l Altera Corporation 423Classic EPLD Family Data Sheet Design Security Timing Model 424 EP610, EP610I, EP910, and EP910I devices have a global feedback configuration; either the macrocell output (Q) or the I/O pin input (1/0) can feed back to the AND array so that it is accessible to all other macrocells. EP1810 macrocells can have either of two feedback configurations: quadrant or dual. Most macrocells in EP1810 devices have a quadrant feedback configuration; either the macrocell output or I/O pin input can feed back to other macrocells in the same quadrant. Selected macrocells in EP1810 devices have a dual feedback configuration: the output of the macrocell feeds back to other macrocells in the same quadrant, and the I/O pin input feeds back to all macrocells in the device. If the associated I/O pin is not used, the macrocell output can optionally feed all macrocells in the device. In this case, the output of the macrocell passes through the tri-state buffer and uses the feedback path between the buffer and the I/O pin. Classic devices contain a programmable security bit that controls access to the data programmed into the device. When this bit is programmed, a proprietary design implemented in the device cannot be copied or retrieved. This feature provides a high level of design security because data within EPROM configuration elements is invisible. The security bit that controls this function and other program data is reset only when the device is erased. Device timing can be analyzed with the MAX+PLUS II software, with a variety of popular industry-standard EDA simulators and timing analyzers, or with the timing model shown in Figure 4. Devices have fixed internal delays that allow the user to determine the worst-case timing for any design. The MAX+PLUS II software provides timing simulation, point-to-point delay prediction, and detailed timing analysis for system- level performance evaluation. Figure 4. Classic Timing Model Global Clock ~ Delay > | al | tics co > Input Register Delay pe) Array Clock | tsu Deby ty Dela "| ty > > on rh) too HES kz Co, ~ tox Bb) Logic Array ~ Delay 4 > tap torr VO K>. Delay Feedback tio Delay trp Altera CorporationClassic EPLD Family Data Sheet Altera Corporation Timing information can be derived from the timing model and parameters for a particular device. External timing parameters represent pin-to-pin timing delays, and can be calculated from the sum of internal parameters. Figure 5 shows the internal timing relationship for internal and external delay parameters. For more information on device timing, refer to Application Note 7&8 (Linderstanding MAX 5000 & Classic Timing} in this data book. 425Classic EPLD Family Data Sheet Figure 5. Classic Switching Waveforms tpandi-<3 ns. Inputs are driven at 3 V for a logie high and VO Pi 0 V for a logic low. m All timing characteristics are measured at 1.5 V. Input Pin Logic Array Input Logic Array Output Output Pin Global Clock Pin Global Clock at Register Data from Logic Array Clock Pin Clock into Logic Array Clock from Logic Array Data from Logic Array Register Output to Logic Array Clock from Logic Array Data from Logic Array Output Pin 426 tpp1 = fin + fap + top tpp2 = fo + tw + tad + top Global Clock Mode Array Clock Mode tacu tac te a A a lop tox High-Impedance Tri-State Altera CorporationClassic EPLD Family Data Sheet Turbo Bit Option Generic Testing Device Programming Altera Corporation Many Classic devices contain a programmable Turbo Bit option to control the automatic power-down feature that enables the low-standby- power mode. When the Turbo Bit option is turned on, the low-standby- power mode is disabled. All AC values are tested with the Turbo Bit option turned on. When the device is operating with the Turbo Bit option turned off (non-Turbo mode), a non-Turbo adder must be added to the appropriate AC parameter to determine worst-case timing. The non- Turbo adder is specified in the AC Operating Conditions tables for each Classic device that supports the Turbo mode. Classic devices are fully functionally tested. Complete testing of each programmable EPROM configuration element and all internal logic elements before and after packaging ensures 100% programming yield. See Figure 6 for AC test measurement conditions. These devices also contain on-board logic test circuitry to allow verification of function and AC specifications during standard production flow. Figure 6. AC Test Conditions Power-supply transients can affect AC -__ voc measurements. Simultaneous transitions of multiple outputs should be avoided for Ri J accurate measurement. Threshold tests 885Q must not be performed under AC Device to Test conditions. Large-amplitude, fast ground- Output System current transients normally occur as the c> device outputs discharge the load capacitances. When these transients flow R2 through the parasitic inductance between 3402 = the device ground pin and the test system ground, significant reductions in observable noise immunity can result. YVY VY C1 (includes JIG capacitance) Classic devices can be programmed on 486- and Pentium-based PCs with the MAX+PLUS II Programmer, an Altera Logic Programmer card, the Master Programming Unit (MPU), and the appropriate device adapter. The MPU performs continuity checking to ensure adequate electrical contact between the adapter and the device. Data I/O, BP Microsystems, and other programming hardware manufacturers also offer programming support for Altera devices. See Programing Hardware Manufacturers in this data book for more information. 427Notes:EP610 EPLD Features High-performance, 16-macrocell Classic EPLD - Combinatorial speeds with tpp as fast as 10 ns - Counter frequencies of up to 100 MHz - Pipelined data rates of up to 125 MHz Programmable I/O architecture with up to 20 inputs or 16 outputs and 2 clock pins EP610 and EP610I devices that are pin-, function-, and programming file-compatible Programmable clock option for independent clocking of all registers Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation Available in the following packages (see Figure ): 24-pin small-outline integrated circuit (plastic SOIC only) 24-pin ceramic and plastic dual in-line package (CerDIP and PDIP) 28-pin plastic J-lead chip carrier (PLCC) Figure 7. EP610 Package Pin-Out Diagrams Package outlines not drawn to scale. Windows in ceramic packages only. e 24 23 22 21 20 19 18 17 16 10 15 INPUT oF 11 14 GND cr 12 13 Weel ohy/ 019d5 Pode eo oo oo 24-Pin SOIC EP610 Altera Corporation VCC INPUT Vo Vo Vo Vo Vo Vo Vo Vo INPUT CLK2 E E cLKi 1 vec > 222 oO 3 Oo 9 Zz oO INPUT [J 2 INPUT SB 403 3 4685 vos vo 3 2 1 28 27 26 vom 4 vo 2 VO vO 5 vo 24 BVO Vom 6 VO vo? vo ep vo vod s V0 (NOTE RYAN 22 F/O vod: vo EP610 21 tV/o vod Vo 20 1 VO INPUT INPUT 19 HNC GND CLK2 13 14 15 16 17 18 OoFoOaonNEO = D2rwF-2zw<* Dez & 56 8 5 & 24-Pin DIP 28-Pin PLCC EP610 EP610 EP610l EP610I 429Classic EPLD Family Data Sheet General EP610 devices have 16 macrocells, 4 dedicated input pins, 16 I/O pins, sos and 2 global clock pins (see Figure 8). Each macrocell can access signals Descri pti on from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 signal is a dedicated global clock input for the registers in macrocells 9 through 16. The CLK2 signal is a dedicated global clock input for registers in macrocells 1 through 8. Figure 8. EP610 Block Diagram Numbers without parentheses are for DIP and SOIC packages. Numbers in parentheses are for J-lead packages. 2 (3) INPUT INPUT 23 (27) 1 (2) CLKi CLK2 13 (16) 3 (4) Macrocell 9 Macrocell 1 22 (26) 4 (5) Macrocell 10 Macrocell 2 21 (25) 5 (6) Macrocell 11 Macrocell 3 20 (24) 6 (7) Macrocell 12 Macrocell 4 19 (23) 7 (8) Macrocell 13 Macrocell 5 18 (22) 8 (9) Macrocell 14 Macrocell 6 17 (21) 9 (10) Macrocell 15 Macrocell 7 16 (20) 10 (12) Macrocell 16 Macrocell 8 15 (18) 11 (13) INPUT INPUT 14 (17) igure shows the typical supply current (Icc) versus frequency of EP610 devices. Figure 9. loc vs. Frequency of EP610 Devices 100 Turbo a ioF = x g Veco = 5.0 V S iol Ta =25C & 1. 8 Non-Turbo o1fF 1 1 1 1 1 1kHz 10kHz 100kHz 1 MHz 10MHz 80 MHz Frequency 430 Altera CorporationClassic EPLD Family Data Sheet Figure 10 shows the typical output drive characteristics of EP610 devices. Figure 10. Output Drive Characteristics of EP610 Devices Drive characteristics may exceed shown curves. EP610-15 & EP610-20 EPLDs 200 150 100 | lo| Output Current (mA) Typ. EP610] EPLDs 100 80 60 40 20 | lo| Output Current (mA) Typ. 80 a reams L lo. x 60 < Veco = 5.0 V 2 L Ta =25C 3 40 5 2 5 Oo L - 20 lou 9 ! ! ! ! 1 2 3 4 5 Vo Output Voltage (V) Voc = 5.0 V Ta = 25C lon 1 1 1 1 1 2 3 4 5 Vo Output Voltage (V) Altera Corporation EP610-25, EP610-30 & EP610-35 EPLDs Voc = 5.0 V L Ty = 25C lon 1 1 1 1 1 2 3 4 5 Vo Output Voltage (V) 431Classic EPLD Family Data Sheet Operati ng The following tables provide information on absolute maximum ratings, oye recommended operating conditions, operating conditions, and Conditions capacitance for EP610 and EP610I devices. EP610 & EP610I Device Absolute Maximum Ratings = Nees (7), (2) ard EP610 EP6101 Symbol Parameter Conditions Min Max Min Max | Unit Voc Supply voltage With respect to ground, 2.0 7.0 -2.0 7.0 Vv V DC input voltage Note (3) -2.0 7.0 05 |Voo+05| V Imax DC Vee or ground current -175 175 mA lout DC output current, per pin 25 25 mA Tste Storage temperature No bias 65 150 65 150 C TaMB Ambient temperature Under bias 65 135 (125) -10 85 C Ty Junction temperature Ceramic packages, under 150 150 C bias Plastic packages, under bias 135 135 C EP610 & EP6101 Device Recommended Operating Conditions = Nate {2} EP610 EP6101 Symbol Parameter Conditions Min Max Min Max | Unit Vec Supply voltage Note (} 4.75 (4.5) | 5.25 (5.5) 4.75 5.25 Vv Vv Input voltage 0 Veco 0 Veco Vv Vo Output voltage 0 Veco 0 Veco Vv Ta Operating temperature For commercial use 0 70 0 70 C For industrial use 40 85 40 85 C ta Input rise time Note (@) 100 (50) 500 ns te Input fall time Nofe (6) 100 (50) 500 ns EP610 & EP610I Device DC Operating Conditions = Note {4} Symbol Parameter Conditions Min Max | Unit Vin High-level input voltage 2.0 Voc + 0.3 Vv Vit Low-level input voltage 0.3 0.8 Vv Vou High-level TTL output voltage lon =-4 mA DC, Neate (7) 2.4 Vv High-level CMOS output voltage lou =0.6 mA DC, Nefes (77, {8} 3.84 Vv VoL Low-level output voltage lo =4 mA DC, Neate (F} 0.45 Vv I) I/O pin leakage current of dedicated input | V| = Voc or ground -10 10 HA pins loz Tri-state output leakage current Vo = Voc or ground -10 10 HA 432 Altera CorporationEP610 & EP610I Device Capacitance iat ff Note {9} Classic EPLD Family Data Sheet EP610 EP610I Symbol Parameter Conditions Min Max Min Max | Unit Cin Input pin capacitance Vin =O V, f= 1.0 MHz 10 8 pF Cio \/O pin capacitance Vout = 0 V, f= 1.0 MHz 12 8 pF Ceik4 CLK1 pin capacitance Vin =0 V, f = 1.0 MHz 20 10 pF Coke CLK2 pin capacitance Vin=0V, f = 1.0 MHz 20 12 pF EP610 Device Ico Supply Current = Nees (2), 10) EP610 Symbol Parameter Conditions Speed Min Typ Max | Unit Grade lect Voc supply current Vi = Voc or ground, no load, 20 150 HA (non-Turbo, standby) Notes (71), 42} lece Voc supply current Vi = Vec or ground, no load, 5 10 (15) mA (non-Turbo, active) f= 1.0 MHz, Nefes (19), 12) lees Voc supply current Vi = Vee or ground, no load, | -15, -20 60 90 (115) mA (Turbo, active) f = 1.0 MHz, Note #72) -25, -30, 45 60 (75) mA -35 EP610I Device Ico Supply Current = Note (18) EP6101 Symbol Parameter Conditions Min Typ Max | Unit lees Voc supply current Vi = Vec or ground, no load, 20 150 HA (non-Turbo, standby) Notes (79), (2) loce Voc supply current Vi = Voc or ground, no load, 3 8 mA (non-Turbo, active) f= 1.0 MHz, Nefes 93), (72) lees Voc supply current Vi = Vec or ground, no load, 65 105 mA (Turbo, active) f= 1.0 MHz, Nefe (72) Altera Corporation 433Classic EPLD Family Data Sheet Notes to tables: (1) See the Overaimne Requirements: Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to 2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) These values are specified under the EP619 & EPSLOE Device Recommended Cperating Conditions on page 432. (5) For EP610 devices, maximum Vcc rise time is 50 ms. For EP610I devices, Vcc rise time is unlimited with monotonic rise. (6) For EP610-15 and EP610-20 devices: tp and tp = 40 ns. For EP610-15 and EP610-20 clocks: tr and tp = 20 ns. (7) The Ipp parameter refers to high-level TTL or CMOS output current; the Ip, parameter refers to low-level TTL output current. (8) This parameter does not apply to EP610I devices. (9) The device capacitance is measured at 25 C and is sample-tested only. The clock-pin capacitance is for dedicated clock inputs only. For EP610-25, EP610-30, and EP610-35 devices: pin 13 has a maximum capacitance of 50 pF; Cpy, Cro, and CeLk = 20 pF. (10) Typical values are for T, = 25 C and Vec =5 V. (11) When the Turbo Bit option is not set (Non-Turbo mode), EP610 devices enter standby mode if no logic transitions occur for 100 ns after the last transition. When the Turbo Bit option is not set, EP6101 devices enter standby mode if no logic transitions occur for 75 ns after the last transition. (12) Measured with a device programmed as a 16-bit counter. 434 Altera CorporationClassic EPLD Family Data Sheet EP610-15 & EP610-20 Device AC Operating Conditions = Nefes (7), External Timing Parameters EP610-15 | EP610-20 Nop Turbo Symbol Parameter Conditions Min | Max} Min] Max] ee 3) | Unit tpp1 Input to non-registered output C1 = 35 pF 15 20 20 ns tpp2 \/O input to non-registered output C1 = 35 pF 17 22 20 ns tpzx Input to output enable C1 = 35 pF 15 20 20 ns tpxz Input to output disable C1 =5 pF, Note 4, 15 20 20 ns tcLr Asynchronous output clear time C1 = 35 pF 15 20 20 ns fax Maximum clock frequency Note {5} 83.3 62.5 0 MHz tsu Global clock input setup time 9 11 20 ns ty Global clock input hold time 0 0 ns ton Global clock high time 6 0 ns te Global clock low time 6 0 ns tco1 Global clock to output delay 11 13 0 ns tent Global clock minimum period 12 16 0 ns font Maximum internal global clock frequency | Nets 6} 83.3 62.5 0 MHz tasu Array clock input setup time 6 8 20 ns tan Array clock input hold time 6 8 0 ns tacu Array clock high time 7 9 ns tac. Array clock low time 7 9 ns toby Output data hold time after clock C1 = 35 pF, Neve (7) 1 1 1 ns taco1 Array clock to output delay 15 20 20 ns tacnt Array clock minimum period 14 18 0 ns facnt Array clock internal maximum frequency | Aiefe /8} 71.4 55.6 0 MHz Internal Timing Parameters EP610-15 | EP610-20 Symbol Parameter Conditions Min | Max} Min} Max] Unit tiny Input pad and buffer delay 4 ns tio \/O input pad and buffer delay 2 ns tap Logic array delay 6 11 ns lop Output buffer and pad delay C1 = 35 pF 5 ns tx Output buffer enable delay C1 = 35 pF 5 ns tyz Output buffer disable delay C1 =5 pF 5 ns tsu Register setup time 5 4 ns ty Register hold time 4 7 ns tic Array clock delay 6 11 ns tics Global clock delay 2 4 ns tep Feedback delay 1 ns loLr Register clear time 6 11 ns Altera Corporation 435Classic EPLD Family Data Sheet EP610-25, EP610-30 & EP610-35 AC Operating Conditions = Netes {1}, 2} External Timing Parameters EP610-25 | EP610-30 | EP610-35 Non Turbo Symbol Parameter Conditions | Min | Max} Min | Max| Min] Max| ere /3) | Unit tpp1 Input to non-registered output C1 = 35 pF 25 30 35 30 ns tpp2 \/O input to non-registered output 27 32 37 30 ns tpzx Input to output enable 25 30 35 30 ns tpxz Input to output disable C1 =5pF, 25 30 35 30 ns Nate (4) tcLr Asynchronous output clear time C1 = 35 pF 27 32 37 30 ns fax Maximum frequency Nofe {8} 47.6 41.7 37 0 MHz tsu Global clock input setup time 21 24 27 30 ns ty Global clock input hold time 0 0 0 0 ns ton Global clock high time 10 11 12 0 ns te Global clock low time 10 11 12 0 ns tco1 Global clock to output delay 15 17 20 0 ns tent Global clock minimum period 25 30 35 0 ns font Max. internal global clock frequency | Afes 3} 40 33.3 28.6 0 MHz tasu Array clock input setup time 8 8 8 30 ns tan Array clock input hold time 12 12 12 0 ns tacu Array clock high time 10 11 12 0 ns tac. Array clock low time 10 11 12 0 ns topH Output data hold time after clock C1 = 35 pF, 1 1 1 ns Note (7) taco1 Array clock to output delay 27 32 37 30 ns tacnt Array clock minimum period 25 30 35 0 ns facnt Max. internal global clock frequency | Nete 4) 40 33.3 28.6 0 MHz 436 Altera CorporationClassic EPLD Family Data Sheet Internal Timing Parameters EP610-25 EP610-30 EP610-35 Symbol Parameter Condition | Min | Max | Min | Max | Min | Max | Unit tiny Input pad and buffer delay 8 9 11 ns tio \/O input pad and buffer delay 2 2 2 ns trap Logic array delay 11 14 15 ns top Output buffer and pad delay C1 = 35 pF 6 7 9 ns tox Output buffer enable delay C1 = 35 pF 6 7 9 ns txz Output buffer disable delay C1=5pF 6 7 9 ns tsy Register setup time 11 11 12 ns ty Register hold time 10 10 10 ns tic Array clock delay 13 16 17 ns tics Global clock delay ns tep Feedback delay ns totR Register clear time 13 16 17 ns Notes to tables: (1) These values are speci: (2) See Application Note 7 (Unders timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (6) The fyyax values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 16-bit counter. fied under the ORY unercied Operating 2} in this data book for information on internal nciitions on page 432. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation 437Classic EPLD Family Data Sheet EP610 Device AC Operating Conditions z 7 i i fs3y Netes {1}, (2) External Timing Parameters EP6101-10 Nop Turbo Symbol Parameter Conditions Min Max Note (3) Unit tpp1 Input to non-registered output C1 = 35 pF 10 25 ns tpp2 \/O input to non-registered output 10 25 ns tpzx Input to output enable 15 25 ns tpxz Input to output disable C1=5pF, 13 25 ns Nove (4) tcLr Asynchronous output clear time C1 = 35 pF 13 25 ns fax Maximum frequency Note (8) 125 0 MHz tsu Global clock input setup time 7 25 ns ty Global clock input hold time 0 ns tou Global clock high time 5 ns te. Global clock low time 5 ns tco1 Global clock to output delay 6.5 ns tent Global clock minimum period 10 25 ns font Maximum internal global clock frequency 100 0 MHz tasu Array clock input setup time 1.5 25 ns tan Array clock input hold time 5.5 0 ns tacu Array clock high time 0 ns tac. Array clock low time 0 ns topH Output data hold time after clock 1 0 ns taco1 Array clock to output delay 12 25 ns tacnt Array clock minimum period 10 25 ns facnt Max. internal array clock frequency Nofe (8) 100 0 MHz 438 Altera CorporationClassic EPLD Family Data Sheet Internal Timing Parameters EP6101-10 Symbol Parameter Conditions Min Max Unit tiny Input pad and buffer delay 1.5 ns tio \/O input pad and buffer delay 0.0 ns trap Logic array delay 5.5 ns top Output buffer and pad delay C1 = 35 pF 3.0 ns tzx Output buffer enable delay C1 = 35 pF 8.0 ns tyz Output buffer disable delay C1=5pF 6.0 ns tsy Register setup time 3.5 ns ty Register hold time 3.5 ns tic Array clock delay 7.5 ns tics Global clock delay 2.0 ns tep Feedback delay 1.0 ns toir Register clear time 8.5 ns Notes to tables: (1) These values are specified under the ! (2) See Application Note 78 (Lindersianding ALAN SGC timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (6) The fyyax values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 16-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. Altera Corporation EPSLOL Device e Recommended Oparating Conditions on page 432. is Classic Tineing) in this data book for more information on Classic 439Notes:EP910 EPLD Features @ High-performance, 24-macrocell Classic EPLD - Combinatorial speeds with tpp as fast as 12 ns - Counter frequencies of up to 76.9 MHz - Pipelined data rates of up to 125 MHz # Programmable I/O architecture with up to 36 inputs or 24 outputs @ = EP910 and EP910I devices that are pin-, function-, and programming file-compatible # Programmable clock option for independent clocking of all registers @ = Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation @ Available in the following packages (see Figure 21): 44-pin plastic J-lead chip carrier (PLCC) - 40-pin ceramic and plastic dual in-line packages (CerDIP and PDIP) Figure 11. EP910 Package Pin-Out Diagrams Package outlines are not drawn to scale. Windows in ceramic packages only. vec INPUT 555 coQD0D INPUT Q2Z2z258$22z28 INPUT Vo 6 5 4 3 2144 43 424140 Vo Vo VO 3965 NC VO 0 38 1/0 0 0 372 VO 0 0 36 1/0 0 0 352 1/0 0 V0 ALTER ab 1/0 0 0 332 1/0 0 Vo 220 1/0 Vo Vo 310 VO Vo Vo 30F 1/0 INPUT NC 200 10 INPUT INPUT 18 19 20 21 2223 24 25 2627 28 CLK2 2555 ge5 55S Z220222 44-Pin PLCC 40-Pin DIP EP910 EP910 EP910l EP910l Altera Corporation 441Classic EPLD Family Data Sheet General Altera EP910 devices can implement up to 450 usable gates of small-scale sys integration (SSI) and medium-scale integration (MSD logic functions. Descri pt on EP910 devices have 24 macrocells, 12 dedicated input pins, 24 I/O pins, and 2 global clock pins (see Figure 12). Each macrocell can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of either the output of the macrocell or the I/O input. The CLK1 and CLK2 signals are the dedicated clock inputs for the registers in macrocells 13 through 24 and 1 through 12, respectively. Figure 12. EP910 Block Diagram Numbers without parentheses are for DIP packages. Numbers in parentheses are for J-lead packages. 2 (3) INPUT L> > <4 <_] INPUT (43) 39 3 (4) INPUT [> > <] INPUT (42) 38 4 (5) INPUT LO> > <4 <]_ INPUT (41) 37 1 (2) CLKi a , CLK2 (24) 21 5 (6) KS Macrocell 13 <-> <> Macrocell 4 -<>]_ (40) 36 6 7) ke Macrocell 14 <> <> Macrocell 2 -< >] (38) 35 7 (8) ko Macrocell 15 <-> +> Macrocell 3 Le>| (37) 34 8 9) eS Macrocell 16 <-> <> Macrocell 4 Lf >| _ (36) 33 9 (10) ke>+ Macrocell 17 >| Global |< Macrocell 5 ee) 32 to) (41) eS Macrocell 18 +>! Bus |<> Macrocell 6 t-te] (343 1 (12) eS} Macrocell 19 <> <> Macrocell 7 Lt] (33) 30 12 (13) eS Macrocell 20 <> <> Macrocell 8 Le] (32) 29 a a3 KS Macrocel 21 +> <> Macrocell 9 Ls] (31) 28 K >}+ acrocell 22 <> <> Macrocell 10 -< > (30) 27 16 (16) keS| 4 Macrocell 23 <> <> Macrocell 11 -fe>| (29) 26 16 (18) keS} Macrocell 24 <> +> Macrocell 12 tk] (28) 2 47 (19) INPUT [=> > 4 <INPUT (27) 24 48 (20) INPUT [>> > t <] INPUT (26) 23 19 (21) INPUT [>> > <4 <] INPUT (25) 22 Figure 15 shows the typical supply current (Icc) versus frequency of EP910 devices. 442 Altera CorporationClassic EPLD Family Data Sheet Figure 13. Ico vs. Frequency of EP910 Devices log Active (mA) Typ. 100 0.1 Turbo Veco = 5.0 V Ta =25C Non- Turbo 1kHz 10kHz 100kHz 1MHz 10MHz 40 MHz Frequency Figure 14 shows the typical output drive characteristics of EP910 devices. Figure 14. Output Drive Characteristics of EP910 Devices Drive characteristics may exceed shown curves. EP910 EPLDs 60 50 40 30 20 | lo | Output Current (mA) Typ. Veo = 5.0 V Ty = 25C lou 1 1 1 1 045 1 2 3 4 5 Altera Corporation Vo Output Voltage (V) EP9101 EPLDs 120 So So 80 a oS | lo| Output Current (mA) Typ. a oS nN So Veo = 5.0 V L Ty = 25C lon 1 1 1 1 0.45 1 2 3 4 5 Vo Output Voltage (V) 443Classic EPLD Family Data Sheet Operating The following tables provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and Conditions capacitance for EP910 and EP910I devices. EP910 & EP910I Device Absolute Maximum Ratings = Note {3} EP910 EP9101 Symbol Parameter Conditions Min Max Min Max | Unit Voc Supply voltage Nofes (2), (8) -2.0 7.0 -2.0 7.0 Vv Vv DC input voltage Notas (2), (3) -2.0 7.0 0.5 Veco +05] V Imax DC Voc or ground current 250 250 mA lout DC output current, per pin 25 25 mA Tste Storage temperature No bias 65 150 65 150 C TaMB Ambient temperature Noe (4) 65 135 -10 85 C Ty Junction temperature Ceramic packages, under 150 150 C bias Plastic packages, under 135 135 C bias EP910 & EP910I Device Recommended Operating Conditions = Nee {8} EP910 EP9101 Symbol Parameter Conditions Min Max Min Max | Unit Vec Supply voltage 4.75 (4.5) | 5.25 (5.5) 4.75 5.25 Vv Vv Input voltage Veco 0 Veco Vv Vo Output voltage Veco 0 Veco Vv Ta Operating temperature For commercial use 70 0 70 C For industrial use 40 85 C ta Input rise time 100 (50) 500 ns te Input fall time 100 (50) 500 ns EP910 & EP910I Device DC Operating Conditions = Neiss {8), {8} Symbol Parameter Conditions Min Max | Unit Vin High-level input voltage 2.0 Veco +03) V Vit Low-level input voltage 0.3 0.8 Vv Vou High-level TTL output voltage lon =4 mA DC, Note 7a) 2.4 Vv High-level CMOS output voltage loy = 0.6 mA DC, Alves 3.84 Vv VoL Low-level output voltage lol = 4 mA DC, Nei 0.45 Vv I, I/O leakage current of dedicated input pins | V, = Voc or ground -10 10 HA loz Tri-state output leakage current Vo = Vec or ground -10 10 HA 444 Altera CorporationClassic EPLD Family Data Sheet EP910 & EP910I Device Capacitance = Neies {8}, 12} EP910 EP9101 Symbol Parameter Conditions Min Max Min Max | Unit Cin Input pin capacitance Vin =0V, f= 1.0 MHz 20 8 pF Cio I/O pin capacitance Vout = 0 V, f = 1.0 MHz 20 8 pF Ceik4 CLK1 pin capacitance Vin =0V, f= 1.0 MHz 20 10 pF Cetke | CLK2 pin capacitance Vin =0V, f= 1.0 MHz 20 12 pF EP910 & EP910I Device Ipc Supply Current = Nieies (8), (8), {8} EP910 EP9101 Symbol Parameter Conditions Min | Typ | Max] Min] Typ | Max | Unit loci Voc supply current Vi = Voc or ground, no load, 20 150 60 150 | vA (non-Turbo, standby) Notes (73), (14) loce Voc supply current V, = Voc or ground, no load, 6 20 4 12 mA (non-Turbo, active) f = 1.0 MHz, Neles (79), (14) lees Voc supply current V, = Vec or ground, no load, 45 80 120 | 150 | mA (Turbo, active) f= 1.0 MHz, Note (74) (100) Notes to tables: (1) See the Opersitne Requirements for Altera Deuices Data Shwet in this data book. (2) Voltage with respect to ground. (3) For EP910 devices, the minimum DC input is -0.3 V; for EP910I devices, the minimum DC input is -0.5 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) Under bias. Extended temperature versions are also available. (5) Numbers in parentheses are for industrial-temperature-range devices. (6) Maximum Vcc rise time for EP910 devices = 50 ms; for EP910I devices, maximum Vcc rise time is unlimited with monotonic rise. (7) For all clocks: tg and tp = 100 ns (50 ns for the industrial-temperature-range version). (8) These values are specified under the EP919 & EPSLO! Device Recommended Operating Conditions on page 444, (9) Typical values are T, = 25 C and Vec =5 V. (10) The Io py, parameter refers to high-level TTL or CMOS output current; the Io, parameter refers to low-level TTL output current. (11) This parameter does not apply to EP910I devices. (12) For EP910 devices: capacitance measured at 25C; sample-tested devices only; clock-pin capacitance for dedicated clock inputs only; pin 21 (high-voltage pin during programming) has a maximum capacitance of 60 pF. Values for EP910I devices are evaluated during initial characterization and design modifications. (13) When the Turbo Bit option is not set (Non-Turbo mode), an EP910 device will enter standby mode if no logic transitions occur for 100 ns after the last transition, and an EP910I device will enter standby mode if no logic transitions occur for 75 ns after the last transition. (14) Measured with a device programmed as a 24-bit counter. Altera Corporation 445Classic EPLD Family Data Sheet EP910 Device AC Operating Conditions = Neies 1}, (2) External Timing Parameters EP910-30 | EP910-35 | EP910-40 Non Turbo Symbol Parameter Conditions | Min | Max} Min | Max} Min| Max} Sete 2) | Unit tpp1 Input to non-registered output C1 = 35 pF 30 35 40 30 ns tpp2 \/O input to non-registered output C1 = 35 pF 33 38 43 30 ns tpzx Input to output enable C1 = 35 pF 30 35 40 30 ns tpxz Input to output disable C1 =5pF, 30 35 40 30 ns Nofe (1) tcLr Asynchronous output clear time C1 = 35 pF 33 38 43 30 ns fax Maximum frequency Note (3) 41.7 37 32.3 0 MHz tsu Global clock input setup time 24 27 31 30 ns ty Global clock input hold time 0 0 0 0 ns ton Global clock high time 12 13 15 0 ns te Global clock low time 12 13 15 0 ns tco1 Global clock to output delay C1 = 35 pF 18 21 24 0 ns tent Global clock minimum clock period | Nee {8} 30 35 40 0 ns font Maximum internal global clock Note 33.3 28.6 25 0 MHz frequency tasu Array clock input setup time 10 10 10 30 ns tan Array clock input hold time 15 15 15 0 ns tacH Array clock high time 15 16 17 0 ns tac. Array clock low time 15 16 17 0 ns topH Output data hold time after clock C1 = 35 pF, 1 1 1 ns Note (73 taco1 Array clock to output delay C1 = 35 pF 33 38 43 30 ns tacnt Array clock minimum clock period 30 35 40 0 ns facnt Max. internal array clock frequency | Nee (8) 33.3 28.6 25 0 MHz 446 Altera CorporationClassic EPLD Family Data Sheet Internal Timing Parameters EP910-30 EP910-35 EP910-40 Symbol Parameter Condition Min | Max | Min | Max | Min | Max | Unit tiny Input pad and buffer delay 9 10 13 ns tio \/O input pad and buffer delay 3 3 3 ns tap Logic array delay 14 16 17 ns lop Output buffer and pad delay C1 = 35 pF 7 9 10 ns tx Output buffer enable delay C1 = 35 pF 7 9 10 ns yz Output buffer disable delay C1=5pF 7 9 10 ns tsu Register setup time 12 13 15 ns ty Register hold time 12 12 12 ns tic Array clock delay 17 19 20 ns tics Global clock delay 2 2 1 ns lep Feedback delay 4 6 8 ns loLr Register clear time 17 19 20 ns Notes to tables: (1) These values are specified under the 910 & EPGLOL Device Recommended Operating Conditions on page 444. (2) See Applicuiion Nole 78 (indersianding MAX S000 & ? Pissing} for more information on Classic timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (6) The fyyax values represent the highest frequency for pipelined data. (6) Measured with a device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. Altera Corporation 447Classic EPLD Family Data Sheet EP910I Device AC Operating Conditions = Notes {7}, {2} Non- External Timing Parameters EP910I-12 | EP910I-15 | EP910I-25 | Turbo Adder Symbol Parameter Conditions | Min] Max} Min} Max} Min | Max} ete (3) | Unit tpp1 Input to non-registered output C1 = 35 pF 12 15 25 40 ns tpp2 I/O input to non-registered output C1 = 35 pF 12 15 25 40 ns tpzx Input to output enable C1 = 35 pF 15 18 28 40 ns tpxz Input to output disable C1 = 35 pF, 15 18 28 40 ns Nate (4) tcLr Asynchronous output clear time C1 = 35 pF 15 18 28 40 ns fax Global clock maximum frequency Nofe (8) 125 100 62.5 0 MHz tsu Global clock input setup time 8 11 16 40 ns ty Global clock input hold time 0 0 0 ns ton Global clock high time 5 6 10 ns te Global clock low time 5 6 10 ns tco1 Global clock to output delay 8 9 14 0 ns tent Global clock minimum clock period C1 =35 pF 13 15 25 40 ns font Maximum internal global clock frequency | Nets {8} 76.9 66.6 40 0 MHz tasu Array clock input setup time 0 2 8 40 ns tan Array clock input hold time 8 9 8 ns tacu Array clock high time 6 7.5 12.5 ns tac. Array clock low time 6 7.5 12.5 ns topH Output data hold time after clock gl = 35 pF, 1 1 1 ns NOS (23 taco1 Array clock to output delay C1 = 35 pF 16 18 22 40 ns tacnt Array clock minimum clock period 13 15 25 40 ns facnt Maximum internal array clock frequency | Afeve (8) 76.9 66.6 40 MHz 448 Altera CorporationClassic EPLD Family Data Sheet Internal Timing Parameters EP9101-12 EP910I-15 EP9101-25 Symbol Parameter Condition Min | Max | Min | Max | Min | Max | Unit tiny Input pad and buffer delay 2 3 2 ns tio \/O input pad and buffer delay 0 0 0 ns trap Logic array delay 8 9 17 ns top Output buffer and pad delay C1 =35 pF 2 3 6 ns tzx Output buffer enable delay C1 =35 pF 5 6 9 ns tyz Output buffer disable delay C1 =5 pF 5 6 9 ns tsy Register setup time 4 5 5 ns ty Register hold time 4 6 11 ns tic Array clock delay 12 12 14 ns tics Global clock delay 4 3 6 ns tep Feedback delay 1 1 3 ns toir Register clear time 11 12 20 ns Notes to tables: (1) These values are specified under the HFO12 (2) See Application Note 78 (inderstandinge MAN 5000 & Classic | timing parameters. (3) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (4) Sample-tested only for an output change of 500 mV. (6) The fyax values represent the highest frequency for pipelined data. (6) Measured with the device programmed as a 24-bit counter. (7) Sample-tested only. This parameter is a guideline based on extensive device characterization and applies for both global and array clocking. PSLOE Device Recommended Operating Concitions on page 444, uabic} in this data book for information on internal Altera Corporation 449Notes:EP1810 EPLD Features @ High-performance, 48-macrocell Classic EPLD - Combinatorial speeds with tpp as fast as 20 ns - Counter frequencies of up to 50 MHz - Pipelined data rates of up to 62.5 MHz Programmable I/O architecture with up to 64 inputs or 48 outputs Programmable clock option for independent clocking of all registers Macrocells individually programmable as D, T, JK, or SR flipflops, or for combinatorial operation @ = Available in the following packages (see Figure 15) - 68-pin ceramic pin-grid array (PGA) - 68-pin plastic J-lead chip carrier (PLCC) Figure 15. EP1810 Package Pin-Out Diagrams Package outlines not drawn to scale. See faite 2 on page 458 of this dala sheet for PGA package pin-out information. Windows in ceramic packages only. a LE00O00OZOND0OONNO SSE 555 05 5555555 PITIC ICI ICICI Pieri ri fit Oomoeonitanrwoareontan L BSS8SBRs QOOQOQOOQOOQOOOOO@ vo chro so H vo | @QOOOOOOOOO gi SB ig VO 12 58 /O 51Q@Q @C) vO Gis 57 VO 4 O) INPUT 14 56 INPUT INPUT E15 56 INPUT G OlO) INPUT C16 54 CLKG/INEUT 117 #3 B CLIG@/INPUT F Cis Bre 520 @ CLK2/INPUT E19 (NOTE A 51 ET GLK3/INPUT E1@@) INPUT G20 50 INPUT INPUT 21 491) INPUT >1@@) INPUT G22 48 INPUT INPUT Ef23 47 VO 88 weg SB 3 Cy 25 45 21QQO 70 C28 EO 1 @O RERSSAGSBSEBBITIY OOOUUOUUOUOUUUOUOUOOOo eee een seen 299999999Q0009099 oO 68-Pin PGA 68-Pin PLCC EP1810 EP1810 Altera Corporation 451Classic EPLD Family Data Sheet General Description 452 Altera EP1810 devices offer large-scale integration (LSI) density, TTL- equivalent speed, and low-power consumption. EP1810 devices have 48 macrocells, 16 dedicated input pins, and 48 I/O pins (see Figure 16). EP1810 devices are divided into four quadrants, each containing 12 macrocells. Of the 12 macrocells in each quadrant, 8 have quadrant feedback and are local macrocells (see Feedback Select on page 25 of this data sheet for more information). The remaining 4 macrocells in the quadrant are global macrocells. Both local and global macrocells can access signals from the global bus, which consists of the true and complement forms of the dedicated inputs and the true and complement forms of the feedbacks from the global macrocells. EP1810 devices also have four dedicated inputs (one in each quadrant) that can be used as quadrant clock inputs. If the dedicated input is used as a clock pin, the input feeds the clock input of all registers in that particular quadrant. Altera CorporationClassic EPLD Family Data Sheet Figure 16. EP1810 Block Diagram Numbers without parentheses are for J-lead packages. Numbers with parentheses are for PGA packages. Quadrant A Quadrant D 2 (F1) Macrocell 48 68 (E1) 3 (G2) Macrocell 47 67 (E2) 4 (G1) < a Macrocell 46 66 (D1) 5 (H2) 5 5 Macrocell 45 85 (D2) 6 (H1) B 3 Macrocell 44 64 (C1) 7 (J2) q q Macrocell 43 63 (C2) 8 (J1) g a Macrocell 42 62 (B1) 9 (K1) 5 = Macrocell 41 61 (B2) 10 (Ke) 8 8 60 (A2) nN (L2) 59 (A3) 12 (K3) 58 (B3) 13 (L3) 57 (A4) 14 (K4) INPUT INPUT 56 (B4) 15 (L4) INPUT INPUT 55 (AS) 16 (K5) INPUT INPUT 54 (BS) 17 (L5) INPUT/CLK1 19 (L6) INPUT/CLK2 INPUT/CLK4 53 (A6) INPUT/CLK3 __ 51 (A7) 20 (K7) INPUT INPUT 50 (B7) 21 (L7) INPUT INPUT 49 (A8) 22 (K8) INPUT INPUT 48 (B8) Quadrant B Quadrant C 23 (L8) 47 (AQ) 24 (KQ) 46 (B9) 25 (L9) om oO 45 (A10) 26 (L10) 5 5 44 (B10) 27 (K10) Macrocell 17 3 3 Macrocell 32 43 (B11) 28 (K11) Macrocell 18 q q Macrocell 31 42 (C11) 29 (J10) Macrocell 19 a a Macrocell 30 41 (C10) 30 (11) Macrocell 20 a a Macrocell 29 40 (D11) 31 (H10) Macrocell 21 8 8 Macrocell 28 39 (D10) 32 (H11) Macrocell 22 - - 27 38 (E11) 33 (G10) Macrocell 23 Macrocell 26 37 (E10) 34 (G11) Macrocell 24 Macrocell 25 36 (F11) EE] Global Macrocells (Local Macrocells Altera Corporation 453Classic EPLD Family Data Sheet Figure 1? shows the typical supply current (Icc) versus frequency for EP1810 EPLDs. Figure 17. Ico vs. Frequency of EP1810 Devices EP1810 loc Active (mA) Typ. 100 0.1 Non-Turbo 10kHz 100 kHz Frequency 1 MHz 10MHz 60 MHz Figure 18 shows the output drive characteristics of EP1810 devices. Figure 18. Output Drive Characteristics of EP1810 Devices Drive characteristics may exceed shown curves. EP1810-20 & EP1810-25 EPLDs 200 -- 6 r 150 - | x OL E = g Vec =5.0V 5 100 F Ta =25C Oo 5 2 3 Oo 50 F- | oO OH ! ! ! ! 1 2 3 4 5 Vo Output Voltage (V) 454 EP1810-35 & EP1810-45 EPLDs 80 - = lot x 60 F- 5 B Te n28C 3 OF = Oo A 5 2 6 | 20+ OH 2 Ll Ll Ll Ll 1 2 3 4 5 Vo Output Voltage (V) Altera CorporationClassic EPLD Family Data Sheet Operating Conditions EP1810 Device Absolute Maximum Ratings Notes (7), The following tables provide information on absolute maximum ratings, recommended operating conditions, operating conditions, and capacitance for EP1810 devices. Symbol Parameter Conditions Min Max Unit Vec Supply voltage With respect to ground, Net 2.0 (0.5) 7.0 Vv Vv DC input voltage With respect to ground, Neve 2.0 (0.5) 7.0 Vv Imax DC Veg or ground current 300 (400) 300 (400) mA lout DC output current, per pin -25 25 mA Tste Storage temperature No bias 65 150 C Tame Ambient temperature Under bias 65 (55) 135 (125) C Ty Junction temperature Under bias (150) C EP1810 Device Recommended Operating Conditions = Nets {2} Symbol Parameter Conditions Min Max Unit Voc Supply voltage Note (4) 4.75 (4.5) 5.25 (5.5) Vv Vv Input voltage Vec Vv Vo Output voltage Veco Vv Ta Operating temperature For commercial use 70 C For industrial use 40 85 C tg Input rise time 50 ns te Input fall time 50 ns EP1810 Device DC Operating Conditions = Netes (8), {7} Symbol Parameter Conditions Min Max Unit Vin High-level input voltage 2.0 Voc + 0.3 Vv Vit Low-level input voltage 0.3 0.8 Vv Vou High-level TTL output voltage lon =-4 mA DC, Note (8) 2.4 Vv High-level CMOS output voltage lou = 0.6 mA DC, Nate (8) 3.84 Vv VoL Low-level output voltage lol = 4 mA DC, Note (&) 0.45 Vv I, \/O pin leakage current of dedicated | V| = Vcc or ground -10 10 HA input pins loz Tri-state output leakage current Vo = Voc or ground -10 10 HA Altera Corporation 455Classic EPLD Family Data Sheet EP1810 Device Capacitance = Nate {8} Symbol Parameter Conditions Min Max | Unit Cin Input pin capacitance Vin = 0 V, f= 1.0 MHz 20 pF Cio \/O pin capacitance Vout = 0 V, f = 1.0 MHz 20 pF Cex Clock pin capacitance Vin =0V, f= 1.0 MHz 25 pF EP1810 Device Ico Supply Current = Notes 2}, (8), (7? EP1810 Symbol Parameter Conditions Speed | Min Typ Max | Unit Grade lees Voc supply current V. = Vee or ground, no load, | -20, -25 50 150 HA (non-Turbo, standby) Note (10) -35, -45 35 150 LA lece Voc supply current V. = Vec or ground, no load, | -20, -25 20 40 mA (non-Turbo, active) f= 1.0 MHz, Note (78) -35, -45 10 30 (40) | mA lees Voc supply current (Turbo, active) | V; = Voc or ground, no load | -20, -25 180 225 (250) | mA f= 1.0 MHz, Nofe (70) -35, -45 100 | 180 (240)} mA Notes to tables: (1) See the Opersiing Requirements for Altera Devices Data Sheet in this data book. (2) Numbers in parentheses are for industrial-temperature-range devices. (3) The minimum DC input is -0.3 V. During transitions, the inputs may undershoot to -2.0 V or overshoot to 7.0 V for periods less than 20 ns under no-load conditions. (4) Maximum Vcc rise time is 50 ms. (6) For EP1810 clocks: tg and tp = 100 ns (50 ns for industrial-temperature-range versions). (6) Typical values are for T, = 25 C and Vcc =5 V. (7) These values are specified under the fPi819 Devic (8) The Icy parameter refers to high-level TTL or CMOS output current; the Ip, parameter refers to low-level TTL output current. (9) Capacitance measured at 25 C. Sample-tested only. Clock-pin capacitance for dedicated clock inputs only. Pin 19 has a maximum capacitance of 160 pF. (10) Measured with a device programmed as four 12-bit counters. 456 Altera CorporationClassic EPLD Family Data Sheet EP1810-20 & EP1810-25 AC Device Operating Conditions Note (} External Timing Parameters EP1810-20 | EP1810-25 Non Turbo Symbol Parameter Conditions Min | Max} Min] Max| Aefes2) | Unit tpp1 Input to non-registered output C1 = 35 pF 20 25 25 ns tpp2 \/O input to non-registered output C1 = 35 pF 22 28 25 ns tsu Global clock setup time 13 17 25 ns ty Global clock hold time 0 0 ns tou Global clock high time 10 0 ns te Global clock low time 10 0 ns tco1 Global clock to output delay C1 = 35 pF 15 18 0 ns tent Minimum global clock period Nofe (9) 20 25 0 ns font Maximum internal frequency Nate (3) 50 40 0 MHz tasu Array clock setup time 10 25 ns tan Array clock hold time 10 0 ns taco1 Array clock to output delay C1 = 35 pF 20 25 25 ns topH Output data hold time after clock C1 = 35 pF, Nate (4) 1 1 ns tacnt Array clock maximum clock period Note (3) 20 25 ns facnt Maximum internal array clock Nofe (3) 50 40 ns frequency fax Maximum clock frequency Note (8) 62.5 50 0 MHz Internal Timing Parameters EP1810-20 | EP1810-25 Non Turbo Symbol Parameter Conditions Min | Max} Min] Max] Aefe2) | Unit tiny Input pad and buffer delay 5 7 0 ns tio \/O input pad and buffer delay 2 3 0 ns tap Logic array delay 9 12 25 ns lop Output buffer and pad delay C1 = 35 pF 6 6 0 ns tx Output buffer enable delay C1 = 35 pF 6 6 0 ns tyz Output buffer disable delay C1 =5pF, Nove (8} 6 6 0 ns tsu Register setup time 10 0 ns ty Register hold time 10 0 ns tic Array clock delay 9 12 25 ns tics Global clock delay 4 0 ns tep Feedback delay 3 -25 ns loLr Register clear time 9 12 25 ns Altera Corporation 457Classic EPLD Family Data Sheet EP1810-35 & EP1810-45 Device AC Operating Conditions Note (} External Timing Parameters EP1810-35 | EP1810-45 Non Turbo Symbol Parameter Conditions Min | Max} Min| Max| Nefe2) | Unit tpp1 Input to non-registered output C1 = 35 pF 35 45 30 ns tpp2 \/O input to non-registered output C1 = 35 pF 40 50 30 ns tsu Global clock setup time 25 30 30 ns ty Global clock hold time 0 0 0 ns tou Global clock high time 12 15 0 ns te Global clock low time 12 15 0 ns tco1 Global clock to output delay C1 = 35 pF 20 25 0 ns tent Minimum global clock period Nofe (9) 35 45 0 ns font Maximum internal frequency Nate (3) 28.6 22.2 0 MHz tasu Array clock setup time 10 11 30 ns tan Array clock hold time 15 18 0 ns taco1 Array clock to output delay C1 = 35 pF 35 45 30 ns topH Output data hold time after clock C1 = 35 pF, Nate (4) 1 1 ns tacnt Array clock maximum clock period Note (3) 35 45 ns facnt Maximum internal array clock Nofe (3) 28.6 22.2 ns frequency fax Maximum clock frequency Note (8) 40 33.3 0 MHz Internal Timing Parameters EP1810-35 | EP1810-45 Non Turbo Symbol Parameter Conditions Min | Max} Min| Max| = Nefe (2) | Unit tiny Input pad and buffer delay 7 6 ns tio \/O input pad and buffer delay 5 5 0 ns tap Logic array delay 19 28 30 ns lop Output buffer and pad delay C1 = 35 pF 9 11 0 ns tx Output buffer enable delay C1 = 35 pF 9 11 0 ns tyz Output buffer disable delay C1 =5pF, Nove (8} 9 11 0 ns tsu Register setup time 10 10 0 ns ty Register hold time 15 18 0 ns tic Array clock delay 19 28 30 ns tics Global clock delay 0 ns tep Feedback delay -30 ns loLr Register clear time 24 32 30 ns 458 Altera CorporationClassic EPLD Family Data Sheet Notes to tables: (1) These values are specified under the fPi810 Device Recommended Operating Conditions on page 458. (2) The non-Turbo adder must be added to this parameter when the Turbo Bit option is off. (3) Measured with a device programmed as four 12-bit counters. (4) Sample-tested only. This parameter is a guideline based on extensive device characterization. This parameter applies for both global and array clocking. (6) The fyyax values represent the highest frequency for pipelined data. (6) Sample-tested only for an output change of 500 mV. Pin-Out Table 2 provides pin-out information for EP1810 devices in 68-pin PGA Information Packages. Table 2. EP1810 PGA Pin-Outs Pin Function Pin Function | Pin Function | Pin Function A2 1/0 Bg VO F10 GND K4 INPUT A3 I/O B10 VO F11 VO K5 INPUT A4 //O0 B11 V0 Gi V0 K6 VCC A5 INPUT C1 V0 G2 V0 K7 INPUT A6 CLK4/INPUT | C2 V0 G10 V0 K8 INPUT A7 ~ CLK3/INPUT | C10 V0 G11 V0 Kg I/O A8 INPUT C11 V0 H1 V0 K10 I/O AQ I/O D1 V0 H2 V0 K11 I/O A10 //O D2 V0 H10 V0 L2 W/O B1 V0 D10 V0 H11 V0 L3 VO B2 I/O D11 V0 J1 V0 L4. INPUT B3 I/O E1 V0 J2 V0 L5 = CLK1I/INPUT B4 INPUT E2 V0 J10 V0 L6 CLK2/INPUT B5 INPUT E10 V0 J11 V0 L7 INPUT B6 VCC E11 V0 K1 V0 L8 VO B7 INPUT F1 V0 K2 V0 Lg VO B8 INPUT F2 GND K3 V0 L10 I/O Altera Corporation 459