Am29LV040B-60RJC - Advanced Micro Devices

July 2003

The following document specifies Spansion memory products that are now offered by both Advanced

Micro Devices and Fujitsu. Although the document is marked with the name of the company that orig-

inally developed the specification, these products will be offered to customers of both AMD and

Fujitsu.

Continuity of Specifications

There is no change to this datasheet as a result of offering the device as a Spansion product. Any

changes that have been made are the result of normal datasheet improvement and are noted in the

document revision summary, where supported. Future routine revisions will occur when appropriate,

and changes will be noted in a revision summary.

Continuity of Ordering Part Numbers

AMD and Fujitsu continue to support existing part numbers beginning with “Am” and “MBM”. To order

these products, please use only the Ordering Part Numbers listed in this document.

For More Information

Please contact your local AMD or Fujitsu sales office for additional information about Spansion

memory solutions.

Am29LV040B

Data Sheet

Publication Number 21354 Revision EAmendment 0 Issue Date March 12, 2003

This Data Sheet st ates AMD’ s current specifi cations regarding the Produc ts described herei n. This Data Sheet may

be revised by subsequent versions or modifications due to changes in technical specificat ions . Publication# 21354 Rev: EAmendment/0

Issue Date: March 12, 2003

Am29LV040B

4 Megabit (512 K x 8-Bit)

CMOS 3.0 Volt-only, Uniform Sector 32-Pin Flash Memory

DISTINCTIVE CHARACTERISTICS

■Single power supply operation

— Full voltage range: 2.7 to 3.6 volt read and write

operations for battery-powered applications

— Regulated voltage range: 3.0 to 3.6 volt read and

write operations and for compatibility with high

performance 3.3 volt microprocessors

■Manufactured on 0.32 µm process technology

■High performance

— Full voltage range: access times as fast as 70 ns

— Regulated voltage range: access times as fast as

60 ns

■Ultra low power consumption (typical values at

5MHz)

— Automatic sleep mode: 0.2 µA

— Standby mode: 0.2 µA

— Read mode: 7 mA

— Program/erase mode: 15 mA

■Flexible sector architecture

— Eight 64 Kbyte sectors

— Any combination of sectors can be erased;

supports full chip erase

— Sector Protection features:

Hardware method of locking a sector to prevent

any program or erase operations within that sector

Sectors can be locked via programming

equipment

■Unlock Bypass Program Command

— Reduces overall programming time when issuing

multiple program command sequences

■Embedded Algorithms

— Embedded Erase algorithms automatically

preprogram and erase the entire chip or any

combination of designated sectors

— Embedded Program algorithms automatically

writes and verifies data at specifi ed addresses

■Minimum 1,000,000 erase cycl es guaranteed

■20-year data retention at 125°C

— Reliable operation for the life of the system

■Package option

— 32-pin PLCC

— 32-pin TSOP

■Compatibility with JEDEC standards

— Pinout and software compatible with single-

power supply Flash

— Superior inadvertent write protection

■Data# Polling and toggle bits

— Provides a software method of detecting program

or erase cycle completion

■Erase Suspend/Resume

— Supports reading data from or programming data

to a sector not being erased

2 Am29LV040B March 12, 2003

GENERAL DESCRIPTION

The Am29LV040B is a single power supply, 4 Mbit, 3.0

Volt-o nly Flash memory device organized as 524,288

bytes. The data appears on DQ0-DQ7. The device is

available in 32-pin PLCC and 32-pin TSOP packages. All

read, erase, and program operations are accomplished

using only a single power supply. The device can also be

programmed in standard EPROM programmers.

The device of fers access times of 60, 70, 90, and 120 ns

allowing high speed microprocessors to operate without

wait states. To eliminate bus contention, the device has

separate control pins—chip enabl e (CE#), write enable

(WE#), and output enable (OE#)—to control normal

read and write operations.

The device requires only a single power supply (2.7

V–3.6V) for both read and write functions. Internally

generated and regulated voltages are provided for the

program and erase operations.

The device is entirely command set compatible with the

JEDEC single-power-supply Flash standard. Com-

mands are written to the command register using

standard microprocessor write timings. Register con-

tents serve as input to an internal state-machine that

controls the erase and programming circuitry. Write

cycles also int ernally latch addresses and data needed

for the programming and erase operations. Reading

data out of the device is similar to reading from other

Flash or EPROM devices.

Device programming occurs by executing the pr ogram

command sequence. This initiates the Embedded

Program algorithm—an internal algorithm that auto-

matically times the program pulse widths and verifies

proper cell margin. The Unlock Bypass mode facili-

tates faster programming times by requiring only two

write cycles to program data instead of four.

Device erasure occurs by executing the erase

command sequence. This initiates the Embedded

Erase algorithm—an internal algorithm that automatically

preprograms the array (if it is not already programmed)

before executing the erase operation. During erase,

the device automatically times the erase pulse widths

and verifies proper cell margin.

The host system can detect whether a program or

erase operation is complete by reading the DQ7 (Data#

Polling) and DQ6 (toggle) status bits . After a prog ram

or erase cycle has be en completed, the device is ready

to read array data or accept another command.

The sector erase architecture allows memory sectors

to be erased and reprogrammed without affecting the

data contents of other sectors. The device is fully

erased when shipped from the factory.

Hardware data protection measures include a low

VCC detector that automatically inhibits write opera-

tions during power transitions. The hardware sector

protection feature disables both program and erase

operations in any combination of the sectors of

memory. This is achieved via p rogramming equipment.

The Erase Suspend feature enables the user to put

erase on hold for any period of time to read data from,

or program data to, any sector that is not selected for

erasure. T rue background erase can thus be achieved.

The device offers two power-saving features. When

addresses have been stable for a specified amount of

time, the device enters the automatic sleep mode.

The system can also place the device into the standby

mode. Power consumption is greatly reduced in both

these modes.

AMD’s Flash technology combines years of Flash

memory manufacturing experience to produce the

highest levels of quality, reliability and cost effective-

ness. The device electrically erases all bits within a

sector simultaneously via Fowler-Nordheim tunneling.

The data is programmed using hot electron injection.

March 12, 2003 Am29LV040B 3
TABLE OF CONTENTS
Product Selecto r Guide  . . . . . . . . . . . . . . . . . . . . .4
Bloc k  Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .  4
Connection Diagram s  . . . . . . . . . . . . . . . . . . . . . . .5
Pin Configuration  . . . . . . . . . . . . . . . . . . . . . . . . . .6
Logic Symbol   . . . . . . . . . . . . . . . . . . . . . . . . . . . .  6
Orderin g Information  . . . . . . . . . . . . . . . . . . . . . . .7
Device Bus Operations . . . . . . . . . . . . . . . . . . .  . . .8
Table 1. Am29LV040B Device Bus Operations . ...............................8
Requirements for Read ing Array Data ............................. ....... .8
Writing Commands/Command Sequences  .............. ................8
Program and Erase Operation Status . ................................... ..9
Standby Mode ......... ................................. ......... ..................... ..9
Automatic Sleep Mode  ................. .......................... ......... .........9
Output Disable Mode ................................................................9
Table 2. Am29LV040BT Sector Address Table ................................9
Autosele ct Mode ............ ........ ......... ........ ......... ......... ........ ........9
Table 3. Am29LV040B Autoselect Codes (High Voltage Method) ..10
Sector Protection/Unprotection ...............................................10
Hardware Data Protection ......................................................10
Low VCC Write Inhibit ......................................................................10
Write Pul se  “Glitch” Protection ............ ................ ................ ............10
Logical Inhibit ................................. ....... ....... ......... ....... ......... ....... ...1 0
Power-Up Write  In h ibit ...... ........... ..................... ................ ..............10
Command Defi nitions  . . . . . . . . . . . . . . . . . . . . . .11
Reading Array Data ................................................................11
Reset Command ... ................. ................. ......... ......... ..............11
Autoselect Command Sequence .. .............. ..... .......................11
Byte Program Command Sequence ....... ................................11
Unlock Bypass Command Sequence ................................ .. ..... ..... ..12
Chip Erase Command Sequence ...........................................12
Figur e 1. Pro g r a m Oper a tion...................... .............................. ...... 12
Sector Erase Command Sequence ........................................13
Erase Suspend/Erase Resume Commands ........... ................13
Figur e 2. Era se  Ope r a ti o n............. .......................... .................... .... 14
Command Defi nitions ............................. ......... .......................15
Table 4. Am29LV040B Command Def initions  ................................. 15
Write Operation Status . . . . . . . .  . . . . . . . . . . . . .16
DQ7: Data# Polling .................................................................16
Figure 3. Data# Polling Algorithm ................................................... 16
DQ6: Toggle Bit I ....................................................................17
DQ2: Toggle Bit II ...................................................................17
Reading Toggle Bits DQ6/DQ2 ..............................................17
Figure 4. Toggle Bit Algorithm......................................................... 18
DQ5: Exceeded Timing Limits ................................................18
DQ3: S e cto r  Er a se  Tim e r ....... ... .. ......... ... ......... ... ......... ... .......18
Table 5. Write Operatio n  Sta tus ................. ..................... ...............19
Absolute Maximum Ratings  . . . . . . . . . . . . . . . . 20
Figure 5. Maximum Negative Overshoot Waveform...................... 20
Figure 6. Maximum Po sitive Ov ershootWaveform....... ................. 20
Operating Ranges. . . . . . . . . . . . . . . . . . . . . . . . . 20
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. ICC1 Current vs. Time (Showing Active and Automatic 
SleepCurrents).................. .................... ..................... ................... 22
Figure 8. Typical ICC1 vs. Frequency.......................... .. ....... ..... .. ... 22
Test Conditions  . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figur e 9. Te st Setup.... ................ ......................... ..........................  23
Table 6. Test Specifications ...........................................................2 3
Key to Switching Waveforms. . . . . . . . . . . . . . . . 23
Figure 10. Input Waveforms and Measurement Levels................. 23
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Operations  ....................................................................24
Figure 11. Read Operations Timings.............................. ...............  24
Erase/Program Operations .....................................................25
Figure 12. Program Operation Timings.......................................... 26
Figure 13. Chip/Sector Erase Operation Timings .......................... 26
Figure 14. Data# Polling Timings (During Embedded Algorithms). 27
Figure 15. Toggle Bit Timings (During Embedded Algorithms)......  27
Figur e 16 . DQ2 vs. DQ6................ ..................... ..................... ....... 28
Alternate CE# Controlled Erase/Program Operations ........ ....29
Figure 17. Alternate CE# Controlled Write Operation Tim ing s ......  30
Erase and Prog ramming  Perf ormance   . . . . . . . 31
Latchup C haracteristics. . . . . . . . . . . . . . . . . . . . 31
TSOP and SO Pin Capacitance . . . . . . . . . . . . . . 31
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 32
TS 032— 3 2 -P i n  Sta n da rd  TS OP ... ... ......... ... ......... .. .......... .. ...32
TSR032—32-Pin Reverse TSOP ...........................................33
PL 032—32-Pin Plastic Leaded Chip Carrier .........................34
Re v is ion Sum ma ry . . . . . . . . . . . . . . . . . . . . . . . . 3 5
Revis i o n A (Ja nu a ry  1 99 8 ) ..... ... ......... .. .......... .. .......... .. ..........35
Revision B (April 1998) ...........................................................35
Revision B+1 (November 1998) ............ ..... ....... .....................35
Revision C (January 1999) ............................ ..... ....................35
Revision C+1 (May 18, 1999) .................................................35
Revision C+2 (July 20, 1999) ................... .......................... ....35
Revision D (November 11, 1999)  ...........................................35
Revision D+1 (November 13, 2000) .......................................35
Revision E (March 12, 2003) ..................................................35

4 Am29LV040B March 12, 2003

PRODUCT SELECTOR GUIDE

Note: See “AC Characteristi cs” for full spe cifications.

BLOCK DIAGRAM

Family Part Number Am29LV040B

Speed Options Regulated Voltage Range: VCC =3.0–3.6 V -60R

Full Voltage Range: VCC = 2.7–3.6 V -70 -90 -120

Max access time, ns (tACC) 60 70 90 120

Max CE# access time, ns (tCE) 60 70 90 120

Max OE# access time, ns (tOE)30303035

Input/Output

Buffers

X-Decoder

Y-Decoder

Chip Enable

Output Enable

Logic

Erase Voltage

Generator

PGM Voltage

Generator

Timer

VCC Detector

State

Control

Command

VCC

VSS

WE#

CE#

OE#

STB

DQ0–DQ7

Sector Switches

Data

Latch

Y-Gating

Cell Matrix

Address Latch

A0–A18

March 12, 2003 Am29LV040B 5

CONNECTION DIAGRAMS

DQ6

A18

DQ5

DQ4

DQ3

13130234

13 17 18 19 2016

DQ0

A14

A13

A11

OE#

A10

CE#

DQ7

A12

A15

A16

VCC

WE#

A17

DQ1

DQ2

VSS

32-Pin PLCC

A11

A13

A14

A17

WE#

VCC

A18

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

32-pin Sta nda rd TSOP

A11

A13

A14

A17

WE#

VCC

A18

A16

A15

A12

OE#

A10

CE#

DQ7

DQ6

DQ5

DQ4

DQ3

VSS

DQ2

DQ1

DQ0

32-Pin Reverse TSOP

6 Am29LV040B March 12, 2003

PIN CONFIGURATION

A0–A18 = 19 address inputs

DQ0–DQ7 = 8 data inputs/outputs

CE# = Chip enable

OE# = Output enable

WE# = Write enable

VCC = 3.0 volt-only single power supply

(see Product Selector Guide for speed

options and volt age supply toleranc es)

VSS = Device ground

LOGIC SYMBOL

19 8

DQ0–DQ7

A0–A18

CE#

OE#

WE#

March 12, 2003 Am29LV040B 7

ORDERING INFORMATION

Standard Products

AMD standard products are available in several packages and operating ranges. The order number (Valid Combi-

nation) is formed by a combination of the elements below.

Valid Combinations

Valid Combinations list configurations planned to be sup-

ported in volume for this device. Consult the local AMD sales

office to confirm availability of specific valid combinations and

to check on newly released combinations.

Am29LV040B -60R E C

TEMPERATURE RANGE

C = Commercial (0°C to +70°C)

I = Industrial (–40°C to +85°C)

E = Extended (–55°C to +125°C)

PA CKAGE TYPE

J = 32-Pin Plastic Leaded Chip Carrier (PL 032)

E = 32-Pin Thin Small Outline Package (TSOP)

Standard Pinout (TS 032)

F = 32-Pin Thin Small Outline Package (TSOP)

Reverse Pinout (TSR032)

SPEED OPTION

See Product Selector Guide and Valid Combinations

DEVICE NUMBER/DESCRIPTION

Am29LV040B

4 Megabit (512 K x 8-Bit) CMOS Flash Memory

3.0 Volt-only Read, Program and Erase

Valid Combinations

AM29LV040B-60R JC, JI, EC, EI, FC, FI

AM29LV040B-70 JC, JI, JE,

EC, EI, EE,

FC, FI, FE

AM29LV040B-90

AM29LV040B-120

8 Am29LV040B March 12, 2003
  
DEVICE BUS OPERATIONS
This section des cribes the re quirements and us e of  the
device bus operations, which are initiated through the
internal command register . The command register itself
does not occupy any addressable memory location.
The register is composed of  latches that  store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the
inputs and control levels t hey require, and the res ulting
output. The following subsections describe each of
these operations in further detail.
Table 1. Am29LV040B Device Bus Operations
Legend:
L = Logic Low = VIL, H = Logic High = VIH, VID = 12.0 ± 0.5  V, X = Don’t  Ca r e,  A IN = Address In, DIN = Data In, DOUT = Data Out
Notes:
1. Addresses are A18–A0.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector 
Protection/Unprotection” section. 
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to VIL. CE# is the power
control and selects the device. OE# is the output
control and gates array data to the output pins. WE#
should remain at VIH. 
The internal state machine is set for reading array data
upon device power-up, or after a hardware reset. This
ensures that no spurious alteration of the memory
content occurs during the power transition. No
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that assert
valid addresses on the device address inputs produce
valid data on the device data outputs. The device
remains enabled for read access until the command
register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to Figure 1 1 for the timing diagram. ICC1 in the
DC Characteristics table represents the active current
specification for reading array data.
Writing Commands/Command Sequences
To write a command or command sequence (which
includes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to VIL, and OE# to VIH.
The device features an Unlock Bypass mode to facil-
itate faster programming. Once the device enters the
Unlock Bypass mode, only two write cycles are
required to program a byte, instead of four. The “Byte
Program Command Sequence” section has details on
programming data to the device using both standard
and Unlock Bypass command sequences.
An erase operat ion can e rase one  sector, multipl e s ec-
tors, or the entire  device. Table 2 indicates the address
space that each sector occupies. A “sector address”
consists of the address bits required to uniquely select
a sector. The “Command Definitions” section has
details on erasing a sector or the entire chip, or sus-
pending/resuming the erase operation.
After the system writes the autoselect command
sequence, the device enters the  autoselect mode. The
system can then read autoselect codes from the
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings
Operation CE# OE# WE# Addresses (Note 1) DQ0–DQ7
Read L L H AIN DOUT
Write L H L AIN DIN
Standby VCC ± 0.3 V X X X High-Z
Output Disable L H H X High-Z
Reset X X X X High-Z
Sector Protect (Note 2) L H L Sector Address, A6 = L, A1 = H, A0 = L DIN, DOUT
Sector Unprotect (Note 2) L H L Sector Address, A6 = H, A1 = H, A0 = L DIN, DOUT
Temporary Sector Unprotect X X X AIN DIN

March 12, 2003 Am29LV040B 9
apply in this mode. Refer to the Autoselect Mode and
Autoselect Command Sequence sections for more
information.
ICC2 in the DC Characteristics table represents the
active current spec ification for the write mode.  The “AC
Characteristics” section contains timing specification
tables and timing diagrams for write operations.
Program and Erase Operation Status
During an erase  or program operat ion, the s ystem may
check the status of the operat ion by reading the status
bits on DQ7–DQ0. Standard read  cycle timings and ICC
read specifications apply. Refer to “Write Operation
Status” for more information, and to “AC Characteris-
tics” for timing diagrams.
Standby Mode
When the system is not  reading or writing to the devic e,
it can place the device in the standby mode. In this
mode, current consumption is  greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input. 
The device enters the CMOS standby mode when the
CE# pin is both held at VCC ± 0.3 V. (Note that this is a
more restricted voltage range than VIH.) If CE# is held
at VIH, but not within VCC ±  0.3 V, the device will be in
the standby mode, but the standby current will be
greater. The device requires standard access time
(tCE) for read access when the device is in either of
these standby modes, before it is ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
ICC3 in the DC Characteristics table represents the
standby current specification. 
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically
enables this mode when addresses remain stable for
tACC + 30 ns. The automatic sleep mode is indepen-
dent of the CE#, WE#, and OE# control signals.
Standard address access timings provide new data
when addresses are changed. While in sleep mode,
output data is latched and always available to the
system. ICC4 in the DC Character istics table represents
the automatic sleep mode current specification.
Output Disable Mode
When the OE# input is at VIH, output  from the device is
disabled. The output pins are placed in the  high imped-
ance state.
Table 2. Am29LV040BT Sector Address Table
Autoselect Mode
The autoselect mode provides manufacturer and
device identification, and sector protection verific ation,
through identifier codes output on DQ7–DQ0. This
mode is primarily intended for programming equipment
to automatically match a device to be programmed with
its corresponding programming algorithm. However,
the autoselect codes can also be accessed in-system
through the command register.
When using programming equipment, the autoselect
mode requires VID (11.5 V to 12.5 V) on address pin
A9. Address pins A6, A1, and A0 must be as shown in
Table 3. In addition, when verifying sector protection,
the sector address must appear on the appropriate
highest order address bits  (see Table 2). Table 3 shows
the remaining address bit s that are don’t care. When all
necessary bits have been set as required, the program-
ming equipment may then read the corresponding
identifier code on DQ7–DQ0.
To access the autoselect codes in-system, the host
system can issue the autoselect command via the
command register, as shown in Table 4. This method
does not require VID. See “Command Definitions” for
details on using the autoselect mode.
Sector A18 A17 A16 Address Range
(in hexadecimal)
SA0 0 0 0 00000h-0FFFFh
SA1 0 0 1 10000h-1FFFFh
SA2 0 1 0 20000h-2FFFFh
SA3 0 1 1 30000h-3FFFFh
SA4 1 0 0 40000h-4FFFFh
SA5 1 0 1 50000h-5FFFFh
SA6 1 1 0 60000h-6FFFFh
SA7 1 1 1 70000h-7FFFFh

10 Am29LV040B March 12, 2003

Table 3. Am29LV040B Autoselect Codes (High Voltage Method)

L = Logic Low = VIL, H = Logic High = VIH, SA = Sector Address, X = Don’t care.

Sector Protection/Unprotection

The hardware sector protection feature disables both

program and erase o peratio ns in any s ector. The hard-

ware sector unprotection feature re-enables both

program and erase operations in previously protected

sectors.

Sector protection/unprotection method intended only

for programming equipment requires VID on address

pin A9 and OE#. This method is compatible with pro-

grammer routines written for earlier 3.0 volt-only AMD

flash devices. Publication number 22168 contains

further details; contact an AMD representative to

request a copy.

The device is shipped with all sectors unprotected.

AMD offers the option of programming and protecting

sectors at its factory prior to shipping the device

through AMD’s ExpressFlash™ Service. Contact an

AMD representative for details.

It is possible to determine whether a sector is protected

or unprotected. See “Auto select Mode” for details.

Hardware Data Protection

The command sequence requirement of unlock cycles

for programming or erasing provides data protection

against inadvertent writes (refer to Table 4 for

command definitions). In addition, the following hard-

ware data protection measures prevent accidental

erasure or programming, which might otherwise be

caused by spurious system level signals during VCC

power-up and power-down transitions, or from system

noise.

Low VCC Write Inhibit

When VCC is less than VLKO, the device does not

accept any write cycles. This protects data during VCC

power-up and power-down. The command register and

all internal program/erase circuit s are disabled, and the

device resets. Subsequent writes are ignored until VCC

is greater than VLKO. The system must provide the

proper signals to the control pins to prevent uninten-

tional writes when VCC is greater than VLKO.

Write Pulse “Glitch” Protection

Noise pulses of less than 5 ns (typical) on OE#, CE# or

WE# do not initiate a write cycle.

Logical In hibit

Write cycles are inhibited by holding any one of OE# =

VIL, CE# = VIH or W E# = V IH. To initiate a write cycle,

CE# and WE# must be a logical zero while OE# is a

logical one.

Po we r - Up Wri t e In hibit

If WE# = CE# = VIL and OE# = VIH during power up, the

device does not accept commands on the rising edge

of WE#. The internal state machine is automatically

reset to reading array data on power-up.

Description CE# OE# WE#

A18

A16

A15

A10 A9

A7 A6

A2 A1 A0

DQ7

DQ0

Manufacturer ID: AMD L L H X X VID XLXLL 01h

Device ID: Am29LV040B L L H X X VID XLXLH 4Fh

Sector Protec tion Verification L L H SA X VID XLXHL

01h

(protected)

00h

(unprotected)

March 12, 2003 Am29LV040B 11
COMMAND DEFINITIONS
Writing specific address and data commands or
sequences into the command register initiates device
operations. Table 4 def ines the v alid register command
sequences. Writing incorrect address and data values
or writing them in the improper sequence may place
the device in an unknown state. A reset command is
then required to r eturn the device to read ing array data.
All addresses are latched on the falling edge of  WE# or
CE#, whichever happens later. All data is latched on
the rising edge of WE# or CE#, whichever happens
first. Refer to the appropriate timing diagrams in the
“AC Characteristics” section.
Reading Array Data
The device is automatically set to reading array data
after device power-up. No commands are required to
retrieve data. The device is also ready to read array
data after completing an Embedded Program or
Embedded Erase algorithm.
After the device  accepts an E rase Suspend command,
the device enters the Erase Suspend mode. The
system can read array data using the standard read
timings, except that if it reads at an address within
erase-suspended sectors, the device outputs status
data. After completing a programming operation in the
Erase Suspend mode, the system may once again
read array data with the same exception. See “Erase
Suspend/Erase Resume Commands” for more infor-
mation on this mode.
The system must issue the reset command to re-
enable the device for reading array data if DQ5 goes
high, or while in the autoselect mode. See the “Reset
Command” section, next.
See also “Requirements for Reading Array Data” in the
“Device Bus Operations” section for more information.
The Read Operations table provides the read parame-
ters, and Figure 11 shows the timing diagram.
Reset Command
Writing the reset command to the device resets the
device to reading array data. Address bits are don’t
care for this command. 
The reset command may be written between the
sequence cycles in an erase command sequence
before erasing begins. This resets the device to
reading array data. Once erasure begin s, however, the
device ignores reset commands until the operation is
complete.
The reset command may be written between the
sequence cycles in a program command sequence
before programming begins. This resets the device to
reading array data (also applies to programming in
Erase Suspend mode). Once programming begins,
however, the device ignores reset commands until the
operation is complete.
The reset command may be written between the
sequence cycles in an autoselec t command sequence.
Once in the  autoselect  mode, the  reset command  must
be written to return to reading array data (also applies
to autoselect during Erase Suspend).
If DQ5 goes high  during a program or  erase operation,
writing the reset command returns the device to
reading array data (also applies during Erase
Suspend).
Autoselect Command Sequence
The autoselect command sequence allows the host
system to access the manufacturer and devices codes,
and determine whether or not a sector is protected.
Table 4 shows the address and data requirements.
This method is an alternative to that shown in Table 3,
which is intended for PROM programmers and requires
VID on address bit A9.
The autoselect command sequence is initiated by
writing two unlock cycles, followed by the autoselect
command. The device then enters the autoselect
mode, and the system may read at any address any
number of times, without initiating another command
sequence. A read cycle at address 00h retrieves the
manufacturer code. A read cycle at address 01h
returns the device code. A read cycle containing a
sector address (SA) and the address 02h return s 01h if
that sector is protected, or 00h if it is unprotected. Refer
to Table 2 for valid sector addresses.
The system must write the reset command to exit the
autoselect mode and return to reading array data.
Byte Program Command Sequence
The byte program command sequence programs one
byte into the device. Programming is a four-bus-cycle
operation. The program command sequence is initi-
ated by writing two unlock write cycles, f ollowed by the
program set-up command. The program address and
data are written next, which in turn initiate the
Embedded Program algorithm. The system is not
required to provide further controls or timings. The
device automatically provides internally generated
program pulses and verify the programmed cell
margin. Table 4 shows the address and data require-
ments for the byte program command sequence. Note
that the autoselect function is unavailable when a
program operation is in progress. 
When the Embedded Program algorithm is complete,
the device then returns to reading array data and
addresses are no longer latched. The system can
determine t he status of  the program  operation by  using

12 Am29LV040B March 12, 2003
  
DQ7 or DQ6. See “Wri te Operation Statu s” for informa-
tion on these status bits . 
Any commands written to the device during the
Embedded Program Algorithm are  ignored. Note  that a
hardware reset immediately terminates the program-
ming operation. The Byte Program command
sequence should be reinitiated once the device has
reset to reading array data, to ensure data integrity.
Programming is allowed in any sequence and across
sector boundaries. A bit cannot be programmed
from a “0” ba ck to a “1”. Attempt ing to do so may halt
the operation and set DQ5 to “1”, or cause the Data#
Polling algorithm to indicate the operation was suc-
cessful. However, a succeeding read will show that the
data is still “0”. Only erase operat ions can convert a “0”
to a “1”.
Unlock Bypass Command Sequence
The unlock bypass feature allows the system to
program bytes to t he devic e fast er than us ing the s tan-
dard program command sequence. The unlock b ypass
command sequence is initiated by first writing two
unlock cycles. This is followed by a third write cycle
containing the unlock bypass command, 20h. The
device then enters the unlock bypass mode. A two-
cycle unlock bypass program command sequence is all
that is required to program in this mode. The first cycle
in this sequence contains the unlock bypass program
command, A0h; the s econd  cycl e contains the program
address and data. Additional data is programmed in
the same manner. This mode dispenses with the initial
two unlock cycles required in the standard program
command sequence, resulting in faster total program-
ming time. Table 4 shows the requirements for the
command sequence.
During the unlock bypass mode, only the Unlock
Bypass Program and  Unlock Bypass Reset  commands
are valid. To exit the unlock bypass mode, the system
must issue the two-cycle unlock bypass reset
command sequence. The first cycle must contain the
data 90h; the second cycle the data 00h. The device
then returns to reading array data.
Figure 1 illustrates the algorithm for the program oper-
ation. See the Erase/Program Operations table in “AC
Characteristics” for parameters, and to Figure 12 for
timing diagrams.
Chip Erase Command Sequence
Chip erase is  a six  bus cy cle operat ion. The c hip  erase
command sequence is initiated by writing two unlock
cycles, followed by a set-up command. Two additional
unlock write cycles are then fol lowed by the chip erase
command, which in turn invokes the Embedded Erase
algorithm. The device does not require the system to
preprogram prior to erase.  The Embedded Erase algo-
rithm automatically pr eprograms and v erifi es the  entire
memory for an all zero data pattern prior to electrical
erase. The system is  not required to provide any con-
trols or timings during t hese operati ons. Tabl e 4 shows
the address and data requirements for the chip erase
command sequence. Note that the autoselect function
is unavailable when an erase operation is in progress.
Any commands written to the chip during the
Embedded Erase algorithm are ignored. Note that a
hardware rese t during the chip eras e operation imme-
diately terminates the operation. The Chip Erase
command sequence should be reinitiated once the
device has returned to reading array data, to ensure
data integrity.
The system can determine the status of the erase oper-
ation by using DQ7, DQ6, or DQ2. See “Write
Operation Status” for information on these status bits.
When the Embedded Erase algorithm is complete, the
device returns to reading ar ray data and addresses are
no longer latched. 
Figure 2 illustrates the algorithm for the erase opera-
tion. See the Erase/Program Operations tables in “AC
START
Write Program
Command Sequence
Data Poll 
from System
Verify Data? No
Yes
Last Address?
No
Yes
Programming
 Completed
Increment Address
Embedded
Program
algorithm
 in progress
Note: See Table 4 for program command sequence.
Figure 1. Program Operation

March 12, 2003 Am29LV040B 13
Characteristics” for parameters, and to Figure 13 for
timing diagrams.
Sector Erase Command Sequence
Sector erase is a six bus cycle operation. The sector
erase command sequence is initiated by writing two
unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the
address of the sector to be erased, and the sector
erase command. Table 4 shows the address and data
requirements for  the sector erase c ommand sequence.
Note that the autoselect function is unavailable when
an erase operation is in progress.
The device does not require the system to preprogram
the memory prior to erase. The Embedded Eras e algo-
rithm automatically programs and verifies the sector for
an all zero data pattern prior to electrical erase. The
system is not required to provide any controls or
timings during these operations. 
After the command sequence is written, a sector erase
time-out of 50 µs begins. During the time-out period,
additional sector addresses and sector erase com-
mands may be writte n. L oading the s ector e rase buffer
may be done in any sequence, and the number of
sectors may be fr om one sector to  all sectors. The t ime
between these additional cycles must be less than 50
µs, otherwise the las t address and command might not
be accepted, and erasure may begin. It is recom-
mended that processor interrupts be disabled during
this time to ensure all commands are accepted. The
interrupts c an be re-enabled after  the last Sector Erase
command is written. If the time between additional
sector erase commands can be assumed to be less
than 50 µs, the system need not monitor DQ3. Any
command other than Sector Erase or Erase
Suspend during the time-out period resets the
device to reading array data. The system must
rewrite the command sequence and any additional
sector addresses and commands.
The system can monito r DQ3 to determine if  the sector
erase timer has timed out. (See the “DQ3: Sector
Erase Timer” section.) The time-out begins from the
rising edge of the final WE# pulse in the command
sequence.
Once the sector erase operation has begun, only the
Erase Suspend command is v alid. All other  commands
are ignored. Note that a hardware reset during the
sector erase operation immediately terminates the
operation. The Sector Erase command sequence
should be reinitiated once the device has returned to
reading array data, to ensure data integrity.
When the Embedded Erase algorithm is complete, the
device returns t o reading array data and addresse s are
no longer latched. The system can determine the
status of the erase operation by using DQ7, DQ6, or
DQ2. (Refer to “W rite Operation St atus” f or information
on these status bits.)
Figure 2 illustrates the algorithm for the erase opera-
tion. Refer to the Erase/Program Operations tables in
the “AC Characteristic s” section for parameters, and to
Figure 13 for timing diagrams.
Erase Suspend/Erase Resume Commands
The Erase Suspend command allows the system to
interrupt a sector erase operation and then read data
from, or program data to, any sector not selected for
erasure. This command is valid only during the sector
erase operation, including the 50 µs time-out period
during the sector erase command sequence. The
Erase Suspend command is ignored if written during
the chip erase operation or Embedded Program algo-
rithm. Writing the Erase Sus pend command during the
Sector Erase time-out immediately terminates the
time-out period and suspends the erase operation.
Addresses are “don’t-cares” when writing the Erase
Suspend command.
When the Erase Suspe nd command is  written d uring a
sector erase operation,  the device requires a maximum
of 20 µs to suspend the erase operation. However,
when the Erase Suspend command is written during
the sector erase time-out, the device immediately ter-
minates the time-out period and suspends the erase
operation.
After the erase operation has been suspended, the
system can read array data from or program data to
any sector not selected for erasure. (The device “erase
suspends” all sectors selected for erasure.) Normal
read and write timings and command definitions  apply.
Reading at any address within erase-suspended
sectors produces status data on DQ7–DQ0. The
system can use DQ7, or DQ6 and DQ2 together, to
determine if a  sector is actively erasing or is  erase-sus-
pended. See “Write Operation Status” for information
on these status bits.
After an erase-suspended program operation is com-
plete, the syst em can  once again read  array data within
non-suspended sectors. The system can determine the
status of t he program operation using the DQ7 or DQ6
status bits, just as in the standard program operation.
See “Write Opera tion Status” for more information.
The system may also write the autoselect command
sequence when the device is in the Erase Suspend
mode. The device allows reading autoselect codes
even at addresses within erasing sectors, since the
codes are not stored in the memory array. When the

14 Am29LV040B March 12, 2003

device exits the autoselect mode, the device reverts to

the Erase Suspend mode, and is ready for another

valid operation. See “Auto select Command Seq uence”

for more information.

The system must write the Erase Resume command

(address bits are “don’t care”) to exit the erase suspend

mode and continue the sector erase operati on. Further

writes of the Resume command are ignored. Another

Erase Suspend command can be written after the

device has resumed erasing.

Notes:

1. See Table 4 for erase command sequence.

2. See “DQ3: Sector Erase Timer” for more information.

Figure 2. Erase Operation

START

Write Erase

Command Sequence

Data Poll

from System

Data = FFh?

Yes

Erasure Completed

Embedded

Erase

algorithm

in progress

March 12, 2003 Am29LV040B 15
Command Definitions
Table 4. Am2 9LV040B Command Definitions
Legend:
X = Don’t care
RA = Address of the memory location to be read. 
RD = Data read from location RA during read operation.
PA = Address of the memory location to be programmed. 
Addresses latch on the falling edge of the WE# or CE# pulse, 
whichever happens later.
PD = Data to be programmed at location P A. Data latches on the 
rising edge of WE# or CE# pulse, whichever happens first.
SA = Address of the sector to be verified (in autoselect mode) or 
erased. Address bits A18–A 13 uniquely select any sector.
Notes:
1. See Table 1 for description of bus operations.
2. All values are in hexadecimal.
3. Except when reading array or autoselect data, all command 
bus cycles are write operations .
4. Address bits  A18–A11 are don’t cares for unlock and 
command cycles.
5. No unlock or command cycles required when reading array 
data.
6. The Reset command is required to return to reading array 
data when device is in the au toselect mode, or if DQ5 goes 
high (while the device is providing status data).
7. The fourth cy cle of the autoselect command sequence is a 
read cycle.
8. The data is 00h for an unprotected sector and 01h for a 
protected sector. See “Autoselect Command Sequence” for 
more information.
9. The Unlock Bypass command is required prior to the Unlock 
Bypass Program command.
10. The Unlock Bypass Reset command is required to return to 
reading array data when the device is in the unlock bypass 
mode.
1 1. The system may read and program in non-erasing sectors, or 
enter the autoselect mode, when in the Erase Suspend 
mode. The Erase Suspend command is valid only during a 
sector erase operation.
12. The Erase Resume command is valid only during the Erase 
Suspend mode.
Command
Sequence
(Note 1)
Cycles
Bus Cycles (Notes 2-4)
First Second Third  Fourth  Fifth  Sixth 
Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Read (Note 5) 1 RA RD
Reset (Note 6) 1 XXX F0
Auto-
select
(Note 7)
Manufacturer ID 4 555 A A 2AA 55 555 90 X00 01
Device ID 4 555 AA 2AA 55 555 90 X01 4F
Sector Protect Verify 
(Note 8) 4 555 AA 2AA 55 555 90 (SA)
X02 00
01
Program 4 555 AA 2AA 55 555 A0 PA PD
Unlock Bypass 3 555 A A 2AA 55 555 20
Unlock Bypass Program (Note 9) 2 XXX A0 PA PD
Unlock Bypass  Reset (Note 10) 2 XXX 90 XXX 00
Chip Er ase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10
Sector Er ase 6 555 AA 2AA 55 555 80 555 AA 2AA 55 SA 30
Erase Suspend (Note 11) 1 XXX B0
Erase Resume (Note 12) 1 XXX 30

16 Am29LV040B March 12, 2003

WRITE OPERATION STATUS

The device provides several bits to determine the

status of a write operation: DQ2, DQ3, DQ5, DQ6, and

DQ7. Table 5 and the following subsections describe

the functions of these bits. DQ7 and DQ6 each offer a

method for determining whether a program or erase

operation is complete or in progress. These three bits

are discussed first.

DQ7: Data# Polling

The Data# Polling bit, DQ7, indicates to the host

system whether an Embedded Algo rithm is in progres s

or completed, or whether the device is in Erase Sus-

pend. Data# Polling is valid after the rising edge of the

final WE# pulse in the program or erase command

sequence.

During the Embedded Program algorithm, the device

outputs on DQ7 the complement of the datum pro-

grammed to DQ7. This DQ7 status also applies to

programming during Erase Suspend. When the

Embedded Program algorithm is complete, the device

outputs the datum programmed to DQ7. The system

must provide the program address to read valid status

information on DQ7. I f a program ad dress f alls within a

protected sector, Data# Polling on DQ7 is active for

approximately 1 µs, then the device returns to reading

array data.

During the Embedded Erase algorithm, Data# Polling

produces a “0” on DQ7. When the Embedded Erase

algorithm is complete, or if the device enters the Erase

Suspend mode, Data# Polling produces a “1” on DQ7.

This is analogous to the complement/true datum output

described for the Embedded Program algorithm: the

erase function changes all the bits in a sector to “1”;

prior to this, the device outputs the “complement,” or

“0.” The system must provide an address within any of

the sectors selected for erasure to read valid status

information on DQ7.

After an erase command sequence is written, if all

sectors selected for erasing are protected, Data#

Polling on DQ7 is active for approximatel y 100 µs, then

the device returns to reading array data. If not all

selected sectors are protected, the Embedded Erase

algorithm erases the unprotected sectors, and ignores

the selected sectors that are protec ted.

When the system detects DQ7 has changed from the

complement to true data, it can read valid data at DQ7–

DQ0 on the following read cycles. This is because DQ7

may change asynchronously with DQ0–DQ6 while

Output Enable (OE#) is asserted low. Figure 14, Data#

Polling Timings (During Embedded Algorithms), in the

“AC Characteristics” section illustrates this.

Table 5 shows the outputs for Data# Polling on DQ7.

Figure 3 shows the Data# Polling algorithm.

DQ7 = Data? Yes

DQ5 = 1?

Yes

FAIL PASS

Read DQ7–DQ0

Addr = VA

Read DQ7–DQ0

Addr = VA

DQ7 = Data?

START

Notes:

1. VA = Valid address for programming. During a sector

erase operation, a valid address is an address within any

sector selected for erasure. During chip erase, a valid

address is any non-protected sector address.

2. DQ7 should be rechecked even if DQ5 = “1” because

DQ7 may change simultaneously with DQ5.

Figur e 3 . Data# Polling A lgorithm

March 12, 2003 Am29LV040B 17
DQ6: Toggle Bit I
Toggle Bit I on DQ6 indicates whether an Embedded
Program or Erase  algorithm is in  progress or complet e,
or whether the device has entered the Erase Suspend
mode. Toggle Bit I may be read at any address, and is
valid after the rising edge of the final WE# pulse in the
command sequence (prior to the program or erase
operation), and during the sector erase time-out.
During an Embedded Program or Erase algorithm
operation, successive read cycles to any address
cause DQ6 to toggle. The system may use either OE#
or CE# to control the read cycles. When the operation
is complete, DQ6 stops toggling.
After an erase command sequence is written, if all
sectors selected for erasing are protected, DQ6
toggles for approximately 100 µs, then returns to
reading array data. If not all selected sectors are pro-
tected, the Embedded Erase algorithm erases the
unprotected sectors, and ignores the selected sectors
that are protected. 
The system can use DQ6 and DQ2 together to deter-
mine whether a sector is actively erasing or is erase-
suspended. When the device is actively erasing (that
is, the Embedded Erase algorit hm is in progress), DQ6
toggles. When the device enters the Erase Suspend
mode, DQ6 stops toggling. However, the system must
also use DQ2 to determine which sectors are erasing
or erase-suspended. Alternatively, the system can use
DQ7 (see the subsection on DQ7: Data# Polling).
If a program address falls within a protected sector,
DQ6 toggles for approximately 2 µs after the program
command sequence is written, then returns to reading
array data.
DQ6 also toggles during the erase-suspend-program
mode, and stops toggling once the Embedded
Program algorithm is complete.
Table 5 shows the outputs for Toggle Bit I on DQ6.
Figure 4 shows the toggle bit algorithm. Figure 15 in the
“AC Characteristics” section shows the toggle bit timing
diagrams. Figure 16 shows the differences between
DQ2 and DQ6 in graphical form. See also the subsec-
tion on DQ2: Toggle Bit II.
DQ2: Toggle Bit II
The “Toggle Bit II” on DQ2, when used with DQ6, indi-
cates whether a particular sector is actively erasing
(that i s, the Embedded  Eras e algorithm  is in prog ress),
or whether that sector is erase-suspended. Toggle Bit
II is valid after the rising edge of the final WE# pulse in
the command sequence.
DQ2 toggles when the system reads at addresses
within those sectors that have been selected for era-
sure. (The system may use either OE# or CE# to
control the read cycles.) But DQ2 cannot distinguish
whether the sector is actively erasing or is erase-sus-
pended. DQ6, by comparison, indicates whether the
device is actively erasing, or is in Erase Suspend, but
cannot distinguish which sectors are selected for era-
sure. Thus, both s tatus bits  are required for sector and
mode information. Ref er to  Table  5 to c ompare output s
for DQ2 and DQ6. 
Figure 4 shows the toggle bit algorithm in flowchart
form, and the section “DQ2: Toggle Bit II” explains the
algorithm. See also the DQ6: Toggle Bit I subsection.
Figure 15 shows the toggle bit timing diagram. Figure
16 shows the differences between DQ2 and DQ6 in
graphical form. 
Reading Toggle Bits DQ6/DQ2
Refer to Figure 4 for the following discussion. When-
ever the system initially begins reading toggle bit
status, it must  read DQ7–DQ0 at least t wice in a row to
determine whether a toggle bit is toggling. T ypically , the
system would note and store  the value of t he togg le bit
after the first read. After the second read, the system
would compare the  new  value of the toggle bit with the
first. If the toggle bit is not toggling, the device has com-
pleted the program or erase operation. The system can
read array data on DQ7–DQ0 on the following read
cycle.
However, if after the initial two read cycles, the system
determines that the toggle bit is still toggling, the
system also should note whether the value of DQ5 is
high (see the section on DQ5). If it is, the system
should then determine again whether the toggle bit is
toggling, since the toggle bit may have stopped tog-
gling just as DQ5 went high. If the toggle bit is no longer
toggling, the device has successfully completed the
program or erase operation. If it is still toggling, the
device did not completed the operation successfully,
and the system must write the reset command to return
to reading array data. 
The remaining scenario is that the system initially
determines that the toggle bit is toggling and DQ5 has
not gone high. The s ystem may continue t o monitor the
toggle bit and DQ5 through successive read cycles,
determining the status as described in the previous
paragraph. Alternatively, it may choose to perform
other system tasks. In this case, the system must start
at the beginning of the algorithm when it returns to
determine the status of the operation (top of Figure 4).

18 Am29LV040B March 12, 2003

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a “1.” This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a “1” to a location that is previously

programmed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a “1.”

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from “0” to “1.” If the time between additional sector

erase commands from the system can be assumed to

be less than 50 µs, the system need not monitor DQ3.

See also the “Sector Erase Command Sequence”

section.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data#

Polling) or DQ6 (Toggle Bit I) to ensure the device has

accepted the command sequence, and then read DQ3.

If DQ3 is “1”, the internally controlled erase cycle has

begun; all further commands (other than Erase Sus-

pend) are ignored until the erase operation is complete.

If DQ3 is “0”, the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system soft ware should check the stat us

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been

accepted. Table 5 shows the outputs for DQ3.

START

Yes

DQ5 = 1?

Yes

Toggle Bit

= Toggle? No

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Read DQ7–DQ0

Toggle Bit

= Toggle?

Read DQ7–DQ0

Twice

Read DQ7–DQ0

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to “1” . See text.

Figure 4. Togg le B it Algori thm

(Notes

1, 2)

(Note 1)

March 12, 2003 Am29LV040B 19

Table 5. Write Operation Status

Notes:

1. DQ5 switches to ‘1’ when an Embedded Program or Embedded Erase operation has exceeded the maximum timing limits.

See “” for more information.

2. DQ7 and DQ2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

Operation DQ7

(Note 2) DQ6 DQ5

(Note 1) DQ3 DQ2

(Note 2)

Standard

Mode Embedded Program Algorithm DQ7# Toggle 0 N/A No toggle

Embedded Erase Algorithm 0 Toggle 0 1 Toggle

Erase

Suspend

Mode

Reading with in Era se

Suspend ed Sec tor 1 No toggle 0 N/A Toggle

Reading with in Non -Er ase

Suspend ed Sec tor Data Data Data Data Data

Erase-Suspend-Program DQ7# Toggle 0 N/A N/A

20 Am29LV040B March 12, 2003

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Plastic Packages . . . . . . . . . . . . . . . –65°C to +15 0°C

Ambient Temperature

with Power Applied . . . . . . . . . . . . . –65°C to +125°C

Voltage with Respect to Ground

VCC (Note 1) . . . . . . . . . . . . . . . . .–0.5 V to +4.0 V

A9, OE# (Note 2) . . . . . . . . . . . .–0.5 V to + 12.5 V

All other pins

(Note 1). . . . . . . . . . . . . . . . . –0.5 V to VCC+0.5 V

Output Short Circuit Current (Note 3) . . . . . . 200 mA

Notes:

1. Minimum DC voltage on input or I/O pins is –0.5 V . During

voltage transitions, input or I/O pins may overshoot VSS

to –2.0 V for periods of up to 20 ns. See Figure 5.

Maximum DC voltage on input or I/O pins is VCC +0.5 V.

During voltage transitions, input or I/O pins may

overshoot to VCC +2.0 V for periods up to 20 ns. See

Figure 6.

2. Minimum DC input voltage on pins A9 and OE# is –0.5 V .

During voltage transitions, A9 and OE# may overshoot

VSS to –2.0 V for periods of up to 20 ns. See Figure 5.

Maximum DC input voltage on pin A9 is +12.5 V which

may overshoot to 14.0 V for periods up to 20 ns.

3. No more than one output may be shorted to ground at a

time. Duration of the short circuit should not be greater

than one second.

Stresses above those listed under “Absolute Maximum

Ratings” may cause permanent damage to the device. This

is a stress rating only; functional operation of the device at

these or any other conditions above those indicated in the

operational sections of this data sheet is not implied.

Exposure of the device to absolute maximum rating

conditio ns for exte nd ed per iod s may affe ct dev ice relia bili ty.

OPERATING RANGES

Commercial (C) Devices

Ambient Temperature (TA) . . . . . . . . . . . 0 °C to +70°C

Industrial (I) Devices

Ambient Temperature (TA) . . . . . . . . . –40°C to +85°C

Extended (E) Devices

Ambient Temperature (TA) . . . . . . . . –55°C to +125°C

VCC Supply Voltages

VCC for regulated voltage range. . . . . . .3.0 V to 3.6 V

VCC for full volt age range. . . . . . . . . . . .2.7 V to 3.6 V

Operating ranges define those limits between which the func-

tionality of the device is guaranteed.

20 ns

+0.8 V

–0.5 V

20 ns

–2.0 V

Figure 5. Maximum Negative

Overshoot Waveform

20 ns

VCC

+2.0 V

VCC

+0.5 V

20 ns

2.0 V

Figure 6. Maximum Positive

Overshoot Waveform

March 12, 2003 Am29LV040B 21
DC CHARACTERISTICS
CMOS Compatible
Notes:
1. The ICC current listed is typically less than 2 mA/MHz, with OE# at VIH. Typical VCC is 3.0 V.
2. Maximum I CC current specifications are tested with VCC=VCCmax.
3. ICC active while Embedded Erase or Embedded Program is in progress.
4. Not 100% tested.
5. Automatic sleep mode enables the low power mode when addresses remain stable for tACC + 30 ns.
Parameter Description Test Conditions Min Typ Max Unit
ILI Input Load Current VIN = VSS to VCC, 
VCC = VCC max ±1.0 µA
ILIT A9 Input Load Current VCC = VCC max; A9 = 12.5 V 35 µA
ILO Output Leakage Current VOUT = VSS to VCC, 
VCC = VCC max ±1.0 µA
ICC1 VCC Active Read Current 
(Notes 1, 2) CE# = VIL, OE# = VIH 5 MHz 7 12 mA
1 MHz 2 4
ICC2 VCC Active Write Current 
(Notes 2, 3, 4) CE# = VIL, OE# = VIH 15 30 mA
ICC3 VCC Standby Current (Note 2) CE# = VCC ± 0.3 V 0.2 5 µA
ICC4 VCC Reset Current (Note 2) 0.2 5 µA
ICC5 Automatic Sleep Mode
(Notes 2, 5) VIH = VCC ± 0.3 V; 
VIL = VSS ± 0.3 V 0.2 5 µA
VIL Input Low Voltage –0.5 0.8 V
VIH Input High Voltage 0.7 x VCC VCC + 0.3 V
VID Voltage for Autoselect and 
Temporary Sector Unprotect VCC = 3.3 V 11.5 12.5 V
VOL Output Low Voltage IOL = 4.0 mA, VCC = VCC min 0.45 V
VOH1 Output High Voltage IOH = –2.0 mA, VCC = VCC min 0.85 VCC V
VOH2 IOH = –100 µA, VCC = VCC min V
CC–0.4
VLKO Low VCC Lock-Out Voltage 
(Note 4) 2.3 2.5 V

22 Am29LV040B March 12, 2003

DC CHARACTERISTICS (continued)

Zero Power Flash

00 500 1000 1500 2000 2500 3000 3500 4000

Supp ly Cu rr e nt in m A

Time in ns

Note: Addresses are switching at 1 MHz

Figure 7. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents)

12345

Frequenc y in MHz

Supply Current in mA

Note: T = 25 °C

Figure 8. Typical ICC1 vs. Frequency

2.7 V

3.6 V

March 12, 2003 Am29LV040B 23

TEST CONDITIONS

Table 6. Test Specifications

KEY TO SWITCHING WAVEFORMS

2.7 kΩ

CL6.2 kΩ

3.3 V

Device

Under

Test

Figure 9. Test Setup

Note: Diodes are IN3064 or equivalent

Test Con dit ion -60R,

-70 -90,

-120 Unit

Output Load 1 TTL gate

Output Load Capacitance, CL

(including jig cap aci tan ce) 30 100 pF

Input Rise and Fall Times 5 ns

Input Pulse Levels 0.0–3.0 V

Input timing measurement

reference levels 1.5 V

Output timing measurement

reference levels 1.5 V

WAVEFORM INPUTS OUTPUTS

Steady

Changing from H to L

Changing from L to H

Don’t Care, Any Change Permitted Changing, State Unknown

Does Not Apply Center Line is High Impedance State (High Z)

3.0 V

0.0 V 1.5 V 1.5 V OutputMeasurement LevelInput

Figure 10. Input Waveforms and Measurement Levels

24 Am29LV040B March 12, 2003

AC CHARACTERISTICS

Read Operations

Notes:

1. Not 100% tested.

2. See Figure 9 and Table 6 for test specifications.

Parameter

Description

Speed Option

JEDEC Std Test Setup -60R -70 -90 -120 Unit

tAVAV tRC Read Cycle Time (Note 1) Min 60 70 90 120 ns

tAVQV tACC Address to Output Delay CE# = VIL

OE# = VIL Max 60 70 90 120 ns

tELQV tCE Chip Enable to Output Delay OE# = VIL Max 60 70 90 120 ns

tGLQV tOE Output Enable to Output Delay Max 30 30 35 50 ns

tEHQZ tDF Chip Enable to Output High Z (Note 1) Max 16 ns

tGHQZ tDF Output Enable to Output High Z (Note 1) Max 16 ns

tOEH Output Enable

Hold Time (Note 1)

Read Min 0 ns

Toggle and

Data# Polling Min 10 ns

tAXQX tOH Output Hold Time From Addresses, CE# or

OE#, Whichever Occurs First (Note 1) Min 0 ns

tCE

Outputs

WE#

Addresses

CE#

OE#

HIGH Z

Output V alid

HIGH Z

Addresses Stable

tRC

tACC

tOEH

tOE

0 V

tDF

tOH

Figure 11. Read Operations Timings

March 12, 2003 Am29LV040B 25

AC CHARACTERISTICS

Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Speed Op tion s

JEDEC Std Description -60R -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 60 70 90 120 ns

tWLAX tAH Address Hold Time Min45454550ns

tDVWH tDS Data Setup Time Min35354550ns

tWLWH tWP Write Pulse Width Min 35 35 35 50 ns

tAVWL tAS Address Set up Time Min 0 ns

tWHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHWL tGHWL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tELWL tCS CE# Setup Time Min 0 ns

tWHEH tCH CE# Hold Time Min 0 ns

tWHWL tWPH Write Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs

tWHWH2 tWHWH2 Sector Erase Operation (Note 2) Typ 0.7 sec

tVCS VCC Setup Time (Note 1) Min 50 µs

26 Am29LV040B March 12, 2003

AC CHARACTERISTICS

OE#

WE#

CE#

VCC

Data

Addresses

tDS

WHWH1

WPH

VCS

555h PA PA

Read Status Data (last two cycles)

A0h

Status D

OUT

Program Command Sequence (last two cycles)

Note: PA = program address, PD = program data, DOUT is the true data at the program address.

Figure 12. Program Operation Timings

OE#

CE#

Addresses

VCC

WE#

Data

2AAh SA

tAH

tWP

tWC tAS

tWPH

555h for chip erase

10 for Chip Erase

30h

tDS

tVCS

tCS

tDH

55h

tCH

Progress Complete

tWHWH2

Erase Command Sequence (last two cycles) Read Status Data

Note: SA = sect or addr ess (for Sector Erase ), V A = V alid Ad dress for rea ding s tatus data (see “Write Operation Status”).

Figure 13. Chip/Sector Erase Operation Timings

March 12, 2003 Am29LV040B 27

AC CHARACTERISTICS

WE#

CE#

OE#

High Z

DQ7

DQ0–DQ6

Complement True

Addresses VA

OEH

VA VA

Status Data

Complement

Status Data True

Valid Data

ACC

Note: VA = Valid address. Illustration shows first status cycle after command sequence, last status read cycle, and array data

read cycle.

Figure 14. Data# Polling T imings (During Embedded Algorithms)

WE#

CE#

OE#

High Z

tOE

DQ6/DQ2

Addresses VA

tOEH

tCE

tCH

tOH

tDF

VA VA

tACC

tRC

Valid DataValid StatusValid Status

(first read) (second read) (stops toggling)

Valid Status

Note: VA = Valid address; not required for DQ6. Illustration shows first two status cycle after command sequence, last status read

cycle, and array data read cycle.

Figure 15. Toggle Bit Timings (During Embedded Algorithms)

28 Am29LV040B March 12, 2003

AC CHARACTERISTICS

Note: The system may use CE# or OE# to toggle DQ2 and DQ6. DQ2 toggles only when read at an address within an

erase-suspended sector.

Figure 16. DQ2 vs. DQ6

Enter

Erase

Enter Erase

Suspend Pro gra m

Erase Suspend

Read Erase Suspend

Read

Erase

WE#

DQ6

DQ2

Erase

Complete

Erase

Suspend

Program

Resume

Embedded

Erasing

March 12, 2003 Am29LV040B 29

AC CHARACTERISTICS

Alternate CE# Controlled Erase/Program Operations

Notes:

1. Not 100% tested.

2. See the “Erase and Programming Performance” section for more information.

Parameter Speed Options

JEDEC Std Description -60R -70 -90 -120 Unit

tAVAV tWC Write Cycle Time (Note 1) Min 60 70 90 120 ns

tELAX tAH Address Hold Time Min 45 45 45 50 ns

tDVEH tDS Data Setup Time Min35354550ns

tELEH tCP CE# Pulse Width Min 35 35 35 50 ns

tAVEL tAS Address Setup Time Min 0 ns

tEHDX tDH Data Hold Time Min 0 ns

tOES Output Enable Setup Time Min 0 ns

tGHEL tGHEL Read Recovery Time Before Write

(OE# High to WE# Low) Min 0 ns

tWLEL tWS WE# Setup Time Min 0 ns

tEHWH tWH WE# Hold Time Min 0 ns

tEHEL tCPH CE# Pulse Width High Min 30 ns

tWHWH1 tWHWH1 Programming Operation (Note 2) Typ 9 µs

tWHWH2 tWHWH2 Sector Erase Op era tion (Note 2) Ty p 0.7 sec

30 Am29LV040B March 12, 2003

AC CHARACTERISTICS

tGHEL

tWS

OE#

CE#

WE#

tDS

Data

tAH

Addresses

tDH

tCP

DQ7# D

OUT

tWC tAS

tCPH

Data# Polling

A0 for program

55 for erase

tWHWH1 or 2

tWH

PD for program

30 for sector erase

10 for chip erase

555 for program

2AA for erase PA for program

SA for sector erase

555 for chip erase

Notes:

1. PA = Program Address, PD = Program Data, DQ7# = complement of the data written to the device, DOUT is the data writte

to the device.

2. Figure indicates the last two bus cycles of the command sequence.

Figure 17. A lternate CE# Controlled Write Operation Timings

March 12, 2003 Am29LV040B 31

ERASE AND PROGRAMMING PERFORMANCE

Notes:

1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 1,000,000 cycles. Additionally,

programming typicals assume checkerboard pattern.

2. Under worst case conditions of 90°C, VCC = 2.7 V (3.0 V for -60R), 1,000,000 cycles.

3. The typical chip programming time is considerably less than the maximum chip programming time listed, since most bytes

program faster than the maximum program times listed.

4. In the pre-programming step of the Embedded Erase algorithm, all bytes are programmed to 00h before erasure.

5. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See

Table 4 for further information on command definitions.

6. The device has a minimum guaranteed erase and program cycle endurance of 1,000,000 cycles.

LATCHUP CHARACTERISTICS

Includes all pins except VCC. Test conditions: VCC = 3.0 V, one pin at a time.

TSOP AND SO PIN CAPACITANCE

Notes:

1. Sampled, not 100% tested.

2. Test conditions TA = 25°C, f = 1.0 MHz.

DATA RETENTION

Parameter Typ (Note 1) Max (Note 2) Unit Comments

Sector Erase Time 0.7 15 s Excludes 00h programm ing

prior to erasure (Note 4)

Chip Erase Time 11 s

Byte Programming Time 9 300 µs Excludes sys tem level

overhead (No te 5)

Chip Programming Time

(Note 3) 4.5 13.5 s

Description Min Max

Input voltage with respect to VSS on all pins except I/O pins

(including A9 and OE#) –1.0 V 12.5 V

Input voltage with respect to VSS on all I/O pins –1.0 V VCC + 1.0 V

VCC Current –100 mA +100 mA

Parameter

Symbol Parameter Description Test Setup Typ Max Unit

CIN Input Capacitance VIN = 0 6 7.5 pF

COUT Output Capacitance VOUT = 0 8.5 12 pF

CIN2 Control Pin Capacitance VIN = 0 7.5 9 pF

Parameter Test Conditions Min Unit

Minimum Pattern Data Retention Time 150°C10Years

125°C20Years

32 Am29LV040B March 12, 2003

PHYSICAL DIMENSIONS*

TS 032—32-Pin Standard TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

March 12, 2003 Am29LV040B 33

PHYSICAL DIMENSIONS

TSR032—32-Pin Reverse TSOP

* For reference only. BSC is an ANSI standard for Basic Space Centering.

Dwg rev AA; 10/99

34 Am29LV040B March 12, 2003

PHYSICAL DIMENSIONS

PL 032—32-Pin Plastic Leaded Chip Carrier

PL 032

Dwg rev AH; 10/99

March 12, 2003 Am29LV040B 35

REVISION SUMMARY

Revision A (January 1998)

Revision B (April 1998)

Expanded data sheet from Advanced Information to

Preliminary version.

Revision B+1 (November 1998)

Connection Diagrams

Corrected the standard TSOP pinout.

Revision C (January 1999)

Distinctive Characteristics

Added 20-year data retention subbullet.

Revision C+1 (May 18, 1999)

Removed preliminary designation from data sheet.

Revision C+2 (July 20, 1999)

Physical Dimensions

Corrected the unit of measurement for the 32-pin

PLCC to inches.

Revision D (November 11, 1999)

Global

Changed all references to 55R speed option (55 ns,

regulated voltage range) to 60R (60 ns, regulated

voltage range).

Physical Dimensions

Replaced all drawings with new versions.

AC Characteristics—Figure 12. Program

Operations Timing and Figure 13. Chip/Sector

Erase Operations

Deleted tGHWL and changed OE# waveform to start at

high.

Revision D+1 (November 13, 2000)

Global

Added table of contents. Deleted burn-in option from

Ordering Information section.

Revision E (March 12, 2003)

Distinctive Characteristics

Corrected the values for the automatic sleep mode and

standby mode.

Comm and Defin itions

Added new global text to first paragraph.

Byte/Word Program Command Sequence, Sector

Erase Command Sequence, and Chip Erase Com-

mand Sequence

Noted that the autoselect function is unavailable when

a program or erase operation is in progress.

Read Operations

Changed the tEHQZ and tGHQZ max to 16 ns for all

speed options.

Trademarks

AMD, the AMD logo, and combinations thereof are registered trademarks of Advanced Micro Devices, Inc.

ExpressFlash is a trademark of Advanced Micro Devices, Inc.

Product names used in this publication are for identification purposes only and may be trademarks of their respective companies.

01/03

Printed in USA

One AMD Place, P.O. Box 3453, Sunnyvale, CA 94088-3453 408-732-2400

TWX 910-339-9280 TELEX 34-6306 800-538-8450 http://www.amd.com

Advanced Micro Devices reserves the right to make changes in its product without notice

in order to improve design or performance characteristics.The performance

characteristics listed in this document are guaranteed by specific tests, guard banding,

design and other practices common to the industry. For specific testing details, contact

your local AMD sales representative.The company assumes no responsibility for the use of

any circuits described herein.

AMD, the AMD Arrow logo and combination thereof, are trademarks of

Advanced Micro Devices, Inc. Other product names are for informational purposes only

and may be trademarks of their respective companies.

North America

ALABAMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(256)830-9192

ARIZONA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (602)242-4400

CALIFORNIA,

Irvine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 49)450-7500

Sunnyvale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)732-2400

COLORADO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (303)741-2900

CONNECTICUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (203)264-7800

FLORIDA,

Clearwater . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (7 2 7)793-0055

Miami (Lakes) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (305)820-1113

GEORGIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (770)814-0224

ILLINOIS,

Chicago . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (630)773-4422

MASSACHUSETTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (781)213-6400

MICHIGAN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 2 48)471-6294

MINNESOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (612)745-0005

NEW JERSEY,

Chatham . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 73)701-1777

NEW YORK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (716)425-8050

NORTH CAROLINA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (919)840-8080

OREGON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (503)245-0080

PENNSYLVANIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (215)340-1187

SOUTH DAKOTA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (605)692-5777

TEXAS,

Austin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (512)346-7830

Dallas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 7 2)985-1344

Houston . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (281)376-8084

VIRGINIA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (703)736-9568

International

AUSTRALIA, North Ryde . . . . . . . . . . . . . . . . . . . . . . . TEL(61)2-88-777-222

BELGIUM,Antwerpen . . . . . . . . . . . . . . . . . . . . . . . .TEL(32)3-248-43-00

BRAZIL, San Paulo . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(55)11-5501-2105

CHINA,

Beijing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)10-6510-2188

Shanghai . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)21-635-00838

Shenzhen . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(86)755-246-1550

FINLAND, Helsinki . . . . . . . . . . . . . . . . . . . . . . TEL(358)881-3117

FRANCE, Paris . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(33)-1-49751010

GERMANY,

Bad Homburg . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(49)-6172-92670

Munich . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(49)-89-450530

HONG KONG, Causeway Bay . . . . . . . . . . . . . . . . . . . TEL(85)2-2956-0388

ITALY, Milan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(39)-02-381961

INDIA, New Delhi . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(91)11-623-8620

JAPAN,

Osaka . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(81)6-6243-3250

Tokyo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TEL(81)3-3346-7600

KOREA, Seoul . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(82)2-3468-2600

RUSSIA, Moscow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(7)-095-795-06-22

SWEDEN, Stockholm . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(46)8-562-540-00

TAIWAN,Taipei . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(886)2-8773-1555

UNITED KINGDOM,

Frimley . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(44)1276-803100

Haydcock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TEL(44)1942-272888

Representatives in U.S. and Canada

ARIZONA,

Tempe - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (480)839-2320

CALIFORNIA,

Calabasas - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(818)878-5800

Irvine - Centaur . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 9 49)261-2123

San Diego - Centaur. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . (858)278-4950

Santa Clara - Fourfront. . . . . . . . . . . . . . . . . . . . . . . . . . . . (408)350-4800

CANADA,

Burnaby, B.C. - Davetek Marketing. . . . . . . . . . . . . . . . . . . . (604)430-3680

Calgary,Alberta - Davetek Marketing. . . . . . . . . . . . . . . . . (403)283-3577

Kanata, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . . . (613)592-9540

Mississauga, Ontario - J-Squared Tech. . . . . . . . . . . . . . . . . . (905)672-2030

St Laurent, Quebec - J-Squared Tech. . . . . . . . . . . . . . . . (514)747-1211

COLORADO,

Golden - Compass Marketing . . . . . . . . . . . . . . . . . . . . . . (303)277-0456

FLORIDA,

Melbourne - Marathon Technical Sales . . . . . . . . . . . . . . . . (321)728-7706

Ft. Lauderdale - Marathon Technical Sales . . . . . . . . . . . . . .(954)527-4949

Orlando - Marathon Technical Sales . . . . . . . . . . . . . . . . . . (407)872-5775

St. Petersburg - Marathon Technical Sales . . . . . . . . . . . . . .( 72 7)894-3603

GEORGIA,

Duluth - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . ( 6 78)584-1128

ILLINOIS,

Skokie - Industrial Reps, Inc. . . . . . . . . . . . . . . . . . . . . . . . .( 8 4 7)967-8430

INDIANA,

Kokomo - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ( 7 65)457-7241

IOWA,

Cedar Rapids - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . (319)294-1000

KANSAS,

Lenexa - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . (913)469-1312

MASSACHUSETTS,

Burlington - Synergy Associates . . . . . . . . . . . . . . . . . . . . . (781)238-0870

MICHIGAN,

Brighton - SAI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(810)227-0007

MINNESOTA,

St. Paul - Cahill, Schmitz & Cahill, Inc. . . . . . . . . . . . . . . . . .(651)699-0200

MISSOURI,

St. Louis - Lorenz Sales . . . . . . . . . . . . . . . . . . . . . . . . . . (314)997-4558

NEW JERSEY,

Mt. Laurel - SJ Associates . . . . . . . . . . . . . . . . . . . . . . . . . (856)866-1234

NEW YORK,

Buffalo - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . .(716)741-7116

East Syracuse - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . (315)437-8343

Pittsford - Nycom, Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(716)586-3660

Rockville Centre - SJ Associates . . . . . . . . . . . . . . . . . . . . (516)536-4242

NORTH CAROLINA,

Raleigh - Quantum Marketing . . . . . . . . . . . . . . . . . . . . . . (919)846-5728

OHIO,

Middleburg Hts - Dolfuss Root & Co. . . . . . . . . . . . . . . . . (440)816-1660

Powell - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . . . (614)781-0725

Vandalia - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . . . .(937)898-9610

Westerville - Dolfuss Root & Co. . . . . . . . . . . . . . . . . . . (614)523-1990

OREGON,

Lake Oswego - I Squared, Inc. . . . . . . . . . . . . . . . . . . . . . . (503)670-0557

UTAH,

Murray - Front Range Marketing . . . . . . . . . . . . . . . . . . . . (801)288-2500

VIRGINIA,

Glen Burnie - Coherent Solution, Inc. . . . . . . . . . . . . . . . . (410)761-2255

WASHINGTON,

Kirkland - I Squared,Inc. . . . . . . . . . . . . . . . . . . . . . . . . . .(425)822-9220

WISCONSIN,

Pewaukee - Industrial Representatives . . . . . . . . . . . . . . . . ( 2 6 2)574-9393

Representatives in Latin America

ARGENTINA,

Capital Federal Argentina/WW Rep. . . . . . . . . . . . . . . . . . . .54-11)4373-0655

CHILE,

Santiago - LatinRep/WWRep. . . . . . . . . . . . . . . . . . . . . . . . . .(+562)264-0993

COLUMBIA,

Bogota - Dimser. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .(571)410-4182

MEXICO,

Guadalajara - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 523)817-3900

Mexico City - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . ( 525)752-2727

Monterrey - LatinRep/WW Rep. . . . . . . . . . . . . . . . . . . . .(528)369-6828

PUERTO RICO,

Boqueron - Infitronics. . . . . . . . . . . . . . . . . . . . . . . . . . . . (787)851-6000

Sales Offices and Representative