1/11April 2001
■HIGH SPE ED: t PD = 5ns (TYP.) at VCC = 5V
■LOW POWER DISSIPATION:
ICC = 4µA(MAX.) at TA=25°C
■HIGH NOISE IMMUNITY:
VNIH = VNIL = 28 % VCC (MIN.)
■50Ω TRANSMISSION LINE DRIVING
CAPABILITY
■SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 24m A (MIN)
■BALANCED PROPAGATI ON DELAYS:
tPLH ≅ tPHL
■OPERATIN G VOLTAGE RANGE:
VCC (O PR) = 2V to 6V
■PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 373
■IMPROVED LATCH-U P IMMUNITY
DESCRIPTION
The 74AC373 is a high-speed CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C2MOS
technology.
These 8 bit D-Typ e l atch are c ont rolled by a latch
enable input (LE) and an output enable input (OE).
While the LE inputs is held at a high level, the Q
outputs will follow the data input. When the LE is
taken low, the Q outputs will be latched at the
logic level of D i nput data. While the (O E) input is
low, the 8 outputs will be in a normal logic state
(high or low logic level); while OE is in high le vel
the outputs will be in a high impedance state.
This device is designed to interface directly High
Speed CMOS systems with TTL and NMOS
components.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
74AC373
OCTAL D-TYPE LATCH
WITH 3 STATE OUTPUTS (NON INVERTED)
PIN CONNECTION AND IE C LOGIC SYMBOLS
ORDER CODES
PACKAGE TUBE T & R
DIP 74AC373B
SOP 74AC373M 74AC373MTR
TSSOP 74AC373TTR
TSSOPDIP SOP
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INPUT AND OUT PUT EQUIVALENT CIRCUIT PIN DESCRIPTION
TRUTH TABLE
X : Don ’t Care
Z : Hi gh Imp edance
NOTE: Output s are latched at the time when the input is taken LOW logic lev el
LOGIC DIAGRAM
Th i s l ogic dia gram has not be used to estimat e propagation del ays
PIN No SYMBOL NAME AND FUNCTION
1OE
3 State Output Enable
Input (Active LOW)
2, 5, 6, 9, 12,
15, 16,19 Q0 to Q7 Data Inputs
3, 4, 7, 8, 13,
14, 17, 18 D0 to D7 3-State Outputs
11 LE Latch Enable Input
10 GND Ground (0V)
20 VCC Positive Supply Voltage
INPUTS OUTPUT
OE LE D Q
HXXZ
L L X NO CHANGE
LHLL
LHHH
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ABSOLUTE MAXIMUM RATING S
Absolute Maximum Ratings are t hose v alues beyond which damage to the device may occur. Functional operation under these conditions is
not implie d .
RECOMMENDE D OPERATING CONDITI ONS
1) VIN from 30% to 70 % of VCC
Symbol Parameter Value Unit
VCC Supply Voltage -0.5 to +7 V
VIDC Input Voltage -0.5 to VCC + 0.5 V
VODC Output Volta ge -0.5 to VCC + 0.5 V
IIK DC Input Diode Current ± 20 mA
IOK DC Output Diode Current ± 20 mA
IODC Output Current ± 50 mA
ICC or IGND DC VCC or Ground Curre nt ± 400 mA
Tstg Storage Temperature -65 to +150 °C
TLLead Temperature (10 sec) 300 °C
Symbol Parameter Value Unit
VCC Supply Voltage 2 to 6 V
VIInput Voltage 0 to VCC V
VOOutput Voltage 0 to VCC V
Top Operating Temperature -55 to 125 °C
dt/dv Input Rise and Fall Time VCC = 3.0, 4.5 or 5.5V (note 1) 8 ns/V
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DC SPE CIFICATI ONS
1) M aximum test du rat i on 2ms, one output loaded at time
2 ) I nciden t wave sw i tc hi ng is gu aranteed on tran sm i ssion l i nes with impedances a s l ow as 50Ω
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
VIH High Level Input
Voltage 3.0 VO = 0.1 V or
VCC-0.1V
2.1 1.5 2.1 2.1 V4.5 3.15 2.25 3.15 3.15
5.5 3.85 2.75 3.85 3.85
VIL Low Level Input
Voltage 3.0 VO = 0.1 V or
VCC-0.1V
1.5 0.9 0.9 0.9 V4.5 2.25 1.35 1.35 1.35
5.5 2.75 1.65 1.65 1.65
VOH High Level Output
Voltage 3.0 IO=-50 µA2.9 2.99 2.9 2.9
V
4.5 IO=-50 µA4.4 4.49 4.4 4.4
5.5 IO=-50 µA5.4 5.49 5.4 5.4
3.0 IO=-12 mA 2.56 2.46 2.4
4.5 IO=-24 mA 3.86 3.76 3.7
5.5 IO=-24 mA 4.86 4.76 4.7
VOL Low Level Output
Voltage 3.0 IO=50 µA0.002 0.1 0.1 0.1
V
4.5 IO=50 µA0.001 0.1 0.1 0.1
5.5 IO=50 µA0.001 0.1 0.1 0.1
3.0 IO=12 mA 0.36 0.44 0.5
4.5 IO=24 mA 0.36 0.44 0.5
5.5 IO=24 mA 0.36 0.44 0.5
IIInput Leakage
Current 5.5 VI = VCC or GND ± 0.1 ± 1 ± 1 µA
Ioz High Impedance
Output Leakege
Current 5.5 VI = VIH or VIL
VO = VCC or GND ± 0.5 ± 5 ± 10 µA
ICC Quiescent Supply
Current 5.5 VI = VCC or GND 44080µA
I
OLD Dynamic Output
Current (note 1, 2) 5.5 VOLD = 1.65 V max 75 50 mA
IOHD VOHD = 3.85 V min -75 -50 mA
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AC EL ECTRI CAL CHARACTERISTICS (CL = 50 pF, RL = 500 Ω, Inp u t tr = tf = 3ns)
(*) Voltage ra nge is 3.3V ± 0.3V
(**) Voltage range is 5.0V ± 0.5V
CAPACITIVE CHARACT ERISTICS
1) C PD is defined as the value of the IC’s internal equivalent capacitance which is calculated f rom the operating current cons umption without
load. (Refer to Test Ci rcuit). Average operating current can be obtained by t he following equation. ICC(opr) = CPD x VCC x fIN + ICC/n ( per c ircuit )
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
tPLH tPHL Propagation Delay
Time
LE to Q
3.3(*) 6.5 12.0 14.0 14.0 ns
5.0(**) 5.0 9.5 10.5 10.5
tPLH tPHL Propagation Delay
Time
D to Q
3.3(*) 6.5 12.0 14.0 14.0 ns
5.0(**) 5.0 9.5 10.5 10.5
tPZL tPZH Output Enable
Time 3.3(*) 7.0 11.0 13.0 13.0 ns
5.0(**) 5.0 8.5 9.5 9.5
tPLZ tPHZ Output Disable
Time 3.3(*) 7.5 12.0 13.0 13.0 ns
5.0(**) 6.5 9.0 10.0 10.0
tWCLOCK Pulse
Width HIGH or
LOW
3.3(*) 1.5 5.5 6.0 6.0 ns
5.0(**) 1.5 4.0 4.5 4.5
tsSetup Time D to
CLOCK, HIGH or
LOW
3.3(*) 0.5 5.5 6.0 6.0 ns
5.0(**) 0.5 4.0 4.5 4.5
thHold Time D to
CLOCK, HIGH or
LOW
3.3(*) -0.5 1.0 5.0 5.0 ns
5.0(**) -0.5 1.0 5.0 5.0
Symbol Parameter
Test Condition Value
Unit
VCC
(V)
TA = 25°C -40 to 85°C -55 to 125°C
Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0 4 pF
COUT Output
Capacitance 5.0 8 pF
CPD Power Dissipation
Capacitance (note
1) 5.0 fIN = 10MHz 20 pF
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TEST CIRCUIT
CL = 50p F or equiva l ent (i nclud es j i g and probe capacitance)
RL = R1 = 500Ω or equivalent
RT = ZOUT of pulse ge nerator (typically 50Ω)
WAVE FORM 1: LE TO Qn PROPAGATION DELAYS, LE MI NIMUN PULSE WIDTH, Dn TO LE SETUP
AND HOLD TIMES (f= 1MHz; 5 0% duty cycle)
TEST SWITCH
tPLH, tPHL Open
tPZL, tPLZ 2VCC
tPZH, tPHZ Open
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WAV EFORM 2: OUTPUT ENABLE AND DISABLE TIMES (f=1MHz; 5 0% duty cycle)
WAVEFORM 3: PROPAGATION DELAY T IME (f=1MHz; 50% duty cycle)
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DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A250.984
B7.80.307
D3.3 0.130
E 0.5 1.78 0.020 0.070
e3 22.86 0.900
F 2.29 2.79 0.090 0.110
G 0.4 0.55 0.016 0.022
I 1.27 1.52 0.050 0.060
L 0.22 0.31 0.009 0.012
M 0.51 1.27 0.020 0.050
N1 4 (min.), 15 (max.)
P 7.9 8.13 0.311 0.320
Q5.710.225
P057H
Ceramic DIP-20 MECHANICAL DATA
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DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A2.650.104
a1 0.10 0.20 0.004 0.007
a2 2.45 0.096
b 0.35 0.49 0.013 0.019
b1 0.23 0.32 0.009 0.012
C0.50 0.020
c1 45 (typ.)
D 12.60 13.00 0.496 0.512
E 10.00 10.65 0.393 0.419
e1.27 0.050
e3 11.43 0.450
F 7.40 7.60 0.291 0.299
L 0.50 1.27 0.19 0.050
M0.750.029
S8 (max.)
P013L
SO-20 MECHANICAL DATA
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DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX.
A1.10.433
A1 0.05 0.10 0.15 0.002 0.004 0.006
A2 0.85 0.9 0.95 0.335 0.354 0.374
b 0.19 0.30 0.0075 0.0118
c 0.09 0.2 0.0035 0.0079
D 6.4 6.5 6.6 0.252 0.256 0.260
E 6.25 6.4 6.5 0.246 0.252 0.256
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.02 56 BSC
K0
o4
o8
o0
o4
o8
o
L 0.50 0.60 0.70 0.020 0.024 0.028
cE
b
A2
A
E1
D
1
PIN 1 IDENTIFICATION
A1 L
K
e
TSSOP20 MECHANICAL DATA
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74AC373
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conseque nces of use of such i nformation nor for any infringement of patents or ot her rights of third parties which may result from
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previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
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